CN115207100A - Trench MOSFET and method of manufacturing the same - Google Patents

Abstract

The application discloses a groove type MOSFET transistor and a manufacturing method thereof, and relates to the technical field of semiconductor devices. The trench MOSFET transistor includes: the substrate comprises a first surface, wherein an epitaxial layer of a first doping type is arranged on the first surface; a well region of a second doping type disposed within the epitaxial layer; the grid groove structure is arranged in the well region; a gate trench structure comprising: a plurality of mutually insulated first field plates disposed between the gate and the bottom of the gate trench structure, each first field plate having the same length in a direction parallel to the first surface; the gate is insulated from the first field plate; the distance between two adjacent first field plates in a direction perpendicular to the first surface is determined by the thickness of each first field plate. According to the method and the device, the uniform distribution of the electric field in the trench MOSFET can be ensured, and the manufacturing process is simplified.

Description

Trench MOSFET transistor and method of making the same

technical field

The present application belongs to the technical field of semiconductor devices, and in particular, relates to a trench MOSFET transistor and a manufacturing method thereof.

Background technique

Metal Oxide Semiconductor Field Effect Transistor (Metal Oxide Semiconductor Field Effect Transistor) MOSFET is a voltage control device with simple driving circuit, low driving power, fast switching speed and high operating frequency.

In the trench MOSFET structure with a single field plate (FP), a peak electric field will appear at the bottom of the drift region on the side of the gate trench structure. Therefore, the electric field distribution is triangular and the electric field distribution is not uniform.

In order to achieve uniform distribution of the electric field in the trench MOSFET transistor, the multi-step MOSFET structure designs the dielectric layer in contact with the deep trench and the drift region into multiple steps. That is, in the direction perpendicular to the substrate, the closer the field plate in the trench is to the substrate, the shorter the length of the field plate in the direction parallel to the substrate, and the thicker the dielectric layer between the field plate and the drift region; In the direction of the substrate, the farther the field plate in the trench is from the substrate, the longer the length of the field plate in the direction parallel to the substrate, and the thinner the dielectric layer between the field plate and the drift region. However, when the multi-step MOSFET structure is fabricated, multiple field plate alignments are required to maintain the symmetry of the stepped dielectric layer, and the fabrication process is complicated.

SUMMARY OF THE INVENTION

Embodiments of the present application provide a trench MOSFET transistor and a manufacturing method thereof, which can ensure uniform electric field distribution in the trench MOSFET transistor and simplify the manufacturing process.

In a first aspect, an embodiment of the present application provides a trench MOSFET transistor, including:

a substrate of a first doping type, the substrate comprising a first surface on which an epitaxial layer of the first doping type is disposed;

a well region of the second doping type disposed within the epitaxial layer;

a gate trench structure disposed in the well region;

The gate trench structure includes:

a gate disposed on the side away from the first surface;

a plurality of mutually insulated first field plates disposed between the gate and the bottom of the gate trench structure, each of the first field plates having the same length in a direction parallel to the first surface ; Insulation between the gate and the first field plate; in the direction perpendicular to the first surface, the distance between two adjacent first field plates is determined by the thickness of each of the first field plates Sure;

The second doping type is opposite to the first doping type.

In some optional embodiments, in a direction perpendicular to the first surface and from the gate to the bottom of the gate trench structure, each of the first field plates has the same thickness, And the distance between two adjacent first field plates increases sequentially.

In some optional embodiments, in a direction perpendicular to the first surface and from the gate to the bottom of the gate trench structure, between two adjacent first field plates The thicknesses of the first field plates decrease sequentially, and the distance between two adjacent first field plates is equal.

In some optional embodiments, the trench MOSFET transistor further comprises:

At least one second field plate is disposed in the gate trench structure, the second field plate is connected to each of the first field plates.

In some optional implementations, the second field plate is connected to a center point of each of the first field plates, and the center point is a plane of each of the first field plates perpendicular to the first surface The center point of the section graphic on the .

In some optional embodiments, on a plane perpendicular to the first surface, the cross-sectional shape of the first field plate is rectangular.

In some optional embodiments, the material of the first field plate is polysilicon.

In some optional implementations, the trench MOSFET transistor further includes:

A doping region of the first doping type disposed in the well region and in contact with the gate trench structure.

In some optional embodiments, the substrate further includes a second surface opposite the first surface, the second surface is provided with a drain structure.

In a second aspect, an embodiment of the present application provides a method for fabricating a trench MOSFET transistor, including:

providing a substrate of a first doping type, the substrate comprising a first surface on which an epitaxial layer of the first doping type is disposed;

forming a well region of the second doping type on a surface of the epitaxial layer remote from the first surface;

forming a trench structure in the epitaxial layer;

forming a first gate oxide layer in the trench structure;

forming a first field plate on the first gate oxide layer, forming a second gate oxide layer on the first field plate, until all of the first field plate is formed within the trench structure, and The second gate oxide layer is formed on the last one of the first field plates; in the direction parallel to the first surface, each of the first field plates has the same length; each of the first field plates has the same length; are insulated from each other, and the gate is insulated from the first field plate; in the direction perpendicular to the first surface, the distance between two adjacent first field plates is determined by each of the first field plates. The thickness of the plate is determined;

A gate electrode and an isolation dielectric layer are formed on the second gate oxide layer to form a gate trench structure.

A trench-type MOSFET transistor provided by an embodiment of the present application includes: a well region built in an epitaxial layer and a gate trench structure built in the well region, and the gate trench structure includes a gate electrode and a gate trench structure. For the plurality of first field plates between the bottoms of the trench structures, in the direction perpendicular to the first surface, the distance between two adjacent first field plates is determined by the thickness of each first field plate. That is to say, the distance between two adjacent field plates is determined according to the thickness of each first field plate. Using the same thickness of each first field plate, the charge compensation effect (the principle of charge balance) increases with the two adjacent first field plates. The distance between the field plates increases and decreases in turn, the distance between two adjacent first field plates is the same, and the charge compensation effect decreases in turn as the thickness between two adjacent first field plates decreases in turn, and then According to the thickness of each first field plate and the distance between two adjacent field plates, different degrees of charge compensation are performed on the drift regions on both sides of the gate trench structure, so that the drift regions on both sides of the gate trench structure are The vertical electric field (ie, the electric field in the direction perpendicular to the first surface) forms a rectangular distribution, and the widening of the depletion region can greatly improve the withstand voltage efficiency of the trench MOSFET device. In the direction parallel to the first surface, each first field plate has the same length. Therefore, during the fabrication of trench MOSFET transistors, multiple field plate alignments are not required to maintain the symmetry of the stepped dielectric layer, simplifying manufacturing process.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present application more clearly, the following briefly introduces the accompanying drawings that need to be used in the embodiments of the present application. For those of ordinary skill in the art, without creative work, the Additional drawings can be obtained from these drawings.

1 is a schematic structural diagram of an embodiment of a trench MOSFET transistor provided by the present application;

2 is another schematic structural diagram of an embodiment of a trench MOSFET transistor provided by the present application;

3 is another structural schematic diagram of an embodiment of a trench MOSFET transistor provided by the present application;

4 is another structural schematic diagram of an embodiment of a trench MOSFET transistor provided by the present application;

5 is a schematic flowchart of an embodiment of a method for manufacturing a trench MOSFET transistor provided by the present application;

6 is a schematic cross-sectional structure diagram of a substrate provided by the present application;

7 is a schematic cross-sectional structure diagram of forming a well region provided by the present application;

8 is a schematic cross-sectional structure diagram of forming a doped region provided by the present application;

9 is a schematic cross-sectional structure diagram of forming a trench structure provided by the present application;

10 is a schematic cross-sectional structure diagram of forming a first gate oxide layer provided by the present application;

11 is a schematic cross-sectional structure diagram of forming a first field plate provided by the present application;

12 is a schematic cross-sectional structure diagram of forming a second gate oxide layer provided by the present application;

13 is a schematic cross-sectional structure diagram of forming all field plates and all second gate oxide layers provided by the present application;

FIG. 14 is a schematic cross-sectional structure diagram of forming a gate trench structure provided by the present application.

Description of reference numbers:

1. Substrate; 11. First surface; 12. Second surface.

2. Epitaxial layer.

3. Well area.

4. Gate trench structure; 41, gate; 42, first field plate; 43, second field plate; 44, trench structure; 45, first gate oxide layer; 46, second gate oxide layer ; 47, isolation dielectric layer.

5. Doping area.

6. Drain structure.

7. Source structure.

Detailed ways

The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application more clear, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, but not to limit the present application. It will be apparent to those skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present application by illustrating examples of the present application.

It should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any relationship between these entities or operations. any such actual relationship or sequence exists. Moreover, the terms "comprising", "comprising" or any other variation thereof are intended to encompass a non-exclusive inclusion such that a process, method, article or device that includes a list of elements includes not only those elements, but also includes not explicitly listed or other elements inherent to such a process, method, article or apparatus. Without further limitation, an element defined by the phrase "comprises" does not preclude the presence of additional identical elements in a process, method, article, or device that includes the element.

FIG. 1 shows a schematic structural diagram of an embodiment of a trench MOSFET transistor provided by an embodiment of the present application.

As shown in FIG. 1 , the trench MOSFET transistor provided by the embodiment of the present application may include:

A substrate 1 of a first doping type, the substrate 1 includes a first surface 11, and an epitaxial layer 2 of a first doping type is disposed on the first surface 11;

a well region 3 of the second doping type disposed in the epitaxial layer 2;

a gate trench structure 4 disposed in the well region 3;

The gate trench structure 4 includes:

the gate electrode 41 arranged on the side away from the first surface 11;

a plurality of mutually insulated first field plates 42 disposed between the gate electrode 41 and the bottom of the gate trench structure 4, in a direction parallel to the first surface 11, each of the first field plates 42 has the same length; The gate 41 is insulated from the first field plate 42; in the direction perpendicular to the first surface 11, the distance between two adjacent first field plates 42 is determined by the thickness of each first field plate 42;

The second doping type is opposite to the first doping type.

A trench-type MOSFET transistor provided by an embodiment of the present application includes: a well region built in an epitaxial layer and a gate trench structure built in the well region, and the gate trench structure includes a gate electrode and a gate trench structure. For the plurality of first field plates between the bottoms of the trench structures, in the direction perpendicular to the first surface, the distance between two adjacent first field plates is determined by the thickness of each first field plate. That is to say, the distance between two adjacent field plates is determined according to the thickness of each first field plate. Using the same thickness of each first field plate, the charge compensation effect (the principle of charge balance) increases with the two adjacent first field plates. The distance between the field plates increases and decreases in turn, the distance between two adjacent first field plates is the same, and the charge compensation effect decreases in turn as the thickness between two adjacent first field plates decreases in turn, and then According to the thickness of each first field plate and the distance between two adjacent field plates, different degrees of charge compensation are performed on the drift regions on both sides of the gate trench structure, so that the drift regions on both sides of the gate trench structure are The vertical electric field (ie, the electric field in the direction perpendicular to the first surface) forms a rectangular distribution, and the widening of the depletion region can greatly improve the withstand voltage efficiency of the trench MOSFET device. In the direction parallel to the first surface, each first field plate has the same length. Therefore, during the fabrication of trench MOSFET transistors, multiple field plate alignments are not required to maintain the symmetry of the stepped dielectric layer, simplifying manufacturing process.

In this embodiment, the first doping type may be N-type, and the second doping type may be P-type. The substrate 1 may be a silicon carbide substrate. The substrate 1 of the first doping type can be an N-type substrate; the epitaxial layer 2 of the first doping type can be an N-type epitaxial layer; the well region 3 of the second doping type can be a P-type well region .

Optionally, a second gate oxide layer 46 may be disposed between two adjacent first field plates 42, so that a plurality of first field plates between the gate 41 and the bottom of the gate trench structure 4 42 are insulated from each other. Correspondingly, a second gate oxide layer 46 may be disposed between the gate electrode 41 and the first field plate 42 to insulate the gate electrode 41 from the first field plate 42 .

The material of the second gate oxide layer 46 may be silicon dioxide (SiO ₂ ), commonly known as silicon oxide.

The second doping type is opposite to the first doping type, it can be understood that the first doping type can be one of N-type or P-type, and the second doping type can be the other of N-type or P-type .

By arranging the first field plate 42 in the gate trench structure 4, since the potential of the first field plate 42 is set to a low potential, in the reverse bias state of the drain, the first field plate 42 has sufficient The charge can be coupled with the drift region. According to the principle of charge balance, the drift region corresponding to the first field plate 42 will couple and induce a depletion region, or even be completely depleted. The net charge in the drift region is zero, and the longitudinal electric field distribution of the trench MSOFET transistor It will present a rectangular distribution similar to a super junction device, thus improving the withstand voltage of the trench MOSFET transistor device, or keeping the device withstand voltage unchanged while increasing the doping concentration of the epitaxial layer 2, reducing the trench MOSFET transistor. On-resistance of the device.

In some optional embodiments, the substrate 1 may further include a second surface 12 opposite to the first surface 11 , and the second surface 12 is provided with the drain structure 6 .

As shown in FIGS. 1 and 2 , in some optional embodiments, on a plane perpendicular to the first surface 11 , the cross-sectional shape of the first field plate 42 is a rectangle or an inverted “V” shape. FIG. 1 shows a schematic structural diagram of a rectangular cross-sectional shape of the first field plate 42 on a plane perpendicular to the first surface 11 , and FIG. 2 shows a plane perpendicular to the first surface 11 of the first field plate 42 . The cross-sectional shape of 42 is a schematic structural diagram of an inverted "V" shape.

Compared with the first field plate 42 with a rectangular cross-sectional shape, the first field plate 42 with an inverted "V" cross-sectional shape is perpendicular to the first surface 11 , the charge compensation effect on the drift region is more linear, and the electric field distribution is more uniform.

In this embodiment, the cross-sectional shape of the first field plate 42 on a plane perpendicular to the first surface 11 is a rectangle or an inverted “V” shape as an example. The cross-sectional shape of the field plate 42 can be set according to the actual situation, which is not limited herein.

As shown in FIGS. 1 and 3 , in some optional embodiments, each first field plate 42 is perpendicular to the first surface 11 and in a direction from the gate 41 to the bottom of the gate trench structure 4 . The thicknesses of the first field plates 42 are the same, and the distance between two adjacent first field plates 42 increases sequentially.

The direction perpendicular to the first surface 11 and from the gate 41 to the bottom of the gate trench structure 4 can be understood as the X direction shown in FIGS. 1 and 3 .

Along the X direction, and the closer to the first surface 11, the greater the distance between two adjacent first field plates 42, the sparser the distribution density of the first field plates 42, and the weaker the charge compensation effect; along the X direction, and The farther away from the first surface 11, the smaller the distance between two adjacent first field plates 42, the denser the distribution density of the first field plates 42, and the stronger the charge compensation effect. Therefore, the side of the gate trench structure 4 drifts. The depletion of the region gradually increases from the bottom of the gate trench structure 4 to the top of the gate trench structure 4, so that the longitudinal electric field of the drift region on both sides of the gate trench structure 4 forms a rectangular distribution, ensuring that the trench MOSFET transistor is The electric field inside is evenly distributed.

Optionally, in the direction perpendicular to the first surface 11 and from the gate 41 to the bottom of the gate trench structure 4 , the thickness of each first field plate 42 is the same, and two adjacent first field plates are The distances between 42 increase sequentially in an arithmetic progression, which can make the vertical electric field of the drift region on both sides of the gate trench structure 4 form a rectangular distribution, and ensure that the electric field in the trench MOSFET transistor is uniformly distributed.

As shown in FIG. 2 and FIG. 4 , in some optional embodiments, in the direction perpendicular to the first surface 11 and from the gate 41 to the bottom of the gate trench structure 4 , two adjacent first The thicknesses between the field plates 42 decrease in sequence, and the distances between two adjacent first field plates 42 are equal.

The distance between two adjacent first field plates 42 is the same, and the depletion effects of the drift regions corresponding to the first field plates 42 with different thicknesses are also different. Specifically, along the X direction, and the closer to the first surface 11, the thinner the thickness of the first field plate 42, which is equivalent to the sparser the distribution density of the first field plate 42, and the weaker the charge compensation effect; along the X direction, the more Away from the first surface 11 , the thicker the thickness of the first field plate 42 is, the denser the distribution density of the first field plate 42 is, and the stronger the charge compensation effect is. Therefore, the depletion of the drift region on the side of the gate trench structure 4 decreases from From the bottom of the gate trench structure 4 to the top of the gate trench structure 4 is gradually strengthened, so that the vertical electric field of the drift region on both sides of the gate trench structure 4 forms a rectangular distribution, ensuring that the electric field in the trench MOSFET transistor is uniformly distributed .

Optionally, in the direction perpendicular to the first surface 11 and from the gate 41 to the bottom of the gate trench structure 4 , the thicknesses between two adjacent first field plates 42 decrease sequentially in an arithmetic progression. In addition, the distances between the two adjacent first field plates 42 are equal, so that the vertical electric field of the drift region on both sides of the gate trench structure 4 can form a rectangular distribution, and the electric field in the trench MOSFET transistor can be uniformly distributed.

As shown in FIG. 3 and FIG. 4 , in some optional embodiments, the trench MOSFET transistor may further include:

At least one second field plate 43 is disposed in the gate trench structure 4 , and the second field plate 43 is connected to each of the first field plates 42 .

In this embodiment, both the material of the first field plate 42 and the material of the second field plate 43 may be polysilicon.

In this embodiment, by arranging at least one second field plate 43 connected to each of the first field plates 42 in the gate trench structure 4 , the potential between each of the first field plates 42 can be kept equal.

In this embodiment, one second field plate 43 is provided in the gate trench structure 4 as an example. In actual implementation, the number of the second field plates 43 in the gate trench structure 4 can be set according to actual conditions. For example, the number of the second field plates 43 is the same as that of the first field plates 42 , each of the first field plates 42 is respectively connected to a different second field plate 43 , and each of the second field plates 43 is connected to each other.

In some optional embodiments, the second field plate 43 may be connected to the center point of each first field plate 42 , and the center point is the cross-sectional pattern of each first field plate 42 on a plane perpendicular to the first surface 11 . center point.

In this embodiment, the second field plate 43 is connected to the center point of each first field plate 42, so that on a plane perpendicular to the first surface 11, the first field plate 42 is axisymmetric with respect to the second field plate 43, The manufacturing process can be simplified.

In other optional embodiments, through holes may be provided on the periphery of the chip to realize electrical connection between each of the first field plates 42, and a short-circuit connection is formed with the source structure 7 or with the metal of the gate 41, so as to achieve Equipotentials between each of the first field plates 42 are all low potentials when the device blocks high voltages.

In some optional embodiments, the trench MOSFET transistor, further comprising:

A doping region 5 of the first doping type is disposed in the well region 3 and in contact with the gate trench structure 4 .

The doping region 5 of the first doping type may be an N-type doping region.

Based on the trench MOSFET transistor provided by the above embodiments, the present application also provides a manufacturing method of the trench MOSFET transistor. A method of manufacturing a trench MOSFET transistor will be described below.

It should be noted that in this embodiment, the first doping type is N-type and the second doping type is P-type as an example. However, in actual implementation, the substrate 1 is not limited to the N-type, but may also be of the P-type. When the substrate 1 is P-type, correspondingly, the conductivity types of the structures such as the epitaxial layer 2 , the well region 3 and the doped region 5 also change.

FIG. 5 shows a schematic flowchart of an embodiment of a method for fabricating a trench MOSFET transistor provided by the present application.

As shown in FIG. 5 , the trench MOSFET transistor fabrication method may include S501 to S506 . Please refer to FIGS. 6 to 14 together. FIGS. 6 to 14 are schematic cross-sectional structural diagrams corresponding to a series of processes of the trench MOSFET transistor fabrication method provided by the present application.

S501 , providing a substrate 1 of a first doping type, the substrate 1 includes a first surface 11 , and an epitaxial layer 2 of a first doping type is disposed on the first surface 11 .

In this embodiment, the substrate 1 of the first doping type is an N-type substrate.

As shown in FIG. 6 , in some optional embodiments, an N-type substrate is provided first, and then epitaxy is performed on the substrate 1 to form an N-type epitaxial layer.

S502 , forming a well region 3 of the second doping type on the surface of the epitaxial layer 2 away from the first surface 11 .

In this embodiment, the well region 3 of the second doping type is a P-type well region.

As shown in FIG. 7 , forming the well region 3 of the second doping type on the surface of the epitaxial layer 2 away from the first surface 11 may include:

Ion doping of the second doping type is performed on the surface of the epitaxial layer 2 away from the first surface 11 to form the well region 3 of the second doping type.

As shown in FIG. 8 , in some optional embodiments, after the well region 3 of the second doping type is formed on the surface of the epitaxial layer 2 away from the first surface 11, it may further include:

Within the well region 3 , a doping region 5 of the first doping type is formed in contact with the gate trench structure 4 .

S503 , forming the trench structure 44 in the epitaxial layer 2 .

As shown in FIG. 9 , forming a trench structure 44 in the epitaxial layer 2 may include:

The trench etching is performed downward on the surface of the epitaxial layer 2 away from the first surface 11 , so that the trench structure 44 is formed in the epitaxial layer 2 .

Specifically, trench etching may be performed downward on the surface of the epitaxial layer 2 away from the first surface 11 by using a mask, so that the trench structure 44 is formed in the epitaxial layer 2 .

S504 , forming a first gate oxide layer 45 in the trench structure 44 .

As shown in FIG. 10 , forming a first gate oxide layer 45 in the trench structure 44 may include:

The upper surface of the trench structure 44 is oxidized to form a first gate oxide layer 45 within the trench structure 44 .

S505 , forming the first field plate 42 on the first gate oxide layer 45 , forming the second gate oxide layer 46 on the first field plate 42 , until all the first field plates 42 are formed in the trench structure 44 , and A second gate oxide layer 46 is formed on the last first field plate 42; in the direction parallel to the first surface 11, each first field plate 42 has the same length; each first field plate 42 is insulated from each other , the gate 41 is insulated from the first field plate 42 ; in the direction perpendicular to the first surface 11 , the distance between two adjacent first field plates 42 is determined by the thickness of each first field plate 42 .

In this embodiment, a manufacturing process in which the cross-sectional shape of the first field plate 42 is rectangular on a plane perpendicular to the first surface 11 is taken as an example. As shown in FIG. 11, a layer of polysilicon is deposited on the first gate oxide layer 45, and photolithography is performed on the layer of polysilicon to form a first field plate 42; as shown in FIG. 12, on the first field plate 42 A second gate oxide layer 46 is formed by depositing on the upper surface of the trench structure 44; the foregoing steps are repeated until all the first field plates 42 are formed in the trench structure 44, and a second gate is formed on the last first field plate 42 An extremely oxide layer 46 . All of the first field plates 42 formed in the trench structure 44 and a second gate oxide layer 46 formed on the last first field plate 42 are shown in FIG. 13 .

The material of the first gate oxide layer 45 and the material of the second gate oxide layer 46 may both be polysilicon.

On the plane perpendicular to the first surface 11 , the cross-sectional shape of the first field plate 42 is an inverted "V" shape in the manufacturing process and on the plane perpendicular to the first surface 11 , the cross-sectional shape of the first field plate 42 is a rectangle. The manufacturing process is similar, the only difference is that after a layer of polysilicon is deposited on the first gate oxide layer 45, an inverted "V"-shaped field plate is formed by utilizing the different etching rates of different crystal phases of the polysilicon. The manufacturing process that the cross-sectional shape of the first field plate 42 is an inverted "V" shape will not be repeated here.

S506 , forming the gate electrode 41 and the isolation dielectric layer 47 on the second gate oxide layer 46 to form the gate trench structure 4 .

As shown in FIG. 14 , a gate electrode 41 is formed on the second gate oxide layer 46 , and the upper surface of the gate electrode 41 is oxidized to form an isolation dielectric layer 47 to form the gate trench structure 4 .

In some optional embodiments, in a direction perpendicular to the first surface 11 and from the gate 41 to the bottom of the gate trench structure 4 , the thicknesses of each first field plate 42 are the same, and two adjacent ones of the first field plates 42 have the same thickness. The distances between the first field plates 42 are sequentially increased.

In some optional embodiments, in a direction perpendicular to the first surface 11 and from the gate 41 to the bottom of the gate trench structure 4 , the thickness between two adjacent first field plates 42 decreases sequentially , and the distance between two adjacent first field plates 42 is equal.

In some alternative embodiments, the first field plate 42 is formed on the first gate oxide layer 45 and the second gate oxide layer 46 is formed on the first field plate 42 until all the trench structures 44 are formed. The first field plate 42, and forming the second gate oxide layer 46 on the last first field plate 42, may also include:

A first field plate 42 and a portion of the second field plate 43 are formed on the first gate oxide layer 45, and a second gate oxide layer 46 is formed on the first field plate 42 and a portion of the second field plate 43 until All the first field plates 42 and the entire second field plate 43 are formed in the trench structure 44 , and the second gate oxide layer 46 is formed on the last first field plate 42 .

In some optional embodiments, the second field plate 43 is connected to the center point of each first field plate 42 , and the center point is the center of the cross-sectional graph of each first field plate 42 on a plane perpendicular to the first surface 11 . point.

In some optional embodiments, on a plane perpendicular to the first surface 11 , the cross-sectional shape of the first field plate 42 is a rectangle or an inverted "V" shape.

In some optional embodiments, the material of the first field plate 42 is polysilicon.

In some optional embodiments, the substrate 1 further includes a second surface 12 opposite to the first surface 11 , and a gate electrode 41 and an isolation dielectric layer 47 are formed on the second gate oxide layer 46 to form a gate trench After the slot structure 4, it can also include:

The drain structure 6 is formed on the second surface 12 .

In some optional implementation manners, after forming the gate electrode 41 and the isolation dielectric layer 47 on the second gate oxide layer 46 to form the gate trench structure 4, it may further include:

A source structure 7 is formed on the side of the well region 3 away from the first surface 11 , and the source structure 7 is in contact with the isolation dielectric layer 47 , the doped region 5 and the well region 3 .

Regarding the method for fabricating the trench MOSFET transistor in the above-mentioned embodiments, various structures and beneficial effects have been described in detail in the embodiments of the trench MOSFET transistor, and will not be described in detail here.

The above are only specific implementations of the present application. Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above-described systems, modules and units may refer to the foregoing method embodiments. The corresponding process in , will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should all cover within the scope of protection of this application.

Claims (10)

1. A trench MOSFET transistor, comprising:

the substrate comprises a first surface, wherein an epitaxial layer of a first doping type is arranged on the first surface;

the well region of the second doping type is arranged in the epitaxial layer;

the grid groove structure is arranged in the well region;

the gate trench structure includes:

the grid electrode is arranged on one side far away from the first surface;

a plurality of mutually insulated first field plates disposed between the gate and the bottom of the gate trench structure, each of the first field plates having the same length in a direction parallel to the first surface; the gate is insulated from the first field plate; in the direction perpendicular to the first surface, the distance between two adjacent first field plates is determined by the thickness of each first field plate;

the second doping type is opposite to the first doping type.

2. The trench MOSFET transistor of claim 1, wherein each of the first field plates has a same thickness in a direction perpendicular to the first surface and from the gate to a bottom of the gate trench structure, and wherein distances between two adjacent first field plates increase sequentially.

3. The trench MOSFET transistor of claim 1, wherein the thickness between two adjacent first field plates decreases in a direction perpendicular to the first surface and from the gate to the bottom of the gate trench structure, and the distance between two adjacent first field plates is equal.

4. The trench MOSFET transistor of claim 1, further comprising:

at least one second field plate disposed within the gate trench structure, the second field plate being connected to each of the first field plates.

5. The trench MOSFET transistor of claim 4, wherein the second field plate is connected to a center point of each of the first field plates, the center point being a center point of a cross-sectional pattern of each of the first field plates in a plane perpendicular to the first surface.

6. The trench MOSFET transistor according to any one of claims 1 to 5, wherein the first field plate has a rectangular cross-sectional shape in a plane perpendicular to the first surface.

7. The trench MOSFET transistor of any one of claims 1-5, wherein the material of the first field plate is polysilicon.

8. The trench MOSFET transistor according to any of claims 1 to 5, further comprising:

and the doped region of the first doping type is arranged in the well region and is in contact with the grid groove structure.

9. The trench MOSFET transistor according to any one of claims 1 to 5, wherein the substrate further comprises a second surface opposite the first surface, the second surface being provided with a drain structure.

10. A method of fabricating a trench MOSFET transistor, comprising:

providing a substrate of a first doping type, wherein the substrate comprises a first surface, and an epitaxial layer of the first doping type is arranged on the first surface;

forming a well region of a second doping type on the surface of the epitaxial layer far away from the first surface;

forming a trench structure in the epitaxial layer;

forming a first grid electrode oxidation layer in the groove structure;

forming a first field plate on the first gate oxide layer, forming a second gate oxide layer on the first field plate until all of the first field plates are formed in the trench structure, and forming the second gate oxide layer on the last first field plate; each of the first field plates has the same length in a direction parallel to the first surface; the first field plates are insulated from each other, and the gate is insulated from the first field plates; in the direction perpendicular to the first surface, the distance between two adjacent first field plates is determined by the thickness of each first field plate;

and forming a grid and an isolation medium layer on the second grid oxide layer to form a grid groove structure.

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