CN115220388A - Control circuit for realizing hard destruction of solid state disk based on low current input - Google Patents

Abstract

The application provides a control circuit for realizing hard destruction of a solid state disk based on low current input, an MCU control chip respectively controls 16 paths of solid state disks to work through 16 paths of switch circuits SW01-SW16, and the control circuit is characterized in that an LT86 series DC-DC power supply conversion chip of ADI Addeno is adopted to control V/2A of external input power supplies (24 to 28), small current provided from the outside is converted into constant voltage and constant current output of 8V/6A through DC-DC conversion, and the constant voltage and constant current are output to the SW01-SW16 solid state disk through the switch circuit to be destroyed.

Description

Control circuit for realizing hard destruction of solid state disk based on low current input

Technical Field

The application belongs to a control circuit for hard destruction of a solid state disk, and particularly relates to a control circuit for realizing hard destruction of a NandFlash solid state disk based on low current input.

Background

A Solid State Drive (SSD) is a hard disk made of an array of Solid State electronic memory chips, and the SSD is composed of a control unit and a memory unit (FLASH chip, DRAM chip), etc. Electronic devices such as computers, servers, and notebooks use hard disks to store data. The solid state disk serving as a data carrier has one of important application points that rapid deletion or destruction of data in various emergency environments is achieved while cracking is prevented by various encryption means due to confidentiality requirements in application industries such as national defense, industry and scientific research.

At present, the destruction modes are mainly divided into two types, namely logic destruction and physical destruction. The logical destruction, generally called soft destruction, is to erase the original data on the storage medium by sending a command without damaging the physical chip, and the data in the hard disk is not destroyed in this way, but the hard disk can be reused. The advantage of logic destruction is that the original chip can be used continuously, and the disadvantage is that the erase time is positively correlated with the storage capacity, and when the capacity is larger, the duration is longer, usually in the order of seconds or even minutes. Physical destruction or hard destruction directly damages the physical chip, and fundamentally ensures that the original data cannot be recovered. Physical destruction generally takes three forms, electrical, chemical and mechanical. The electrical destruction is common in the emergency destruction, and the specific method is that through the control of a trigger switch, a system supplies high voltage and high current to be applied to particles of the memory chip, and the particles of the memory chip are physically burnt out, so that data in the particles can be destroyed and cannot be recovered.

The mode of high voltage heavy current hard destruction, through high voltage breakdown Nand chip inner circuit earlier, exert heavy current again and carry out the heat and burn out, burn out Nand inner circuit completely, carry out the physics destruction from inside, make hard disk data unable recovery. Fig. 1 is a control principle framework diagram of an existing high-voltage large-current hard destruction mode, a destruction circuit directly applies high-voltage large current to a hard disk through a switch circuit to perform breakdown, but the high-voltage large current of a destruction power supply may generate overcurrent or overvoltage influence on superior/upstream equipment of the hard disk, and overall safety is affected.

Disclosure of Invention

The application provides a control circuit for realizing the hard destruction of a NandFlash solid state disk based on low current input, which converts small current provided outside the solid state disk into large current to destroy an NAND internal circuit, so that the NAND internal circuit is in a low impedance short circuit state, and the purpose of thoroughly destroying the NAND internal circuit is achieved.

Specifically, the control circuit for realizing the hard destruction of the NandFlash solid state disk based on low current input is characterized in that an ADI Addenno LT86 series DC-DC power supply conversion chip is adopted to control an external input power supply (24 to 28) V/2A, small current provided from the outside is converted into constant voltage and constant current output of 8V/6A through DC-DC conversion, and the constant voltage and constant current is output to the SW01-SW16 solid state disk through a switch circuit for destruction.

Further, pin1: SYNC, external clock synchronous input, pin grounded, low ripple burst mode operation under low output load.

Further, the source conversion chip Pin2: TR/SS, output tracking and soft start pins, control the slope of the output voltage during start-up.

Further, pin3: RT for setting the switching frequency; and (3) Pin4: EN/UV, enable pin, turn off when pin is low, turn on when pin is high.

Further, pin5-7 of the power conversion chip: VIN, an external power supply input pin and the supporting voltage of 3.4V-42V; pin8-14: GND, power switch ground, connects pins 8-14 together through ground.

Further, the power conversion chip Pin15-19: SW, internal power switch circuit, output connected to inductor L3 and boost capacitor C580, outputs a stable voltage current.

Further, the power conversion chip Pin20: VBST for supplying a driving voltage; a Pin21: INTVcc, which supplies voltage to the internal power driver and control circuit; a Pin22: BIAS connected to the output to output 3.3V or more voltage.

Further, pin23: PGOOD, open drain output pin of internal comparator, keep low level; and a Pin24: the FeedBack pin of the output voltage is used for monitoring the output voltage; pin25-27: ISP/ISN/IMON, output current feedback pin for monitoring output current.

Further, pin28: the ICTRL is a current adjusting pin and is used for adjusting the magnitude of output current according to the feedback of the ISP/ISN/IMON; and a Pin29: GND, power switch ground circuit.

Further, a control method of a control circuit for realizing the hard destruction of the NandFlash solid state disk based on low current input comprises the following steps:

the MCU starts to enter a destruction preparation stage when monitoring that the destruction voltage lasts for 50ms;

a destruction preparation stage: the PCIE _12V power supply is closed, and whether the destruction voltage lasts for more than 200ms or not is continuously monitored;

if the destruction voltage lasts for more than 200ms, starting to enter a destruction implementation stage;

if the destruction voltage does not last for 200ms, a PCIE _12V power supply is turned on, and the monitoring stage is returned;

a destroying implementation stage: SW01-SW16 are 16 paths of switches in total to control GPIO (high level is effective, and destruction is executed);

the 16 paths of GPIO are output at intervals of 10ms, each output of each path of GPIO is 160ms waveform, wherein the high level width is 10ms, the low level width is 150ms, namely 10ms is opened, and 150ms is closed;

the output is circulated all the time according to a period of 160ms, the GPIO output is ended when the whole destroying process exceeds 2s, and the GPIO output keeps default low level or tri-state; and finishing the destroying process.

The invention has the beneficial effects that: an external input power supply is (24 to 28) V/2A input, and a 8V/6A constant-voltage constant-current solid-state hard disk is output through DC-DC conversion; the hard destruction needs to be thoroughly destroyed by depending on large current; after the destroying process and the destroying are finished, the superior equipment cannot be influenced; the application converts the conventional high-voltage and high-current destroying condition into high-current destroying, and reduces the condition for realizing hard destroying; the application scene of the hard destruction requirement of the solid state disk is expanded.

Drawings

In order to more clearly illustrate the embodiments of the present application or technical solutions in related arts, the drawings used in the description of the embodiments or prior arts will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

The structures, proportions, and dimensions shown in the drawings and described in the specification are for illustrative purposes only and are not intended to limit the scope of the present disclosure, which is defined by the claims, but rather by the claims, it is understood that these drawings and their equivalents are merely illustrative and not intended to limit the scope of the present disclosure.

Fig. 1 is a frame diagram of the control principle of hard destruction in the prior art;

fig. 2 is a control circuit for hard destruction of a solid state disk according to an embodiment of the present application;

FIG. 3 is a control schematic block diagram of an embodiment of the present application;

fig. 4 is a flowchart of hard destruction of a solid state disk according to an embodiment of the present application.

Detailed Description

Embodiments of the present application will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the application are shown, and in which it is to be understood that the embodiments described are merely illustrative of some, but not all, of the embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The application provides a control circuit for realizing the hard destruction of a NandFlash solid state disk based on low current input, an external input power supply of the destruction control circuit is (24-28) V/2A input, small current provided outside the solid state disk is converted into constant voltage and constant current output of 8V/6A through DC-DC conversion, and a NAND internal circuit is destroyed by large current to enable the interior of the NAND internal circuit to be in a low impedance short circuit state; after the destroying process and the destroying are finished, the superior equipment cannot be influenced.

Referring to fig. 2, in a framework diagram of a destruction control principle of an embodiment of the present application, an MCU control chip controls 16 solid state disks to work through 16 switching circuits SW01 to SW16, an external input power supply of the control circuit is (24 to 28) V/2A input, small current provided from the outside is converted into constant voltage and constant current output of 8V/6A through DC-DC conversion, and the constant voltage and constant current is output to each solid state disk through the switching circuit to be destroyed.

The control circuit for hard destruction of the solid state disk mainly converts a small current provided from the outside into a constant voltage and constant current output of 8V/6A through a DC-DC power conversion chip and a peripheral circuit, and referring to fig. 3, the control circuit for hard destruction of the NandFlash solid state disk based on low current input according to the embodiment of the present application is shown in fig. 3:

the voltage conversion chip adopts an ADI Addeno LT86 series DC-DC power supply conversion chip, the input end of the control circuit provides 24V to 28V voltage, after the ADI LT86 voltage reduction switching regulator is used for adding working voltage, the change of the output end can cause the change of larger current due to the small current change of the input end, the change of the output end is several times to dozens of times larger than the change of the input end, because the built-in current sensing amplifier has monitoring and control functions, the circuit utilizes an electronic component transistor with amplification property to ensure stable voltage and current output.

The control circuit based on the LT86 series DC-DC power conversion chip has the following input and output of each pin:

a ratio of Pin1: SYNC, external clock synchronous input, this pin is grounded, so as to carry out low ripple burst mode operation under low output load;

and (3) Pin2: TR/SS, output tracking and soft start pin, the pin allows users to control the slope of the output voltage in the starting process;

and a Pin3: RT for setting the switching frequency;

and (3) Pin4: EN/UV, enable pin, close when the pin is the low level, open when the pin is the high level;

5-7 of Pin: VIN, an external power supply input pin and the supporting voltage of 3.4V-42V;

pin8-14: GND, a power switch grounding circuit, and pins 8-14 are connected together through the grounding circuit;

15-19 of Pin: SW, internal power switch circuit, the output is connected with inductor L3 and boost capacitor C580, output the stable voltage current;

and a Pin20: VBST for supplying a driving voltage;

a Pin21: INTVcc, which supplies voltage to the internal power driver and control circuit;

a Pin22: BIAS connected to the output to output 3.3V voltage and over;

and a Pin23: PGOOD, open drain output pin of internal comparator, keep low level;

and a Pin24: the FeedBack pin of the output voltage is used for monitoring the output voltage;

pin25-27: ISP/ISN/IMON, output current feedback foot, is used for monitoring the output current;

a Pin28: the ICTRL is an electric current adjusting pin and adjusts the size of output current according to the feedback of the ISP/ISN/IMON;

and a Pin29: GND, power switch ground circuit.

The flow of converting externally provided small current into output 8V/6A constant voltage and constant current, and outputting the constant voltage and constant current to each path of solid state disk for destruction through the switch circuit is shown in the attached figure 4:

the MCU starts to enter a destruction preparation stage when monitoring that the destruction voltage lasts for 50ms;

a destruction preparation stage: the PCIE _12V power supply is closed, and whether the destruction voltage lasts for more than 200ms or not is continuously monitored;

if the destruction voltage lasts for more than 200ms, starting to enter a destruction implementation stage;

if the destruction voltage does not last for 200ms, a PCIE _12V power supply is turned on, and the monitoring stage is returned;

a destroying implementation stage: SW01-SW16 have 16 paths of switches to control GPIO (high level is effective and destruction is executed);

the 16 paths of GPIO are output at intervals of 10ms, each output of each path of GPIO is a 160ms waveform, wherein the high level width is 10ms, and the low level width is 150ms (equivalent to 10ms on and 150ms off);

the destruction signal time of the single-path solid state disk is 10ms, the duty signal time is 150ms, the time sequence sequentially indicates that the first switch circuit signal is high level, large current is input to destroy the first path of solid state disk, and the signals of other paths of solid state disks are low level and have no output current; then, for the second 10ms, the signal of the second switch circuit is at a high level, a large current is input to destroy the second path of solid state disk, and the signals of other paths of solid state disks are at a low level and have no output current; analogizing to the 16 th 10ms in turn, wherein the 16 th switching circuit signal is at a high level, a large current is input to destroy the 16 th path of solid state disk, and the signals of other paths of solid state disks are at low levels and have no output current; the first destruction period is 160ms;

the output is circulated all the time according to a period of 160ms, the GPIO output is ended when the whole destroying process exceeds 2s, and the GPIO output keeps default low level or tri-state; and finishing the destroying process.

The embodiments in the present description are described in a progressive manner, or in a parallel manner, or in a combination of a progressive manner and a parallel manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments can be referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.

It should be noted that in the description of the present application, it should be understood that the terms "upper", "lower", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, which are only used for convenience of description and simplification of the description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application. When a component is referred to as being "connected" to another component, it can be directly connected to the other component or intervening components may also be present.

It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in an article or apparatus that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A control circuit for realizing hard destruction of a solid state disk based on low current input is characterized in that an MCU control chip controls 16 paths of solid state disks to work through 16 paths of switch circuits 01-16 respectively, an LT86 series DC-DC power supply conversion chip of sub-Deno controls V/2A of an external input power supply (24-28), small current provided from the outside is converted into constant voltage and constant current output of 8V/6A through DC-DC conversion, and the constant voltage and constant current are output to the switch circuits 01-16 solid state disks for destruction through the switch circuits.

2. The control circuit for realizing hard destruction of the solid state disk based on low current input according to claim 1, wherein a power conversion chip Pin1: SYNC, external clock synchronous input, pin grounded, low ripple burst mode operation under low output load.

3. The control circuit for realizing hard destruction of the solid state disk based on the low current input according to claim 1, wherein a power conversion chip Pin2: TR/SS, output tracking and soft start pins, control the slope of the output voltage during start-up.

4. The control circuit for realizing hard destruction of the solid state disk based on the low current input according to claim 1, wherein a power conversion chip Pin3: RT for setting the switching frequency; and (3) Pin4: EN/UV, enable pin, turn off when pin is low, turn on when pin is high.

5. The control circuit for realizing hard destruction of the solid state disk based on the low current input according to claim 1, wherein a power conversion chip Pin5-7: VIN, an external power supply input pin and the supporting voltage of 3.4V-42V; pin8-14: GND, power switch ground, connects pins 8-14 together through ground.

6. The control circuit for realizing hard destruction of the solid state disk based on the low current input according to claim 1, wherein the power conversion chip has a Pin15-19: the output of the internal power switch circuit is connected with the inductor L3 and the boost capacitor C580, and stable voltage and current are output.

7. The control circuit for realizing hard destruction of the solid state disk based on low current input according to claim 1, wherein a power conversion chip Pin20: VBST for supplying a driving voltage; a Pin21: INTVcc, which supplies voltage to the internal power driver and control circuit; a Pin22: BIAS connected to the output to output 3.3V or more voltage.

8. The control circuit for realizing hard destruction of the solid state disk based on low current input according to claim 1, wherein a Pin23: PGOOD, open drain output pin of internal comparator, keep low level; and a Pin24: a FeedBack pin for output voltage, for monitoring the output voltage; pin25-27: ISP/ISN/IMON, output current feedback pin for monitoring output current.

9. The control circuit for realizing hard destruction of the solid state disk based on the low current input according to claim 1, wherein a Pin28: the ICTRL is a current adjusting pin and is used for adjusting the magnitude of output current according to the feedback of the ISP/ISN/IMON; and a Pin29: GND, power switch ground circuit.

10. The control method of the control circuit for realizing hard destruction of the solid state disk based on low current input according to any one of claims 1 to 9, comprising the following steps:

the MCU starts to enter a destruction preparation stage when monitoring that the destruction voltage lasts for 50ms;

a destruction preparation stage: the PCIE _12V power supply is closed, and whether the destruction voltage lasts for more than 200ms or not is continuously monitored;

if the destruction voltage lasts for more than 200ms, starting to enter a destruction implementation stage;

if the destruction voltage does not last for 200ms, a PCIE _12V power supply is turned on, and the monitoring stage is returned;

a destroying implementation stage: the switching circuits 01 to 16 control GPIO (high level is effective, and destruction is executed); the 16 paths of GPIO are output at intervals of 10ms, each output of each path of GPIO is 160ms waveform, wherein the high level width is 10ms, the low level width is 150ms, namely 10ms is opened, and 150ms is closed;

the output is circulated all the time according to a period of 160ms, the GPIO output is ended when the whole destroying process exceeds 2s, and the GPIO output keeps default low level or tri-state; and finishing the destroying process.

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