CN115237482B

CN115237482B - SOC start-up starting method based on RISC-V

Info

Publication number: CN115237482B
Application number: CN202210966944.9A
Authority: CN
Inventors: 李康; 张琦滨; 刘鹏; 汪争; 韩文燕; 严大卫; 刘杰; 职文豪
Original assignee: Wuxi Advanced Technology Research Institute
Current assignee: Wuxi Advanced Technology Research Institute
Priority date: 2022-08-11
Filing date: 2022-08-11
Publication date: 2025-08-15
Anticipated expiration: 2042-08-11
Also published as: CN115237482A

Abstract

The present invention relates to the field of microelectronics, and more particularly to a RISC-V-based SOC startup method, comprising the following steps: setting a startup mode by setting chip pin levels; storing a ZSBL program in a BootROM and executing the ZSBL program after a chip power-on reset; executing the ZSBL program to connect to an SPI controller and, depending on the startup mode, transfer a FSBL program from an SPI SD card or SPI FLASH to an ITIM; jumping to the ITIM to execute the FSBL program; the FSBL program to configure a PLL frequency increase, cancel a DDR controller reset, perform DDR memory control training, and then transfer a BBL and an OS to the DDR; and jumping to the BBL program and OS program in the DDR to complete system startup. The present invention has the following beneficial effects: using the ITIM to perform the startup process improves the efficiency of SOC startup.

Description

SOC start-up starting method based on RISC-V

Technical Field

The invention relates to the technical field of microelectronics, in particular to an SOC start-up starting method based on RISC-V.

Background

The current SOC power-on process with wider application can be implemented by two different addresses, namely, the external Flash is started to be implemented and the internal ROM is started to be implemented. Different power-up addresses may be selected by the value of the chip pin. When the external Flash starts to execute, the software sets a power-on boot program, carries codes and data in the Flash into the ITCM and the DTCM, and then jumps to the ITCM to start to execute. When the execution starts from ROM, fixed code is stored in ROM, and it jumps directly to ITCM to continue execution. The manner in which execution starts from the internal ROM and then from the ITCM makes sense only when the ITCM is initialized by the debugger during the debug phase. Otherwise, the initialization program is not available in the ITCM, so that the ITCM cannot be normally executed. From the above, ITCM and DTCM are used as instruction memory and data memory, but there are no caches and DDR per se, so the advantages of time-division multiplexing of TCM and Cache switching are not fully exerted. In addition, only two start-up modes of Flash and ROM are supported. The other SOC starting flow includes the PC pointing to the Reset Vector ROM after power-on Reset to determine which start-up starting mode, ZSBL to select where to transfer the FSBL to the L2 LIM according to the pin selection, FSBL to configure the PLL for up-conversion, DDR PLL, PHY and controller, download BBL to DDR Memory, enable the L2 LIM to be configured to the L2 Cache mode, jump to DDR Memory to execute BBL. From the above, although the L2 Cache is multiplexed into LIM as a Memory for startup, the startup efficiency is improved. However, in most single-core SOCs, L2 Cache is not used, so that the scheme cannot be used on a wider SOC. Therefore, it is necessary to study the technology of the SOC start-up to improve the efficiency of the SOC start-up and to provide a richer start-up mode as much as possible.

The applicant has found, through searching, that chinese patent CN102467472a, for example, is the closest prior art to the present application. The BOOT starting device comprises a memory interface module, a DMA bus interface module, a BOOT processing module and a parameter configuration module, wherein the memory interface module is provided with a memory bus interface and is used for being connected with an external memory, the DMA bus interface module is provided with a DMA bus interface and is used for carrying data in the external memory to a storage space corresponding to a target address, the BOOT processing module is respectively connected with the memory interface module and the DMA bus interface module and is used for sending data read-write commands to the external memory through the memory interface module and converting data transmitted by the external memory into data matched with the DMA bus interface module, and the parameter configuration module is used for configuring parameters of the DMA bus interface module, the memory interface module and the BOOT processing module. The starting efficiency of the SOC is improved by adding hardware, new hardware is introduced, the cost of the SOC is improved, and the problem of low starting efficiency of the current SOC can not be solved.

Disclosure of Invention

The technical problem to be solved by the invention is that a high-efficiency start-up starting scheme suitable for a common SOC is lacking at present. The SOC startup starting method based on the RISC-V can improve the startup starting efficiency of the SOC supporting the RISC-V framework.

The technical scheme adopted by the invention is that the SOC start-up starting method based on RISC-V comprises the following steps:

setting a starting mode by setting the pin level of a chip, wherein the starting mode comprises a maintenance start starting mode and a self-guiding start starting mode, an FSBL program, a BBL program and an OS program are stored in SPI SD CARD in the maintenance start starting mode, and the FSBL program, the BBL program and the OS program are stored in SPI FLASH in the self-guiding start starting mode;

storing ZSBL programs in BootRom, and executing ZSBL programs from the BootRom after the chip is powered on and reset;

The ZSBL program execution turns on the SPI controller, and carries the FSBL program to the ITIM from SPI SD CARD or SPI FLASH according to the starting mode;

after the ZSBL program is executed, jumping to an ITIM to execute the FSBL program;

the FSBL program executes the steps of configuring the PLL to raise the frequency, canceling the reset of the DDR controller and performing DDR memory control training, and then carrying BBL and OS from SPI SD CARD or SPI FLASH to DDR;

after the FSBL program is executed, jumping to BBL programs and OS programs in the DDR, and completing the starting of the system.

Preferably, the method for executing ZSBL programs from BootRom comprises the following steps:

after the chip is powered on and reset, the core PC points to the MSEL register of Modelsel ROM and takes the value, the jump is carried out according to the value of the MSEL register, and the value of the MSEL register of Modelsel ROM is determined by a chip pin;

When the MSEL register is 00B, the method is started in a Debug mode, the PC jumps to an interrupt service routine of debugger modules, when the MSEL register is not 00B, the method is started in a BootRom mode, and the PC jumps to a ZSBL program in the BootRom.

Preferably, the ZSBL program specifically performs the following steps:

Carrying the FSBL program from SPI FLASH or SPI SD CARD according to the value selection of the MSEL register, carrying the FSBL program from SPI FLASH to ITIM if the value of the MSEL register is 01B or 11B, and carrying the FSBL program from SPI SD CARD to ITIM if the value of the MSEL register is 10B;

And jumping the PC to the starting address of the FSBL program at the ITIM, and completing the execution of ZSBL programs.

Preferably, the method for configuring the ITIM comprises:

ICache is configured into ITIM mode, which specifically comprises:

opening ITIM items in ICache, wherein the ITIM items in the last row are used for exiting the ITIM mode;

After the chip is powered on and reset, when the operation is written to the ITIM item, the empty item of the ITIM is directly applied for use, and when the operation is written to the ITIM item of the last row, the ITIM mode is exited.

Preferably, the method for carrying the FSBL program to the ITIM comprises:

The row address write operation to the ITIM obtains the allocation of ITIM space at the same time;

sequentially reading FSBL program segments, and starting a sequential write operation from the 0 th row address of the ITIM;

After all FSBL programs are written to ITIM, writing a 0 to the next row of ITIM addresses indicates that ITIM space is released and ITIM mode is exited.

The core-completed FSBL program will read to 0 at the last row of ITIM addresses, then release ITIM space and exit ITIM mode.

Preferably, the FSBL program specifically performs the following steps:

configuring PLL parameters, which are stored in the SCU part and enable up-conversion;

After the inquiry PLL locks, the core is switched to the target frequency;

Resetting the device, and resetting the DDR;

performing DDR memory control training;

Loading BBL program and OS program from SPI FLASH or SPI SD CARD into DDR, and taking the 0x8000_0000 address of DDR as starting address;

the PC jumps to 0x8000_0000 to execute BBL program and OS program to complete system start.

Preferably, the PLL includes a Core PLL and a DDR PLL, and after both the Core PLL and the DDR PLL are queried to lock, the Core is switched to the target frequency.

The method has the beneficial effects that the start-up starting flow is carried out by means of the ITIM, the start-up starting efficiency of the SOC is improved, the requirement on SOC hardware is low, the start-up starting of the SOC is widely applicable, various start-up starting modes are provided, and the start-up starting of different purposes of the SOC is facilitated.

Other features and advantages of the present invention will be disclosed in the following detailed description of the invention and the accompanying drawings.

Drawings

The invention is further described with reference to the accompanying drawings:

FIG. 1 is a flow chart of a start-up method of SOC based on RISC-V according to an embodiment of the present invention.

Fig. 2 is a flowchart of a method for executing ZSBL a program from BootRom according to an embodiment of the present invention.

Fig. 3 is a flowchart illustrating a program execution method according to an embodiment ZSBL of the present invention.

Fig. 4 is a schematic flow chart of an ITIM method for configuring an embodiment of the present invention.

Fig. 5 is a flowchart illustrating an embodiment of a method for transferring an FSBL program to an ITIM.

Fig. 6 is a flowchart of an FSBL program execution method according to an embodiment of the present invention.

Detailed Description

The technical solutions of the embodiments of the present invention will be explained and illustrated below with reference to the drawings of the embodiments of the present invention, but the following embodiments are only preferred embodiments of the present invention, and not all embodiments. Based on the examples in the implementation manner, other examples obtained by a person skilled in the art without making creative efforts fall within the protection scope of the present invention.

In the following description, directional or positional relationships such as the terms "inner", "outer", "upper", "lower", "left", "right", etc., are presented for convenience in describing the embodiments and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the invention.

Noun interpretation ZSBL (Zero Stage Bootloader), initial phase loader. FSBL (FIRST STAGE boot loader), first phase loader. SOC (system on chip), system on chip. RISC-V is an open Instruction Set Architecture (ISA) built based on Reduced Instruction Set Computing (RISC) principles, with V denoted as the fifth generation of RISC. RISC (Reduced Instruction Set Computer RISC) reduced instruction set computers. An ITIM (Instruction TIGHTLY INTEGRATED Memory) Instruction is tightly coupled to Memory, iCache (Instruction Cache), instruction cache. PLL (Phase-Locked Loops), phase-Locked loop or frequency multiplier. OS (Operating System) operating system. BBL (bios boot loader) second stage boot procedure.

Referring to fig. 1, the SOC start-up starting method based on RISC-V includes the following steps:

Step A01) setting a starting mode by setting the pin level of a chip, wherein the starting mode comprises a maintenance starting mode and a self-guiding starting mode, FSBL programs, BBL programs and OS programs are stored in SPI SD CARD in the maintenance starting mode, and FSBL programs, BBL programs and OS programs are stored in SPI FLASH in the self-guiding starting mode;

step A02) storing ZSBL programs in BootRom, and executing ZSBL programs from BootRom after the chip is powered on and reset;

step A03) ZSBL program execution turns on the SPI controller, and carries the FSBL program to the ITIM from SPI SD CARD or SPI FLASH according to the starting mode;

After the execution of the program in step A04) ZSBL is finished, jumping to the ITIM to execute the FSBL program;

Step A05), the FSBL program executes configuration PLL frequency raising, the DDR controller reset is canceled, DDR memory control training is carried out, and then BBL and OS are carried into DDR from SPI SD CARD or SPI FLASH;

step A06) after the FSBL program is executed, jumping to BBL program and OS program in DDR, and completing the system start. By adopting the memory space of the ITIM mode, the efficiency of starting the work can be improved.

Referring to fig. 2, the method for executing ZSBL programs from BootRom includes:

Step B01), after the chip is powered on and reset, the core PC points to the MSEL register of Modelsel ROM and takes the value, the jump is carried out according to the value of the MSEL register, and the value of the MSEL register of Modelsel ROM is determined by a chip pin;

Step B02) starting in Debug mode when the value of the MSEL register is 00B, skipping the PC to the service interruption program of debugger module, starting in BootRom mode when the value of the MSEL register is not 00B, and skipping the PC to the ZSBL program in BootRom. After power-on reset, the core, S_Bus, modelsel ROM and the like work under the condition of an external crystal oscillator of 50 Mhz. The PC of the core points to the 0x1004 value and jumps according to MSEL [1:0], and the contents of Modelsel ROM are shown in Table 1. Where 0x1004 is the MSEL register address.

Table 1 Modelsel ROM content

Address	Contents
		0x1000	The MSEL pin state
0x1004	auipc t0,0
		0x1008	lw t1,-4(t0)
0x100c	slli t1,t1,0x3
		0x1010	add t0,t0,t1
0x1014	lw t0,252(t0)
		0x1018	jr,t0

And selecting a Debug mode to start or a Boot Rom mode to start according to MSEL [1:0 ]. As shown in table 2, the contents of the MSEL register and the startup mode mapping table are described, and the corresponding startup mode is completed according to the contents of the MSEL register. The MSEL register stores two bits of data.

Table 2 MSEL register contents and startup mode mapping table

Referring to fig. 3, the zsbl procedure specifically performs the following steps:

Step C01) selecting to transfer the FSBL program from the SPI FLASH or SPI SD CARD according to the value of the MSEL register, as shown in table 3, transferring the FSBL program from the SPI FLASH to the ITIM if the value of the MSEL register is 01B or 11B, and transferring the FSBL program from SPI SD CARD to the ITIM if the value of the MSEL register is 10B;

Step C02) jumps the PC to the start address of the FSBL program at ITIM, completing the execution of ZSBL programs.

Table 3 MSEL register contents and FSBL program storage location mapping table

MSEL	FSBL position
		01	SPI FLASH
10	SPI SD card
		11	SPI FLASH

Referring to fig. 4, the method for configuring ITIM includes:

ICache is configured into ITIM mode, which specifically comprises:

step D01) opening ITIM items in ICache, wherein the ITIM items in the last row are used for exiting the ITIM mode;

Step D02) after the chip is powered on and reset, when the chip is written into the ITIM item, the empty item of the ITIM is directly applied for use, and when the chip is written into the ITIM item of the last row, the ITIM mode is exited.

Referring to fig. 5, a method for carrying an FSBL program to an ITIM includes:

e01) writing the row address of the ITIM to obtain the allocation of the ITIM space at the same time;

Step E02) sequentially reading the FSBL program segments, and sequentially writing from the 0 th row address of the ITIM;

step E03) after all FSBL programs are written to ITIM, writing 0 to the next row ITIM address indicates that ITIM space is released and ITIM mode is exited.

Referring to fig. 6, the fsbl program specifically performs the following steps:

Step F01) configuring PLL parameters, which are stored in the SCU part and enable up-conversion;

Step F02), after inquiring the PLL locking, switching the core to the target frequency;

Step F03), canceling the reset of the device and canceling the reset of the DDR;

F04) performing DDR memory control training;

step F05) loading BBL program and OS program from SPI FLASH or SPI SD CARD into DDR, and taking the 0x8000_0000 address of DDR as the initial address;

step F06) the PC jumps to 0x8000_0000 to execute BBL program and OS program, and completes system start.

The PLL includes a Core PLL and a DDR PLL, and after both the Core PLL and the DDR PLL are queried to lock, the Core is switched to the target frequency.

The method has the beneficial effects that the start-up starting flow is carried out by means of the ITIM, the start-up starting efficiency of the SOC is improved, the requirement on SOC hardware is low, the start-up starting of the SOC is applicable to a wider range, various start-up starting modes are provided, and the start-up starting of different purposes of the SOC is facilitated.

While the invention has been described in terms of embodiments, it will be appreciated by those skilled in the art that the invention is not limited thereto but rather includes the drawings and the description of the embodiments above. Any modifications which do not depart from the functional and structural principles of the present invention are intended to be included within the scope of the appended claims.

Claims

1. A start-up starting method of SOC based on RISC-V is characterized in that,

The method comprises the following steps:

2. The SOC start-up method based on RISC-V as set forth in claim 1, wherein,

The method for executing ZSBL programs from BootRom comprises the following steps:

3. The SOC start-up method based on RISC-V as set forth in claim 2, wherein,

The ZSBL program specifically performs the following steps:

4. A method of starting up an SOC based on RISC-V according to any one of claims 1 to 3, wherein the method of configuring ITIM comprises:

ICache is configured into ITIM mode, which specifically comprises:

5. The SOC start-up method based on RISC-V as set forth in claim 4, wherein,

The method for carrying the FSBL program to the ITIM comprises the following steps:

6. A SOC start-up method based on RISC-V according to any of claims 1 to 3, characterized in that the FSBL procedure specifically performs the following steps:

After the inquiry PLL locks, the core is switched to the target frequency;

Resetting the device, and resetting the DDR;

performing DDR memory control training;

7. A start-up method of SOC based on RISC-V according to any of claims 1 to 3, wherein the PLL comprises Core PLL and DDR PLL, and the Core and DDR PLL are switched to the target frequency after both the Core PLL and DDR PLL are queried to lock.