CN115241328B - A method for preparing a single carrier detector - Google Patents

Abstract

The invention discloses a preparation method of a single carrier detector, which ensures that the diffusion depth of an active region of the single carrier detector covers the whole intrinsic type In _0.53Ga_0.47 As absorption layer by optimizing the time and the concentration of Zn diffusion, so that the intrinsic type In _0.53Ga_0.47 As absorption layer has proper p-type doping In the central region of the detector, the concentration of Zn doping of the intrinsic type In _0.53Ga_0.47 As absorption layer is gradually reduced from top to bottom, and the doping gradient forms a weak electric field In the intrinsic type In _0.53Ga_0.47 As absorption layer, which is favorable for transporting electrons In the intrinsic type In _0.53Ga_0.47 As absorption layer and improving the speed of the detector.

Description

A method for preparing a single carrier detector

Technical Field

The invention relates to the technical field of photoelectric detectors, and in particular to a method for preparing a single carrier detector.

Background technique

With the continuous development and increasing maturity of optoelectronic communication technology, the performance of existing optical communication systems such as response speed and bandwidth will be difficult to meet people's needs. As a very important part of optoelectronic communication systems, photoelectric signal detectors are also a current research hotspot.

Traditional PIN-type balanced detectors use both electrons and holes as carriers. The response speed of the detector is mainly affected by the holes with larger effective mass. Therefore, there is an urgent need for a detector with a significantly improved response speed compared to the traditional PIN-type detector. At the same time, the Zn diffusion process generally has a tailing phenomenon, which poses a great threat to traditional balanced detectors.

Summary of the invention

In order to solve the deficiencies of the above technical solutions, an object of the present invention is to provide a method for preparing a single carrier detector.

Another object of the present invention is to provide a single carrier detector.

The purpose of the present invention is achieved through the following technical solutions.

A method for preparing a single carrier detector comprises the following steps:

Step 1: Using MOCVD or MBE deposition method, an N-type InP buffer layer, an N-type DBR reflection region, an N-type InP drift layer, an N-type InGaAsP transition layer (one or more layers), an intrinsic In _0.53 Ga _0.47 As absorption layer, an intrinsic In _0.52 Al _0.48 As electron diffusion barrier layer and an intrinsic InP cap layer are sequentially grown on a semi-insulating InP substrate;

Step 2: Depositing a SiN film on the upper surface of the intrinsic InP cap layer by PECVD;

Step 3: forming a Zn diffusion window pattern on the surface of the SiN film by using a photoresist, removing the SiN film on the Zn diffusion window pattern array by etching to expose the intrinsic InP cap layer below, and removing the photoresist after etching to form a Zn diffusion window;

Step 4: Diffusing Zn in the Zn diffusion window region by MOCVD or a furnace tube method to form a P-type diffusion region and an inactive region surrounding the P-type diffusion region, wherein the region diffused with Zn includes an intrinsic InP cap layer, an intrinsic In _0.52 Al _0.48 As electron diffusion barrier layer and an intrinsic In _0.53 Ga _0.47 As absorption layer, and after Zn diffusion, the intrinsic InP cap layer, the In _0.52 Al _0.48 As electron diffusion barrier layer and the In _0.53 Ga _0.47 As absorption layer are converted into P-type, wherein the P-type doping concentration in the intrinsic In _0.53 Ga _0.47 As absorption layer gradually decreases from top to bottom, forming a P-type In _0.53 Ga _0.47 As absorption layer with a P-type doping concentration gradient;

Step 5: using photoresist to form a step pattern on the upper surface of the SiN film and the P-type diffusion region, and forming a step region and an N-type contact region surrounding the step region by step etching, wherein the step region includes a P-type diffusion region, and the radius difference between the step region and the P-type diffusion region is 5 to 50 μm, and the step etching region includes an intrinsic InP cap layer, an intrinsic In _0.52 Al _0.48 As electron diffusion barrier layer, an intrinsic In _0.53 Ga _0.47 As absorption layer, an N-type InGaAsP transition layer (1 layer or multiple layers), an N-type InP drift layer, an N-type DBR reflection region and an N-type InP buffer layer;

Step 6: using photoresist to form a continuous P-type metal electrode pattern in a region on one side of the Zn diffusion window and on the upper surface of the SiN film adjacent to the region, evaporating metal on the outer surface of the P-type metal electrode pattern and performing metal stripping, annealing, and forming a P-type metal electrode, wherein the P-type metal electrode pattern and the upper surface of the P-type diffusion region are in ohmic contact;

Step 7: using photoresist to form an N-electrode pattern on the N-type contact area around the step area, using electron beam evaporation or magnetron sputtering to evaporate metal, and performing metal stripping and annealing to form an N-type metal electrode, the N-type metal electrode contacts the N-type InP buffer layer to form an ohmic contact, wherein there is a gap between the N-type metal electrode and the step area, and the distance of the gap is 5 to 50 μm;

Step 8: Apply BCB or PBO material on all exposed upper surfaces by means of glue coating, and form BCB or PBO patterns by means of photolithography and development. The BCB or PBO patterns cover the side of the step area. After photolithography and development, the N-type metal electrode and the P-type metal electrode are exposed, and the passivation of the side of the step area is completed by baking and curing. The thickness of the coating is 1 to 20 μm.

Step nine: Deposit a SiN anti-reflection film on the outer surface of the detector using a PECVD deposition method;

Step 10: using photoresist to form a VIA hole pattern directly above the P-type metal electrode and the N-type metal electrode, removing the SiN anti-reflection film in the VIA hole pattern by etching to expose the P-type metal electrode and the N-type metal electrode, and removing the photoresist after etching to obtain a VIA hole;

Step 11: Thinning and polishing the back side of the semi-insulating InP substrate.

In the above technical solution, the thickness of the N-type InP buffer layer is 0.5 μm, and the doping concentration is 5×10 ¹⁷ /cm ³ .

In the above technical solution, in step 1, the N-type DBR reflection zone is composed of multiple layers of InP and InAlGaAs, the thickness of each layer of InP and InAlGaAs is 1/4 of the effective wavelength of light with a wavelength of 1550nm in the material, the number of InP and InAlGaAs layers is greater than or equal to 10, and the reflectivity of the N-type DBR reflection zone for light with a wavelength of 1300-1700nm is greater than or equal to 70%.

In the above technical solution, in step 1, the thickness of the intrinsic type In _0.53 Ga _0.47 As absorption layer is 1-4 μm.

In the above technical solution, in step 1, the thickness of the N-type InP drift layer is 0.1-1 μm, and the doping concentration is 5×10 ¹⁵ -2×10 ¹⁷ /cm ³ .

In the above technical solution, in step 1, the thickness of the intrinsic type In _0.52 Al _0.48 As electron diffusion barrier layer is 10-200 nm.

In the above technical solution, in step 2, the thickness of the SiN film is 100 nm.

In the above technical solution, in step 4, the P-type doping concentration of the intrinsic In _0.53 Ga _0.47 As absorption layer is reduced from 5×10 ¹⁷ to 5×10 ¹⁸ /cm ³ to 1×10 ¹⁷ to 5×10 ¹⁷ /cm ³ from top to bottom.

In the above technical solution, in step 4, the P-type diffusion region is circular, and its radius is 10 to 2000 μm.

In the above technical solution, in step nine, the thickness of the SiN anti-reflection film is 200 nm, and the reflectivity of the SiN anti-reflection film for light with a wavelength of 1310 nm to 1700 nm is greater than or equal to 70%.

In the above technical solution, in step eleven, the thickness of the semi-insulating InP substrate after thinning and polishing is 50 to 200 μm.

The single carrier detector obtained by the above preparation method.

The advantages and beneficial effects of the present invention are:

The present invention discloses a method for preparing a single carrier detector, which is mainly a method combining Zn diffusion and steps. Among them, Zn diffusion is used to form a P-type metal contact area, and the step pattern is larger than the diameter of the Zn diffusion and is used to form electrical isolation. The advantages of this are:

1. By optimizing the diffusion time and concentration of Zn, the diffusion depth of the active area of the single-carrier detector covers the entire intrinsic In _0.53 Ga _0.47 As absorption layer, which can ensure that the intrinsic In _0.53 Ga _0.47 As absorption layer has appropriate p-type doping in the central area of the detector. The concentration of Zn doping in the intrinsic In _0.53 Ga _0.47 As absorption layer gradually decreases from top to bottom. The doping gradient will form a weak electric field in the intrinsic In _0.53 Ga _0.47 As absorption layer, which will help the transport of electrons in the intrinsic In _0.53 Ga _0.47 As absorption layer and improve the speed of the detector.

2. The tailing phenomenon is common in Zn diffusion process. In the single carrier detector of the present invention, the tailing phenomenon of Zn diffusion is reasonably utilized. The tailing Zn doping will produce a doping gradient in the intrinsic In _0.53 Ga _0.47 As absorption layer, which is helpful for the transport of electrons in the intrinsic In _0.53 Ga _0.47 As absorption layer.

3. The present invention adopts a semi-insulating InP substrate and limits the active area of Zn diffusion to the step area through step corrosion, which can not only achieve electrical insulation but also minimize the capacitance of the detector, thereby improving the switching speed and bandwidth of the detector.

4. The diameter of the step region is larger than the diameter of the Zn diffusion region. Therefore, the side of the step region is a semi-insulating high-resistance material (BCB or PBO material). The dark current can be further reduced by optimizing the side passivation.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic flow chart of step 1 of the single carrier detector of the present invention.

FIG. 2 is a schematic flow chart of step 2 to step 4 of the single carrier detector of the present invention.

FIG. 3 is a schematic flow chart of step 5 of the single carrier detector of the present invention.

FIG. 4 is a schematic flow chart of step 6 to step 7 of the single carrier detector of the present invention.

FIG. 5 is a schematic flow chart of step eight of the single carrier detector of the present invention.

FIG. 6 is a schematic flow chart of step nine of the single carrier detector of the present invention.

FIG. 7 is a schematic flow chart of step 10 of the single carrier detector of the present invention.

in,

1: Semi-insulating InP substrate,

2: N-type InP buffer layer,

3: N-type DBR reflection area,

4: N-type InP drift layer,

5: N-type InGaAsP transition layer,

6: Intrinsic type In _0.53 Ga _0.47 As absorption layer,

7: Intrinsic type In _0.52 Al _0.48 As electron diffusion barrier,

8: Intrinsic InP cap layer,

9: SiN film,

10: Zn diffusion window,

11: P-type diffusion region,

12: Step area,

13: P-type metal electrode,

14: N-type metal electrode,

15: BCB or PBO graphics,

16: SiN anti-reflection film,

17: VIA hole.

Detailed ways

The technical solution of the present invention is further described below in conjunction with specific embodiments.

Example 1

As shown in FIGS. 1-7 , this embodiment provides a method for preparing a single carrier detector, comprising the following steps:

Step 1: Using MOCVD or MBE deposition method, an N-type InP buffer layer 2, an N-type DBR reflection region 3, an N-type InP drift layer 4, an N-type InGaAsP transition layer 5 (one or more layers), an intrinsic In _0.53 Ga _0.47 As absorption layer 6, an intrinsic In _0.52 Al _0.48 As electron diffusion barrier layer 7 and an intrinsic InP cap layer 8 are sequentially grown on a semi-insulating InP substrate 1, wherein the thickness of the N-type InP buffer layer 2 is 0.5 μm and the doping concentration is 5×10 ¹⁷ /cm ³ , which is used to better match the difference in lattice constants between the semi-insulating InP substrate 1 and the epitaxial layer material on the N-type InP buffer layer 2 caused by different growth conditions, and ensure the growth quality of the epitaxial layer; the N-type DBR reflection area 3 is composed of multiple layers of InP and InAlGaAs, the thickness of each layer of InP and InAlGaAs is 1/4 of the effective wavelength of the light with a wavelength of 1550nm in the material, the emission wavelength of InAlGaAs is 1190nm, the thickness is 93nm, the number of InP and InAlGaAs layers is greater than or equal to 10, and the reflectivity of the N-type DBR reflection area 3 for the light with a wavelength of 1550nm is greater than 80%; the thickness of the N-type InP drift layer 4 is 1μm, and the doping concentration is 5×10 ¹⁵ /cm ³ ; the intrinsic type In _0.53 Ga _0.47 The thickness of the As absorption layer 6 is 1 μm, which is a photogenerated carrier generation layer. The thickness of this layer is relatively low, which reduces the diffusion time of photogenerated electrons in this layer. At the same time, since the N-type DBR reflection layer can reflect the unabsorbed light back to the intrinsic In _0.53 Ga _0.47 As absorption layer for secondary absorption, this ensures the response speed of the single-carrier detector; the thickness of the intrinsic In _0.52 Al _0.48 As electron diffusion blocking layer 7 is 20 nm, which is used to block the photogenerated electrons from diffusing upward, thereby ensuring the single-carrier transport characteristics of the detector.

Step 2: Deposit a SiN film 9 on the upper surface of the intrinsic InP cap layer 8 by using PECVD (Plasma Enhanced Chemical Vapor Deposition), and the thickness of the SiN film 9 is 100 nm.

Step three: Use photoresist to form a Zn diffusion window 10 pattern array on the surface of the SiN film 9, and use etching to remove the SiN film 9 on the Zn diffusion window 10 pattern array to expose the intrinsic InP cap layer 8 below. After etching, remove the photoresist to form a Zn diffusion window 10.

Step 4: Diffusing Zn in the Zn diffusion window 10 region by MOCVD or furnace tube method to form a P-type diffusion region 11 and an inactive region surrounding the P-type diffusion region 11, wherein the region diffused with Zn includes an intrinsic InP cap layer 8, an intrinsic In _0.52 Al _0.48 As electron diffusion barrier layer 7 and an intrinsic In _0.53 Ga _0.47 As absorption layer 6. After Zn diffusion, the intrinsic InP cap layer 8, the In _0.52 Al _0.48 As electron diffusion barrier layer 7 and the In _0.53 Ga _0.47 As absorption layer are converted into P-type, wherein the P-type doping concentration in the In _0.53 Ga _0.47 As absorption layer gradually decreases from top to bottom, forming a P-type In _0.53 Ga _0.47 As absorption layer with a P-type doping concentration gradient, wherein the concentration decreases from 2×10 ¹⁸ /cm ³ to 1×10 ¹⁷ /cm ³ , wherein the upper surface of the P-type diffusion region 11 is circular, and its radius is 25 μm.

Step 5: Use photoresist to form a step pattern on the upper surface of the SiN film 9 and the P-type diffusion region 11, and form a step region 12 and an N-type contact region surrounding the step region 12 by step etching, wherein the step region 12 includes the P-type diffusion region 11, and the radius difference between the step region 12 and the P-type diffusion region 11 is 10 μm, and the step etching area includes an intrinsic InP cap layer 8, an intrinsic In _0.52 Al _0.48 As electron diffusion barrier layer 7, an intrinsic In _0.53 Ga _0.47 As absorption layer 6, an N-type InGaAsP transition layer 5 (1 layer or multiple layers), an N-type InP drift layer 4, an N-type DBR reflection region 3 and an N-type InP buffer layer 2.

Step six: Use photoresist to form a continuous P-type metal electrode 13 pattern in the area on one side of the Zn diffusion window 10 and on the upper surface of the SiN film 9 adjacent to the area, evaporate metal on the outer surface of the P-type metal electrode pattern and perform metal stripping and annealing to form a P-type metal electrode 13. The P-type metal electrode pattern and the SiN film 9 are in ohmic contact.

Step seven: Using the photoresist step region 12 on one side to form an N-electrode pattern on the N-type contact region, using electron beam evaporation or magnetron sputtering to evaporate metal, and performing metal stripping and annealing to form an N-type metal electrode 14, the N-type metal electrode 14 contacts the N-type InP buffer layer 2 to form an ohmic contact, wherein there is a gap between the N-type metal electrode 14 and the step region 12, and the distance of the gap is 5 to 50 μm.

Step eight: Use a glue coating method to apply BCB or PBO material on all exposed upper surfaces, and use photolithography and development methods to form a BCB or PBO pattern 15. The BCB or PBO pattern 15 covers the side of the step area 12. After photolithography and development, the N-type metal electrode 14 and the P-type metal electrode 13 are exposed, and baked and cured to complete the passivation of the side of the step area 12. The coating thickness is 4μm.

Step nine: Deposit SiN anti-reflection film 16 on all exposed outer surfaces by PECVD deposition method. The thickness of the SiN anti-reflection film 16 is 200 nm. The reflectivity of the SiN anti-reflection film 16 for light with a wavelength of 1550 nm is greater than 90%.

Step ten: Use photoresist to form a VIA hole 17 pattern directly above the P-type metal electrode 13 and the N-type metal electrode 14, and use an etching method to remove the SiN anti-reflection film 16 in the VIA hole 17 pattern, so that the P-type metal electrode 13 and the N-type metal electrode 14 are exposed. After the etching is completed, remove the photoresist to obtain the VIA hole 17.

Step 11: Thinning and polishing the back side of the semi-insulating InP substrate 1. After thinning and polishing, the thickness of the semi-insulating InP substrate is 150 μm.

The single carrier detector obtained by the preparation method of this embodiment adopts the front incidence mode, and the light is incident through the SiN anti-reflection film 16 and is absorbed by the intrinsic In _0.53 Ga _0.47 As absorption layer 6. The light that is not completely absorbed is reflected back to the intrinsic In _0.53 Ga _0.47 As absorption layer 6 through the N-type DBR reflection area 3, thereby undergoing secondary absorption.

The present invention is described above by way of example. It should be noted that, without departing from the core of the present invention, any simple deformation, modification or other equivalent replacement that can be made by those skilled in the art without inventive labor falls within the protection scope of the present invention.

Claims (9)

1. A method for preparing a single carrier detector, characterized in that it comprises the following steps: Step 1: using MOCVD or MBE deposition method to sequentially grow an N-type InP buffer layer (2), an N-type DBR reflection region (3), an N-type InP drift layer (4), an N-type InGaAsP transition layer (5), an intrinsic In _0.53 Ga _0.47 As absorption layer (6), an intrinsic In _0.52 Al _0.48 As electron diffusion barrier layer (7) and an intrinsic InP cap layer (8) on a semi-insulating InP substrate (1); Step 2: Depositing a SiN film (9) on the upper surface of the intrinsic InP cap layer (8) by using PECVD; Step 3: forming a Zn diffusion window (10) pattern on the surface of the SiN film (9) by using a photoresist, removing the SiN film (9) on the Zn diffusion window (10) pattern array by using an etching method to expose the intrinsic type InP cap layer (8) below, and removing the photoresist after the etching is completed to form the Zn diffusion window (10); Step 4: using MOCVD or a furnace tube method to diffuse Zn in the Zn diffusion window (10) region to form a P-type diffusion region (11) and an inactive region surrounding the P-type diffusion region (11), wherein the region diffused with Zn includes an intrinsic InP cap layer (8), an intrinsic In _0.52 Al _0.48 As electron diffusion barrier layer (7) and an intrinsic In _0.53 Ga _0.47 As absorption layer (6); after the Zn diffusion, the intrinsic InP cap layer (8), the In _0.52 Al _0.48 As electron diffusion barrier layer (7) and the In _0.53 Ga _0.47 As absorption layer (6) are converted into P-type, wherein the P-type doping concentration in the intrinsic In _0.53 Ga _0.47 As absorption layer (6) gradually decreases from top to bottom, thereby forming a P-type In _0.53 Ga _0.47 As absorption layer (6) having a P-type doping concentration gradient; Step 5: using photoresist to form a step pattern on the upper surface of the SiN film (9) and the P-type diffusion region (11), and performing step etching to form a step region (12) and an N-type contact region surrounding the step region (12), wherein the step region (12) includes the P-type diffusion region (11), the radius difference between the step region (12) and the P-type diffusion region (11) is 5 to 50 μm, and the step etching region includes an intrinsic InP cap layer (8), an intrinsic In _0.52 Al _0.48 As electron diffusion barrier layer (7), an intrinsic In _0.53 Ga _0.47 As absorption layer (6), an N-type InGaAsP transition layer (5), an N-type InP drift layer (4), an N-type DBR reflection region (3) and an N-type InP buffer layer (2); Step 6: using photoresist to form a continuous P-type metal electrode pattern in a region on one side of the Zn diffusion window (10) and on the upper surface of the SiN film (9) adjacent to the region, evaporating metal on the outer surface of the P-type metal electrode pattern and performing metal stripping, annealing, and forming a P-type metal electrode (13), wherein the P-type metal electrode pattern and the upper surface of the P-type diffusion region (11) are in ohmic contact; Step 7: using photoresist to form an N-electrode pattern on the N-type contact area around the step area (12), using electron beam evaporation or magnetron sputtering to evaporate metal, and performing metal stripping and annealing to form an N-type metal electrode (14), wherein the N-type metal electrode (14) contacts the N-type InP buffer layer (2) to form an ohmic contact, wherein a gap exists between the N-type metal electrode (14) and the step area (12), and the distance of the gap is 5-50 μm; Step 8: applying BCB or PBO material on all exposed upper surfaces by means of glue coating, forming a BCB or PBO pattern (15) by means of photolithography and development, wherein the BCB or PBO pattern (15) covers the side of the step region (12), exposing the N-type metal electrode (14) and the P-type metal electrode (13) after photolithography and development, and baking and curing to complete the passivation of the side of the step region (12), wherein the coating thickness is 1 to 20 μm; Step nine: depositing a SiN anti-reflection film (16) on all exposed outer surfaces by using a PECVD deposition method; Step ten: using photoresist to form a VIA hole (17) pattern directly above the P-type metal electrode (13) and the N-type metal electrode (14), removing the SiN anti-reflection film (16) in the VIA hole (17) pattern by etching, so that the P-type metal electrode (13) and the N-type metal electrode (14) are exposed, and removing the photoresist after the etching is completed to obtain the VIA hole (17); Step 11: Thinning and polishing the back side of the semi-insulating InP substrate (1). 2 . The preparation method according to claim 1 , characterized in that, in step 1, the thickness of the N-type InP buffer layer ( 2 ) is 0.5 μm, and the doping concentration is 5×10 ¹⁷ /cm ³ . 3. The preparation method according to claim 1 is characterized in that in step 1, the N-type DBR reflection area (3) is composed of multiple layers of InP and InAlGaAs, the thickness of each layer of InP and InAlGaAs is 1/4 of the effective wavelength of light with a wavelength of 1550nm in the material, the number of layers of InP and InAlGaAs is greater than or equal to 10, and the reflectivity of the N-type DBR reflection area (3) for light with a wavelength of 1300-1700nm is greater than or equal to 70%. 4. The preparation method according to claim 1, characterized in that, in step 1, the thickness of the intrinsic In _0.53 Ga _0.47 As absorption layer (6) is 1-4 μm; the thickness of the N-type InP drift layer (4) is 0.1-1 μm, and the doping concentration is 5×10 ¹⁵ -2×10 ¹⁷ /cm ³ ; the thickness of the intrinsic In _0.52 Al _0.48 As electron diffusion barrier layer (7) is 10-200 nm. 5. The preparation method according to claim 1, characterized in that, in step 2, the thickness of the SiN film (9) is 100 nm. 6. The preparation method according to claim 1, characterized in that in step 4, the P-type doping concentration of the intrinsic In _0.53 Ga _0.47 As absorption layer (6) decreases from 5×10 ¹⁷ to 5×10 ¹⁸ /cm ³ from top to bottom to 1×10 ¹⁷ to 5×10 ¹⁷ /cm ³ . 7. The preparation method according to claim 1, characterized in that, in step 4, the P-type diffusion region (11) is circular, and its radius is 10 to 2000 μm. 8. The preparation method according to claim 1, characterized in that, in step nine, the thickness of the SiN anti-reflection film (16) is 200 nm, and the reflectivity of the SiN anti-reflection film (16) for light with a wavelength of 1310 nm to 1700 nm is greater than or equal to 70%. 9. The preparation method according to claim 1, characterized in that in step 11, the thickness of the semi-insulating InP substrate (1) after thinning and polishing is 50-200 μm.