CN115242220B - Digital shaping filter with dynamically reconfigurable order and folding circuit structure and its design method - Google Patents
Digital shaping filter with dynamically reconfigurable order and folding circuit structure and its design methodInfo
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- CN115242220B CN115242220B CN202210882888.0A CN202210882888A CN115242220B CN 115242220 B CN115242220 B CN 115242220B CN 202210882888 A CN202210882888 A CN 202210882888A CN 115242220 B CN115242220 B CN 115242220B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
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- H03H17/02—Frequency selective networks
- H03H17/06—Non-recursive filters
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- H—ELECTRICITY
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- H03H17/00—Networks using digital techniques
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- H03H2017/0081—Theoretical filter design of FIR filters
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Abstract
The present disclosure provides an order dynamically reconfigurable folded circuit structure digital shaping filter and a design method. The digital shaping filter comprises a data redefining logic unit, a data shifting register unit, a first adder unit, an impulse response coefficient register file unit, a reconstruction completion flag register unit, a multiplier unit, a second adder unit, an order number reconstruction register unit, a time sequence control logic unit and an output logic unit, wherein the data redefining logic unit is used for carrying out bit width conversion, the data shifting register unit is used for storing output data of the data redefining logic unit, the first adder unit is used for carrying out addition operation according to a folding circuit structure, the impulse response coefficient register file unit is used for writing impulse response coefficients, the reconstruction completion flag register unit is used for sending out reconstruction completion signals, the multiplier unit is used for carrying out multiplication operation and receiving output signals of the reconstruction completion flag register unit, the second adder unit is used for carrying out addition operation on the output data of the multiplier unit, the order number reconstruction register unit is used for writing the order number of the digital shaping filter, the time sequence control logic unit is used for selecting the result data, and the output logic unit is used for outputting the result data.
Description
Technical Field
The present disclosure relates to the field of digital signal processing technologies, and in particular, to a digital shaping filter with an order dynamically reconfigurable folding circuit structure and a design method thereof.
Background
Digital signal processing techniques are widely used in the fields of radar signal processing, wireless transmission, satellite communications, etc., and digital filters are the main components of digital signal processing. In radar signal processing and wireless communication systems, the frequency bandwidth and power of signals are limited to a certain extent, the frequency bandwidth and the power of signals are wide in frequency band, the frequency spectrum utilization rate is high, the low-loss modulation signal shaping filtering technology is one of key technologies for realizing a high-speed data transmission system, and the shaping filtering technology can improve the utilization rate of frequency bands on the premise of eliminating intersymbol interference and achieving optimal detection. With the development of digital signal processing technology and high-speed large-scale digital integrated circuit technology, digital shaping filters have the characteristics of high precision, high flexibility and convenience for large-scale integration compared with analog shaping filters, so that digital shaping filters are mostly adopted in shaping filters.
In implementing the disclosed concept, the inventor finds that there is at least a problem in the related art in that, after the design of the digital shaping filter is completed, the hardware structure is determined, the parameters need to be reselected in order to change the characteristics of the digital shaping filter, and then the hardware structure of the digital shaping filter is rearranged, thereby wasting a lot of time and resources.
Disclosure of Invention
In view of this, the present disclosure provides a digital shaping filter with dynamically reconfigurable folding circuit structure and a design method thereof.
An aspect of the present disclosure provides an order dynamically reconfigurable folded circuit structure digital shaping filter, comprising:
the data redefinition logic unit is used for carrying out bit width conversion on input data;
The data shift register unit is used for storing the output data of the data redefinition logic unit, wherein the data shift register unit comprises a plurality of data shift registers, and the output data of the data redefinition logic unit is sequentially stored in the plurality of data shift registers according to time sequence;
The first adder unit is used for carrying out addition operation on the output data of the data shift register unit according to the folding circuit structure;
An impulse response coefficient register file unit for writing the impulse response coefficient of the digital shaping filter;
A reconstruction completion flag register unit for sending out a reconstruction completion signal in case the order reconstruction register unit completes the reconstruction;
A multiplier unit for multiplying the output data of the first adder unit according to the impulse response coefficient and receiving the output signal of the reconstruction completion flag register unit;
The second adder unit is used for adding the output data of the multiplier unit under the condition that the multiplier unit receives the reconstruction completion signal;
an order reconstruction register unit for writing the order of the digital shaping filter;
the time sequence control logic unit is used for controlling the selection output logic unit to select result data according to the order reconstruction register unit;
and the selection output logic unit is used for outputting result data according to the control of the time sequence control logic unit.
According to an embodiment of the present disclosure, the first adder unit is further configured to perform an addition operation on data stored in an mth data shift register and data stored in an nth data shift register of the plurality of data shift registers according to a folded circuit structure in the case where an order is 2i, where i is an integer greater than 0, mε [1, i ], nε [ i+1,2i ], M, N are integers, and m+n=2i+1, and
Under the condition that the order is 2j-1, carrying out addition operation on data stored in an X-th data shift register and data stored in a Y-th data shift register in a plurality of data shift registers according to a folding circuit structure, wherein j is an integer greater than 0, X epsilon [1, j-1], Y epsilon [ j+1,2j-1], X, Y are integers, and X+Y=2j.
According to an embodiment of the present disclosure, the multiplier unit is further configured to multiply data obtained by adding the first adder unit with an order of 2i with data of the impulse response coefficient register file unit, and
And multiplying the data obtained by adding the first adder unit under the condition that the order is 2j-1 and the data in the j-th data shift register by the data of the impulse response coefficient register file unit.
According to an embodiment of the present disclosure, the order reconstruction register unit is further configured to determine a maximum order of reconstruction of the digital shaping filter according to a hardware structure of the digital shaping filter.
According to the embodiment of the disclosure, the data transmission mode of the folding circuit structure adopts a multi-stage data pipeline mode, wherein the first adder unit, the multiplier unit, the second adder unit and the selection output logic unit all comprise a register structure, so that the digital shaping filter can output result data in each clock cycle.
According to an embodiment of the present disclosure, the digital shaping filter further includes:
the impulse response coefficient is quantized at fixed point, expressed by the following formula:
Wherein D 1 represents the impulse response coefficient after quantization, D 2 represents the impulse response coefficient before quantization, C is the quantization base, and K is the bit width of the quantization base.
According to an embodiment of the present disclosure, the data bit width stored by the order reconstruction register unit is configured to be determined from the digital shaping filter;
the impulse response coefficient register file unit stores data bit widths configured to be determined from the digital shaping filter;
the data bit width stored by the data shift register unit is configured to be the same as the data bit width output by the data redefinition logic unit;
The first adder unit stores a data bit width configured to be one bit more than the data bit width stored by the data shift register unit;
The data bit width stored by the multiplier unit is configured as the sum of the data bit width stored by the register in the first adder unit and the data bit width stored by the impulse response coefficient register file unit;
the second adder unit stores a data bit width configured to be determined by a bit width of the output data of the multiplier unit.
According to an embodiment of the present disclosure, wherein the second adder unit stores a data bit width configured to be added by a bit width of the output data of the multiplier unitWhere H is the maximum order that the hardware structure of the shaping filter can support.
Another aspect of the present disclosure also provides a method for designing an order dynamically reconfigurable folded circuit structure digital shaping filter, including:
Determining an impulse response coefficient and a reconfigurable order according to the performance parameters of the digital shaping filter, and carrying out fixed-point quantization on the impulse response coefficient;
Inputting the impact response coefficient and the order number after fixed-point quantization into a digital shaping filter;
Reconstructing and configuring an impulse response coefficient register file unit and an order reconstruction register unit according to the bit width of a register in the digital shaping filter;
selecting a corresponding folding circuit structure according to the order to calculate to obtain result data;
outputting the result data.
According to an embodiment of the present disclosure, selecting a corresponding folded circuit structure according to an order to calculate to obtain result data includes:
In the case of an order of 2i, the first adder unit performs an addition operation on the data stored in the mth data shift register and the data stored in the nth data shift register of the plurality of data shift registers according to the folding circuit structure, wherein i is an integer greater than 0, M [1, i ], N [ e [ i+1,2i ], M, N are integers, and M+N=2i+1, and
Under the condition that the order is 2j-1, the first adder unit performs addition operation on the data stored in the X-th data shift register and the data stored in the Y-th data shift register in the plurality of data shift registers according to the folding circuit structure, wherein j is an integer greater than 0, X epsilon [1, j-1], Y epsilon [ j+1,2j-1], X, Y are integers, and X+Y=2j.
According to the embodiment of the disclosure, the order and the impulse response coefficient of the digital shaping filter are respectively written into the order reconstruction register unit and the impulse response coefficient register file unit, the digital shaping filter is reconstructed, the reconstruction completion flag register unit sends out signals when the reconstruction is completed, so that the digital shaping filter starts to calculate and select output logic unit selection result data to output through the time sequence control logic unit, the digital shaping filter can be quickly generated on the basis of not changing a hardware circuit in a reconstruction mode, hardware repeated design can be avoided in the selectable order range of the digital shaping filter, so that the technical problems that in the related art, after the design of the digital shaping filter is completed, the hardware structure is determined, the parameters need to be reselected when the characteristics of the digital shaping filter need to be changed, and then the hardware structure of the digital shaping filter is rearranged and wired, a great amount of time and resources are wasted are further reduced, the design cost is saved, and the designed hardware module has reusability are overcome.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments thereof with reference to the accompanying drawings in which:
FIG. 1 schematically illustrates a block diagram of an order dynamically reconfigurable folded circuit architecture digital shaping filter, in accordance with an embodiment of the present disclosure;
FIG. 2 schematically illustrates a flow chart of a method of designing an order dynamically reconfigurable folded circuit architecture digital shaping filter in accordance with an embodiment of the present disclosure, and
Fig. 3 schematically illustrates a flow chart of a method of designing an order dynamically reconfigurable folded circuit architecture digital shaping filter according to yet another embodiment of the present disclosure.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The terms "comprises," "comprising," and/or the like, as used herein, specify the presence of stated features, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, or components.
All terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art unless otherwise defined. It should be noted that the terms used herein should be construed to have meanings consistent with the context of the present specification and should not be construed in an idealized or overly formal manner.
Where a convention analogous to "at least one of A, B and C, etc." is used, in general such a convention should be interpreted in accordance with the meaning of one of skill in the art having generally understood the convention (e.g., "a system having at least one of A, B and C" would include, but not be limited to, systems having a alone, B alone, C alone, a and B together, a and C together, B and C together, and/or A, B, C together, etc.). Where a formulation similar to at least one of "A, B or C, etc." is used, in general such a formulation should be interpreted in accordance with the ordinary understanding of one skilled in the art (e.g. "a system with at least one of A, B or C" would include but not be limited to systems with a alone, B alone, C alone, a and B together, a and C together, B and C together, and/or A, B, C together, etc.).
In the related art, different systems need to design digital shaping filters with different filtering characteristics, and often require a designer to design and verify the digital shaping filters again, which wastes a lot of time and effort. Particularly in chip designs of Application Specific Integrated Chips (ASICs) or System On Chip (SOCs), their reusability as important modules is poor. Moreover, there are more and more cases where a digital shaping filter is designed by using a Field Programmable Gate Array (FPGA), and when parameters of the digital shaping filter are selected, a circuit structure is fixed after synthesis and layout wiring are performed, and the parameters must be reselected to change the characteristics, so that a lot of time is wasted.
In view of this, the present disclosure proposes a digital shaping filter of an order dynamic reconfigurable folding circuit structure, by writing the order and impulse response coefficients of the digital shaping filter into an order reconfiguration register unit and an impulse response coefficient register file unit, respectively, to reconfigure the digital shaping filter, and in the case of the completion of the reconfiguration, by signaling a reconfiguration completion flag register unit, so that the digital shaping filter starts to calculate and select output logic unit selection result data to output through a timing control logic unit, by this reconfiguration, the digital shaping filter can be quickly generated without changing hardware circuits, hardware repetitive design can be avoided in the range of the selectable orders of the digital shaping filter, so that the technical problems that the characteristics of the digital shaping filter need to be reselected after the design of the digital shaping filter are determined by the hardware structure, and a lot of time and resources are wasted, the resource cost is further reduced, and the design is made reusable by the hardware structure of the digital shaping filter are overcome at least in part.
Fig. 1 schematically illustrates a block diagram of an order dynamically reconfigurable folded circuit architecture digital shaping filter 100, in accordance with an embodiment of the present disclosure.
As shown in fig. 1, the digital shaping filter 100 includes a data redefinition logic unit 101, a data shift register unit 102, a first adder unit 103, an impulse response coefficient register file unit 104, a reconstruction completion flag register unit 105, a multiplier unit 106, a second adder unit 107, an order reconstruction register unit 108, a timing control logic unit 109, and a selection output logic unit 110.
The data redefinition logic unit 101 is configured to perform bit width transformation on input data.
The data shift register unit 102 is configured to store output data of the data redefinition logic unit, where the data shift register unit includes a plurality of data shift registers, and the output data of the data redefinition logic unit is sequentially stored in the plurality of data shift registers according to a time sequence.
The first adder unit 103 is configured to add output data of the data shift register unit according to the folding circuit structure.
An impulse response coefficient register file unit 104 for writing the impulse response coefficient of the digital shaping filter.
A reconstruction completion flag register unit 105 for issuing a reconstruction completion signal in the case where the order reconstruction register unit completes reconstruction.
And a multiplier unit 106 for multiplying the output data of the first adder unit according to the impulse response coefficient and receiving the output signal of the reconstruction completion flag register unit.
And a second adder unit 107 for adding the output data of the multiplier unit when the multiplier unit receives the reconstruction completion signal.
An order reconstruction register unit 108 for writing the order of the digital shaping filter.
The timing control logic unit 109 is configured to control the selection output logic unit to select the result data according to the order reconstruction register unit.
The selection output logic unit 110 is configured to output result data according to control of the timing control logic unit.
According to embodiments of the present disclosure, the data redefinition logic 101 may perform a bit width transformation on the received data. For example, the received 1-bit data "0" may be converted into 2-bit data "11" by the data redefinition logic unit 101, or the received 1-bit data "1" may be converted into 2-bit data "01" by the data redefinition logic unit 101.
According to an embodiment of the present disclosure, the input terminal of the data shift register unit 102 is connected to the output terminal of the data redefinition logic unit 101, and the data shift register unit 102 may include a plurality of data shift registers, and the output data of the data redefinition logic unit may be output according to a time sequence and then stored in the corresponding data shift register according to the time sequence.
According to an embodiment of the present disclosure, an input terminal of the first adder unit 103 is connected to an output terminal of the data shift register unit 102, and the first adder unit 103 may perform an addition operation on output data of the data shift register unit.
According to an embodiment of the present disclosure, the first adder unit 103 may perform addition operation by a folded circuit structure.
According to an embodiment of the present disclosure, the impulse response coefficients of the digital shaping filter may be written to the impulse response coefficient register file unit 104 by a processor.
According to an embodiment of the present disclosure, the reconstruction completion flag register unit 105 may issue a reconstruction completion signal to the multiplier unit in case the order reconstruction register unit of the digital shaping filter completes reconstruction. The reconfiguration complete flag register unit may be deactivated before the digital shaping filter is reconfigured, and the reconfiguration complete flag register unit is caused to issue a reconfiguration complete signal after the digital shaping filter is configured.
According to an embodiment of the present disclosure, an input terminal of the multiplier unit 106 may be connected to output terminals of the impulse response coefficient register file unit 104 and the reconstruction completion flag register unit 105, and the multiplier unit 106 may receive an output signal of the reconstruction completion flag register unit 105.
According to an embodiment of the present disclosure, the multiplier unit 106 may multiply the output data of the first adder unit according to the impulse response coefficient, for example, may multiply the impulse response coefficient with the output data of the first adder unit.
According to an embodiment of the present disclosure, an input of the second adder unit 107 may be connected to an output of the multiplier unit 106, and the second adder unit 107 may perform an addition operation on output data of the multiplier unit.
According to an embodiment of the present disclosure, the order of the digital shaping filter may be written into the order reconstruction register unit 108 by the processor.
According to an embodiment of the present disclosure, the input terminal of the timing control logic unit 109 is connected to the output terminal of the order reconstruction register unit 108, and the order of the digital shaping filter can be determined by the order reconstruction register unit 108, and then the selection output logic unit is controlled to select the result data at the corresponding timing.
According to an embodiment of the present disclosure, the selection output logic unit 110 outputs result data according to the control of the timing control logic unit.
According to the embodiment of the disclosure, the order and the impulse response coefficient of the digital shaping filter are respectively written into the order reconstruction register unit and the impulse response coefficient register file unit, the digital shaping filter is reconstructed, the reconstruction completion flag register unit sends out signals when the reconstruction is completed, so that the digital shaping filter starts to calculate and select output logic unit selection result data to output through the time sequence control logic unit, the digital shaping filter can be quickly generated on the basis of not changing a hardware circuit in a reconstruction mode, hardware repeated design can be avoided in the selectable order range of the digital shaping filter, so that the technical problems that in the related art, after the design of the digital shaping filter is completed, the hardware structure is determined, the parameters need to be reselected when the characteristics of the digital shaping filter need to be changed, and then the hardware structure of the digital shaping filter is rearranged and wired, a great amount of time and resources are wasted are further reduced, the design cost is saved, and the designed hardware module has reusability are overcome.
According to an embodiment of the disclosure, the first adder unit is further configured to perform an addition operation on data stored in an mth data shift register and data stored in an nth data shift register of the plurality of data shift registers according to a folded circuit structure in a case where an order is 2i, where i is an integer greater than 0, M e [1, i ], N e [ i+1,2i ], M, N are integers, and m+n=2i+1.
Under the condition that the order is 2j-1, carrying out addition operation on data stored in an X-th data shift register and data stored in a Y-th data shift register in a plurality of data shift registers according to a folding circuit structure, wherein j is an integer greater than 0, X epsilon [1, j-1], Y epsilon [ j+1,2j-1], X, Y are integers, and X+Y=2j.
According to an embodiment of the present disclosure, for example, in the case where the order of the digital shaping filter is 6, data may be stored in the data shift register unit through 6 data shift registers, and then data stored in the 1 st data shift register and data stored in the 6 th data shift register are added by the first adder unit, data stored in the 2 nd data shift register and data stored in the 5 th data shift register are added, and data stored in the 3 rd data shift register and data stored in the 4 th data shift register are added to obtain three sets of data.
For another example, in the case where the order of the digital shaping filter is 7, data may be stored in the data shift register unit through 7 data shift registers, then the data stored in the 1 st data shift register and the data stored in the 7 th data shift register are added by the first adder unit, the data stored in the 2 nd data shift register and the data stored in the 6 th data shift register are added, and the data stored in the 3 rd data shift register and the data stored in the 5 th data shift register are added to obtain three sets of data.
According to an embodiment of the present disclosure, the multiplier unit is further configured to multiply data obtained by adding the first adder unit with the order of 2i with data of the impulse response coefficient register file unit.
And multiplying the data obtained by adding the first adder unit under the condition that the order is 2j-1 and the data in the j-th data shift register by the data of the impulse response coefficient register file unit.
According to an embodiment of the present disclosure, the data of the impulse response coefficient register file unit may be an impulse response coefficient.
According to the embodiment of the present disclosure, for example, in the case where the order of the digital shaping filter is 6, three times of multiplication operations are required to multiply the three sets of data in the first adder with the impulse response coefficients, respectively. If the data in the data shift register unit is directly multiplied by the impulse response coefficient without going through the folding circuit, six multiplication operations are required.
For another example, in the case where the order of the digital shaping filter is 7, it is necessary to perform four multiplication operations by multiplying three sets of data in the first adder by the impulse response coefficient and multiplying the data stored in the 4 th data shift register by the impulse response coefficient, respectively, by the multiplier unit. If the data in the data shift register unit is directly multiplied by the impulse response coefficient without going through the folding circuit, seven multiplication operations are required. Therefore, after the data shift register unit is subjected to addition operation through the folding circuit structure, half of multiplication operation logic resources are reduced, calculation resources are saved, and calculation efficiency is improved.
According to an embodiment of the present disclosure, the order reconstruction register unit is further configured to determine a maximum order of reconstruction of the digital shaping filter according to a hardware structure of the digital shaping filter.
According to the embodiment of the disclosure, the hardware structure of the digital shaping filter determines the maximum order that can be reconstructed, and the hardware structure of the digital shaping filter can be designed to be the maximum order and input to the order reconstruction register unit, so that the dynamic reconstruction of the order is realized in a range smaller than the maximum order, in theory, the larger the maximum order design of the digital shaping filter, the larger the selection range of the order is in the realization.
According to the embodiment of the disclosure, the data transmission mode of the folding circuit structure adopts a multi-stage data pipeline mode, wherein the first adder unit, the multiplier unit, the second adder unit and the selection output logic unit all comprise a register structure, so that the digital shaping filter can output result data in each clock cycle.
According to the embodiment of the disclosure, the first adder unit, the multiplier unit, the second adder unit and the selection output logic unit all comprise a register structure, so that the digital shaping filter can store data in each unit, and each unit can calculate in the same period in a multi-stage data pipeline mode adopted by the digital shaping filter, so that a new operation result is output in each clock period. The calculation efficiency of the digital shaping filter and the subsequent working speed of signal processing are improved.
According to an embodiment of the present disclosure, the digital shaping filter further includes:
the impulse response coefficient is quantized at fixed point, expressed by the following formula:
Wherein D 1 represents the impulse response coefficient after quantization, D 2 represents the impulse response coefficient before quantization, C is the quantization base, and K is the bit width of the quantization base.
According to the embodiment of the disclosure, when the fixed-point design is performed on the hardware circuit of the digital forming filter, the impact response coefficient needs to be quantized at fixed points, when the equivalent bit number is higher than 16 bits, the average value of quantization errors in the passband of the digital forming filter is smaller than 0.1, so that the design requirement can be met, in order to avoid unnecessary bit width waste, and simultaneously, the requirement on precision is ensured, the impact response coefficient can be quantized according to the following formula:
wherein D 1 represents the impulse response coefficient after quantization, D 2 represents the impulse response coefficient before quantization, C is the quantization base, the quantization base is the absolute value of the impulse response coefficient with the smallest absolute value among the impulse response coefficients, K is the bit width of the quantization base, and the wider the number of bits of the quantization base is, the greater the accuracy is.
According to an embodiment of the present disclosure, the data bit width stored by the order reconstruction register unit is configured to be determined from the digital shaping filter.
The impulse response coefficient register file unit stores a data bit width configured to be determined from the digital shaping filter.
The data shift register unit stores a data bit width configured to be the same as the data bit width outputted by the data redefinition logic unit.
The first adder unit stores a data bit width configured to be one bit more than the data bit width stored by the data shift register unit.
The data bit width stored by the multiplier unit is configured as the sum of the data bit width structure stored by the register in the first adder unit and the data bit width stored by the impulse response coefficient register file unit.
The second adder unit stores a data bit width configured to be determined by a bit width of the output data of the multiplier unit.
According to the embodiments of the present disclosure, the data bit width stored in the order reconstruction register unit and the data bit width stored in the impulse response coefficient register file unit may be set according to the characteristics and accuracy requirements of the digital shaping filter.
According to an embodiment of the present disclosure, the data bit width stored in the data shift register unit may be the same as the data bit width output by the data redefinition logic unit, for example, the data bit width output by the data redefinition logic unit is 2 bits, and the data bit width stored in the data shift register unit is also 2 bits.
According to an embodiment of the present disclosure, the data bit width stored by the first adder unit may be one bit more than the data bit width stored by the data shift register unit, for example, the data bit width stored by the data shift register unit is 2 bits, and the data bit width stored by the first adder unit may be 3 bits.
According to an embodiment of the present disclosure, the data bit width stored by the multiplier unit may be a sum of the data bit width stored by the impulse response coefficient register file unit and the register structure in the first adder unit.
According to an embodiment of the present disclosure, wherein the second adder unit stores a data bit width configured to be added by a bit width of the output data of the multiplier unitWhere H is the maximum order that the hardware structure of the shaping filter can support.
Fig. 2 schematically illustrates a flow chart of a method of designing an order dynamically reconfigurable folded circuit architecture digital shaping filter, in accordance with an embodiment of the present disclosure.
As shown in FIG. 2, the method includes operations S201-S205.
In operation S201, an impulse response coefficient and a reconfigurable order are determined according to a performance parameter of the digital shaping filter, and the impulse response coefficient is fixed-point quantized.
In operation S202, the fixed-point quantized impulse response coefficient and the order are input to the digital shaping filter.
In operation S203, the impulse response coefficient register file unit and the order reconstruction register unit are reconfigured according to the bit widths of the registers in the digital shaping filter.
In operation S204, the corresponding folded circuit structure is selected according to the order to calculate the result data.
In operation S205, result data is output.
According to the embodiment of the disclosure, the frequency response of the digital shaping filter meets the raised cosine characteristic, the Matlab can be used for generating the impulse response coefficient and the order of the corresponding characteristic, the digital shaping filter can be realized by a finite length unit impulse response (FIR) digital filter, when the Matlab is used for generating parameters, the fact that if the truncated length is L symbols, W sampling points (determined by the sampling rate) are taken in each symbol interval T, and LW sampling points are taken to represent the truncated impulse response of the filter. The truncated length L generated by rcosine functions of Matlab is generally 4-10 code elements, and L is required to meet the system performance requirement and the order of a filter is not too large so as to save resources.
According to an embodiment of the present disclosure, the order and impulse response coefficients of the digital shaping filter may be written into the order reconstruction register unit and the impulse response coefficient register file unit with a processor, and when the bit width of the written impulse response coefficient is smaller than the bit width of the designed impulse response coefficient register, the impulse response coefficient needs to be written into the high order bits of the impulse response coefficient register file unit, and the remaining low order bits need to be written with 0.
According to embodiments of the present disclosure, the corresponding folded circuit structure may be selected by parity determination of the data in the order reconstruction register.
According to the embodiment of the disclosure, the order and the impulse response coefficient of the digital shaping filter are respectively written into the order reconstruction register unit and the impulse response coefficient register file unit, the digital shaping filter is reconstructed, the reconstruction completion flag register unit sends out signals when the reconstruction is completed, so that the digital shaping filter starts to calculate and select output logic unit selection result data to output through the time sequence control logic unit, the digital shaping filter can be quickly generated on the basis of not changing a hardware circuit in a reconstruction mode, hardware repeated design can be avoided in the selectable order range of the digital shaping filter, so that the technical problems that in the related art, after the design of the digital shaping filter is completed, the hardware structure is determined, the parameters need to be reselected when the characteristics of the digital shaping filter need to be changed, and then the hardware structure of the digital shaping filter is rearranged and wired, a great amount of time and resources are wasted are further reduced, the design cost is saved, and the designed hardware module has reusability are overcome.
According to an embodiment of the present disclosure, selecting a corresponding folded circuit structure according to an order to calculate to obtain result data includes:
In the case of the order of 2i, the first adder unit performs an addition operation on the data stored in the mth data shift register and the data stored in the nth data shift register in the plurality of data shift registers according to the folding circuit structure, where i is an integer greater than 0, M e [1, i ], N e [ i+1,2i ], M, N are integers, and m+n=2i+1.
Under the condition that the order is 2j-1, the first adder unit performs addition operation on the data stored in the X-th data shift register and the data stored in the Y-th data shift register in the plurality of data shift registers according to the folding circuit structure, wherein j is an integer greater than 0, X epsilon [1, j-1], Y epsilon [ j+1,2j-1], X, Y are integers, and X+Y=2j.
According to an embodiment of the present disclosure, for example, in the case where the order of the digital shaping filter is 6, data may be stored in the data shift register unit through 6 data shift registers, and then data stored in the 1 st data shift register and data stored in the 6 th data shift register are added by the first adder unit, data stored in the 2 nd data shift register and data stored in the 5 th data shift register are added, and data stored in the 3 rd data shift register and data stored in the 4 th data shift register are added to obtain three sets of data.
For another example, in the case where the order of the digital shaping filter is 7, data may be stored in the data shift register unit through 7 data shift registers, then the data stored in the 1 st data shift register and the data stored in the 7 th data shift register are added by the first adder unit, the data stored in the 2 nd data shift register and the data stored in the 6 th data shift register are added, and the data stored in the 3 rd data shift register and the data stored in the 5 th data shift register are added to obtain three sets of data.
Fig. 3 schematically illustrates a flow chart of a method of designing an order dynamically reconfigurable folded circuit architecture digital shaping filter according to yet another embodiment of the present disclosure.
As shown in fig. 3, the method can be applied to a signal processing system, a data transmission system, and the like, and the method includes operations S301 to S310.
In operation S301, characteristic parameters of the digital shaping filter are extracted according to performance requirements of the system for the digital shaping filter.
In operation S302, an impulse response coefficient and an order corresponding to the characteristic parameter are generated by Matlab.
In operation S303, the impulse response coefficient is fixed-point quantized according to the accuracy requirement of the system.
In operation S304, bit widths of respective units of the digital shaping filter are determined and hardware system structural design is performed.
In operation S305, an order register unit and an impulse response coefficient register file unit are configured.
In operation S306, it is determined whether the order is even, and in the case where the order is determined to be even, operation S307 is performed, and in the case where the order is determined to be odd, operation S308 is performed.
In operation S307, a calculation is performed by the even-numbered corresponding folding circuit configuration.
In operation S308, a calculation is performed by the odd-numbered corresponding folding circuit structure.
In operation S309, it is determined whether the filter characteristics are changed after the parameter reconstruction is completed, and in the case where it is determined to change the filter characteristics, operation S305 is performed, and in the case where it is determined not to change the filter characteristics, operation S310 is performed.
In operation S310, the system outputs result data of the corresponding characteristics according to the configured parameters.
According to the embodiment of the disclosure, the characteristics of the digital shaping filter are changed by reconstructing the parameters of the digital shaping filter, so that the method is simple and flexible, the required digital shaping filter can be quickly generated on the basis of not changing a hardware circuit, the method can adapt to various systems with different frequencies and bandwidths, repeated design is avoided, resource waste is reduced, design cost is saved, and a hardware module has reusability.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams or flowchart illustration, and combinations of blocks in the block diagrams or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions. Those skilled in the art will appreciate that the features recited in the various embodiments of the disclosure and/or in the claims may be combined in various combinations and/or combinations, even if such combinations or combinations are not explicitly recited in the disclosure. In particular, the features recited in the various embodiments of the present disclosure and/or the claims may be variously combined and/or combined without departing from the spirit and teachings of the present disclosure. All such combinations and/or combinations fall within the scope of the present disclosure.
The embodiments of the present disclosure are described above. These examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.
Claims (8)
1. An order dynamically reconfigurable folded circuit architecture digital shaping filter comprising:
the data redefinition logic unit is used for carrying out bit width conversion on input data;
The data shift register unit is used for storing the output data of the data redefinition logic unit, wherein the data shift register unit comprises a plurality of data shift registers, and the output data of the data redefinition logic unit is sequentially stored in the plurality of data shift registers according to time sequence;
the first adder unit is used for carrying out addition operation on the output data of the data shift register unit according to the folding circuit structure;
An impulse response coefficient register file unit for writing the impulse response coefficient of the digital shaping filter;
A reconstruction completion flag register unit for sending out a reconstruction completion signal in case the order reconstruction register unit completes the reconstruction;
A multiplier unit, configured to multiply output data of the first adder unit according to the order and receive an output signal of the reconstruction completion flag register unit;
a second adder unit configured to perform an addition operation on output data of the multiplier unit when the multiplier unit receives the reconstruction completion signal;
an order reconstruction register unit for writing an order of the digital shaping filter;
The time sequence control logic unit is used for controlling the selection output logic unit to select result data according to the order reconstruction register unit;
The selection output logic unit is used for outputting the result data according to the control of the time sequence control logic unit;
The first adder unit is further configured to perform an addition operation on data stored in an mth data shift register and data stored in an nth data shift register of the plurality of data shift registers according to the folding circuit structure in the case where the order is 2i, where i is an integer greater than 0, ,M, N are integers, and M+N=2i+1, and
In the case that the order is 2j-1, adding the data stored in the X-th data shift register and the data stored in the Y-th data shift register of the plurality of data shift registers according to the folding circuit structure, wherein j is an integer greater than 0,,X, Y are integers, and x+y=2j.
2. The digital shaping filter of claim 1,
The multiplier unit is also used for multiplying the data obtained by the first adder unit by the data obtained by the addition operation under the condition that the order is 2i and the data of the impulse response coefficient register file unit, and
And multiplying the data obtained by adding the first adder unit under the condition that the order is 2j-1 and the data in the j-th data shift register by the data of the impulse response coefficient register file unit.
3. The digital shaping filter of claim 1,
The order reconstruction register unit is further configured to determine a maximum order of reconstruction of the digital shaping filter according to a hardware structure of the digital shaping filter.
4. A digital shaping filter according to claim 1 to 3,
The data transmission mode of the folding circuit structure adopts a multi-stage data pipeline mode, wherein the first adder unit, the multiplier unit, the second adder unit and the selection output logic unit all comprise a register structure, so that the digital shaping filter can output the result data in each clock cycle.
5. A digital shaping filter according to any of claims 1 to 3, further comprising:
and carrying out fixed-point quantization on the impact response coefficient, wherein the fixed-point quantization is represented by the following formula:
(1)
wherein, the Representing the quantized impulse response coefficients,The impulse response coefficient before quantization is represented, C is the quantization base, and K is the bit width of the quantization base.
6. A digital shaping filter according to claim 1 to 3,
The order reconstruction register unit stores a data bit width configured to be determined from the digital shaping filter;
the impulse response coefficient register file unit stores data bit widths configured to be determined from the digital shaping filter;
the data bit width stored by the data shift register unit is configured to be the same as the data bit width output by the data redefinition logic unit;
The first adder unit stores data bit width configured to be one bit more than the data bit width stored by the data shift register unit;
The data bit width stored by the multiplier unit is configured as the sum of the data bit width stored by the register in the first adder unit and the data bit width stored by the impulse response coefficient register file unit;
The second adder unit stores a data bit width configured to be determined by a bit width of output data of the multiplier unit.
7. The digital shaping filter according to claim 6, wherein the data bit width stored by the second adder unit is configured to be added by the bit width of the output data of the multiplier unitWherein H is the maximum order that can be supported by the hardware structure of the shaping filter.
8. A design method of an order dynamic reconfigurable folding circuit structure digital shaping filter comprises the following steps:
Determining an impulse response coefficient and a reconfigurable order according to the performance parameters of the digital shaping filter, and carrying out fixed-point quantization on the impulse response coefficient;
Inputting the impact response coefficient after fixed-point quantization and the order into the digital shaping filter;
reconstructing and configuring an impulse response coefficient register file unit and an order reconstruction register unit according to the bit width of a register in the digital shaping filter, wherein the impulse response coefficient register file unit is configured to write an impulse response coefficient of the digital shaping filter, and the order reconstruction register unit is configured to write an order of the digital shaping filter;
selecting a corresponding folding circuit structure according to the order to calculate to obtain result data;
outputting the result data;
The step of selecting the corresponding folding circuit structure according to the order to calculate to obtain result data includes:
in the case of the order of 2i, adding the data stored in the mth data shift register and the data stored in the nth data shift register of the plurality of data shift registers according to the folding circuit structure by using a first adder unit, wherein i is an integer greater than 0, ,M, N are integers, and M+N=2i+1, and
And adding the data stored in the X-th data shift register and the data stored in the Y-th data shift register in the plurality of data shift registers according to the folding circuit structure by using a first adder unit under the condition that the order is 2j-1, wherein j is an integer greater than 0,,X, Y are integers, and x+y=2j.
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