CN115285927A - Structure and process of sealing multi-layer vacuum cavity by CVD for MEMS chip - Google Patents

Abstract

A multi-layer vacuum cavity structure sealed by CVD for a MEMS chip, wherein: the substrate is a wafer structure, a first layer of silicon is grown on a first oxide layer by CVD or epitaxy, and a second layer is formed on the second oxide layer Silicon layer; through holes are provided on the second silicon layer to form a low vacuum chamber and a high vacuum chamber, and multiple chambers are provided. During the CVD process, inert gas is introduced, and the low vacuum chamber is The chamber is formed in a high pressure or normal pressure state. A process for sealing a multi-layer vacuum cavity structure of a MEMS chip by CVD, comprising the steps of: opening a hole on a second silicon layer through a photolithography and etching process, and forming a low vacuum chamber and a high vacuum chamber through a gaseous HF etching process Vacuum degree chamber; the advantages of the present invention: using different vacuum degrees to prepare micro-chambers, and sealing the micro-chambers through different CVD deposition techniques, so as to achieve multi-chamber, different vacuum degree states, and It can also effectively reduce the chip area and reduce the cost.

Description

A CVD-sealed multi-layer vacuum chamber structure and process for MEMS chips

technical field

The invention relates to the fields of sensors and the like, in particular to a CVD-sealed multilayer vacuum chamber structure and process for MEMS chips.

Background technique

At present, the technology used for multi-chamber MEMS devices is to etch multiple chambers on the cover wafer, and then use the wafer bonding process to bond the cover wafer and the device wafer together to form multiple Chambers with different vacuum levels. The chip area using the wafer bonding process will increase, which is not conducive to low-cost production.

Contents of the invention

The object of the present invention is to overcome the above-mentioned problems, and provides a CVD-sealed multi-layer vacuum chamber structure and process for MEMS chips.

The invention provides a CVD-sealed multi-layer vacuum cavity structure for MEMS chips, which is characterized in that: the CVD-sealed multi-layer vacuum cavity structure for MEMS chips includes a substrate 1, a first layer of oxide layer 2, a first layer of Silicon layer 3, second oxide layer 4, second silicon layer 5, low vacuum chamber 6, high vacuum chamber 7, first sealing structure 8, second sealing structure 9;

Wherein: the substrate 1 is a wafer structure, and the first oxide layer 2 is grown on the substrate 1 through an oxidation process;

The first layer of silicon layer 3 is grown on the first layer of oxide layer 2 by CVD or epitaxy, and the structure required by the device is formed by using photolithography and etching processes;

The first layer of silicon layer 3 is a polysilicon or single crystal silicon layer, and there is a second layer of oxide layer 4 on the first layer of silicon layer 3; a second layer of silicon layer 5 is grown on the second layer of oxide layer 4 by CVD or epitaxial process;

The second layer of silicon layer 5 is provided with a through hole, and a low vacuum chamber 6 and a high vacuum chamber 7 are formed through a gaseous HF etching process, and a plurality of chambers are provided;

Through the first CVD process on the second silicon layer 5, the oxide layer grown by CVD is used to form the first plugging structure 8 for the through hole with a smaller size. Degree chamber 6 forms the chamber of high pressure or normal pressure state;

A second CVD process is performed on the second silicon layer 5 , and the remaining through holes are formed by using the CVD-grown oxide layer to form a second plugging structure 9 .

A kind of technology that MEMS chip uses CVD sealing multi-layer vacuum chamber structure, comprises the steps:

Step 1: The substrate 1 has a wafer structure, the first oxide layer 2 is a sacrificial layer and an insulating layer, and the first oxide layer 2 is grown on the substrate 1 through an oxidation process;

Step 2: The first silicon layer 3 is grown on the first oxide layer 2 by CVD or epitaxy, and the required structure of the device is formed by photolithography and etching processes;

Step 3: growing a second oxide layer 4 on the first silicon layer 3 by including but not limited to an oxidation process;

Step 4: Etch the desired shape of the device on the second oxide layer 4 by photolithography and etching process;

Step 5: growing a second silicon layer 5 on the second oxide layer 4 by CVD or epitaxial process;

Step 6: Open holes on the second silicon layer 5 through photolithography and etching processes, and form a low vacuum chamber 6 and a high vacuum chamber 7 through a gaseous HF etching process; each chamber is different according to its purpose. The size of the opening of the chamber is also different;

Step 7: Through the first CVD process on the second silicon layer 5, use the CVD-grown oxide layer, that is, the first plugging structure 8, for the through-holes with relatively small size. During the CVD process, inject inert gas , the low-vacuum chamber 6 forms a chamber in a high-pressure or normal-pressure state, and the through-holes with larger sizes are not sealed in this process;

Step 8: Carry out a second CVD process on the second silicon layer 5, and use the oxide layer grown by CVD to form the second plugging structure 9 for the remaining through holes with relatively large sizes;

During the CVD process, a vacuum is drawn and a reactive gas is introduced to ensure that a vacuum or a low-pressure state is formed inside the high-vacuum chamber 7 .

The substrate 1 is a silicon wafer.

In the CVD process performed on the second silicon layer 5, the oxide layer grown by CVD is silicon oxide, silicon nitride and silicon oxynitride.

The first silicon layer 3 and the second silicon layer 5 are polycrystalline silicon or single crystal silicon layers.

The main purpose of sealing twice is to form chambers with different vacuum degrees through different processes.

The multi-chamber structure applied in the field of MEMS devices. The vacuum levels of the chambers of this multi-chamber structure can be different vacuum levels. This structure is widely used in MEMS inertial sensors, MEMS infrared sensors, radio frequency sensors and other fields.

Advantages of the present invention:

The MEMS chip of the present invention uses CVD to seal the multi-layer vacuum chamber structure and process, and adopts different methods to form the specific structure. The microchambers are prepared under the conditions of different vacuum degrees, and the microchambers are sealed by different CVD deposition techniques. In this way, the state of multi-chambers and different vacuum degrees can be achieved, and the chip area can be effectively reduced, and the cost can be reduced.

Description of drawings

Below in conjunction with accompanying drawing and embodiment the present invention is described in further detail:

Figure 1 is a schematic diagram of the structure of a CVD-sealed multilayer vacuum chamber for MEMS chips;

Fig. 2 is a schematic diagram of the structure after step one;

Fig. 3 is after step 2, structural representation;

Fig. 4 is a structural schematic diagram after step three;

Fig. 5 is a structural schematic diagram after step four;

Fig. 6 is a structural schematic diagram after step five;

Fig. 7 is a structural schematic diagram after step six;

Fig. 8 is a structural schematic diagram after step seven;

Fig. 9 is a schematic diagram of the structure after step eight.

Detailed ways

Example 1

The invention provides a CVD-sealed multi-layer vacuum cavity structure for MEMS chips, which is characterized in that: the CVD-sealed multi-layer vacuum cavity structure for MEMS chips includes a substrate 1, a first layer of oxide layer 2, a first layer of Silicon layer 3, second oxide layer 4, second silicon layer 5, low vacuum chamber 6, high vacuum chamber 7, first sealing structure 8, second sealing structure 9;

Wherein: the substrate 1 is a wafer structure, and the first oxide layer 2 is grown on the substrate 1 through an oxidation process;

The first layer of silicon layer 3 is grown on the first layer of oxide layer 2 by CVD or epitaxy, and the structure required by the device is formed by using photolithography and etching processes;

The first layer of silicon layer 3 is a polysilicon or single crystal silicon layer, and there is a second layer of oxide layer 4 on the first layer of silicon layer 3; a second layer of silicon layer 5 is grown on the second layer of oxide layer 4 by CVD or epitaxial process;

The second layer of silicon layer 5 is provided with a through hole, and a low vacuum chamber 6 and a high vacuum chamber 7 are formed through a gaseous HF etching process, and a plurality of chambers are provided;

Through the first CVD process on the second silicon layer 5, the oxide layer grown by CVD is used to form the first plugging structure 8 for the through hole with a smaller size. Degree chamber 6 forms the chamber of high pressure or normal pressure state;

A second CVD process is performed on the second silicon layer 5 , and the remaining through holes are formed by using the CVD-grown oxide layer to form a second plugging structure 9 .

A kind of technology that MEMS chip uses CVD sealing multi-layer vacuum chamber structure, comprises the steps:

Step 1: The substrate 1 has a wafer structure, the first oxide layer 2 is a sacrificial layer and an insulating layer, and the first oxide layer 2 is grown on the substrate 1 through an oxidation process;

Step 2: The first silicon layer 3 is grown on the first oxide layer 2 by CVD or epitaxy, and the required structure of the device is formed by photolithography and etching processes;

Step 3: growing a second oxide layer 4 on the first silicon layer 3 by including but not limited to an oxidation process;

Step 4: Etch the desired shape of the device on the second oxide layer 4 by photolithography and etching process;

Step 5: growing a second silicon layer 5 on the second oxide layer 4 by CVD or epitaxial process;

Step 6: Open holes on the second silicon layer 5 through photolithography and etching processes, and form a low vacuum chamber 6 and a high vacuum chamber 7 through a gaseous HF etching process; each chamber is different according to its purpose. The size of the opening of the chamber is also different;

Step 7: Through the first CVD process on the second silicon layer 5, use the CVD-grown oxide layer, that is, the first plugging structure 8, for the through-holes with relatively small size. During the CVD process, inject inert gas , the low-vacuum chamber 6 forms a chamber in a high-pressure or normal-pressure state, and the through-holes with larger sizes are not sealed in this process;

Step 8: Carry out a second CVD process on the second silicon layer 5, and use the oxide layer grown by CVD to form the second plugging structure 9 for the remaining through holes with relatively large sizes;

During the CVD process, a vacuum is drawn and a reactive gas is introduced to ensure that a vacuum or a low-pressure state is formed inside the high-vacuum chamber 7 .

The substrate 1 is a silicon wafer.

In the CVD process performed on the second silicon layer 5, the oxide layer grown by CVD is silicon oxide, silicon nitride and silicon oxynitride.

The first silicon layer 3 and the second silicon layer 5 are polycrystalline silicon or single crystal silicon layers.

The main purpose of sealing twice is to form chambers with different vacuum degrees through different processes.

Example 2

The invention provides a CVD-sealed multi-layer vacuum cavity structure for MEMS chips, which is characterized in that: the CVD-sealed multi-layer vacuum cavity structure for MEMS chips includes a substrate 1, a first layer of oxide layer 2, a first layer of Silicon layer 3, second oxide layer 4, second silicon layer 5, low vacuum chamber 6, high vacuum chamber 7, first sealing structure 8, second sealing structure 9;

Wherein: the substrate 1 is a wafer structure, and the first oxide layer 2 is grown on the substrate 1 through an oxidation process;

The first layer of silicon layer 3 is grown on the first layer of oxide layer 2 by CVD or epitaxy, and the structure required by the device is formed by using photolithography and etching processes;

The first layer of silicon layer 3 is a polysilicon or single crystal silicon layer, and there is a second layer of oxide layer 4 on the first layer of silicon layer 3; a second layer of silicon layer 5 is grown on the second layer of oxide layer 4 by CVD or epitaxial process;

The second layer of silicon layer 5 is provided with a through hole, and a low vacuum chamber 6 and a high vacuum chamber 7 are formed through a gaseous HF etching process, and a plurality of chambers are provided;

Through the first CVD process on the second silicon layer 5, the oxide layer grown by CVD is used to form the first plugging structure 8 for the through hole with a smaller size. Degree chamber 6 forms the chamber of high pressure or normal pressure state;

A second CVD process is performed on the second silicon layer 5 , and the remaining through holes are formed by using the CVD-grown oxide layer to form a second plugging structure 9 .

A kind of technology that MEMS chip uses CVD sealing multi-layer vacuum chamber structure, comprises the steps:

Step 1: The substrate 1 has a wafer structure, the first oxide layer 2 is a sacrificial layer and an insulating layer, and the first oxide layer 2 is grown on the substrate 1 through an oxidation process;

Step 2: The first silicon layer 3 is grown on the first oxide layer 2 by CVD or epitaxy, and the required structure of the device is formed by photolithography and etching processes;

Step 3: growing a second oxide layer 4 on the first silicon layer 3 by including but not limited to an oxidation process;

Step 4: Etch the desired shape of the device on the second oxide layer 4 by photolithography and etching process;

Step 5: growing a second silicon layer 5 on the second oxide layer 4 by CVD or epitaxial process;

Step 6: Open holes on the second silicon layer 5 through photolithography and etching processes, and form a low vacuum chamber 6 and a high vacuum chamber 7 through a gaseous HF etching process; each chamber is different according to its purpose. The size of the opening of the chamber is also different;

Step 7: Through the first CVD process on the second silicon layer 5, use the CVD-grown oxide layer, that is, the first plugging structure 8, for the through-holes with relatively small size. During the CVD process, inject inert gas , the low-vacuum chamber 6 forms a chamber in a high-pressure or normal-pressure state, and the through-holes with larger sizes are not sealed in this process;

Step 8: Carry out a second CVD process on the second silicon layer 5, and use the oxide layer grown by CVD to form the second plugging structure 9 for the remaining through holes with relatively large sizes;

During the CVD process, a vacuum is drawn and a reactive gas is introduced to ensure that a vacuum or a low-pressure state is formed inside the high-vacuum chamber 7 .

The main purpose of sealing twice is to form chambers with different vacuum degrees through different processes.

Matters not covered in the present invention are known technologies.

The above-mentioned embodiments are only to illustrate the technical concept and characteristics of the present invention, and the purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly, and not to limit the protection scope of the present invention. All equivalent changes or modifications made according to the spirit of the present invention shall fall within the protection scope of the present invention.

Claims (5)

1. A CVD seals multilayer vacuum cavity structure for MEMS chip which characterized in that: the CVD sealed multilayer vacuum cavity structure for the MEMS chip comprises a substrate (1), a first oxide layer (2), a first silicon layer (3), a second oxide layer (4), a second silicon layer (5), a low-vacuum-degree cavity (6), a high-vacuum-degree cavity (7), a first blocking structure (8) and a second blocking structure (9);

wherein: the substrate (1) is of a wafer structure, and the first oxide layer (2) grows on the substrate (1) through an oxidation process;

growing a first silicon layer (3) on the first oxide layer (2) through CVD or epitaxy, and forming a structure required by a device by utilizing photoetching and etching processes;

the first silicon layer (3) is a polycrystalline silicon layer or a monocrystalline silicon layer, and a second oxide layer (4) is arranged on the first silicon layer (3); a second silicon layer (5) is grown on the second oxide layer (4) through a CVD or epitaxial process;

a through hole is formed in the second silicon layer (5), and a low-vacuum-degree cavity (6) and a high-vacuum-degree cavity (7) are formed through a gaseous HF corrosion process and are provided with a plurality of cavities;

forming a first blocking structure (8) on the second silicon layer (5) through a first CVD (chemical vapor deposition) process by using an oxide layer grown by CVD of the through hole with a smaller size, introducing inert gas in the CVD process, and forming a chamber with a high pressure or normal pressure state in the low vacuum degree chamber (6);

and carrying out a second CVD process on the second silicon layer (5), and forming a second blocking structure (9) by using the CVD grown oxide layer of the residual through hole.

2. The process for sealing a multilayer vacuum chamber structure by CVD for MEMS chip of claim 1, wherein: the process for sealing the multilayer vacuum cavity structure by using the CVD for the MEMS chip comprises the following steps:

the method comprises the following steps: the substrate (1) is of a wafer structure, the first oxide layer (2) is a sacrificial layer and an insulating layer, and the first oxide layer (2) grows on the substrate (1) through an oxidation process;

step two: growing a first silicon layer (3) on the first oxide layer (2) through CVD or epitaxy, and forming a structure required by the device through photoetching and etching processes;

step three: growing a second oxide layer (4) on the first silicon layer (3) by an oxidation process including but not limited to;

step four; etching the shape required by the device on the second oxide layer (4) by photoetching and etching processes;

step five: growing a second silicon layer (5) on the second oxide layer (4) by CVD or epitaxial process;

step six: forming a through hole on the second silicon layer (5) through photoetching and etching processes, and forming a low vacuum degree cavity (6) and a high vacuum degree cavity (7) through a gaseous HF corrosion process; each chamber is different according to the application, and the size of the through hole of the chamber is also different;

step seven: an oxide layer which grows through the through holes with relatively small sizes by means of CVD (chemical vapor deposition) is a first blocking structure (8) on the second silicon layer (5) through a first CVD (chemical vapor deposition) process, inert gas is introduced in the CVD process, a chamber with high pressure or normal pressure is formed in the low-vacuum-degree chamber (6), and the through holes with large sizes are not blocked in the process;

step eight: carrying out a second CVD process on the second silicon layer (5), and forming a second blocking structure (9) by using an oxide layer grown by CVD for the through hole with a relatively large residual size;

in the CVD process, vacuum pumping is carried out, and reactive gas is introduced to ensure that the inside of the high vacuum degree chamber (7) is in a vacuum or low pressure state.

3. The process for sealing a multilayer vacuum chamber structure by CVD for a MEMS chip according to claim 2, wherein: the substrate (1) is a silicon wafer.

4. The process for sealing a multilayer vacuum chamber structure by CVD for a MEMS chip according to claim 2, wherein: the CVD process carried out on the second silicon layer (5) utilizes CVD to grow oxide layers of silicon oxide, silicon nitride and silicon oxynitride.

5. The process for sealing a multilayer vacuum chamber structure by CVD for a MEMS chip according to claim 2, wherein: the first silicon layer (3) and the second silicon layer (5) are polysilicon or monocrystalline silicon layers.

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