CN115309337A - Memory operation method, memory and memory system - Google Patents

Abstract

Embodiments of the present invention provide a method for operating a memory, a memory, and a storage system. Wherein, the memory includes: a plurality of storage planes; and a peripheral circuit coupled with the storage planes, wherein; the peripheral circuit includes: a buffer device coupled between the first storage plane and the second storage plane, Wherein, the buffer device is configured to read the first data from the first storage plane and transmit the first data to the second storage plane; or read the second data from the second storage plane , and transmit the second data to the first storage plane; wherein, the first storage plane and the second storage plane are any two storage planes in the plurality of storage planes.

Description

Method for operating memory, memory and storage system

technical field

The present invention relates to the technical field of memory, in particular to a method for operating a memory, a memory and a storage system.

Background technique

Recently, with the development of memory, memory may be volatile or nonvolatile. Non-volatile memory, capable of retaining data even when power is not applied, has become widely used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices. According to the structural configuration of the storage array contained in the memory, the memory can be classified into a single storage plane (Plane) type and a multi storage plane (Plane) type. A single-plane type memory includes memory arrays arranged in a single plane, and a multi-plane type memory includes memory arrays arranged in multiple planes. At present, the data transmission between planes in the memory needs to be realized by the memory control coupled with the memory, and the existing circuit design cannot support the data transmission between the storage planes (Planes) inside the memory.

Contents of the invention

In view of this, the present invention provides a memory operation method, memory and storage system, in which a buffer device is added in the peripheral circuit of the memory, and the buffer device is coupled between the first storage plane and the second storage plane of the memory, so The buffer device can be used to read data from the first storage plane and transfer to the second storage plane, or to read data from the second storage plane and transfer to the first storage plane.

In order to achieve the above object, technical solution of the present invention is achieved in that way:

In a first aspect, an embodiment of the present invention provides a memory, including:

comprising: a plurality of storage planes; and peripheral circuits coupled to the storage planes, wherein;

The peripheral circuit includes: a buffer device coupled between the first storage plane and the second storage plane, wherein the buffer device is used to read the first data from the first storage plane and send the first data to the second storage plane. transferring the first data to two storage planes; or, reading second data from the second storage plane, and transmitting the second data to the first storage plane;

Wherein, the first storage plane and the second storage plane are any two storage planes among the plurality of storage planes.

In the above solution, the buffer device includes a clock buffer component, a first buffer component corresponding to the first storage plane, a second buffer component corresponding to the second storage plane, and a conversion buffer component, wherein;

The clock buffer component is configured to receive an original clock signal and a first read enable signal of the first storage plane; when the first read enable signal is valid, generate the original clock signal based on the original clock signal The first sub-input clock signal of the first storage plane; sending the first sub-input clock signal to the first buffer component;

A first buffer component, coupled to the clock buffer component, for receiving the first read enable signal and the first sub-input clock signal; when the first read enable signal is valid, based on The first sub-input clock signal outputs a first output signal; transmits the first output signal to the conversion buffer; the first output signal includes a first output clock signal, a first data signal, first address signal;

The conversion buffer component is configured to receive the first output signal, the first read enable signal, and the first write enable signal of the second storage plane; signal and the first write enable signal are valid, convert the first output clock signal, the first data signal, and the first address signal included in the first output signal into the second The first input signal of the storage plane; the first input signal includes: a first input clock signal, a second data signal used to represent the first data, and a second address signal; and transmits the second address signal to the second buffer component the first input signal;

The second buffer component is configured to receive the first input signal and the first write enable signal; when the first write enable signal is valid, based on the first input clock signal generating a first write clock signal; generating a first write address based on the second address signal; generating the first data based on the second data signal; Data is written at the first write address of the second storage plane.

In the above solution, the clock buffer is also coupled to the second buffer component, and is used to receive the original clock signal and the second read enable signal of the second storage plane; 2. When the read enable signal is valid, generate a second sub-input clock signal based on the original clock signal; send the second sub-input clock signal to the second buffer component;

The second buffer component is configured to receive the second read enable signal and the second sub-input clock signal; when the second read enable signal is valid, based on the second sub-input clock Signal outputs a second output signal; transmits the second output signal to the conversion buffer; the second output signal includes a second output clock signal, a third data signal representing the second data, a third address signal;

The conversion buffer component is configured to receive the second output signal, the second read enable signal and the second write enable signal of the first storage plane; When the second write enable signal is valid, convert the second output clock signal, the second data signal, and the third address signal included in the second output signal into the first storage plane The second input signal of the second input signal; the second input signal includes a second input clock signal, a fourth data signal and a fourth address signal for representing the second data; the second input signal is transmitted to the first buffer component input signal;

The first buffer component is configured to receive the second input signal and the second write enable signal; when the second write enable signal is valid, generate a second input clock signal based on the second input clock signal Two write clock signals; generate a second write address based on the fourth address signal; generate the second data based on the fourth data signal; write the second data based on the second write clock signal into the second write address of the first storage plane.

In the above solution, the clock buffer component includes: a first tri-state buffer and a second tri-state buffer, wherein;

The input end of the first tri-state buffer and the input end of the second tri-state buffer are connected to the original clock signal;

The enable terminal of the first tri-state buffer is connected to the first read enable signal, and the output terminal outputs the first sub-input clock signal;

The enable terminal of the second tri-state buffer is connected to the second read enable signal, and the output terminal outputs the second sub-input clock signal.

In the above solution, the first buffer assembly includes: a first buffer group, a second buffer group and a third buffer group, wherein;

The first buffer group includes a first clock buffer; the first clock buffer is used to access the first sub-input clock signal and a first read enable signal; When the enable signal is valid, generate a first output clock signal based on the first sub-input clock signal; transmit the first output clock signal to the conversion buffer component;

The second buffer group includes a first data buffer; the first data buffer is used to access the first read enable signal and first data; When the signal is valid, generate the first data signal based on the first data; transmit the first data signal to the conversion buffer component; the first data is based on the first sub-input clock signal from the read at the first read address of the first storage plane;

The third buffer group includes a first address buffer; the first address buffer is used to access the first read enable signal and a first read address; When the enable signal is valid, generate the first address signal based on the first read address; transmit the first address signal to the conversion buffer component.

In the above solution, the first buffer group further includes a second clock buffer; the second clock buffer is used to receive the second write enable signal and the second input clock signal; in the generating the second write clock signal based on the second input clock signal when the second write enable signal is valid;

The third buffer group also includes a second address buffer; the second address buffer is used to receive the second write enable signal and the fourth address signal; generating a second write address based on the fourth address signal when the enable signal is valid;

The second buffer group also includes a second data buffer; the second data buffer is used to receive the fourth data signal and the second write enable signal; When the enable signal is valid, generating the second data based on the fourth data signal; writing the second data into the first storage plane based on the second write clock signal address.

In the solution above, the structure of the second buffer component is the same as that of the first buffer component.

In the above solution, the conversion buffer component includes: a clock conversion group, an address conversion group and a data conversion group, wherein;

The clock conversion group is used to receive the first output clock signal, the first read enable signal and the first write enable signal; the first read enable signal and the first write enable signal When the first write enable signals are all valid, generate the first input clock signal based on the first output clock signal; transmit the first input clock signal to the second buffer component;

The address conversion group is used to receive the first address signal, the first read enable signal and the first write enable signal; When both write enable signals are valid, generate the second address signal based on the first address signal; transmit the second address signal to the second buffer component;

The data conversion group is used to receive the first data signal, the first read enable signal and the first write enable signal; When both write enable signals are valid, generate the second data signal based on the first data signal; transmit the second data signal to the second buffer component.

In the above solution, the clock conversion group is also used to receive the second output clock signal, the second read enable signal and the second write enable signal; When both the enable signal and the second write enable signal are valid, generate the second input clock signal based on the second output clock signal; transmit the second input clock signal to the first buffer component;

The address conversion group is used to receive the third address signal, the second read enable signal and the second write enable signal; When both write enable signals are valid, generate the fourth address signal based on the third address signal; transmit the fourth address signal to the first buffer component;

The data conversion group is used to receive the third data signal, the second read enable signal and the second write enable signal; When both write enable signals are valid, generate the fourth data signal based on the third data signal; transmit the fourth data signal to the first buffer component.

In the above scheme, the clock conversion group includes: a first group of buffers and a second group of buffers; the first group of buffers includes a third tri-state buffer and a fourth tri-state buffer; the first group of buffers The two groups of buffers include a fifth tri-state buffer and a sixth tri-state buffer;

Wherein, the input end of the third tri-state buffer is connected to the output end of the fourth tri-state buffer; the output end of the third tri-state buffer is connected to the input end of the fourth tri-state buffer connected; the enable end of the third tri-state buffer is connected to the first read enable signal; the enable end of the fourth tri-state buffer is connected to the second write enable signal;

The input end of the third tri-state buffer, the output end of the fourth tri-state buffer, the input end of the fifth tri-state buffer, and the output end of the sixth tri-state buffer are connected;

The output end of the fifth tri-state buffer is connected to the input of the sixth tri-state buffer; the enable end of the fifth tri-state buffer is connected to the second read enable signal; the The enable terminal of the sixth tri-state buffer is connected to the first write enable signal.

In the above solution, the structures of the address conversion group and the data conversion group are the same as the clock conversion group.

In the above solution, the peripheral circuit also includes an I/O interface and a control logic unit, wherein,

The control logic unit is configured to receive a first command through the I/O interface; based on the first command, control the buffer device to read first data from the first storage plane, and send data to the second storage plane. transfer the first data to the first storage plane; or read the second data from the second storage plane and transfer the second data to the first storage plane.

In the second aspect, an embodiment of the present invention provides a memory operation method, which is applied to the memory including peripheral circuits, and the operation method includes:

receiving the first command;

Based on the first command, read the first data from the first storage plane, and transfer the first data to the second storage plane; or, read the second data from the second storage plane, and transfer the first data to the first storage plane. transmitting said second data face-to-face;

Wherein, the first storage plane and the second storage plane are any two storage planes among the plurality of storage planes included in the memory.

In the above solution, reading the first data from the first storage plane based on the first command, and transmitting the first data to the second storage plane includes:

Obtaining a first read enable signal based on the first command; receiving an original clock signal;

When the first read enable signal is valid, a first sub-input clock signal is generated based on the original clock signal; a first output signal is based on the first sub-input clock signal; the first output signal includes a first outputting a clock signal, a first data signal for representing first data, and a first address signal;

When the first read enable signal and the first write enable signal of the second storage plane are valid, the first output clock signal included in the first output signal, the first data signal, the first address signal is converted into the first input signal of the second storage plane; the first input signal includes: a first input clock signal, a second data signal used to represent the first data, a second address signal; the first write enable signal is obtained based on the first command;

When the first write enable signal is valid, generate a first write clock signal based on the first input clock signal; generate a first write address based on the second address signal; generate a first write address based on the second data signal generating the first data; writing the first data at the first write address of the second storage plane based on the first write clock signal.

In the above scheme,

Reading the second data from the second storage plane based on the first command, and transmitting the second data to the first storage plane, includes:

deriving a second read enable signal based on the first command; and receiving an original clock signal;

generating a second sub-input clock signal based on the original clock signal when the second read enable signal is valid;

outputting a second output signal based on the second sub-input clock signal; the second output signal includes a second output clock signal, a third data signal representing the second data, and a third address signal;

When the second read enable signal and the second write enable signal of the first storage plane are valid, the second output clock signal contained in the second output signal, the second data signal, the third address signal is converted into a second input signal of the first storage plane; the second input signal includes a second input clock signal, a fourth data signal representing the second data, and a second input signal Four address signals; the second write enable signal is obtained based on the first command;

When the second write enable signal is valid, generate a second write clock signal based on the second input clock signal; generate a second write address based on the fourth address signal; generate a second write address based on the fourth data signal generating the second data; writing the second data at the second write address of the first storage plane based on the second write clock signal.

In a third aspect, an embodiment of the present invention further provides a storage system, including: one or more of the above-mentioned memories; and a memory controller coupled to the memories; the memory controller is configured to: send Various operation commands.

In the solution above, the storage system is a solid state disk or a memory card.

Embodiments of the present invention provide a method for operating a memory, a memory, and a storage system. Wherein, the memory includes: a plurality of storage planes; and a peripheral circuit coupled to the storage planes, wherein; the peripheral circuit includes: a buffer device coupled between the first storage plane and the second storage plane, Wherein, the buffer device is configured to read the first data from the first storage plane, and transmit the first data to the second storage plane; or, read the second data from the second storage plane , transmitting the second data to the first storage plane; wherein, the first storage plane and the second storage plane are any two storage planes among the plurality of storage planes. In the memory provided by the embodiment of the present invention, a buffer device is provided between the storage planes, and the buffer device is used to transfer the data of one storage plane to the other storage plane without using a coupled memory controller. Direct data transmission between internal storage planes is convenient and fast.

Description of drawings

Aspects of the invention are best understood from the following detailed description when read with the accompanying figures. Note that, in accordance with the standard practice in industry assembly, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

FIG. 1 shows a block diagram of an exemplary system with a memory in the related art;

Figure 2 shows a schematic diagram of an exemplary memory card with memory;

Figure 3 shows a schematic diagram of an exemplary solid-state drive (SSD) with memory;

4 shows a schematic diagram of an exemplary memory including peripheral circuits;

FIG. 5 shows a schematic diagram of an organizational structure of a storage array contained in a memory;

Figure 6 shows a side view of a cross-section of an exemplary memory array comprising NAND memory strings;

7 shows a block diagram of an exemplary memory including a memory array and peripheral circuits;

FIG. 8 shows a schematic structural diagram of a memory provided by an embodiment of the present invention;

Fig. 9 shows a schematic structural diagram of a buffer device provided by an embodiment of the present invention;

FIG. 10 shows a schematic structural diagram of a clock buffer component provided by an embodiment of the present invention;

Fig. 11 shows a schematic structural diagram of a first buffer assembly provided by an embodiment of the present invention;

Fig. 12 shows a schematic structural diagram of a conversion buffer assembly provided by an embodiment of the present invention;

FIG. 13 shows a schematic structural diagram of a clock conversion group provided by an embodiment of the present invention;

Fig. 14 shows a schematic diagram of the principle structure provided by the embodiment of the present invention;

FIG. 15 shows a schematic structural diagram of a clock buffer component provided by an embodiment of the present invention;

Fig. 16 shows a schematic structural diagram of a buffer component associated with a storage plane provided by an embodiment of the present invention;

Fig. 17 shows a schematic structural diagram of a conversion buffer assembly provided by an embodiment of the present invention;

FIG. 18 shows a schematic flowchart of a method for operating a memory provided by an embodiment of the present invention.

Detailed ways

The following disclosure provides many different embodiments, or examples, for implementing different features of the presented subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are examples only, not limiting. For example, in the following description, a first feature formed on or over a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include that additional features may be formed over the first feature and the second feature. An embodiment in which the first feature and the second feature may not be in direct contact between the two features. Additionally, the invention may repeat reference numerals and/or letters in various instances. Such repetition is for the sake of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or configurations discussed.

In addition, spatially relative terms such as "under", "beneath", "lower", "above", "upper" may be used herein to describe an element or feature for convenience of description Relationship to another element or feature(s) as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The technical solution of the present invention will be described in detail below in conjunction with the accompanying drawings.

FIG. 1 shows a block diagram of an exemplary system with memory in the related art. In FIG. 1, the system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a pointing device, a wearable electronic device, a smart sensor, a virtual reality (VR, Virtual Reality ) device, an augmented reality (AR, Argument Reality) device, or any other suitable electronic device having a memory therein. As shown in FIG. 1 , the system 100 may include a host 108 and a storage system 102, wherein the storage system 102 has one or more memories 104 and a memory controller 106; the host 108 may be a processor of an electronic device, such as a central processing unit ( CPU, Central Processing Unit) or a system on chip (SoC, System of Chip), where the system on chip may be, for example, an application processor (AP, Application Processor). Host 108 may be configured to send data to or receive data from memory 104 . Specifically, the memory 104 may be any memory disclosed in the present invention. For example, phase change random access memory (PCRAM, Phase Change Random Access Memory), three-dimensional NAND flash memory, and the like.

According to some implementations, memory controller 106 is coupled to memory 104 and host 108 . And configured to control the memory 104 . Memory controller 106 may manage data stored in memory 104 and communicate with host 108 . In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as in a Secure Digital (SD, Secure Digital) card, a Compact Flash (CF, Compact Flash) card, a general-purpose serial USB (Universal Serial Bus) flash drives, or other media intended for use in electronic devices in low duty cycle environments such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment, such as a solid state drive (SSD, Solid State Drive) or an embedded multimedia card (eMMC, embedded Muti Media Card), where the SSD Or eMMC is used as data storage for mobile devices in high duty cycle environments such as smartphones, tablets, laptops, and enterprise storage arrays. The memory controller 106 may be configured to control operations of the memory 104, such as read, erase and program operations. Memory controller 106 may also be configured to manage various functions related to data stored or to be stored in memory 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, and the like. In some implementations, the memory controller 106 is further configured to process an Error Correction Code (ECC, Error Correction Code) on data read from or written to the memory 104 . Memory controller 106 may also perform any other suitable functions, such as formatting memory 104 . Memory controller 106 may communicate with external devices (eg, host 108 ) according to a particular communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, peripheral component interconnection (PCI, Peripheral Component Interconnection) protocol, PCI Express (PCI-E , PCI Express) protocol, Advanced Technology Attachment (ATA, Advanced Technology Attachmnet) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI, SmallComputer Small Interface) protocol, Enhanced Small Disk Interface (ESDI, Enhanced Small DiskInterface ) protocol, Integrated Drive Electronics (IDE, Integrated Drive Electronics) protocol, Firewire protocol, etc.

Memory controller 106 and one or more memories 104 may be integrated into various types of storage devices, eg, included in the same package (eg, Universal Flash Storage (UFS) package or eMMC package). That is, the storage system 102 can be implemented and packaged into different types of terminal electronic products. In one example as shown in FIG. 2 , memory controller 106 and a single memory 104 may be integrated into memory card 202 . Memory cards can include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD , SDHC), UFS, etc. The memory card may also include a memory card connector 204 that couples the memory card with a host (eg, host 108 in FIG. 1 ). In another example as shown in FIG. 3 , memory controller 106 and multiple memories 104 may be integrated into SSD 302 . The SSD may also include an SSD connector 304 that couples the SSD to a host (eg, host 108 in FIG. 1 ). In some embodiments, the storage capacity and/or operating speed of the SSD is greater than the storage capacity and/or operating speed of the memory card. In addition, the memory controller 106 can also be configured to control the erasing, reading, and writing operations of the memory 104 .

Figure 4 shows a schematic diagram of an exemplary memory including peripheral circuitry. As shown in FIG. 4, the memory 104 may include a storage array 401 and a peripheral circuit 402 coupled to the storage array 401, wherein the storage array 401 may be a NAND flash storage array, wherein the storage unit 406 is an array of NAND memory strings 408 Provided in the form of , each NAND memory string 408 extends vertically above a substrate (not shown). In some embodiments, each NAND memory string 408 includes a plurality of memory cells 406 coupled in series and stacked vertically. Each storage cell 406 may hold a continuous analog value, such as a voltage or charge, depending on the number of electrons trapped within the storage area of the storage cell 406 . Each memory cell 406 may be a floating gate type memory cell including a floating gate transistor, or a charge trap type memory cell including a charge trap transistor.

In some embodiments, each memory cell 406 is a single-level cell (SLC, Single Level Cell) with two possible memory states and thus can store one bit of data, for example, the first memory state "0" may correspond to the first memory state "0" A voltage range, and the second memory state "1" may correspond to the second voltage range. In some embodiments, each storage unit 406 is a multi-level cell (MLC, MultiLevel Cell) with multiple memory states and therefore can store multi-bit data, for example, MLC can store two bits per unit, and three bits per unit. (Also known as Trinary Level Cell (TLC, Trinary Level Cell), or store four bits per unit (also known as Quadruple Level Cell (QLC, Quadruple LevelCell). Each MLC can be programmed to take possible programming to take range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to change from The erased state assumes one of three possible programming levels. A fourth nominal storage value can be used for the erased state.

As shown in FIG. 4, each NAND memory string 408 may include a source select gate (SSG) 410 at its source terminal and a drain select gate (DSG) 412 at its drain terminal. SSG 410 and DSG 412 may be configured to activate selected NAND memory strings 408 (columns of the array) during read and program (or write) operations. In some embodiments, the sources of the NAND memory strings 408 in the same block 404 are coupled by the same source line (SL) 414 (eg, a common SL). In other words, according to some embodiments, all NAND memory strings 408 in the same block 404 have an array common source (ACS). According to some implementations, the DSG 412 of each NAND memory string 408 is coupled to a corresponding bit line 416 from which data can be read and written via an output bus (not shown). In some embodiments, each NAND memory string 408 is configured to pass a select voltage (eg, above the threshold voltage of the transistor with DSG 412 ) or a deselect voltage (eg, 0 volts (V )) is applied to the corresponding DSG 412 and/or a select voltage (eg, higher than the threshold voltage of a transistor with SSG 410 ) or a deselect voltage (eg, 0 V) is applied to the corresponding SSG 410 via one or more SSG lines 415 Selected or deselected.

As shown in FIG. 4, NAND memory string 408 may be organized into a plurality of blocks 404, each of which may have a common source line 414 (eg, coupled to ground). In some embodiments, each block 404 is a basic unit of data with an erase operation, ie, all memory cells 406 on the same block 404 are erased simultaneously. In order to erase the memory cells 406 in the selected block 404, a bias coupled to the selected block 404 and on the same side as the selected block 404 (Plane Source lines 414 of unselected blocks 404 in ). It should be understood that, in some examples, erase operations may be performed at the half-block level, at the quarter-block level, or with any suitable number or fraction of blocks. Memory cells 406 of adjacent NAND memory strings 408 may be coupled by word lines 418 that select which row of memory cells 406 receives read and program operations. In some implementations, the memory cells 406 coupled on the same word line 418 are referred to as a page 420 . A page 420 is a basic data unit for a program operation or a read operation, and the size of a page 420 in units of bits may be related to the number of NAND memory strings 408 coupled by word lines 418 in one block 404 . Each word line 418 may include a plurality of control gates (gate electrodes) at each memory cell 406 in a corresponding page 420 and a gate line coupling the control gates.

The organizational structure of the storage array 401 inside the memory is shown in FIG. 5 . The storage array 401 can be divided into several DIEs (or called LUNs), each DIE has several storage planes (Planes), each Plane has several blocks (Blocks), each Block has several pages (Pages), Each Page corresponds to a word line (Wordline), and the Wordline is connected to tens of thousands of storage units 406 . Among them, DIE/LUN is the basic unit for receiving and executing operation commands. As shown in Figure 5, LUN0 and LUN1 can receive and execute different commands at the same time (but there are still certain restrictions, and the flash memory restrictions of different manufacturers are different). However, in a LUN, only one command can be independently executed at a time, and it is not possible to perform read access to other pages while writing to one of the pages. A LUN is divided into several planes, one or two planes are common in the market, and now there are four planes of flash memory. Each Plane has its own independent cache cache (CacheRegister) and page cache (Page Register), whose size is equal to the size of a Page. When the memory controller coupled with the memory is writing a certain Page, it first transfers the data from the memory controller to the Cache Register of the Plane corresponding to the Page, and then writes the data in the entire Cache Register to the storage unit; the read Time is the opposite, first read the data of this Page from the storage unit to the Cache Register, and then pass it to the memory controller on demand. The so-called on-demand means that when we read data, it is not necessary to transfer the data of the entire Page to the memory controller, but to select data transmission on demand. But remember, whether you are reading data from the storage unit to the Cache Register or writing the data in the Cache Register to the storage unit, the unit is Page.

6 shows a side view of a cross-section of an exemplary memory array including NAND memory strings. As shown in FIG. 6 , NAND memory string 408 may extend vertically above substrate 602 through memory stack layer 604 . The substrate 602 may comprise silicon (eg, monocrystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable Material.

The memory stack layer 604 may include alternating gate conductive layers 606 and gate-to-gate dielectric layers 508 . The number of pairs of gate conductive layer 606 and gate-to-gate dielectric layer 508 in memory stack layer 604 may determine the number of memory cells 406 in memory array 401 . The gate conductive layer 606 may include conductive materials including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some implementations, each gate conductive layer 606 includes a metal layer, eg, a tungsten layer. In some embodiments, each gate conductive layer 606 includes a doped polysilicon layer. Each gate conductive layer 606 may include a control gate surrounding the memory cell 406 and may extend laterally at the top of the memory stack layer 604 as a DSG line 413 and at the bottom of the memory stack layer 604 as a SSG line 415 , or extend laterally between the DSG line 413 and the SSG line 415 as a word line 418 .

As shown in FIG. 6 , NAND memory string 408 includes a channel structure 612 extending vertically through memory stack layer 604 . In some embodiments, the channel structure 612 includes a semiconductor material(s) filled (eg, as the semiconductor channel 620 ) and a dielectric material(s) (eg, as the memory film 618 ). trench hole. In some embodiments, semiconductor channel 620 includes silicon, eg, polysilicon. In some embodiments, the memory film 618 is a composite dielectric layer including a tunneling layer 626 , a storage layer 624 (also referred to as a “charge trapping/storage layer”), and a blocking layer 622 . The channel structure 612 may have a cylindrical shape (eg, a pillar shape). According to some embodiments, the semiconductor channel 620 , the tunneling layer 626 , the storage layer 624 and the barrier layer 622 are radially arranged in this order from the center of the pillar towards the outer surface of the pillar. The tunneling layer 626 may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 624 may include silicon nitride, silicon oxynitride, or any combination thereof. Barrier layer 622 may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film 618 may include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO).

According to some embodiments, as shown in FIG. 6 , a well 614 (eg, a P-well and/or an N-well) is formed in the substrate 602 and the source terminal of the NAND memory string 408 is in contact with the well 614 . For example, source line 414 may be coupled to well 614 to apply an erase voltage to well 614 (ie, the source of NAND memory string 408 ) during an erase operation. In some implementations, the NAND memory string 408 also includes a channel plug 616 at the drain terminal of the NAND memory string 408 . It should be understood that although not shown in FIG. 6 , additional components of the memory array 401 may be formed, including but not limited to gate line gaps/source contacts, local contacts, interconnect layers, and the like. It should be noted that, in some embodiments, the semiconductor channel 620 shown in FIG. 6 directly extends to the well 614 , and the gray plug above the well 614 in FIG. 6 is not needed. That is to say, the memory structure shown in FIG. 6 is only exemplary, and the data transmission device provided by the embodiment of the present invention is applicable to any memory structure.

Referring back to FIG. 4 , peripheral circuitry 402 may be coupled to memory array 401 through bit lines 416 , word lines 418 , source lines 414 , SSG lines 415 , and DSG lines 413 . Peripheral circuitry 402 may include any suitable analog, digital, and mixed-signal circuitry for applying voltage and/or current signals via bit lines 416, word lines 418, source lines 414, SSG lines 415, and DSG lines 413. Sensing voltage signals and/or current signals to and from each target memory cell 406 facilitates operation of the memory array 401 . The peripheral circuit 402 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, FIG. 7 shows some exemplary peripheral circuits. Peripheral circuit 402 includes page buffer/sense amplifier 704, column decoder/bit line driver 706, row decoder/word line driver 708, voltage generator 710, control Logic unit 712 , registers 714 , interface 716 and data bus 718 . It should be understood that in some examples, additional peripheral circuitry not shown in FIG. 7 may also be included.

The page buffer/sense amplifier 704 may be configured to read data from and program (write) data to the memory array 401 according to control signals from the control logic unit 712 . In one example, page buffer/sense amplifier 704 may store a page of programming data (write data) to be programmed into one page 420 of memory array 401 . In another example, page buffer/sense amplifier 704 may perform a program verify operation to ensure that data has been correctly programmed into memory cell 406 coupled to selected word line 418 . In yet another example, page buffer/sense amplifier 704 may also sense a low power signal from bit line 416 representing a data bit stored in memory cell 406 and amplify the small voltage swing during a read operation to a recognizable logic level. Column decoder/bit line driver 706 may be configured to be controlled by control logic unit 712 and to select one or more NAND memory strings 408 by applying bit line voltages generated from voltage generator 710 .

Row decoder/word line driver 708 may be configured to be controlled by control logic unit 712 and select/deselect blocks 404 of memory array 401 and select/deselect word lines 418 of blocks 404 . Row decoder/wordline driver 708 may also be configured to drive wordline 418 using a wordline voltage generated from voltage generator 710 . In some implementations, the row decoder/wordline driver 708 can also select/deselect and drive the SSG line 415 and the DSG line 413 . As described in detail below, row decoder/word line driver 708 is configured to perform erase operations on memory cells 406 coupled to selected word line(s) 418 . The voltage generator 710 may be configured to be controlled by the control logic unit 712, and generate word line voltages (eg, read voltages, program voltages, pass voltages, local voltages, verify voltages, etc.), bit line voltages to be supplied to the memory array 401, line voltage and source line voltage.

Control logic unit 712 may be coupled to each of the peripheral circuits described above and configured to control the operation of each of the peripheral circuits. Registers 714 may be coupled to the control logic unit 712 and include status registers, command registers and address registers for storing status information, command operation codes (OP codes) and command addresses for controlling the operation of each peripheral circuit. Interface 716 may be coupled to control logic unit 712 and act as a control buffer to buffer and relay control commands received from a host (not shown) to control logic unit 712 and to buffer status received from control logic unit 712 information and relay it to the host. Interface 716 may also be coupled to column decoder/bitline driver 706 via data bus 718 and act as a data I/O interface and data buffer to buffer and relay data to or from memory array 401 or buffer data.

Based on the storage system and memory described above, the current data transmission between Planes in the memory needs to be realized by the memory control coupled with the memory (specifically, the user reads the data of a certain Plane through the I/O interface, and then The pre-read data is transmitted to another Plane through the I/O interface, and the existing circuit design cannot support data transmission between storage planes (Planes) within the memory. In order to solve the above technical problems, as shown in FIG. 8, an embodiment of the present invention provides a memory 104, which may include: a storage array 401; the storage array includes a plurality of storage planes; and peripheral circuits coupled to the storage planes 402, of which;

The peripheral circuit 402 includes: a buffer device 80 coupled between the first storage plane and the second storage plane, wherein the buffer device is used to read the first data from the first storage plane and send transfer the first data to the second storage plane; or, read the second data from the second storage plane, and transmit the second data to the first storage plane;

Wherein, the first storage plane and the second storage plane are any two storage planes among the plurality of storage planes.

It should be noted that the basic structure of the memory 104 here is also as described above in FIGS. 1 to 7 , including a memory array, peripheral circuits, control logic units included in the peripheral circuits, and the like. In the embodiment of the present invention, a buffer device 80 is newly added between Planes, so as to realize direct data transmission between Planes without indirect data transmission between Planes by means of a memory controller. The first storage plane and the second storage plane described here are any two storage planes among the plurality of storage planes. That is, in the memory, a buffer device can be coupled between any two storage planes. The buffer device is used for reading data from the first storage plane and transmitting to the second storage plane; or reading data from the second storage plane and transmitting to the first storage plane. The use of the first data and the second data is only for the convenience of distinguishing the working process of the above two buffer devices, and does not limit the present invention.

In some embodiments, as shown in FIG. 9 , the buffer device 80 may include a clock buffer component 901, a first buffer component 902 corresponding to the first storage plane, and a clock buffer component 902 corresponding to the second storage plane. The second buffer component 903 and the conversion buffer component 904, wherein;

The clock buffer component is configured to receive an original clock signal and a first read enable signal of the first storage plane; when the first read enable signal is valid, generate the original clock signal based on the original clock signal The first sub-input clock signal of the first storage plane; sending the first sub-input clock signal to the first buffer component;

A first buffer component, coupled to the clock buffer component, for receiving the first read enable signal and the first sub-input clock signal; when the first read enable signal is valid, based on The first sub-input clock signal outputs a first output signal; transmits the first output signal to the conversion buffer; the first output signal includes a first output clock signal, a first data signal, first address signal;

The conversion buffer component is configured to receive the first output signal, the first read enable signal, and the first write enable signal of the second storage plane; signal and the first write enable signal are valid, convert the first output clock signal, the first data signal, and the first address signal included in the first output signal into the second The first input signal of the storage plane; the first input signal includes: a first input clock signal, a second data signal used to represent the first data, and a second address signal; and transmits the second address signal to the second buffer component the first input signal;

The second buffer component is configured to receive the first input signal and the first write enable signal; when the first write enable signal is valid, based on the first input clock signal generating a first write clock signal; generating a first write address based on the second address signal; generating the first data based on the second data signal; Data is written at the first write address of the second storage plane.

Described here is the structure of the buffer device and how it reads first data from the first storage plane and transfers it to the second storage plane.

Wherein, the original clock signal may be an external input clock signal, or may be generated by an internal control logic unit of the memory, and its function is to realize the basic clock signal for data transmission between storage planes. The first read enable signal of the first storage plane is an enable signal for reading the first storage plane. The clock buffer component receives a first read enable signal and an original clock signal, and generates a first sub-input of the first storage plane based on the original clock signal when the first read enable signal is valid A clock signal, the first sub-input clock signal is an input clock signal of the first storage plane. It should be noted that the first read enable signal can be active at low level or active at high level, and the specific form depends on the specific circuit design.

The obtained first sub-input clock signal is sent to the first buffer component coupled to the clock buffer component. The first buffer component receives the first sub-input clock signal and the first read enable signal, and when the first read enable signal is valid, the first buffer component based on the first The sub-input clock signal outputs a first output signal, and sends the first output signal to the conversion buffer component. Wherein, the first output signal includes a first output clock signal, a first data signal representing the first data, and a first address signal, that is, the first buffer component outputs the first output clock signal, the first data signal and a first address signal, wherein the first data is data read from the first storage plane based on the first sub-input clock signal; the first address signal is based on the first data in the first A signal generated by an address of a storage plane; the first output clock signal is a clock signal for outputting a first address signal and a first data signal from the first buffer component.

Here, the function of the conversion buffer component is to convert the first output signal into the first input signal of the second storage plane when the first read enable signal and the first write enable signal are valid, wherein , the first input signal includes: a first input clock signal, a second data signal used to represent the first data, and a second address signal; the first input clock signal is used to generate a write to the second storage surface The clock signal of data; the second data signal is a converted signal of the first data signal, which still represents the first data; the second address signal is an address signal converted by the first address signal, used to represent Write the second data into the write address of the second storage plane.

Then, the second buffer component is related to the second storage plane, it receives the first write enable signal and the first input signal, and when the first write enable signal is valid, based on the The first input clock signal generates a first write clock signal; generates a first write address based on a second address signal; generates first data based on a second data signal, and then writes the first write clock signal based on the first write clock signal. A data is written at the first writing address of the second storage plane.

After the above process, the first data in the first storage plane can also be written into the second storage plane.

In some embodiments, the second data in the second storage plane can also be written into the first storage plane. Specifically, each component in the buffer device can work as follows:

The clock buffer is also coupled to the second buffer component, and is used to receive the original clock signal and the second read enable signal of the second storage plane; when the second read enable When the signal is valid, generate a second sub-input clock signal based on the original clock signal; send the second sub-input clock signal to the second buffer component;

The second buffer component is configured to receive the second read enable signal and the second sub-input clock signal; when the second read enable signal is valid, based on the second sub-input clock Signal outputs a second output signal; transmits the second output signal to the conversion buffer; the second output signal includes a second output clock signal, a third data signal representing the second data, a third address signal;

The conversion buffer component is configured to receive the second output signal, the second read enable signal and the second write enable signal of the first storage plane; When the second write enable signal is valid, convert the second output clock signal, the second data signal, and the third address signal included in the second output signal into the first storage plane The second input signal of the second input signal; the second input signal includes a second input clock signal, a fourth data signal and a fourth address signal for representing the second data; the second input signal is transmitted to the first buffer component input signal;

The first buffer component is configured to receive the second input signal and the second write enable signal; when the second write enable signal is valid, generate a second input clock signal based on the second input clock signal Two write clock signals; generate a second write address based on the fourth address signal; generate the second data based on the fourth data signal; write the second data based on the second write clock signal into the second write address of the first storage plane.

It should be noted that the process described here is the reverse process of the process of reading data from the first storage plane and writing the data to the second storage plane described above. How to implement it is similar to the process described above. The description should be understood and will not be repeated here.

Based on the foregoing description of the buffer device, for the clock buffer component, as shown in FIG. 10 , the clock buffer component 901 includes: a first tri-state buffer 1001 and a second tri-state buffer 1002, wherein;

The input end of the first tri-state buffer and the input end of the second tri-state buffer are connected to the original clock signal;

The enable terminal of the first tri-state buffer is connected to the first read enable signal, and the output terminal outputs the first sub-input clock signal;

The enable terminal of the second tri-state buffer is connected to the second read enable signal, and the output terminal outputs the second sub-input clock signal.

It should be noted that the clock buffer component described here is only an example, and it includes two tri-state buffers: a first tri-state buffer and a second tri-state buffer, wherein the first tri-state buffer is When a read enable signal is valid, output the first sub-input clock signal related to the first storage plane based on the original clock signal for later use; the second tri-state buffer is valid when the second read enable signal , output a second sub-input clock signal related to the second storage plane based on the original clock signal for later use. In actual application, the first read enable signal and the second read enable signal are not valid at the same time.

It can be understood that it is only described as an example that the clock buffer component includes two tri-state buffers. In fact, the clock buffer component may include a tri-state buffer with N input terminals connected to the original clock signal, and the enable terminal connected to the read enable signal of each storage plane; wherein, N is an integer greater than 2.

For the first buffer assembly, as shown in FIG. 11, the first buffer assembly 902 includes: a first buffer group 1101, a second buffer group 1102, and a third buffer group 1103, wherein;

The first buffer group includes a first clock buffer; the first clock buffer is used to access the first sub-input clock signal and a first read enable signal; When the enable signal is valid, generate a first output clock signal based on the first sub-input clock signal; transmit the first output clock signal to the conversion buffer component;

The second buffer group includes a first data buffer; the first data buffer is used to access the first read enable signal and first data; When the signal is valid, generate the first data signal based on the first data; transmit the first data signal to the conversion buffer component; the first data is based on the first sub-input clock signal from the read at the first read address of the first storage plane;

The third buffer group includes a first address buffer; the first address buffer is used to access the first read enable signal and a first read address; When the enable signal is valid, generate the first address signal based on the first read address; transmit the first address signal to the conversion buffer component.

It should be noted that the first buffer component corresponds to the first storage plane. Described here is the process of the first buffer component generating the first output signal. Here, the enable signals of the first clock buffer included in the first buffer group, the first data buffer included in the second buffer group, and the first address buffer included in the third buffer group are the first read enable signals. can signal. When the first read enable signal is valid, the first clock buffer generates a first output clock signal based on the first sub-input clock signal, and converts the first output clock signal to the connected buffer component transmission; the first data buffer generates a first data signal based on the first data, and transmits the first data signal to the conversion buffer component, wherein the first data is the control logic unit of the memory based on the first data signal A sub-input clock signal is read from the first read address of the first storage plane; the first address buffer generates a first address signal based on the first read address, and transmits to the conversion buffer component the first address signal.

The foregoing is the logic for the first buffer component to read the first data from the first storage plane, and the first buffer component can also write data to the first storage plane. Therefore, in some embodiments, the first buffer group It also includes a second clock buffer; the second clock buffer is used to receive the second write enable signal and a second input clock signal; when the second write enable signal is valid, based on the The second input clock signal generates the second write clock signal;

The third buffer group also includes a second address buffer; the second address buffer is used to receive the second write enable signal and the fourth address signal; generating a second write address based on the fourth address signal when the enable signal is valid;

The second buffer group also includes a second data buffer; the second data buffer is used to receive the fourth data signal and the second write enable signal; When the enable signal is valid, generating the second data based on the fourth data signal; writing the second data into the first storage plane based on the second write clock signal address.

It should be noted that, here, the process of writing data into the first storage plane and the aforementioned process of reading data from the first storage plane are opposite to each other. What works here is the write enable signal, that is, when the second write enable signal is valid, data will be written into the first storage plane.

Since the structure of the second storage plane is similar to that of the first storage plane, in some embodiments, the structure of the second buffer assembly is the same as that of the first buffer assembly.

For the conversion buffer component, as shown in FIG. 12, the conversion buffer component 903 includes: a clock conversion group 1201, an address conversion group 1202 and a data conversion group 1203, wherein;

The clock conversion group is used to receive the first output clock signal, the first read enable signal and the first write enable signal; the first read enable signal and the first write enable signal When the first write enable signals are all valid, generate the first input clock signal based on the first output clock signal; transmit the first input clock signal to the second buffer component;

The address conversion group is used to receive the first address signal, the first read enable signal and the first write enable signal; When both write enable signals are valid, generate the second address signal based on the first address signal; transmit the second address signal to the second buffer component;

The data conversion group is used to receive the first data signal, the first read enable signal and the first write enable signal; When both write enable signals are valid, generate the second data signal based on the first data signal; transmit the second data signal to the second buffer component.

Described here is the process of converting the first output signal into the first input signal by the conversion buffer component, which is to realize the process of transmitting the first data of the first storage plane to the second storage plane. When both the first read enable signal of the first storage plane and the first write enable signal of the second storage plane are valid, the first output signal output from the first buffer component is converted to be input to the second A first input signal in a buffer component.

In some embodiments, the clock conversion group is also used to receive the second output clock signal, the second read enable signal and the second write enable signal; When both the fetch enable signal and the second write enable signal are valid, generate the second input clock signal based on the second output clock signal; transmit the second input clock signal to the first buffer component ;

The address conversion group is used to receive the third address signal, the second read enable signal and the second write enable signal; When both write enable signals are valid, generate the fourth address signal based on the third address signal; transmit the fourth address signal to the first buffer component;

The data conversion group is used to receive the third data signal, the second read enable signal and the second write enable signal; When both write enable signals are valid, generate the fourth data signal based on the third data signal; transmit the fourth data signal to the first buffer component.

Described here is the process of converting the second output signal into the second input signal by the conversion buffer component, which is to realize the process of transmitting the second data of the second storage plane to the first storage plane. When both the second write enable signal of the first storage plane and the second read enable signal of the second storage plane are valid, the second output signal output by the second buffer component is converted into the second output signal to be input to the first storage plane. A second input signal in a buffer component.

For the clock conversion group, referring to FIG. 13, the clock conversion group 1201 may include: a first group of buffers 1301 and a second group of buffers 1302; the first group of buffers 1301 includes a third three-state a buffer 1301-1 and a fourth tri-state buffer 1301-2; the second group of buffers includes a fifth tri-state buffer 1302-1 and a sixth tri-state buffer 1302-2;

Wherein, the input end of the third tri-state buffer is connected to the output end of the fourth tri-state buffer; the output end of the third tri-state buffer is connected to the input end of the fourth tri-state buffer connected; the enable end of the third tri-state buffer is connected to the first read enable signal; the enable end of the fourth tri-state buffer is connected to the second write enable signal;

The input end of the third tri-state buffer, the output end of the fourth tri-state buffer, the input end of the fifth tri-state buffer, and the output end of the sixth tri-state buffer are connected;

The output end of the fifth tri-state buffer is connected to the input of the sixth tri-state buffer; the enable end of the fifth tri-state buffer is connected to the second read enable signal; the The enable terminal of the sixth tri-state buffer is connected to the first write enable signal.

It should be noted that this only describes how the clock conversion group utilizes two sets of buffers to realize the transition from the output clock signal of the first storage plane to the input clock signal of the second storage plane, and how to convert the output clock signal of the second storage plane to the second storage plane. A transition of the input clock signal for a memory plane. It can be understood that, in fact, the clock conversion group may include N sets of buffers, which can realize the conversion of clock signals in any two storage planes. The first output clock signal/second input clock signal and the first input clock signal/second output clock signal in FIG. 13 have been described above and will not be repeated here.

In some embodiments, the structure of the address translation group and the structure of the data translation group are the same as that of the clock translation group.

In some embodiments, the structure of the data conversion group is the same as the structure of the clock conversion group; the structure of the address conversion group is compared with the structure of the clock conversion group, and it also includes an address offset function. Components to write data from one storage plane to a specified address on another storage plane.

In some embodiments, the peripheral circuit also includes an I/O interface and a control logic unit, wherein,

The control logic unit is configured to receive a first command through the I/O interface; based on the first command, control the buffer device to read first data from the first storage plane, and send data to the second storage plane. transfer the first data to the first storage plane; or read the second data from the second storage plane and transfer the second data to the first storage plane.

It should be noted that data can be directly transmitted between the storage planes in the previous memory, but the data transmission between which two storage planes, which storage plane to read from, which storage plane to store into, and the timing of transmission, etc. are all controlled by The memory controller performs control, that is, the memory controller sends the first command to the control logic unit of the memory through the I/O interface, and then the control logic unit parses which storage plane to read from and which storage plane to store based on the first command. The necessary information is transmitted between the storage planes, etc., so as to realize the data transmission between the storage planes. That is to say, the sending of the first command can be transmitted to the control logic unit by the memory controller included in the storage system through the I/O interface included in the peripheral circuit, and the control logic unit parses the first command to obtain which storage plane Read, store to which storage plane, etc., transmit necessary information, so as to realize data transmission between storage planes.

In order to understand the present invention, the embodiment of the present invention is illustrated with FIGS. 14 to 17 . Figure 14 shows a schematic diagram of the principle structure provided by an embodiment of the present invention; Figure 15 shows a schematic structural diagram of a clock buffer component provided by an embodiment of the present invention; Figure 16 shows a buffer component associated with a storage plane provided by an embodiment of the present invention A schematic structural diagram of FIG. 17 shows a schematic structural diagram of a conversion buffer assembly provided by an embodiment of the present invention.

In FIG. 14, the implementation principle of the method provided by the embodiment of the present invention can be as follows: the original clock signal is input to the clock buffer component, and the sub-input clock signal clk_in_x entering the storage plane Plane(x) is generated; then, the clk_in_x is transmitted to the Plane (x) The corresponding buffer component, the buffer component generates output signals including the output clock signal clk_plane_x, the address signal addr_plane_x, and the data signal data_plane_x based on the clk_in_x and the read enable signal, so as to complete the reading of Plane(x). Then, this output signal is input to the conversion buffer component, and the conversion buffer component converts the output signal of Plane(x) into the input signal of Plane(y) including clock signal clk_plane_y, address signal addr_plane_y and data signal data_plane_y, which will give the input signal Input to the buffer component corresponding to Plane(y), and the buffer component corresponding to Plane(y) writes the data read from Plane(x) into Plane(y) based on these input signals and the write enable signal, In this way, the direct transmission of data from Plane(x) to Plane(y) is completed. It should be noted that the arrows in the conversion buffer component in FIG. 14 are bidirectional, that is, the direct transmission of data from Plane(y) to Plane(x) can also be completed. The specific process is similar to the above, and will not be repeated here. It should be noted that Plane(x) can be any storage plane in PLANE0~PLANEN corresponding to each buffer component as shown in Figure 14; Plane(y) can be the Any other storage plane. clk_in_x is any one of clk_in_0 to clk_in_n. The storage plane corresponding to the cache component is not shown in FIG. 14 , and there is a one-to-one correspondence between the storage plane and the corresponding cache component. For a specific relationship between the two, refer to the aforementioned FIG. 9 .

A structure of the clock buffer component in FIG. 14 is shown in FIG. 15 . The input terminals of N tri-state buffers are connected together to access the original clock signal; the enable terminal of each tri-state buffer is connected to the read enable signal of the corresponding storage plane, and the output terminal is connected to the corresponding storage plane. For example, the enable port of the tri-state buffer corresponding to Plane(0) is connected to the read enable signal en_read_plane_0 corresponding to Plane(0), and the sub-input clock signal clk_in_0 corresponding to Plane(0) is output. And so on.

A structure of the buffer assembly corresponding to the storage plane in FIG. 14 is shown in FIG. 16 . Because the buffer components corresponding to each storage plane have the same structure. FIG. 16 only uses the buffer component corresponding to Plane(0) as an example for illustration.

Specifically, the buffer assembly includes: a first buffer group, a second buffer group and a third buffer group, wherein;

The first buffer group includes a first clock buffer and a second clock buffer; wherein, the input terminal of the first clock buffer is connected to the sub-input clock signal clk_in_0 corresponding to Plane (0), and the terminal is enabled Input the read enable signal en_read_plane_0 corresponding to Plane (0), the output terminal outputs the output clock signal clk_plane_0; the input terminal of the second clock buffer is connected to the input clock signal clk_plane_0, and the enable terminal is connected to the corresponding to Plane (0) The write enable signal en_write_plane_0, the output terminal outputs the write clock signal corresponding to Plane(0);

The second buffer group includes a first data buffer and a second data buffer; wherein, the input of the first data buffer is connected to the data read from Plane (0) based on the sub-input clock signal, so that The energy terminal is connected to en_read_plane_0, and the output terminal outputs the data signal data_plane_0 corresponding to the data read in Plane (0); the input terminal of the second data buffer is connected to the data signal generated by the data read from other storage planes, The enable terminal is connected to en_write_plane_0, and the output terminal outputs the data read from other storage planes;

The third buffer group includes a first address buffer and a second address buffer; wherein, the input of the first address buffer accesses the read address (the data read in Plane (0) is in Plane (0) )), the enable terminal is connected to en_read_plane_0, and the output terminal outputs the address signal addr_plane_0 corresponding to Plane (0); the input terminal of the second address buffer is connected to the address signal addr_plane_0 corresponding to Plane (0), enabling The terminal is connected to en_write_plane_0, and the output terminal outputs the write address corresponding to Plane(0).

Wherein, in an optional implementation manner, when reading Plane(0), en_write_plane_0=0; en_read_plane_0=1; when writing Plane(0), en_write_plane_0=1; en_read_plane_0=0.

A structure of the conversion buffer component in FIG. 14 is shown in FIG. 17 . The conversion buffer component includes: a clock conversion group, an address conversion group and a data conversion group, wherein; according to the structure shown in FIG. 17, the structure of the address conversion group and the data conversion group is the same as that of the clock conversion group.

The following only describes the structure of the clock conversion group.

The clock conversion group includes N groups of buffers connected to each other, and each group of buffers includes two tri-state buffers, wherein one tri-state buffer is controlled by the read enable signal of the corresponding storage plane, and the other tri-state buffer It is controlled by the write enable signal of the corresponding storage plane. In this way, the conversion of clock signals between different storage planes is realized.

It should be noted that based on the structure of the conversion buffer component in Figure 17, the address division of Plane(x) is the same as that of Plane(y), in other words, the data read from Plane(x) Position in Plane(x) is the same as storing it in Plane(y). It should be understood that, for the storage address, an offset can also be performed to store it at a specified location in Plane(y). The specific design of how to add offset components is based on actual needs to obtain the required address.

Here, when reading PLANE(X), en_read_plane_x=1, en_write_plane_x=0, and other buffer enable signals are 0. When writing to PLANE(X), en_read_plane_x=0, en_write_plane_x=1, and other buffer enable signals are 0.

In the memory provided by the embodiment of the present invention, a buffer device is provided between the storage planes, and the buffer device is used to transfer the data of one storage plane to the other storage plane without using a coupled memory controller. Direct data transmission between internal storage planes of the memory is convenient and fast.

Based on the same inventive concept, as shown in FIG. 18 , an embodiment of the present invention also provides a method for operating a memory, which is applied to peripheral circuits included in the memory. The operation method includes:

S1801: Receive a first command;

S1802: Read first data from the first storage plane based on the first command, and transmit the first data to the second storage plane; or, read second data from the second storage plane, and transfer the first data to the second storage plane. A storage plane transmits the second data;

Wherein, the first storage plane and the second storage plane are any two storage planes among the plurality of storage planes included in the memory.

In some embodiments, the reading the first data from the first storage plane based on the first command, and transmitting the first data to the second storage plane includes:

Obtaining a first read enable signal based on the first command; receiving an original clock signal;

When the first read enable signal is valid, a first sub-input clock signal is generated based on the original clock signal; a first output signal is based on the first sub-input clock signal; the first output signal includes a first outputting a clock signal, a first data signal for representing first data, and a first address signal;

When the first read enable signal and the first write enable signal of the second storage plane are valid, the first output clock signal included in the first output signal, the first data signal, the first address signal is converted into the first input signal of the second storage plane; the first input signal includes: a first input clock signal, a second data signal used to represent the first data, a second address signal; the first write enable signal is obtained based on the first command;

When the first write enable signal is valid, generate a first write clock signal based on the first input clock signal; generate a first write address based on the second address signal; generate a first write address based on the second data signal generating the first data; writing the first data at the first write address of the second storage plane based on the first write clock signal.

In some embodiments, reading the second data from the second storage plane based on the first command, and transferring the second data to the first storage plane includes:

deriving a second read enable signal based on the first command; and receiving an original clock signal;

generating a second sub-input clock signal based on the original clock signal when the second read enable signal is valid;

outputting a second output signal based on the second sub-input clock signal; the second output signal includes a second output clock signal, a third data signal representing the second data, and a third address signal;

When the second read enable signal and the second write enable signal of the first storage plane are valid, the second output clock signal contained in the second output signal, the second data signal, the third address signal is converted into a second input signal of the first storage plane; the second input signal includes a second input clock signal, a fourth data signal representing the second data, and a second input signal Four address signals; the second write enable signal is obtained based on the first command;

When the second write enable signal is valid, generate a second write clock signal based on the second input clock signal; generate a second write address based on the fourth address signal; generate a second write address based on the fourth data signal generating the second data; writing the second data at the second write address of the first storage plane based on the second write clock signal.

It should be noted that the technical solution described in the operation method and the aforementioned technical solution of the memory belong to the same inventive concept, and both have the same technical features. description, then the nouns appearing here can be understood according to the meaning of the foregoing description, and will not be repeated here.

An embodiment of the present invention also provides a storage system, including: one or more memories described in any one of the preceding items;

And a memory controller coupled to the memory; the memory controller is configured to: send various operation commands to the memory. Wherein, the various operation commands may include the first command.

It should be noted that the storage system here includes the aforementioned memory, both of which have the same technical features. The structure of the memory and the nouns appearing in the technical solution of the present invention have been described in detail above. Then, the nouns appearing here, It can be understood according to the meaning of the foregoing description, and details are not repeated here.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention.

Claims (17)

1. A memory, comprising: a plurality of storage surfaces; and peripheral circuitry coupled to the storage surface, wherein;

the peripheral circuit includes: the buffer device is coupled between the first storage surface and the second storage surface, and is used for reading first data from the first storage surface and transmitting the first data to the second storage surface; or, reading second data from the second storage surface and transmitting the second data to the first storage surface;

wherein the first storage surface and the second storage surface are any two storage surfaces of the plurality of storage surfaces.

2. The memory according to claim 1, wherein the buffering means comprises: clock buffering subassembly, with first buffering subassembly that first memory surface corresponds, with second buffering subassembly, conversion buffering subassembly that second memory surface corresponds, wherein:

the clock buffer component is used for receiving an original clock signal and a first read enabling signal of the first storage surface; generating a first sub-input clock signal of the first storage plane based on the original clock signal when the first read enable signal is active; sending the first sub-input clock signal to the first buffer component;

a first buffer component coupled to the clock buffer component for receiving the first read enable signal and the first sub-input clock signal; outputting a first output signal based on the first sub-input clock signal when the first read enable signal is active; transmitting the first output signal to the conversion buffer; the first output signal comprises a first output clock signal, a first data signal for representing first data, and a first address signal;

the conversion buffer component is used for receiving the first output signal, the first read enable signal and a first write enable signal of the second storage surface; converting the first output clock signal, the first data signal, and the first address signal included in the first output signal into a first input signal of the second storage plane when the first read enable signal and the first write enable signal are asserted; the first input signal comprises: a first input clock signal, a second data signal representing the first data, a second address signal; transmitting the first input signal to the second buffer component;

the second buffer component is used for receiving the first input signal and the first write enable signal; generating a first write clock signal based on the first input clock signal if the first write enable signal is active; generating a first write address based on the second address signal; generating the first data based on the second data signal; writing the first data to the second storage surface at the first write address based on the first write clock signal.

3. The memory of claim 2, wherein the clock buffer is further coupled to the second buffering component for receiving the original clock signal and a second read enable signal for the second storage plane; generating a second sub-input clock signal based on the original clock signal when the second read enable signal is active; sending the second sub-input clock signal to the second buffer component;

the second buffer component is configured to receive the second read enable signal and the second sub-input clock signal; outputting a second output signal based on the second sub-input clock signal when the second read enable signal is active; transmitting the second output signal to the conversion buffer; the second output signal comprises a second output clock signal, a third data signal for representing the second data, and a third address signal;

the conversion buffer component is used for receiving the second output signal, the second read enable signal and a second write enable signal of the first storage surface; converting the second output clock signal, the second data signal, and the third address signal included in the second output signal into a second input signal of the first storage plane when the second read enable signal and the second write enable signal are asserted; the second input signal comprises a second input clock signal, a fourth data signal for representing the second data, and a fourth address signal; transmitting the second input signal to the first buffer component;

the first buffer component is used for receiving the second input signal and the second write enable signal; generating a second write clock signal based on the second input clock signal when the second write enable signal is active; generating a second write address based on the fourth address signal; generating the second data based on the fourth data signal; writing the second data at the second write address of the first storage plane based on the second write clock signal.

4. The memory of claim 3, wherein the clock buffering component comprises: a first tri-state buffer and a second tri-state buffer, wherein;

the input end of the first tri-state buffer and the input end of the second tri-state buffer are connected with the original clock signal;

the enabling end of the first tri-state buffer is connected with the first read enabling signal, and the output end of the first tri-state buffer outputs the first sub input clock signal;

and the enabling end of the second tri-state buffer is connected with the second read enabling signal, and the output end of the second tri-state buffer outputs the second sub input clock signal.

5. The memory of claim 3, wherein the first buffer component comprises: a first buffer group, a second buffer group, and a third buffer group, wherein;

the first buffer group comprises a first clock buffer; the first clock buffer is used for accessing the first sub input clock signal and a first read enabling signal; generating a first output clock signal based on the first sub-input clock signal when the first read enable signal is active; transmitting the first output clock signal to the conversion buffer component;

the second buffer group comprises a first data buffer; the first data buffer is used for accessing the first read enabling signal and first data; generating the first data signal based on the first data when the first read enable signal is active; transmitting the first data signal to the conversion buffer component; the first data is read from a first read address of the first storage surface based on the first sub-input clock signal;

the third buffer group comprises a first address buffer; the first address buffer is used for accessing the first read enabling signal and a first read address; generating the first address signal based on the first read address when the first read enable signal is active; transmitting the first address signal to the translation buffer component.

6. The memory of claim 5, wherein the first buffer group further comprises a second clock buffer; the second clock buffer is used for receiving the second write enable signal and a second input clock signal; generating the second write clock signal based on the second input clock signal while the second write enable signal is active;

the third buffer group further comprises a second address buffer; the second address buffer is used for receiving the second write enable signal and the fourth address signal; generating a second write address based on the fourth address signal when the second write enable signal is active;

the second buffer group further comprises a second data buffer; the second data buffer is configured to receive the fourth data signal and the second write enable signal; generating the second data based on the fourth data signal when the second write enable signal is active; writing the second data at the second write address of the first storage plane based on the second write clock signal.

7. The memory of claim 6, wherein the structure of the second buffer component is the same as the structure of the first buffer component.

8. The memory of claim 3, wherein the translation buffer component comprises: a clock translation group, an address translation group and a data translation group, wherein;

the clock conversion group is used for receiving the first output clock signal, the first read enable signal and the first write enable signal; generating the first input clock signal based on the first output clock signal when the first read enable signal and the first write enable signal are both active; transmitting the first input clock signal to the second buffer component;

the address translation set is configured to receive the first address signal, the first read enable signal, and the first write enable signal; generating the second address signal based on the first address signal when the first read enable signal and the first write enable signal are both active; transmitting the second address signal to the second buffering component;

the data conversion group is used for receiving the first data signal, the first read enable signal and the first write enable signal; generating the second data signal based on the first data signal when the first read enable signal and the first write enable signal are both active; transmitting the second data signal to the second buffer component.

9. The memory of claim 8, wherein the clock transition group is further configured to receive the second output clock signal, the second read enable signal, and the second write enable signal; generating the second input clock signal based on the second output clock signal when the second read enable signal and the second write enable signal are both active; transmitting the second input clock signal to the first buffer component;

the address translation set is configured to receive the third address signal, the second read enable signal, and the second write enable signal; generating the fourth address signal based on the third address signal when the second read enable signal and the second write enable signal are both active; transmitting the fourth address signal to the first buffer component;

the data conversion group is used for receiving the third data signal, the second read enable signal and the second write enable signal; generating the fourth data signal based on the third data signal when the second read enable signal and the second write enable signal are both asserted; transmitting the fourth data signal to the first buffer component.

10. The memory of claim 9, wherein the set of clock transitions comprises: a first set of buffers and a second set of buffers; the first set of buffers comprises a third tri-state buffer and a fourth tri-state buffer; the second set of buffers comprises a fifth tri-state buffer and a sixth tri-state buffer;

wherein an input terminal of the third tri-state buffer is connected with an output terminal of the fourth tri-state buffer; the output end of the third tri-state buffer is connected with the input end of the fourth tri-state buffer; the enabling end of the third tri-state buffer accesses the first read enabling signal; the enabling end of the fourth tri-state buffer is connected with the second write enabling signal;

the input end of the third tri-state buffer, the output end of the fourth tri-state buffer, the input end of the fifth tri-state buffer and the output end of the sixth tri-state buffer are connected;

the output end of the fifth tri-state buffer is connected with the input end of the sixth tri-state buffer; the enabling end of the fifth tri-state buffer accesses the second read enabling signal; and the enabling end of the sixth tri-state buffer accesses the first write enabling signal.

11. A memory as claimed in any one of claims 8 to 10, wherein the structure of the set of address translations and the structure of the set of data translations are the same as the structure of the set of clock translations.

12. The memory of claim 1, wherein the peripheral circuitry further comprises an I/O interface and control logic unit, wherein,

the control logic unit is used for receiving a first command through the I/O interface; controlling the buffer device to read first data from the first storage surface and transmit the first data to the second storage surface based on the first command; or reading second data from the second storage surface and transmitting the second data to the first storage surface.

13. An operating method of a memory, applied to a peripheral circuit included in the memory, the operating method comprising:

receiving a first command;

reading first data from a first storage surface based on the first command, and transmitting the first data to a second storage surface; or reading second data from the second storage surface and transmitting the second data to the first storage surface;

the first storage surface and the second storage surface are any two storage surfaces in a plurality of storage surfaces included in the memory.

14. The method of claim 13, wherein reading first data from a first storage surface based on the first command, and transferring the first data to a second storage surface comprises:

obtaining a first read enable signal based on the first command; receiving an original clock signal;

generating a first sub-input clock signal based on the original clock signal when the first read enable signal is active; a first output signal based on the first sub-input clock signal; the first output signals comprise a first output clock signal, a first data signal used for representing first data, and a first address signal;

converting the first output clock signal, the first data signal, and the first address signal included in the first output signal into a first input signal of the second storage plane when the first read enable signal and a first write enable signal of the second storage plane are asserted; the first input signal comprises: a first input clock signal, a second data signal representing the first data, a second address signal; the first write enable signal is obtained based on the first command;

generating a first write clock signal based on the first input clock signal while the first write enable signal is active; generating a first write address based on the second address signal; generating the first data based on the second data signal; writing the first data to the second storage surface at the first write address based on the first write clock signal.

15. The method of claim 14, wherein reading second data from the second storage surface based on the first command, and transferring the second data to the first storage surface comprises:

obtaining a second read enable signal based on the first command; and receiving an original clock signal;

generating a second sub-input clock signal based on the original clock signal when the second read enable signal is active;

outputting a second output signal based on the second sub-input clock signal; the second output signal comprises a second output clock signal, a third data signal for representing the second data, and a third address signal;

converting the second output clock signal, the second data signal, and the third address signal included in the second output signal into a second input signal of the first storage plane when the second read enable signal and a second write enable signal of the first storage plane are asserted; the second input signal comprises a second input clock signal, a fourth data signal for representing the second data, and a fourth address signal; the second write enable signal is obtained based on the first command;

generating a second write clock signal based on the second input clock signal when the second write enable signal is active; generating a second write address based on the fourth address signal; generating the second data based on the fourth data signal; writing the second data at the second write address of the first storage plane based on the second write clock signal.

16. A storage system, comprising: one or more memories as claimed in any one of claims 1 to 12;

and a memory controller coupled to the memory; the memory controller to: various operation commands are sent to the memory.

17. The storage system according to claim 16, wherein the storage system is a Solid State Disk (SSD) or a memory card.

Images