CN115344826A - Computing device, method of operation, and machine-readable storage medium - Google Patents

Abstract

The invention provides a computing device, an operating method and a machine-readable storage medium. In an embodiment according to the invention, the method of operation comprises: checking data type information carried by a current instruction, wherein the data type information represents the data type of a target operand corresponding to the current instruction; when the data type information indicates that the data type of the target operand is the self-adaptive data type, reading metadata corresponding to the target operand to acquire the actual data type of the target operand from the metadata; and executing the current instruction to process the target operand based on the actual data type of the target operand recorded by the metadata.

Description

Computing device, method of operation, and machine-readable storage medium

technical field

The present invention relates to an instruction set, and in particular to a computing device, an operating method and a machine-readable storage medium.

Background technique

Generally speaking, when writing a calculation program (program), the writer knows the data type of the operand (or operand, operand), so the writer can write instructions with "specified (fixed) data type" information into the calculation program, and then use a compiler to compile the calculation program. For example, the calculation program may include a load instruction with the information "32-bit floating point number" (fixed data type), which is used to load an operand whose data type is "32-bit floating point number" from the memory to the calculation core (eg tensor core, tensor core). Alternatively, the calculation program may include matrix multiply and accumulate (MMA) instructions with information "32-bit floating-point numbers" (fixed data type) to make the calculation check the loaded "32-bit floating-point numbers The two operands of " perform matrix multiplication calculation. However, there are cases where the data type of an operand may be undefined at compile time (data type is unknown). For example, the data type of the calculation result of the hidden layer (Hidden layer) of the Convolutional Neural Network (CNN) operation program may be dynamically determined after the calculation is actually performed. However, the current instruction set does not support "indeterminate data types".

Contents of the invention

The present invention provides a computing device and its operating method, as well as a machine-readable storage medium to support adaptive data types. Adaptive data types mean that the data type is unknown at compile time.

In an embodiment according to the present invention, the operation method includes: checking the data type information carried by the current instruction, wherein the data type information indicates the data type of the target operand (operand) corresponding to the current instruction; when the data type information indicates When the data type of the target operand is an adaptive data type, read the metadata (meta data) corresponding to the target operand to obtain the actual data type of the target operand from the metadata, or directly obtain the the actual data type; and based on the actual data type of the target operand recorded in the metadata, execute the current instruction to process the target operand.

In an embodiment according to the present invention, the machine-readable storage medium is used to store non-transitory machine-readable instructions. The operating method of the computing device may be implemented when the non-transitory machine readable instructions are executed by a computer.

In an embodiment according to the present invention, the computing device includes a memory and a computing core. Memory is used to store the destination operand. The computing core is coupled to the memory. The operation core checks the data type information of the current instruction, wherein the data type information indicates the data type of the target operand corresponding to the current instruction. When the data type information indicates that the data type of the target operand is an adaptive data type, the operation core reads the metadata corresponding to the target operand, so as to obtain the actual data type of the target operand from the metadata, or directly obtain the The actual data type of the target operand. Based on the actual data type of the target operand recorded in the metadata, the operation core executes the current instruction to process the target operand.

Based on the above, the operation core can check the data type information of the current instruction to determine whether the data type of the target operand corresponding to the current instruction is a fixed (specified) data type or an adaptive data type. The fixed data type means that the data type of the target operand is known at compile time. The adaptive data type means that the data type of the target operand is unknown when compiling, but is determined dynamically when the program is executed. The actual data type of the target operand is recorded in the metadata corresponding to the target operand when the program is executed. Before the operation core executes the current instruction, the operation core checks the data type of the target operand of the current instruction. When the data type of the target operand is an adaptive data type, the operation core may obtain the actual data type of the target operand from the metadata corresponding to the target operand, or directly obtain the actual data type of the target operand. Based on the actual data type of the target operand recorded in the metadata, the computing core can correctly execute the current instruction to process the target operand.

Description of drawings

FIG. 1 is a schematic diagram of a circuit block of a computing device according to an embodiment of the present invention.

FIG. 2 is a schematic flowchart of an operating method of a computing device according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of a circuit block diagram of a computing core according to an embodiment of the present invention.

FIG. 4 is a schematic circuit block diagram of a computing core according to another embodiment of the present invention.

Explanation of reference signs

100: computing device

110: memory

120: computing core

121: Operation circuit

122, 126: operand buffer

123: conversion unit

124: load unit

125: status register

Dconv: Operand

Dm: metadata

Dorig: calculation result

S210～S250: steps

ST: Statistical results

Detailed ways

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the drawings and description to refer to the same or like parts.

As used throughout this specification, including the claims, the term "coupled (or connected)" may refer to any means of connection, direct or indirect. For example, if it is described that a first device is coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be connected through other devices or The second device is indirectly connected to the second device through some connection means. The terms "first" and "second" mentioned in the entire description of this case (including the claims) are used to name the name of the component (element), not to limit the upper or lower limit of the number of components, nor to limit the number of components. Restricts the order of components. In addition, wherever possible, components/members/steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Components/components/steps using the same symbols or using the same terms in different embodiments can refer to related descriptions.

FIG. 1 is a schematic diagram of a circuit block of a computing device 100 according to an embodiment of the present invention. The computing device 100 shown in FIG. 1 includes a memory 110 and a computing core 120 . The memory 110 is used for storing operands. This embodiment does not limit the specific data structure of the operand. For example, in the application of neural network, the operand can be vector, tensor or other data. Based on the actual design, the operand can be a matrix (matrix), or any one of multiple blocks after a matrix is divided. The size of the matrix and the size of the block can be determined according to actual design. For example, in some applications, the size of a block (operand) can be 32*32, 64*64 or other sizes.

The computing core 120 is coupled to the memory 110 . In different application examples, the calculation core 120 includes a tensor core (tensor core), a general matrix multiply (general matrix multiply, GEMM) core, an arithmetic logic unit (arithmetic logic unit, ALU) and/or other calculation units . According to different design requirements, in some embodiments, the implementation of the computing core 120 may be a hardware circuit. In some other embodiments, the computing core 120 may be implemented in firmware (firmware), software (software, ie program), or a combination of the two. In some other embodiments, the computing core 120 may be implemented in a combination of hardware, firmware, and software.

In terms of hardware, the above computing core 120 may be implemented as a logic circuit on an integrated circuit. For example, the relevant functions of the computing core 120 can be implemented in one or more controllers, microcontrollers (Microcontroller), microprocessors (Microprocessor), application-specific integrated circuits (Application-specific integrated circuit, ASIC), digital Various logic blocks, modules and circuits in a signal processor (digital signal processor, DSP), field programmable logic gate array (Field Programmable Gate Array, FPGA) and/or other processing units. Related functions of the computing core 120 can be implemented as hardware circuits, such as various logic blocks, modules and circuits in an integrated circuit, by using hardware description languages (such as Verilog HDL or VHDL) or other suitable programming languages.

In terms of software and/or firmware, the related functions of the computing core 120 may be implemented as programming codes. For example, the computing core 120 is realized by using general programming languages (such as C, C++ or assembly language) or other suitable programming languages. The programming code may be recorded/stored in a non-transitory machine-readable storage medium. In some embodiments, the machine-readable storage medium includes, for example, a semiconductor memory and/or a storage device. The semiconductor memory includes memory card, read only memory (Read Only Memory, ROM), flash memory (FLASH memory), programmable logic circuit or other semiconductor memory. The storage device includes a tape, a disk, a hard disk drive (HDD), a solid-state drive (SSD), or other storage devices. An electronic device (such as a computer, a central processing unit (Central Processing Unit, CPU), a controller, a microcontroller, or a microprocessor) can read and execute the programming code from the machine-readable storage medium, thereby realizing calculation related functions of the core 120. Alternatively, the programming code may be provided to the electronic device via any transmission medium (such as a communication network or broadcast waves, etc.). The communication network is, for example, the Internet, a wired communication network, a wireless communication network or other communication media.

FIG. 2 is a schematic flowchart of an operating method of a computing device according to an embodiment of the present invention. In some embodiments, the operation method of the computing device shown in FIG. 2 may be implemented in firmware or software (software, ie a program). For example, the relevant operations of the operating method of the computing device shown in FIG. 2 can be implemented as non-transitory machine-readable instructions (programming codes or programs), and the non-transitory machine-readable instructions can be stored in a machine-readable storage medium. The operating method of the computing device shown in FIG. 2 can be implemented when the non-transitory machine-readable instructions are executed by a computer. In other embodiments, the operation method of the computing device shown in FIG. 2 may be implemented in hardware, such as the computing device 100 shown in FIG. 1 .

The computing core 120 can fetch instructions (hereinafter referred to as current instructions) from the memory 110 . For example, the computing core 120 may fetch a load instruction, a matrix multiply and accumulate (MMA) instruction or other instructions from the memory 110 . Generally speaking, assuming that the current instruction is used to process one or more operands, the current instruction carries the data type information of the one or more operands. The data type information indicates the data type of the target operand corresponding to the current instruction. The data type information represents any "fixed (specified) data type", assuming the data type is known at compile time. For example, according to the actual application situation, the fixed data type may be 4-bit signed integer (signed integer) s4, 8-bit signed integer (s8), 8-bit unsigned integer (unsigned integer) u8, 8-bit floating point number f8 , 8-bit brain float bf8, 16-bit signed integer s16, standard 16-bit float f16, 16-bit brain float bf16, standard 32-bit float f32, 32-bit fast float Point number (fastfloat) ff32 or 32-bit floating point number f32+. In addition, according to the actual application situation, the operand may be a scalar, a vector, a matrix, a tensor or other operands. For example, in the application of the neural network, based on the actual design, the operand may be any one of multiple blocks after a matrix is divided. The size of the matrix and the size of the block can be determined according to actual design. For example, in some applications, the size of a block (operand) can be 32*32, 64*64 or other sizes.

In some cases, the data type of the target operand corresponding to the current instruction may not be determined at compile time (the data type is temporarily unknown). For example, the data type of the calculation result of the hidden layer (Hidden layer) of the Convolutional Neural Network (CNN) operation program may be dynamically determined after the calculation is actually performed. The instruction set of this embodiment can support "uncertain data type", that is, adaptive data type (adaptive data type). The adaptive data type means that the data type of the target operand is unknown (undefined) at compile time, but is dynamically determined at actual execution time.

Please refer to Figure 1 and Figure 2. In step S210, the computing core 120 may check the data type information of the current instruction. When the data type information indicates that the data types of all target operands of the current instruction are fixed data types (the determination result of step S220 is "No"), the operation core 120 may execute the current instruction based on the fixed data types to Process the target operand (step S230). According to the actual design, in some embodiments, step S230 may be a well-known practice, so it will not be repeated here.

The specific content of the data type information may be determined according to actual design. For example (but not limited thereto), the data type information may include 4 coded bits. When the 4-bit coded bit (data type information) is the first value (for example, 0), it means that the fixed data type is a 4-bit signed integer s4. When the data type information is the second value (for example, 1), it means that the fixed data type is an 8-bit signed integer s8. When the data type information is a third value (for example, 2), it means that the fixed data type is an 8-bit unsigned integer u8. When the data type information is the fourth value (for example, 3), it means that the fixed data type is a standard 16-bit floating point number f16. When the data type information is the fifth value (for example, 4), it means that the fixed data type is a standard 32-bit floating point number f32. When the data type information is the sixth value (for example, 5), it means that the fixed data type is a 16-bit brain floating point number bf16. When the data type information is the seventh value (for example, 9), it means that the fixed data type is an 8-bit floating point number f8 with a 4-bit exponent. When the data type information is the eighth value (for example, 10), it means that the fixed data type is an 8-bit brain floating point number bf8 with a 5-bit exponent. When the data type information is the ninth value (for example, 15), it indicates that the data type of the target operand is an adaptive data type.

When the data type information indicates that the data type of any target operand of the current instruction is an adaptive data type (the judgment result of step S220 is "Yes"), the operation core 120 can read the metadata corresponding to the target operand (meta data) to obtain the actual data type of the target operand from the metadata, or directly obtain the actual data type of the target operand (step S240). The specific content of the metadata can be determined according to the actual design. For example (but not limited thereto), the metadata may include an actual data type field for recording the actual data type of the target operand corresponding to the metadata. As one of many examples, the actual data type recorded in the actual data type field includes an 8-bit floating-point number with a first structure, an 8-bit floating-point number with a second structure, or a 16-bit floating-point number with a third structure . For example, assume that the actual data type field includes a 2-bit encoded number. When the code number is 0, it means that the actual data type of the target operand is an 8-bit floating-point number with "1-bit sign (sign), 5-bit exponent (exponent) and 2-bit mantissa (mantissa)" (first structure). Wherein, the symbols are used to represent positive and negative signs. When the encoding number is 1, it means that the actual data type of the target operand is an 8-bit floating point number of "1-bit sign, 4-bit exponent and 3-bit mantissa" (second structure). When the encoding number is 2, it means that the actual data type of the target operand is a 16-bit floating point number of "1-bit sign, 5-bit exponent and 10-bit mantissa" (third structure).

In some embodiments, the metadata may further include a scaling factor field, which is used to record the displacement (offset) of the exponent of the target operand. The calculation core 120 can convert the long-format data into short-format data according to the range of the exponent value of each element in the target operand (eg block). For example, assuming that the exponent values of all elements in a certain block (target operand) range from 10 to 20, the operation core 120 can move the exponent value range from 10 to 20 to the exponent value range from 0 to 10, and move The amount "-10" is described in the scaling factor field of the metadata. Therefore, when the computing core 120 executes the current instruction, the computing core 120 can restore the range of exponent values of all elements in the target operand from "0-10" to "10~20".

Based on the actual data type of the target operand recorded in the metadata, the computing core 120 may execute the current instruction to process the target operand (step S250 ). For example, assume that the current command includes a load command. When the data type information carried by the load instruction indicates that the data type of the target operand is an adaptive data type, the operation core 120 can read the metadata corresponding to the target operand from the memory 110, so as to obtain the target operand from the metadata. The actual data type (step S240 ), and then record the metadata and the actual data type in a register (register) inside the operation core 120 , such as a state register (state register) or other registers. Therefore, based on the actual data type of the target operand recorded in the metadata, the computing core 120 may execute a load instruction (current instruction) to load the target operand from the memory 110 into the computing core 120 . Assume further that the current instruction includes a matrix multiply and accumulate (MMA) instruction. When the data type information carried by the MMA instruction indicates that the data type of the target operand is an adaptive data type, the operation core 120 can directly obtain the actual data type of the target operand from its internal register (step S240).

FIG. 3 is a schematic circuit block diagram of the computing core 120 according to an embodiment of the present invention. The operation core 120 shown in FIG. 3 includes an operation circuit 121 , an operand buffer (operand buffer) 122 and a conversion unit (conversion unit) 123 . The calculation circuit 121 generates a calculation result after completing the calculation of the previous layer, and stores the calculation result Dorig in the operand buffer 122 . According to the actual design, in different embodiments, the operand buffer 122 can be configured inside the operation circuit 121, or outside the operation circuit 121, or be configured in a reduction buffer (reduction buffer), or be configured In thread local registers. In addition, the computing circuit 121 can count numerical features of the calculation result Dorig to generate a statistical result ST to the conversion unit 123 .

The operand buffer 122 can provide the calculation result Dorig to the conversion unit 123 . The conversion unit 123 converts the calculation result Dorig into an operand Dconv (target operand) having a data type suitable for next layer calculation and metadata Dm corresponding to the operand Dconv based on the statistical result ST. During actual execution, the conversion unit 123 dynamically determines the data type of the operand Dconv, so the conversion unit 123 records the actual data type of the operand Dconv in the metadata Dm corresponding to the operand Dconv, and then combines the operand Dconv with the metadata Dm is stored in memory 110 .

FIG. 4 is a schematic circuit block diagram of the computing core 120 according to another embodiment of the present invention. The operation core 120 shown in FIG. 4 includes an operation circuit 121 , a load unit 124 , a state register 125 and an operand buffer 126 . The loading unit 124 is coupled to the memory 110 . The status register 125 is coupled between the loading unit 124 and the operation circuit 121 . The operand buffer 126 is coupled between the loading unit 124 and the operation circuit 121 . According to actual design, in different embodiments, the operation circuit 121 may include a tensor core, a general matrix multiplication (GEMM) core, an arithmetic logic unit (ALU) and/or other operation units.

As an illustrative example, assume that the current command includes a load command. When the data type information carried by the load instruction indicates that the data type of the target operand is an adaptive data type, the loading unit 124 can read the metadata corresponding to the target operand from the memory 110, so as to obtain the target operand from the metadata. actual data type. The loading unit 124 stores the metadata in the state register 125 for use by the operation circuit 121 . In addition, the loading unit 124 may read the target operand from the memory 110 based on the “actual data type of the target operand” described in the metadata. The loading unit 124 stores the target operand in the operand buffer 126 for use by the operation circuit 121 .

As another illustrative example, assume that the current instruction includes a matrix multiply and accumulate (MMA) instruction, and the target operands (the first operand and the second operand) corresponding to the matrix multiply and accumulate instruction have been loaded by the previously executed load Instructions are loaded into operand buffer 126 . Furthermore, the first operand corresponds to first metadata and the second operand corresponds to second metadata. It can be deduced from the description in the previous paragraph that the previously executed load instruction can combine the first metadata and the actual data type recorded in the first metadata (the actual data type of the first operand) with the first The binary data and the actual data type recorded in the second metadata (the actual data type of the first operand) are stored in the status register 125 . When the data type information of the matrix multiply and accumulate instruction indicates that the data type of the first operand is an adaptive data type, the operation circuit 121 can directly obtain the actual data type of the first operand from the status register 125 . When the data type information of the matrix multiply and accumulate instruction indicates that the data type of the second operand is an adaptive data type, the operation circuit 121 can directly obtain the actual data type of the second operand from the status register 125 . Based on the actual data type of the first operand and the actual data type of the second operand, the operation circuit 121 can correctly read the first operand and the second operand from the operand buffer 126, and correctly Perform matrix multiplication with two operands.

To sum up, the operation core 120 can check the data type information of the current instruction to determine whether the data type of the target operand corresponding to the current instruction is a fixed (specified) data type or an adaptive data type. The fixed data type means that the data type of the target operand is known at compile time. The adaptive data type means that the data type of the target operand is unknown when compiling, but is determined dynamically when the program is executed. When the program is actually executed, the actual data type of the target operand is recorded in the metadata corresponding to the target operand. Before the computing core 120 executes the current instruction, the computing core 120 may check the data type of the target operand corresponding to the current instruction. When the data type of the target operand is an adaptive data type, the calculation core 120 may obtain the actual data type of the target operand from the metadata corresponding to the target operand. Based on the actual data type of the target operand recorded in the metadata, the computing core 120 can correctly execute the current instruction to process the target operand.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.

Claims (27)

1. A method of operation of a computing device, the method of operation comprising:

checking data type information carried by a current instruction, wherein the data type information represents a data type of a target operand corresponding to the current instruction;

when the data type information indicates that the data type of the target operand is an adaptive data type, reading metadata corresponding to the target operand to obtain the actual data type of the target operand from the metadata, or directly obtaining the actual data type of the target operand; and

based on the actual data type of the target operand that is recorded by the metadata, the current instruction is executed to process the target operand.

2. The method of claim 1, wherein the adaptive data type indicates that a data type of the target operand is unknown at compile time and is dynamically determined at execution time.

3. The method of operation of claim 1, further comprising:

when the data type information indicates that the data type of the target operand is a fixed data type, the current instruction is executed to process the target operand based on the fixed data type.

4. The method of operation of claim 3, wherein the fixed data type comprises a 4-bit signed integer, an 8-bit unsigned integer, an 8-bit floating point, an 8-bit brain floating point, a 16-bit signed integer, a standard 16-bit floating point, a 16-bit brain floating point, a standard 32-bit floating point, a 32-bit fast floating point, or a floating point above 32 bits.

5. The method of claim 4, wherein the fixed data type is a 4-bit signed integer s4 when the data type information is a first value, the fixed data type is an 8-bit signed integer s8 when the data type information is a second value, the fixed data type is an 8-bit unsigned integer u8 when the data type information is a third value, the fixed data type is a standard 16-bit floating point f16 when the data type information is a fourth value, the fixed data type is a standard 32-bit floating point f32 when the data type information is a fifth value, the fixed data type is a 16-bit brain floating point bf16 when the data type information is a sixth value, the fixed data type is an 8-bit floating point f8 with a 4-bit exponent when the data type information is a seventh value, the fixed data type is an 8-bit floating point with a 5-bit exponent when the data type information is an eighth value, and the data type is adapted to the target data type operation.

6. The method of claim 1, wherein the current instruction comprises a load instruction, the method further comprising:

when the data type information carried by the load instruction indicates that the data type of the target operand is the self-adaptive data type, reading the metadata corresponding to the target operand from a memory so as to obtain the actual data type of the target operand from the metadata;

storing the metadata and the actual data type recorded by the metadata in a state register of an operation core;

reading the target operand from the memory based on the actual data type of the target operand recorded by the metadata; and

depositing the target operand in an operand buffer of the arithmetic core.

7. The method of operation of claim 6, wherein the arithmetic core comprises a tensor core, a universal matrix multiplication core, or an arithmetic logic unit.

8. The method of operation of claim 1 wherein the current instruction comprises a matrix multiply and accumulate instruction, the target operand comprises a first operand and a second operand, the metadata comprises a first metadata and a second metadata, the first metadata corresponds to the first operand, the second metadata corresponds to the second operand, the method further comprising:

when the data type information carried by the matrix multiply-accumulate instruction indicates that the data type of the first operand is the self-adaptive data type, directly acquiring the actual data type of the first operand from a state register of an operation core;

when the data type information carried by the matrix multiply and accumulate instruction indicates that the data type of the second operand is the adaptive data type, directly acquiring the actual data type of the second operand from the state register of the operation core;

reading the first operand and the second operand from an operand buffer of the arithmetic core based on the actual data type of the first operand and the actual data type of the second operand; and

performing a matrix multiplication calculation on the first operand and the second operand.

9. The method of claim 1, wherein the metadata comprises an actual data type field for describing the actual data type of the target operand to which the metadata corresponds.

10. The method of operation of claim 9, wherein the real data type specified by the real data type field comprises an 8-bit floating point number having a first structure, an 8-bit floating point number having a second structure, or a 16-bit floating point number having a third structure.

11. The method of operation of claim 10 wherein the first structure is a "1-bit symbol, a 5-bit exponent, and a 2-bit mantissa", the second structure is a "1-bit symbol, a 4-bit exponent, and a 3-bit mantissa", and the third structure is a "1-bit symbol, a 5-bit exponent, and a 10-bit mantissa".

12. The method of operation of claim 9 wherein the metadata further comprises a scale factor field to document an amount of shift in the exponent of the target operand.

13. The method of operation of claim 1, further comprising:

generating a calculation result through an operation core;

counting the numerical characteristics of the calculation result through the operation core to generate a statistical result;

converting, by the computation core, the computation result into the target operand and the metadata based on the statistical result; and

and storing the target operand and the metadata in a memory.

14. A machine-readable storage medium storing non-transitory machine-readable instructions which, when executed by a computer, may implement a method of operation of the computing device of any of claims 1-13.

15. A computing device, the computing device comprising:

a memory for storing a target operand; and

an operation core coupled to the memory, wherein,

the arithmetic core checks data type information carried by a current instruction, wherein the data type information represents the data type of the target operand corresponding to the current instruction;

when the data type information indicates that the data type of the target operand is an adaptive data type, the arithmetic core reads metadata corresponding to the target operand to obtain an actual data type of the target operand from the metadata, or directly obtains the actual data type of the target operand; and

the arithmetic core executes the current instruction to process the target operand based on the actual data type of the target operand documented by the metadata.

16. The computing device of claim 15, wherein the adaptive data type represents a data type of the target operand that is unknown at compile time and dynamically determined at execution time.

17. The computing device of claim 15,

when the data type information indicates that the data type of the target operand is a fixed data type, the arithmetic core executes the current instruction to process the target operand based on the fixed data type.

18. The computing device of claim 17, wherein the fixed data type comprises a 4-bit signed integer, an 8-bit unsigned integer, an 8-bit floating point number, an 8-bit brain floating point number, a 16-bit signed integer, a standard 16-bit floating point number, a 16-bit brain floating point number, a standard 32-bit floating point number, a 32-bit fast floating point number, or a floating point number greater than 32 bits.

19. The computing device of claim 18, wherein the fixed data type is a 4-bit signed integer s4 when the data type information is a first value, the fixed data type is an 8-bit signed integer s8 when the data type information is a second value, the fixed data type is an 8-bit unsigned integer u8 when the data type information is a third value, the fixed data type is a standard 16-bit floating point f16 when the data type information is a fourth value, the fixed data type is a standard 32-bit floating point f32 when the data type information is a fifth value, the fixed data type is a 16-bit brain floating point bf16 when the data type information is a sixth value, the fixed data type is an 8-bit floating point f8 with a 4-bit exponent when the data type information is a seventh value, the fixed data type is an 8-bit brain floating point bf8 with a 5-bit exponent when the data type information is an eighth value, and the data type is adaptable to the target data type operation when the data type information is a ninth value.

20. The computing device of claim 15, wherein the current instruction comprises a load instruction, and wherein the arithmetic core comprises:

a load unit coupled to the memory, wherein when the data type information carried by the load instruction indicates that the data type of the target operand is the adaptive data type, the load unit reads the metadata corresponding to the target operand from the memory to obtain the actual data type of the target operand from the metadata, and the load unit reads the target operand from the memory based on the actual data type of the target operand recorded by the metadata;

a status register coupled to the load unit, wherein the load unit stores the metadata and the actual data type recorded by the metadata in the status register; and

an operand buffer coupled to the load unit, wherein the load unit stores the target operand in the operand buffer.

21. The computing device of claim 20, wherein the computational core further comprises:

an arithmetic circuit coupled to the status register and the operand buffer, wherein the arithmetic circuit comprises a tensor core, a universal matrix multiplication core, or an arithmetic logic unit.

22. The computing device of claim 15, wherein the current instruction comprises a matrix multiply and accumulate instruction, and wherein the arithmetic core comprises:

an operand buffer to store the target operand, wherein the target operand comprises a first operand and a second operand;

a status register for storing the metadata and the actual data type recorded by the metadata, wherein the metadata includes a first metadata and a second metadata, the first metadata corresponds to the first operand, and the second metadata corresponds to the second operand; and

an arithmetic circuit coupled to the status register and the operand buffer, wherein

When the data type information carried by the matrix multiply and accumulate instruction indicates that the data type of the first operand is the adaptive data type, the arithmetic circuit directly acquires the actual data type of the first operand from the state register;

when the data type information carried by the matrix multiply-and-accumulate instruction indicates that the data type of the second operand is the adaptive data type, the arithmetic circuit directly acquires the actual data type of the second operand from the status register;

based on the actual data type of the first operand and the actual data type of the second operand, the arithmetic circuitry reads the first operand and the second operand from the operand buffer; and

the arithmetic circuit performs a matrix multiplication calculation on the first operand and the second operand.

23. The computing device of claim 15, wherein the metadata comprises an actual data type field to record the actual data type of the target operand to which the metadata corresponds.

24. The computing device of claim 23, wherein the actual data type recited in the actual data type field comprises an 8-bit floating point number having a first structure, an 8-bit floating point number having a second structure, or a 16-bit floating point number having a third structure.

25. The computing device of claim 24, wherein the first structure is a "1-bit symbol, a 5-bit exponent, and a 2-bit mantissa", wherein the second structure is a "1-bit symbol, a 4-bit exponent, and a 3-bit mantissa", and wherein the third structure is a "1-bit symbol, a 5-bit exponent, and a 10-bit mantissa".

26. The computing device of claim 23, wherein the metadata further comprises a scale factor field to document an amount of shift in exponent for the target operand.

27. The computing device as claimed in claim 15, wherein the computing core generates a computation result, the computing core performs statistics on a numerical characteristic of the computation result to generate a statistical result, the computing core converts the computation result into the target operand and the metadata based on the statistical result, and the computing core stores the target operand and the metadata in the memory.

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