CN115378420A - Level conversion circuit, voltage measuring device and voltage measuring method - Google Patents

Abstract

A level conversion circuit, a voltage measurement device and a voltage measurement method are provided. The level shift circuit includes: the voltage-controlled power supply comprises a current mirror circuit unit, an output circuit unit, a voltage dividing circuit unit, an output end and an input end, wherein the input end is used for receiving input voltage, the output end is used for providing output voltage, the current mirror circuit unit comprises a first end connected with first power supply voltage, a second end connected with the output end and a third end connected with the voltage dividing circuit unit, the current mirror circuit unit is configured to provide mirror current at the second end and the third end, the output circuit unit is connected between the second power supply voltage and the output end and receives the input voltage from the input end, the output circuit unit is configured to provide the output voltage at the output end based on control of the second power supply voltage under control of the input voltage, and the voltage dividing circuit unit is connected between the second power supply voltage and the third end of the current mirror circuit unit. The method can improve the accuracy of level conversion.

Description

Level conversion circuit, voltage measuring device and voltage measuring method

technical field

Embodiments of the present disclosure relate to a level conversion circuit, a voltage measurement device and a voltage measurement method.

Background technique

With the continuous development of semiconductor technology, multiple circuit modules are integrated inside the chip, and these circuit modules have multiple voltage domains. In order to meet the level requirements of multiple circuit modules, level conversion is often required, and in order to ensure that the chip is in a normal working environment, it is necessary to monitor the voltage of each important node in the chip to ensure that the chip is in a normal working state.

Contents of the invention

At least one embodiment of the present disclosure provides a level conversion circuit, including: a current mirror circuit unit, an output circuit unit, a voltage divider circuit unit, an output terminal and an input terminal, the input terminal is used to receive an input voltage, and the output terminal is used to provide an output Voltage, the current mirror circuit unit includes a first end connected to the first power supply voltage, a second end connected to the output end and a third end connected to the voltage dividing circuit unit, the current mirror circuit unit is configured to provide a mirror image at the second end and the third end current, the output circuit unit is connected between the second supply voltage and the output terminal, and receives the input voltage from the input terminal, the output circuit unit is configured to provide an output voltage at the output terminal based on the control of the second supply voltage under the control of the input voltage, The voltage dividing circuit is connected between the second power supply voltage and the third terminal of the current mirror circuit unit.

For example, in the level conversion circuit provided in an embodiment of the present disclosure, the current mirror circuit unit includes a first transistor and a second transistor, the gate of the first transistor is connected to the gate of the second transistor, and the The gate of the first transistor is connected to the first pole of the first transistor, and is commonly connected to the voltage dividing circuit unit, the second pole of the first transistor is connected to the first terminal, and the second The second pole of the transistor is connected to the first terminal, the first pole of the second transistor is connected to the second terminal, and the specifications of the first transistor and the second transistor are the same.

For example, in the level conversion circuit provided in an embodiment of the present disclosure, the output circuit unit includes a third transistor, the gate of the third transistor is connected to the input terminal to receive the input voltage, and the third transistor The second pole is connected to the output terminal, and the first pole of the third transistor is connected to the second power supply voltage.

For example, in the level conversion circuit provided in an embodiment of the present disclosure, the voltage dividing circuit unit includes a fourth transistor, and the gate of the fourth transistor and the first pole of the fourth transistor are commonly connected to the second power supply voltage , the second pole of the fourth transistor is connected to the third terminal of the current mirror circuit unit.

For example, in the level conversion circuit provided by an embodiment of the present disclosure, the specifications of the first transistor and the fourth transistor are the same.

For example, the level conversion circuit provided in an embodiment of the present disclosure further includes: a reference voltage generating unit configured to provide a reference voltage, one of the first power supply voltage and the second power supply voltage being the reference voltage.

For example, in the level conversion circuit provided by an embodiment of the present disclosure, the reference voltage generation unit includes a bandgap voltage reference circuit, wherein the bandgap voltage reference circuit provides the reference voltage.

For example, in the level conversion circuit provided in an embodiment of the present disclosure, the reference voltage generating unit further includes a unity gain buffer, wherein the first end of the unit gain buffer is connected to the bandgap voltage reference circuit , the second end of the unit gain buffer is connected to the first end of the current mirror circuit unit.

For example, in the level conversion circuit provided in an embodiment of the present disclosure, the first power supply voltage is the reference voltage, and each of the current mirror circuit unit, the output circuit unit and the voltage divider circuit unit includes at least one transistor , each of the at least one transistor is a P-type metal oxide semiconductor field effect transistor.

For example, in the level conversion circuit provided in an embodiment of the present disclosure, the second power supply voltage is the reference voltage, and each of the current mirror circuit unit, the output circuit unit and the voltage divider circuit unit includes at least one transistor , each of the at least one transistor is an N-type metal oxide semiconductor field effect transistor.

At least one embodiment of the present disclosure provides a voltage measurement device, including: a measurement voltage generation unit and a signal processing unit, and the measurement voltage generation unit includes the level conversion circuit described in any of the above embodiments, an input voltage receiving terminal and a measurement voltage output Terminal, the input voltage receiving terminal is used to receive the input voltage from the input voltage signal terminal, the measured voltage output terminal is connected to the signal processing unit, the level conversion circuit is connected to the input voltage receiving terminal, and configured To receive the input voltage and provide an output voltage to the measurement voltage output terminal, the signal processing unit includes a first signal receiving terminal and a second signal receiving terminal, the first signal receiving terminal is connected to the measurement voltage output terminal The terminal is connected to receive the output voltage, the second signal receiving terminal is used to receive a reference voltage, and the signal processing unit is configured to output a measurement result of the output voltage based on the reference voltage.

For example, in the voltage measurement device provided in an embodiment of the present disclosure, the measurement voltage generating unit includes a first level conversion circuit and a second level conversion circuit, and the measurement voltage generation unit further includes a first switch unit, a second Two switch units and a third switch unit, the first level conversion circuit is connected to the measurement voltage output terminal through the first switch unit, and the second level conversion circuit is connected to the measured voltage output terminal through the second switch unit The measurement voltage output terminal is connected, the measurement voltage output terminal is also connected to the input voltage signal terminal through the third switch unit, and the first level conversion circuit and the second level conversion circuit also receive the reference voltage The first power supply voltage connected to the first level conversion circuit is the reference voltage, and the second power supply voltage connected to the second level conversion circuit is the reference voltage.

For example, in the voltage measuring device provided in an embodiment of the present disclosure, the first switch unit, the second switch unit and the third switch unit are configured to respond to a control signal, and when the input voltage is in the signal processing unit In the case of the voltage measurement range, the control signal is used to control the first switch unit to disconnect the measured voltage output terminal from the first level conversion circuit, and the second switch unit to disconnect The second level conversion circuit is connected to the measurement voltage output terminal and the third switch unit conducts the input voltage signal terminal and the measurement voltage output terminal; when the input voltage is lower than the signal processing unit In the case of the minimum value of the voltage measurement range, the control signal is used to control the first switch unit to turn on the measurement voltage output terminal and disconnect the first level conversion circuit and the second switch unit The second level conversion circuit is connected to the measurement voltage output terminal and the third switch unit is disconnected from the input voltage signal terminal to the measurement voltage output terminal; when the input voltage is greater than the signal processing In the case of the maximum value of the voltage measurement range of the unit, the control signal is used to control the first switch unit to disconnect the connection between the measured voltage output terminal and the first level conversion circuit, and the second switch The unit turns on the second level conversion circuit and the measurement voltage output terminal, and the third switch unit disconnects the connection between the input voltage signal terminal and the measurement voltage output terminal.

For example, in the voltage measurement device provided by an embodiment of the present disclosure, the signal processing unit includes a digital-to-analog conversion unit.

At least one embodiment of the present disclosure provides a voltage measurement method, which is applied to the voltage measurement device provided in the above embodiment, and the voltage measurement method includes: responding to the input voltage receiving end receiving the input voltage, comparing the input voltage and the voltage measurement range of the signal processing unit to obtain a comparison result; based on the comparison result, generate the control signal; according to the control signal, control the first switch unit, the second switch unit and the Opening or closing of the third switch unit; and measuring the output voltage provided by the measurement voltage output terminal by the signal processing unit, and outputting a measurement result.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present disclosure more clearly, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure .

FIG. 1 shows a block diagram of a level conversion circuit provided by at least one embodiment of the present disclosure;

FIG. 2 shows a circuit structure of a level conversion circuit provided by at least one embodiment of the present disclosure;

FIG. 3 shows a circuit structure of a level conversion circuit provided by at least one embodiment of the present disclosure;

Fig. 4 shows a schematic block diagram of a voltage measuring device provided by at least one embodiment of the present disclosure;

Fig. 5 shows a schematic diagram of a circuit structure of a voltage measurement device provided by at least one embodiment of the present disclosure; and

Fig. 6 shows a flowchart of a voltage measurement method provided by at least one embodiment of the present disclosure.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Apparently, the described embodiments are some of the embodiments of the present disclosure, not all of them. Based on the described embodiments of the present disclosure, all other embodiments obtained by persons of ordinary skill in the art without creative effort fall within the protection scope of the present disclosure.

Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the usual meanings understood by those skilled in the art to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Likewise, words like "a", "an" or "the" do not denote a limitation of quantity, but mean that there is at least one. "Comprising" or "comprising" and similar words mean that the elements or items appearing before the word include the elements or items listed after the word and their equivalents, without excluding other elements or items. Words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "Down", "Left", "Right" and so on are only used to indicate the relative positional relationship. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

Different voltage domains often appear between multiple circuit modules in a chip. For example, when each circuit module communicates through the bus, some of the circuit modules connected to the bus use a 3V voltage domain, and some use a 5V voltage domain. The level conversion circuit can realize the conversion between high level and low level between circuit modules in different voltage domains, so that the module circuits in different voltage domains can communicate better. Not only that, the level conversion circuit can also realize the conversion of impedance; even the level conversion circuit has certain isolation and filtering functions. Therefore, the level conversion unit plays a very important role in the chip. However, due to the influence of factors such as temperature, power supply voltage, and process errors, the conversion accuracy of the level conversion unit is relatively low.

At least one embodiment of the present disclosure provides a level conversion circuit, a voltage measurement device and a voltage measurement method. The level conversion circuit method includes: a current mirror circuit unit, an output circuit unit, a voltage dividing circuit unit, an output terminal and an input terminal, the input terminal is used to receive the input voltage, the output terminal is used to provide the output voltage, and the current mirror circuit unit includes a connection The first terminal of the first supply voltage, the second terminal connected to the output terminal and the third terminal connected to the voltage dividing circuit unit, the current mirror circuit unit is configured to provide mirror current at the second terminal and the third terminal, and the output circuit unit is connected to the second terminal. Between the two power supply voltages and the output terminal, and receiving the input voltage from the input terminal, the output circuit unit is configured to provide an output voltage at the output terminal based on the control of the second power supply voltage under the control of the input voltage, and the voltage divider circuit is connected to the second Between the supply voltage and the third terminal of the current mirror circuit unit. This method can improve the precision of level conversion.

At least one embodiment of the present disclosure provides a voltage measurement device, including: a measurement voltage generation unit and a signal processing unit, the measurement voltage generation unit includes the level conversion circuit of any of the above embodiments, an input voltage receiving terminal and a measurement voltage output terminal, The input voltage receiving end is used to receive the input voltage from the input voltage signal end, the measuring voltage output end is connected to the signal processing unit, the level conversion circuit is connected to the input voltage receiving end, and is configured to receive the input voltage, and provide the measuring voltage output end Output voltage, the signal processing unit includes a first signal receiving end and a second signal receiving end, the first signal receiving end is connected to the measurement voltage output end to receive the output voltage, the second signal receiving end is used to receive the reference voltage, the signal processing unit is configured Based on the reference voltage, the measurement result of the output voltage is output. The voltage measurement device can increase the voltage measurement range of the signal processing unit.

Fig. 1 shows a block diagram of a level conversion circuit 100 provided by at least one embodiment of the present disclosure.

As shown in FIG. 1 , the level conversion circuit 100 includes a current mirror circuit unit 101 , a voltage dividing circuit unit 102 , an output circuit unit 103 , an output terminal Pout and an input terminal Pin.

The input terminal Pin is used to receive the input voltage Vin, and the output terminal Pout is used to provide the output voltage Vout.

The current mirror circuit unit 101 includes a first terminal P1 connected to the first power supply voltage V1 , a second terminal P2 connected to the output terminal Pout and a third terminal P3 connected to the voltage divider circuit unit 102 . The current mirror circuit unit 101 is configured to provide a mirror current at the second terminal P2 and the third terminal P3.

The voltage divider circuit 102 is connected between the second power supply voltage V2 and the third terminal P3 of the current mirror circuit unit 101 .

The output circuit unit 103 is connected between the second power supply voltage V2 and the output terminal Pout, and receives the input voltage Vin from the input terminal Pin. The output circuit unit 103 is configured to provide the output voltage Vout at the output terminal Pout based on the control of the second power supply voltage V2 under the control of the input voltage Vin.

The level conversion circuit mirrors the current through the current mirror circuit unit, so that the current flowing through the voltage divider circuit unit 102 and the output circuit unit 103 are the same, thereby reducing the influence of errors such as temperature and process, and effectively improving the level conversion accuracy.

FIG. 2 shows a circuit structure 200 of a level conversion circuit 100 provided by at least one embodiment of the present disclosure.

As shown in FIG. 2 , in the circuit structure 200 , the current mirror circuit unit 101 includes a first transistor M1 and a second transistor M2 . The specifications of the first transistor M1 and the second transistor M2 are the same.

In the embodiments of the present disclosure, the same specification means, for example, that the two transistors have the same physical parameters such as channel aspect ratio and threshold voltage. For example, the two transistors may be Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) of the same type. For example, physical parameters such as channel aspect ratio and threshold voltage of the first transistor M1 and the second transistor M2 are the same. For example, the first transistor M1 and the second transistor M2 may both be P-type MOSFETs (hereinafter referred to as P-type transistors) or N-type metal-oxide-semiconductor field-effect transistors (hereinafter referred to as N-type transistors).

As shown in FIG. 2, in the circuit structure 200, the gate Gate of the first transistor M1 is connected to the gate Gate of the second transistor M2, the gate M1 of the first transistor is connected to the first pole of the first transistor M1, and Commonly connected to the voltage dividing circuit unit 102, the second pole of the first transistor M1 is connected to the first terminal P1. The second pole of the second transistor M2 is connected to the first terminal P1, and the first pole of the second transistor M2 is connected to the second terminal P2. The first end P1 is connected to the first power supply voltage V1.

For example, the first transistor M1 is a P-type transistor, a first pole of the first transistor M1 is a drain of the P-type transistor, and a second pole of the first transistor M1 is a source of the P-type transistor. As shown in Figure 2, the gate and drain of the P-type tube are connected together to form a diode, and the gate and drain of the P-type tube are connected together and then connected to the voltage divider circuit unit 102 through the third terminal. The source of the P-type tube is connected to the first terminal P1.

The gate and drain of the first transistor M1 are connected together, and the gate of the first transistor M1 and the gate of the second transistor M2 are connected together to form a current mirror structure.

In some embodiments of the present disclosure, the second transistor M2 has the same specifications as the first transistor M1, so if the first transistor is a P-type transistor, the second transistor M2 is also a P-type transistor. If the second transistor M2 is a P-type transistor, the first pole of the second transistor M2 is the drain of the P-type transistor, and the second pole of the second transistor M2 is the source of the P-type transistor. As shown in FIG. 2 , the source of the second transistor M2 is connected to the first terminal P1 , and the drain of the second transistor M2 is connected to the output terminal Pout through the second terminal P2 .

In some embodiments of the present disclosure, the output circuit unit 103 may include a third transistor M3. The gate Gate of the third transistor M3 is connected to the input terminal Pin to receive the input voltage Vin, the second pole of the third transistor M3 is connected to the output terminal Pout, and the first pole of the third transistor M3 is connected to the second power supply voltage V2.

In some embodiments of the present disclosure, the third transistor M3 may be a P-type transistor or an N-type transistor.

In some embodiments of the present disclosure, as shown in FIG. 2 , the voltage dividing circuit unit 102 includes a fourth transistor M4. The gate Gate of the fourth transistor M4 and the first pole of the fourth transistor M4 are commonly connected to the second power supply voltage V2 , and the second pole of the fourth transistor M4 is connected to the third terminal P3 of the current mirror circuit unit 101 .

The gate Gate of the fourth transistor M4 is connected with the first pole of the fourth transistor M4, so that the fourth transistor M4 also forms a diode form, which is the same as the first transistor M1, thereby reducing the size of the first transistor M1 and the fourth transistor M1. The voltage division of M4 is affected by temperature, process, etc. to provide level conversion accuracy.

In some embodiments of the present disclosure, the specifications of the first transistor M1 and the fourth transistor M4 are the same. For "same specifications", please refer to the description above. The same specifications of the first transistor M1 and the fourth transistor M4 can ensure the same voltage drop across the first transistor M1 and the fourth transistor M4, thereby reducing the influence of temperature, process, etc., and improving the precision of level shifting.

In the example shown in FIG. 2, for example, if the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M3 are all P-type transistors, the second power supply voltage V2 is smaller than the first power supply voltage V1, so that The current direction is from the first terminal P1 to the node P4.

For example, the second supply voltage may be grounded.

In some embodiments of the present disclosure, as shown in FIG. 1 , the level conversion circuit 100 may further include a reference voltage generation unit 104 . The reference voltage generating unit 104 is configured to provide a reference voltage Vref, and one of the first power supply voltage V1 and the second power supply voltage V2 is the reference voltage.

In the examples of FIGS. 1 and 2 , the first power supply voltage V1 is the reference voltage Vref. In other embodiments of the present disclosure, the second power supply voltage is used as the reference voltage Vref, please refer to the example in FIG. 3 .

For example, in the circuit structure 200 shown in FIG. 2 , besides the current mirror circuit unit 101 , the output circuit unit 103 and the voltage dividing circuit unit 102 , a reference voltage generation unit 104 may also be included. The reference voltage generation unit 104 provides the reference voltage Vref, that is, the first terminal P1 receives the reference voltage Vref from the reference voltage generation unit- 104 .

As shown in FIG. 2 , the reference voltage generation unit 104 includes a bandgap voltage reference circuit BG_vref. The bandgap voltage reference circuit BG_vref provides a reference voltage Vref. The reference voltage generated by the bandgap voltage reference circuit BG_vref does not change with subsequent circuits (ie, the current mirror circuit unit 101, the output circuit unit 103, and the voltage divider circuit unit 102), thereby providing a highly stable and high-precision reference voltage Vref.

As shown in FIG. 2 , the bandgap voltage reference circuit BG_vref is connected to the power supply voltage Vdd to receive the power supply voltage Vdd and provide a reference voltage Vref. The reference voltage Vref provided by the bandgap voltage reference circuit BG_vref can reduce the error caused by the power supply voltage, because the reference voltage Vref provided by the bandgap voltage reference circuit BG_vref is a parameter that does not vary with temperature, process and power supply voltage.

As shown in FIG. 2 , the reference voltage generation unit 104 further includes a unity gain buffer 114 . A first terminal of the unit gain buffer 114 is connected to the bandgap voltage reference circuit BG_vref, and a second terminal of the unit gain buffer 114 is connected to the first terminal P1 of the current mirror circuit unit 101 .

The unity gain buffer 114 receives the reference voltage Vref provided by the bandgap voltage reference circuit BG_vref, and provides the reference voltage Vref to the current mirror circuit unit 101 .

The unity gain buffer 114 can isolate the bandgap voltage reference circuit BG_vref from subsequent circuits, thereby further ensuring that the bandgap voltage reference circuit BG_vref provides a highly stable and high-precision reference voltage Vref.

As shown in FIG. 2 , for example, the first transistor M1 , the second transistor M2 , the third transistor M3 and the fourth transistor M4 are all the same P-type transistors. The first transistor M1 and the fourth transistor M4 are connected in a diode form. The first transistor M1 and the fourth transistor M4 divide the voltage, so Vref=Vgs1+Vgs4. Vgs1 and Vgs4 represent gate-source voltages of the first transistor M1 and the fourth transistor M4, respectively.

Since the specifications of the first transistor M1 and the fourth transistor M4 are the same, Vgs1=Vgs4=Vref/2.

The first transistor M1 and the second transistor M2 mirror the current through a current mirror, so Id1=Id2, Vgs2=Vgs1, Vgs2=Vgs3. Id1 and Id2 respectively represent the current flowing through the first transistor M1 and the second transistor M2, Vgs2 represents the gate-source voltage of the second transistor M2, and Vgs3 represents the gate-source voltage of the third transistor M3. Therefore, it is ensured that the difference between Vin and Vout is the gate-source voltage of the third transistor M3, so Vout=Vin+Vgs3=Vin+Vref/2.

Therefore, Vout is only related to the reference voltage Vref and the input Vin, which eliminates the influence of errors such as temperature and process, and effectively improves the level conversion accuracy. Moreover, in the circuit structure 200 of FIG. 2 , the output voltage Vout is greater than the input voltage Vin, therefore, the circuit structure 200 plays a role of boosting voltage.

In some embodiments of the present disclosure, the second power supply voltage V2 is the reference voltage Vref, the current mirror circuit unit 101, the output circuit unit 103 and the voltage divider circuit unit 102 each include at least one transistor, each of the at least one transistor is It may be an N-type metal oxide semiconductor field effect transistor.

FIG. 3 shows a circuit structure 300 of a level conversion circuit 100 provided by at least one embodiment of the present disclosure.

As shown in FIG. 3 , in the circuit structure 300, the current mirror circuit unit 101 includes a first transistor M'1 and a second transistor M'2. The specifications of the first transistor M'1 and the second transistor M'2 are the same.

The gate Gate of the first transistor M'1 is connected to the gate Gate of the second transistor M'2, the gate M'1 of the first transistor is connected to the first pole of the first transistor M'1, and is connected to the branch In the voltage circuit unit 102, the second pole of the first transistor M'1 is connected to the first terminal P1. The second pole of the second transistor M'2 is connected to the first terminal P1, and the first pole of the second transistor M'2 is connected to the second terminal P2. The first terminal P1 is connected to the first power supply voltage V'1.

For example, the first transistor M'1 is an N-type transistor, the first pole of the first transistor M'1 is the drain of the N-type transistor, and the second pole of the first transistor M'1 is the source of the N-type transistor. As shown in Figure 3, the gate and drain of the N-type tube are connected together to form a diode, and the gate and drain of the N-type tube are connected together and then connected to the voltage divider circuit unit 102 through the third terminal. The source of the N-type tube is connected to the first terminal P1.

The gate and drain of the first transistor M'1 are connected together, and the gate of the first transistor M'1 and the gate of the second transistor M'2 are connected together to form a current mirror structure.

In some embodiments of the present disclosure, the second transistor M'2 has the same specifications as the first transistor M'1, so if the first transistor M'1 is an N-type transistor, the second transistor M'2 is also an N-type transistor. type tube. As shown in Figure 2, the source of the second transistor M'2 is connected to the first terminal P1, and the drain of the second transistor M'2 is connected to the output terminal P'out through the second terminal P2.

In some embodiments of the present disclosure, the output circuit unit 103 may include a third transistor M'3. The gate Gate of the third transistor M'3 is connected to the input terminal P'in to receive the input voltage Vin, the second pole of the third transistor M'3 is connected to the output terminal P'out, and the first pole of the third transistor M'3 is connected to The second supply voltage V'2.

In the example of Fig. 3, the third transistor M'3 is an N-type transistor.

In some embodiments of the present disclosure, as shown in FIG. 3 , the voltage dividing circuit unit 102 includes a fourth transistor M'4. The gate Gate of the fourth transistor M'4 and the first pole of the fourth transistor M'4 are commonly connected to the second power supply voltage V'2, and the second pole of the fourth transistor M'4 is connected to the current mirror circuit unit 101 The third terminal P3 is connected.

The gate Gate of the fourth transistor M'4 is connected to the first pole of the fourth transistor M'4, so that the fourth transistor M'4 also forms a diode, which is the same as the first transistor M'1, thereby reducing the The voltage division of the first transistor M'1 and the fourth transistor M'4 is affected by temperature, process, etc., so as to provide level conversion precision.

In some embodiments of the present disclosure, the specifications of the first transistor M'1 and the fourth transistor M'4 are the same. The same specifications of the first transistor M'1 and the fourth transistor M'4 can ensure the same voltage drop on the first transistor M'1 and the fourth transistor M'4, thereby reducing the influence of temperature, process, etc., and improving level conversion accuracy.

In the example shown in FIG. 3, for example, if the first transistor M'1, the second transistor M'2, the third transistor M'3 and the fourth transistor M'3 are all N-type transistors, the second power supply voltage V '2 is greater than the first power supply voltage V'1, so that the current direction is from the node P'4 to the first terminal P1.

For example, the first supply voltage V'1 may be grounded.

As shown in FIG. 3 , the circuit structure 300 may include a reference voltage generating unit 104 in addition to the current mirror circuit unit 101 , the output circuit unit 103 and the voltage dividing circuit unit 102 . The reference voltage generation unit 104 is configured to provide a reference voltage Vref, and the second power supply voltage V'2 is the reference voltage Vref.

For example, as shown in FIG. 3 , the reference voltage generation unit 104 provides the reference voltage Vref, that is, the node P'4 receives the reference voltage Vref from the reference voltage generation unit 104.

In the example of FIG. 3, except that the reference voltage generation unit 104 provides the reference voltage Vref to the node P4, other features are the same as the reference voltage generation unit 104 in the circuit structure of FIG. related description.

As shown in FIG. 2, for example, the first transistor M'1, the second transistor M'2, the third transistor M'3 and the fourth transistor M'4 are all the same N-type transistors. The first transistor M'1 and the fourth transistor M'4 are connected in the form of a diode. The first transistor M'1 and the fourth transistor M'4 divide the voltage, so Vref=Vgs'1+Vgs'4. Vgs'1 and Vgs'4 represent gate-source voltages of the first transistor M'1 and the fourth transistor M'4, respectively.

Since the specifications of the first transistor M'1 and the fourth transistor M'4 are the same, Vgs'1=Vgs'4=Vref/2.

The first transistor M'1 and the second transistor M'2 mirror the current through a current mirror, so Id'1=Id'2, Vgs'2=Vgs'1, Vgs'2=Vgs'3. Id'1 and Id'2 respectively represent the current flowing through the first transistor M'1 and the second transistor M'2, Vgs'2 represents the gate-source voltage of the second transistor M'2, Vgs'3 represents the second transistor Gate-to-source voltage of M'3. Therefore, it is ensured that the difference between Vin and Vout is the gate-source voltage of the third transistor M'3, so Vout=Vin-Vgs'3=Vin-Vref/2.

Therefore, Vout is only related to the reference voltage Vref and the input Vin, which eliminates the influence of errors such as temperature and process, and effectively improves the level conversion accuracy. Moreover, in the circuit structure 300 of FIG. 3 , the output voltage Vout is lower than the input voltage Vin, therefore, the circuit structure 300 functions as a step-down voltage.

The circuit structures of FIG. 2 and FIG. 3 are examples of a boost level conversion circuit and a buck level conversion circuit, respectively. It should be understood that the present disclosure does not limit the boost level conversion circuit to the circuit structure shown in FIG. 2 and the buck level conversion circuit to the circuit structure shown in FIG. 3 . For example, multiple transistors in the step-up level conversion circuit may be N-type transistors and P-type transistors, or all of the multiple transistors are N-type transistors, but not necessarily the first transistor M1 and the second transistor M1 shown in FIG. The second transistor M2, the third transistor M3 and the fourth transistor M4 are all P-type transistors. The first transistor M1 , the second transistor M2 , the third transistor M3 and the fourth transistor M4 use transistors with the same specifications to eliminate the influence of errors such as temperature and process, and effectively improve the precision of level shifting.

Another aspect of the present disclosure provides a voltage measuring device. Fig. 4 shows a schematic block diagram of a voltage measuring device 400 provided by at least one embodiment of the present disclosure.

As shown in FIG. 4 , the voltage measurement device 400 includes a measurement voltage generation unit 401 and a signal processing unit 402 .

The measurement voltage generating unit 401 includes the level conversion circuit 411 provided in any one of the foregoing embodiments, an input voltage receiving terminal In1 and a measurement voltage output terminal Out1. For example, the level conversion circuit 411 may be the level conversion circuit shown in FIG. 2 and/or the level conversion circuit shown in FIG. 3 .

The input voltage receiving terminal In1 is used to receive the input voltage Vin from the input voltage signal terminal In2 , and the measuring voltage output terminal Out1 is connected to the signal processing unit 402 .

The level conversion circuit 411 is connected to the input voltage receiving terminal In1 and configured to receive the input voltage Vin, and the level conversion circuit 411 is connected to the measurement voltage output terminal Out1 to provide the output voltage Vout to the measurement voltage output terminal Out1.

The signal processing unit 402 includes a first signal receiving end 412 and a second signal receiving end 422 . The first signal receiving terminal 412 is connected to the measuring voltage output terminal Out1 to receive the output voltage Vout. The second signal receiving end 422 is used for receiving the reference voltage Vref. The signal processing unit 402 is configured to output a measurement result of the output voltage Vout based on the reference voltage Vref.

For example, the reference voltage Vref is provided to the signal processing unit 402 by the bandgap voltage reference circuit BG_vref.

The voltage measurement device includes a level conversion circuit 411, so when the input voltage Vin is not within the voltage measurement range of the signal processing unit, the level conversion circuit 411 can be used to convert the input voltage Vin into an output voltage Vout within the voltage measurement range, thereby The signal processing unit is used to measure the output voltage Vout to obtain a measurement result, and then to obtain a measurement result of the input voltage Vin. Therefore, the voltage measurement device can increase the voltage measurement range of the signal processing unit.

For example, the voltage measurement range of the signal processing unit 402 is [a, b]. When the level conversion circuit 411 is the level conversion circuit shown in FIG. 2, the level conversion circuit 411 can boost the input voltage, thereby The voltage measurement device 400 can use the signal processing unit 402 to measure an input voltage smaller than the minimum value a in the voltage measurement range. Both a and b are greater than 0, for example.

For another example, when the level shifting circuit 411 is the level shifting circuit shown in FIG. The input voltage is measured at the maximum value b in the range.

As shown in FIG. 4 , the bandgap voltage reference circuit BG_vref not only provides the reference voltage Vref to the signal processing unit 402 , but also provides the reference voltage to the level conversion circuit 411 . For example, the circuit diagram is an example of FIG. 2 , and the reference voltage Vref is used as the first power supply voltage. For another example, the circuit diagram is an example of FIG. 3 , and the reference voltage Vref is used as the second power supply voltage.

Fig. 5 shows a schematic diagram of a circuit structure 500 of a voltage measuring device 400 provided by at least one embodiment of the present disclosure.

As shown in FIG. 5 , in a circuit structure 500 , the measurement voltage generation unit 401 includes a first level conversion circuit 501 and a second level conversion circuit 502 .

The measurement voltage generating unit 401 further includes a first switching unit s1 , a second switching unit s2 and a third switching unit s3 . The first switch unit s1 , the second switch unit s2 and the third switch unit s3 may be, for example, single pole single throw switches, triodes, MOSFETs and the like.

The first level conversion circuit 501 is connected to the measurement voltage output terminal Out1 through the first switch unit s1 . The second level conversion circuit 502 is connected to the measurement voltage output terminal Out1 through the second switch unit s2. The measurement voltage output terminal Out1 is also connected to the input voltage signal terminal In2 through the third switch unit s3.

The first level shifting circuit 501 and the second level shifting circuit 502 also receive the reference voltage Vref, the first power supply voltage V1 connected to the first level shifting circuit 501 is the reference voltage Vref, and the second level shifting circuit 502 is connected to the first power supply voltage Vref. The second power supply voltage V2 is the reference voltage Vref.

In this embodiment, the first level conversion circuit 501 may have the circuit structure shown in FIG. 2 . As shown in FIG. 2 , the first power supply voltage V1 is the reference voltage Vref, and the first level conversion circuit 501 is used to boost the input voltage Vin. The second level conversion circuit 502 may have the circuit structure shown in FIG. 3 . As shown in FIG. 3 , the second power supply voltage V'2 is the reference voltage Vref, and the second level conversion circuit 502 is used to step down the input voltage Vin.

In the circuit structure 500, the first switching unit s1, the second switching unit s2 and the third switching unit s3 are configured to respond to a control signal. The control signal is, for example, from a control device such as a processor.

In the case that the input voltage Vin is within the voltage measurement range [a, b] of the signal processing unit 402, the control signal is used to control the first switch unit s1 to disconnect the measured voltage output terminal Out1 from the first level conversion circuit 501 , The second switch unit s2 disconnects the connection between the second level conversion circuit 502 and the measurement voltage output terminal Out1, and the third switch unit s3 conducts the input voltage signal terminal In2 and the measurement voltage output terminal Out1.

For example, the first switch unit s1, the second switch unit s2 and the third switch unit s3 are SPST switches. If a<Vin<b, the first switch unit s1 is turned off, the second switch unit s2 is turned off, and the second switch unit s2 is turned off. The three-switch unit s3 is closed.

For another example, the first switch unit s1, the second switch unit s2 and the third switch unit s3 are MOSFET tubes. If a<Vin<b, the first switch unit s1 is turned off, the second switch unit s2 is turned off, and the third switch unit s3 is turned on.

In the case where the input voltage Vin is less than the minimum value a of the voltage measurement range of the signal processing unit 402, the control signal is used to control the first switch unit s1 to turn on the measurement voltage output terminal Out1 and the first level conversion circuit 501, the second switch The unit s2 disconnects the second level conversion circuit 502 from the measurement voltage output terminal Out1 and the third switch unit s3 disconnects the input voltage signal terminal In2 from the measurement voltage output terminal Out1.

For example, the first switch unit s1, the second switch unit s2 and the third switch unit s3 are SPST switches. If Vin<a, the first switch unit s1 is closed, the second switch unit s2 is opened, and the third switch unit s3 is disconnected.

For another example, the first switch unit s1, the second switch unit s2 and the third switch unit s3 are MOSFET tubes. If Vin<a, the first switch unit s1 is turned on, the second switch unit s2 is turned off, and the third switch unit s3 due.

When the input voltage Vin is greater than the maximum value of the voltage measurement range b of the signal processing unit 402, the control signal is used to control the first switch unit s1 to disconnect the measurement voltage output terminal Out1 from the first level conversion circuit 501, the second The second switch unit s2 connects the second level conversion circuit 502 to the measurement voltage output terminal Out1 and the third switch unit s3 disconnects the input voltage signal terminal In2 from the measurement voltage output terminal Out1.

For example, the first switch unit s1, the second switch unit s2 and the third switch unit s3 are single-pole single-throw switches. If Vin>b, the first switch unit s1 is turned off, the second switch unit s2 is closed, and the third switch unit s3 is disconnected.

For another example, the first switch unit s1, the second switch unit s2, and the third switch unit s3 are MOSFET tubes. If Vin>b, the first switch unit s1 is turned off, the second switch unit s2 is turned on, and the third switch unit s3 due.

The embodiment shown in FIG. 5 includes a first level shifting circuit 501 for boosting and a second level shifting circuit 502 for stepping down, so that by controlling the first switch unit s1, the second switch unit s2 and the second The three-switch unit s3 can boost or step down the input voltage Vin, or not process the input voltage Vin, so that the input voltage Vin can be flexibly converted to the voltage measurement range of the signal processing unit 402, and the voltage can be improved. The voltage measurement range of the measuring device. The voltage measurement device not only improves the measurable range of voltage, but also solves the influence of errors additionally introduced by temperature, process and power supply voltage, effectively guarantees the accuracy of measurement, and realizes a wider application range.

In some embodiments of the present disclosure, the signal processing unit 402 may be an analog-to-digital converter (ADC).

As shown in FIG. 5 , the voltage measuring device 500 may further include a reference voltage generation unit 403 , and the reference voltage generation unit 403 provides a reference voltage Vref to the second signal receiving terminal 422 . The reference voltage generation unit 403 is similar to the reference voltage generation unit 104 in FIG. 2 and FIG. 3 , please refer to the above description.

In the example of FIG. 5 , the reference voltage generation unit 403 not only provides the reference voltage Vref to the second signal receiving terminal 422 , but also provides the reference voltage Vref to the first level conversion circuit 501 and the second level conversion circuit 502 . That is, in the example of FIG. 5 , the same reference voltage generation unit 403 is used to provide the reference voltage Vref to the second signal receiving terminal 422 , the first level conversion circuit 501 and the second level conversion circuit 502 . Using the same reference voltage generating unit 403 to provide the reference voltage Vref to the second signal receiving terminal 422 , the first level conversion circuit 501 and the second level conversion circuit 502 can simplify the circuit and reduce the cost of the voltage measurement device.

In some other embodiments of the present disclosure, the reference voltage generation unit that provides the reference voltage to the second signal receiving terminal 422 may be the same as the reference voltage generation unit that provides the reference voltage to the first level conversion circuit 501 and the second level conversion circuit 502 Units are different.

For example, the output voltage Vout is compared with the reference voltage signal and Vref by the ADC to obtain a digitized coefficient k, k=Vout/Vref, so that the output voltage Vout=k can be calculated according to the k output from the output terminal Out2 of the ADC and the reference voltage Vref ×Vref. After the output voltage Vout is obtained, Vin=Vout+Vref/2 or Vin=Vout-Vref/2 can be further obtained according to Vout=Vin-Vref/2 or Vout=Vin+Vref/2, thereby realizing the control of the input voltage Vin Measurement.

Fig. 6 shows a flowchart of a voltage measurement method provided by at least one embodiment of the present disclosure.

The voltage measurement method is applied to the voltage measurement device provided in any one of the above embodiments.

As shown in FIG. 6, the voltage measurement method may include steps S10 to S40.

Step S10: In response to receiving the input voltage at the input voltage receiving end, compare the input voltage with the voltage measurement range of the signal processing unit, and obtain a comparison result.

Step S20: Generate a control signal based on the comparison result.

Step S30: Control the opening or closing of the first switch unit, the second switch unit and the third switch unit according to the control signal.

Step S40: Measure the output voltage by the signal processing unit, and output the measurement result.

The voltage measurement method can generate a control signal according to the comparison result of the input voltage and the voltage measurement range, so that the control signal can generate an output voltage within the voltage measurement range according to the input voltage, thereby realizing the measurement of the input voltage. This method not only improves the measurable range of the voltage, but also solves the influence of errors additionally introduced by temperature, process and power supply voltage, effectively guarantees the accuracy of measurement, and realizes a wider application range.

For step S10 , for example, in the example of FIG. 5 , the input voltage receiving terminal In1 receives the input voltage Vin.

For example, the input voltage Vin is sent to the comparator or the processor at the same time, so that the input voltage Vin and the voltage measurement range of the signal processing unit are compared by the comparator or the processor.

For step S20 , for example, the processor generates control signals for controlling the first switch unit s1 , the second switch unit s2 and the third switch unit s3 according to the comparison result.

For step S30, for example, the voltage measurement range is [a, b], if a<Vin<b, then the first switch unit s1 is turned off, the second switch unit s2 is turned off, and the third switch unit s3 is turned on. If Vin<a, the first switch unit s1 is turned on, the second switch unit s2 is turned off, and the third switch unit s3 is turned off. If Vin>b, the first switch unit s1 is turned off, the second switch unit s2 is turned on, and the third switch unit s3 is turned off.

For step S40, for example, the ADC measures the output voltage Vout, and the output terminal Out2 of the ADC outputs the measurement result.

The measurement result is, for example, a digitized coefficient k, k=Vout/Vref. According to the digitization coefficient k and the reference voltage Vref, the output voltage Vout=k×Vref can be calculated. After the output voltage Vout is obtained, Vin=Vout+Vref/2 or Vin=Vout-Vref/2 can be further obtained according to Vout=Vin-Vref/2 or Vout=Vin+Vref/2, thereby realizing the control of the input voltage Vin Measurement.

It should be noted that, in the embodiments of the present disclosure, each step of the voltage measurement method corresponds to the aforementioned voltage measurement device. For the voltage measurement method, reference may be made to relevant descriptions of the voltage measurement device, and details will not be repeated here.

The following points need to be explained:

(1) Embodiments of the present disclosure The drawings only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to common designs.

(2) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

The above description is only a specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims (15)

1. A level conversion circuit, comprising: a current mirror circuit unit, an output circuit unit, a voltage divider circuit unit, an output terminal and an input terminal, Wherein, the input terminal is used to receive an input voltage, and the output terminal is used to provide an output voltage, The current mirror circuit unit includes a first end connected to the first power supply voltage, a second end connected to the output end, and a third end connected to the voltage dividing circuit unit, and the current mirror circuit unit is configured to Two terminals and the third terminal provide mirror current, The output circuit unit is connected between the second power supply voltage and the output terminal, and receives the input voltage from the input terminal, the output circuit unit is configured to be based on the first voltage under the control of the input voltage Two supply voltage controls provide an output voltage at the output, The voltage divider circuit is connected between the second power supply voltage and the third terminal of the current mirror circuit unit. 2. The level conversion circuit according to claim 1, wherein the current mirror circuit unit comprises a first transistor and a second transistor, The gate of the first transistor is connected to the gate of the second transistor, the gate of the first transistor is connected to the first pole of the first transistor, and is commonly connected to the voltage dividing circuit unit, The second pole of the first transistor is connected to the first terminal, The second pole of the second transistor is connected to the first terminal, the first pole of the second transistor is connected to the second terminal, Wherein, the specifications of the first transistor and the second transistor are the same. 3. The level conversion circuit according to claim 1 or 2, wherein the output circuit unit comprises a third transistor, The gate of the third transistor is connected to the input terminal to receive the input voltage, the second pole of the third transistor is connected to the output terminal, and the first pole of the third transistor is connected to the second power supply Voltage. 4. The level conversion circuit according to claim 2, wherein the voltage dividing circuit unit comprises a fourth transistor, Wherein, the gate of the fourth transistor and the first pole of the fourth transistor are commonly connected to the second power supply voltage, and the second pole of the fourth transistor is connected to the third terminal of the current mirror circuit unit connect. 5. The level conversion circuit according to claim 4, wherein the specifications of the first transistor and the fourth transistor are the same. 6. The level conversion circuit according to claim 1, further comprising: a reference voltage generating unit configured to provide a reference voltage, Wherein, one of the first power supply voltage and the second power supply voltage is the reference voltage. 7. The level conversion circuit according to claim 6, wherein the reference voltage generation unit comprises a bandgap voltage reference circuit, wherein the bandgap voltage reference circuit provides the reference voltage. 8. The level conversion circuit according to claim 7, wherein the reference voltage generating unit further comprises a unity gain buffer, wherein a first end of the unit gain buffer is connected to the bandgap voltage reference circuit , the second end of the unit gain buffer is connected to the first end of the current mirror circuit unit. 9. The level conversion circuit according to claim 6, wherein the first power supply voltage is the reference voltage, Each of the current mirror circuit unit, the output circuit unit and the voltage divider circuit unit includes at least one transistor, and each of the at least one transistor is a P-type metal oxide semiconductor field effect transistor. 10. The level conversion circuit according to claim 6, wherein the second power supply voltage is the reference voltage, Each of the current mirror circuit unit, the output circuit unit and the voltage divider circuit unit includes at least one transistor, and each of the at least one transistor is an N-type metal oxide semiconductor field effect transistor. 11. A voltage measurement device, comprising: a measurement voltage generation unit and a signal processing unit, Wherein, the measurement voltage generation unit comprises the level conversion circuit according to any one of claims 1-10, an input voltage receiving terminal and a measurement voltage output terminal, The input voltage receiving end is used to receive the input voltage from the input voltage signal end, the measurement voltage output end is connected to the signal processing unit, The level conversion circuit is connected to the input voltage receiving end and is configured to receive the input voltage and provide an output voltage to the measurement voltage output end, The signal processing unit includes a first signal receiving end and a second signal receiving end, the first signal receiving end is connected to the measurement voltage output end to receive the output voltage, The second signal receiving end is used for receiving a reference voltage, and the signal processing unit is configured to output a measurement result of the output voltage based on the reference voltage. 12. The voltage measuring device according to claim 11 , wherein the measurement voltage generation unit comprises a first level conversion circuit and a second level conversion circuit, The measurement voltage generation unit further includes a first switch unit, a second switch unit, and a third switch unit, The first level conversion circuit is connected to the measurement voltage output terminal through the first switch unit, The second level conversion circuit is connected to the measurement voltage output terminal through the second switch unit, The measurement voltage output terminal is also connected to the input voltage signal terminal through the third switch unit, Wherein, the first level conversion circuit and the second level conversion circuit also receive the reference voltage, the first power supply voltage connected to the first level conversion circuit is the reference voltage, and the The second power supply voltage connected to the second level conversion circuit is the reference voltage. 13. The voltage measuring device according to claim 12, wherein the first switching unit, the second switching unit and the third switching unit are configured to respond to a control signal, Wherein, in the case that the input voltage is within the voltage measurement range of the signal processing unit, the control signal is used to control the first switch unit to disconnect the measured voltage output terminal from the first level The connection of the conversion circuit, the second switch unit disconnects the connection between the second level conversion circuit and the measurement voltage output terminal, and the third switch unit conducts the input voltage signal terminal and the measurement voltage output end; In the case that the input voltage is less than the minimum value of the voltage measurement range of the signal processing unit, the control signal is used to control the first switch unit to conduct the measurement voltage output terminal and the first level The conversion circuit, the second switch unit disconnects the connection between the second level conversion circuit and the measurement voltage output terminal, and the third switch unit disconnects the connection between the input voltage signal terminal and the measurement voltage output terminal ; In the case where the input voltage is greater than the maximum value of the voltage measurement range of the signal processing unit, the control signal is used to control the first switch unit to disconnect the measured voltage output terminal from the first level The connection of the conversion circuit, the second switch unit turns on the second level conversion circuit and the measurement voltage output terminal, and the third switch unit disconnects the input voltage signal terminal and the measurement voltage output terminal connect. 14. The voltage measurement device according to claim 11, wherein the signal processing unit comprises a digital-to-analog conversion unit. 15. A voltage measurement method, applied to the voltage measurement device according to claim 12, said voltage measurement method comprising: In response to the input voltage receiving end receiving the input voltage, comparing the input voltage with the voltage measurement range of the signal processing unit to obtain a comparison result; generating the control signal based on the comparison result; controlling opening or closing of the first switch unit, the second switch unit and the third switch unit according to the control signal; and The signal processing unit measures the output voltage provided by the measurement voltage output terminal and outputs a measurement result.

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