CN115378441A - A Design Method of Polar Code Distributed Source Codec System Based on FPGA - Google Patents

Abstract

The invention discloses a design method of a polarization code distributed information source coding and decoding system based on FPGA, which adopts a polarization code as a channel code, punches check bits of the polarization code, and provides a code rate self-adaption scheme of the distributed information source coding and decoding system under the condition of introducing a feedback mechanism of a cyclic redundancy check code, so that the system can transmit the least check code words on the premise of obtaining a correct decoding result, thereby improving the compression ratio of an information source. The experimental results show that: the invention can achieve 497Kbps throughput rate on FPGA.

Description

A Design Method of Polar Code Distributed Source Codec System Based on FPGA

technical field

The invention belongs to the technical field of information source encoding, and in particular relates to a design method of a polar code distributed information source encoding and decoding system based on FPGA.

Background technique

With the development of technologies such as wireless sensor networks, monitoring technologies, and satellite communications, resource-constrained terminals have been more and more widely used. Since this type of terminal faces resource constraints due to its low power consumption and miniaturization requirements in specific scenarios, the complexity of calculation must be considered in the process of data compression and encoding. The traditional source coding scheme uses joint coding to compress the transmitted data. Since this scheme requires a large amount of calculation at the coding end, it is no longer suitable for terminal equipment in these fields. The Distributed Source Coding (DSC) scheme encodes independently at the encoding end, and uses the correlation between sources to jointly decode at the decoding end, thereby transferring a large number of calculation processes from the resource-sensitive encoding end to the resource-sensitive end. The resource-insensitive decoding end, so distributed source coding is more suitable for occasions where the resources of the encoding end are limited.

At present, a lot of work has been done in the academic circle on how to implement distributed source coding on FPGA. Tharini C et al. proposed to use a clustering algorithm based on spatial correlation to improve the performance of distributed source coding, and implemented it on FPGA based on low energy consumption technology. Xu Dijia from Beijing University of Posts and Telecommunications used LDPC codes as channel codes to implement a syndrome-based joint distributed source channel codec on FPGA. Lu Shun of Sichuan University studied the distributed source codec system of LDPC code check digit, designed a hardware implementation scheme based on FPGA, and achieved good results. As the first channel coding method that has been strictly proven to reach the Shannon limit, the polar code has better error detection performance, lower coding and decoding complexity, and better code rate compatibility, so the FPGA-based The polar code distributed source codec system has high research value, and there is no precedent for implementing a polar code-based distributed source codec system on FPGA.

Contents of the invention

The purpose of the present invention is to reduce the complexity of the coding end and at the same time improve the compression rate of the information source as much as possible. The present invention uses the combination of CRC check code and system polar code to design a code rate self-adaptive scheme. Compared with the traditional method of transmitting with fixed code rate, this scheme can greatly improve the source compression rate .

The basic idea of the present invention is to use the correlation between information sources, use a side information sequence generated by the side information processing module according to the binary input sequence and the crossover probability as the information bit sequence, and use the check bit encoded by the system polar code The sequence is cached in the puncturing module, and the check bit sequence is sent to the decoding module bit by bit according to the feedback signal of the decoding module, and the unsent bits are equivalent to being punctured, thereby achieving the purpose of improving the source compression rate.

Among them, for data encoding, CRC check encoding is first performed on 128-bit data to obtain a 16-bit CRC check sequence, and the 144-bit data is used as input for system polar code encoding to obtain a 112-bit polar code check bit sequence , and then the 128-bit sequence obtained by splicing this sequence with the 16-bit CRC check sequence is used as the output of the encoding module. The data such as check digit index and G matrix required in the encoding module are first generated by matlab and then imported into vivado to generate the corresponding ROM to realize the call of the data.

In the design of the code rate adaptive scheme, the key step to improve the source compression rate is the process of the puncturing module transmitting the check sequence one by one, so how to transmit the least code words under the premise of ensuring the correct decoding result Key issues for adaptation programmes. When the puncturing module transmits data to the decoding module for the first time, it first transmits a certain number of bits of data at one time according to the size of the information entropy corresponding to the crossover probability. Because when the transmitted data is too small and the code rate is lower than the information entropy, theoretically the decoding module cannot decode correctly. According to the data and side information sequence transmitted by the puncturing module for the first time, the decoding module starts to try to use the polar code SC decoding algorithm to decode, obtain a decoding sequence, and then perform CRC verification on the decoding sequence, if the verification fails, then If the decoding sequence is wrong, a signal is fed back to the puncturing module to request more parity bits. After receiving the feedback signal, the puncturing module transmits one bit of check bit information to the decoding module in order to make it decode and check again, and repeat this process until the decoding and check succeed to obtain the correct decoding sequence and output it.

The side information processing module simulates a virtual channel, which generates a side information to the decoding module with a certain cross probability of the source sequence. The greater the crossover probability, the greater the difference between the side information and the source sequence, and the more check bits are required for decoding. The product of the crossover probability and the length of the source sequence is the actual number of bits that differ between the side information sequence and the source sequence, and the bit position of the specific difference is achieved by inverting the corresponding bit through a random sequence index.

The decoding module includes two processes of polar code decoding and CRC checking. Among them, the polar code decoding algorithm adopts the system polar code SC (Successive Cancellation) continuous elimination decoding algorithm, which is the most classic polar code decoding algorithm, and it is considered to be implemented on a resource-constrained platform such as FPGA. Compared with the SCL decoding algorithm and the CA-SCL decoding algorithm, the SC decoding algorithm has the advantages of low computational complexity, less resource occupation, and low decoding delay.

Specifically, in the polar code decoding process, since the f operation in the SC decoding algorithm is too complicated to be implemented on hardware, the minimum sum decoding algorithm is used for optimal design. Since the logarithmic likelihood ratio is always involved in the calculation in the form of floating-point numbers during the operation process, it is more complicated to directly operate on floating-point numbers in FPGA, because FPGA directly operates on reg type data with a certain number of digits. Therefore, the log-likelihood ratio in the form of a floating-point number should be fixed-point quantized into a fixed-point number with a certain number of bits. If the number of quantization bits is larger, the decoding process needs to occupy more resources; if the number of quantization bits is too small, the decoding performance will be reduced. Finally, this paper adopts a 4-bit specific point quantization scheme, that is, all log likelihood ratios are represented by 4 bits, and because the log likelihood ratios are positive and negative, and the minimum sum decoding algorithm requires the log likelihood ratios to be positive and negative The symbol value is directly involved in the operation, so the form of complement code is used, that is, 1000~0111 corresponds to -8~7.

Description of drawings

Fig. 1 is the design flowchart of the present invention.

Fig. 2 is an overall RTL design diagram of the present invention.

Fig. 3 is a simulation waveform diagram in the present invention.

Fig. 4 is a diagram of resource occupation results in the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, and are not intended to limit the present invention. Those skilled in the art may make some non-essential improvements and adjustments to implement the present invention based on the content of the above invention. Still belong to the protection scope of the present invention.

In Fig. 1, a kind of design method of the polar code distributed source codec system based on FPGA, comprises the following steps:

(1) Data encoding, inputting the source sequence of 128 bits into the encoding module, first generating the CRC check sequence, and then encoding the system polar code, outputting the encoding sequence of 128 bits to the puncturing module;

(2) Side information generation, input the 128-bit source sequence into the side information processing module, add virtual noise to the source sequence according to the pre-set crossover probability, generate a side information sequence of equal length, and output it to the decoder module;

(3) For data transmission, the puncturing module first caches the input code sequence, and when transmitting data for the first time, transmits a certain number of codewords in order according to the information entropy corresponding to the crossover probability. Subsequent codewords are sent bit by bit in order according to whether the feedback signal output by the decoding module is received;

(4) Data decoding and verification, after receiving enough verification code words, decode to get the correct decoding result and output it.

Among them, step 1 is divided into the following steps:

① Generate a 16-bit CRC check sequence and splice it with a 128-bit source sequence to form a 144-bit sequence;

② Encode the 144-bit long sequence with a systematic polar code, and obtain a 112-bit coded sequence according to the parity index;

③The 112-bit coding sequence and the 16-bit CRC check sequence are spliced and output.

Specifically, in the step 2, the length of the input sequence is 128 bits, and the set crossover probability is 0.03, so the side information is different from the source sequence by round(128×0.03)=4 bits. The first four bits of a random sequence are used as an index to invert the corresponding bits of the source sequence and output as a side information sequence.

In the step 3, the information entropy of the crossover probability is calculated according to the following formula:

H＝ _-plog2 (p)-(1-p) _log2 (1-p)

In the actual design, set the crossover probability p=0.03, then the information entropy H=0.1944. The product of the information entropy and the length of the check sequence is 0.1944×128=24.8832, so the puncturing module transmits the check sequence of the first 25 bits to the decoding module for the first time after receiving the coded sequence. According to the code rate adaptive scheme, in the subsequent transmission process, each time a feedback signal from the decoding module is received, the next parity bit is sent to the decoding module in sequence.

Specifically, in the step 4, in order to facilitate the deployment of the polar code SC decoding algorithm in the FPGA, the present invention adopts the minimum sum decoding algorithm, which can simplify the complex f operation and g operation as follows:

f(L ₁ ,L ₂ )=sgn(L ₁ )sgn(L ₂ )min(|L ₁ |,|L ₂ |)

g(L ₁ ,L ₂ ,u)=(-1) ^u L ₁ +L ₂

In the quantization scheme of the logarithmic likelihood ratio, a 4-bit fixed-point quantization scheme is adopted to quantize the loglikelihood ratio originally in the form of a floating-point number into a 4-bit fixed-point number. The quantization formula is as follows:

Specifically, in the CRC check process in step 4, the 144-bit polar code decoding sequence is ANDed with each row of a 16×144 CRC check matrix, and then bitwise XORed to obtain a 16-bit array, if the array is 0, it means that the decoding is successful through the CRC check, and finally the CRC check sequence in the 144-bit polar code decoding sequence is removed, and the remaining 128-bit decoding result is output , and pull the output valid signal high.

Referring to Figure 2, the FPGA-based polar code distributed source codec system consists of four modules. encode is the encoding module, which encodes complex data; bsc is the side information generation module, which completes the processing of side information; del is the puncturing module, which is the core module of the code rate adaptive scheme, responsible for transmitting check digit data; decode is the decoding module , responsible for polar code decoding and CRC check. The system input clock clk frequency is set to 200MHz. The source sequence source is input into the system in a serial manner. The reset signal rst is controlled by the IO pin of the development board, and the effective mode is active low.

Referring to Figure 3, after the design of the FPGA-based polar code distributed source encoding and decoding system is completed, in order to verify the correctness of the system function, use the simulation tool that comes with Vivado to perform simulation verification by writing testbench. The simulation parameters are configured as follows: code length N=256, number of information bits K=128, code rate R=0.5, crossover probability p=0.03. It can be seen from the simulation waveform diagram that the puncturing module transmits a 25-bit check sequence to the decoding module for the first time. After the first decoding fails, the puncturing module continues to transmit bit by bit. After the sequence, the decoding module obtains the correct decoding result, outputs the 128-bit decoding sequence decode_data, and pulls the output valid signal out_en high.

Referring to Figure 4, after the integration of the FPGA-based polar code distributed source codec system is completed, the resource occupation is in line with the resource limit of the development board.

The design method of a kind of FPGA-based polar code distributed source encoding and decoding system proposed by the present invention is designed and implemented on the VC707 evaluation board of Xilinx Company with the Virtex-7 series chip xc7vx485tffg1761-2 as the main control chip, And use 128-bit random binary sequence to carry out the performance test, the experimental data shows that the throughput of the system can reach 497Kbps.

Claims (4)

1. a design method based on FPGA-based polar code distributed source codec system, is characterized in that mainly comprising the following steps: (1) Data encoding, inputting the 128bit binary input sequence to the encoding module for CRC check sequence generation and polar code encoding, and outputting the 128bit encoded code word check bit sequence; (2) Side information generation, according to the size of the crossover probability, a side information sequence with the same length and correlation as the input sequence is generated, and output to the decoding module; (3) For data transmission, the puncturing module transmits codewords bit by bit to the decoding module in order according to the designed code rate adaptive scheme; (4) Data feedback and decoding, after combining the encoded codeword check bit sequence and the side information information bit sequence, polar code decoding and CRC check are performed, and the feedback signal or decoded code word is output according to the check result. 2. the design method of the polar code distributed information source codec system based on FPGA as claimed in claim 1, it is characterized in that in the step (1) data coding comprises generating CRC check sequence and polar code coding two The process, wherein the CRC check polynomial used to generate the CRC check sequence is g(x)=x ¹⁶ +x ¹⁵ +x ² +1, and the polar code encoding adopts the method of systematic polar code encoding, including the following steps: (1) data such as G matrix and information bit index in the ROM are read out and stored in the register; (2) Splicing the binary input sequence and the CRC check sequence as the information bit sequence, multiplying this sequence with the G matrix, and obtaining the non-systematic code word of the polar code; (3) According to the information bit index, keep the polar code information bit unchanged, after checking the position is zero, then multiply it with the G matrix to obtain the polar code system code word; (4) According to the information bit index, the parity bits in the codeword of the polar code system are extracted to form the codeword parity sequence. 3. the design method of the polar code distributed information source encoding and decoding system based on FPGA as claimed in claim 1, it is characterized in that in step (3), after the puncturing module receives the coding code word parity sequence, first one by one Transmit a sequence of N/2×[-plog ₂ p-(1-p)log ₂ (1-p)] bits in total, where N represents the length of the code word, p represents the crossover probability, and then transmit the unidentified codes one by one according to the subsequent feedback signal Transmitted parity bits. 4. the design method of the polar code distributed information source codec system based on FPGA as claimed in claim 1, it is characterized in that data feedback and decoding comprise the following steps in the step (4): (1) Recover the side information information bit sequence and the punctured check bit sequence according to the information bit and check bit index, and reorganize into a 256-bit sequence; (2) Use the systematic polar code SC (Successive Cancellation) continuous elimination decoding method to decode the 256-bit sequence. In the hardware implementation process, the minimum sum decoding algorithm is used for optimization, and the log likelihood Ratio for 4-bit specific point quantization processing; (3) Perform CRC check on the decoding result, if the CRC check is not passed, output a feedback signal to the puncturing module to enable the system to perform re-decoding; if the CRC check is passed, then output the decoded codeword.

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