CN115412033A - Comparator and decision feedback equalization circuit - Google Patents

Abstract

The present application provides a comparator and a decision feedback equalization circuit. The comparator includes a first input circuit, a second input circuit, a first positive feedback circuit, a second positive feedback circuit and an output circuit. The first input circuit is used for Generate the first differential signal according to the first input signal and the first reference signal, the second input circuit is used to generate the second differential signal according to the second input signal and the second reference signal in the sampling stage, and the first positive feedback circuit is used to accelerate the first differential signal The difference between a differential signal, the second positive feedback circuit is used to accelerate the difference between the second differential signal, and the output circuit is used to compare the voltage signal of the output terminal of the first input circuit and the voltage of the output terminal of the second input circuit in the regeneration phase The signal is amplified and latched to output the comparison result. This solution can increase the response rate of the comparator and reduce the power consumption of the comparator.

Description

Comparator and decision feedback equalization circuit

technical field

The present application relates to integrated circuits, in particular to a comparator and a decision feedback equalization circuit.

Background technique

Today, people's demand for mobile devices such as mobile phones, tablets and various wearable accessories has greatly increased, which greatly enriches our daily life and work.

However, due to the limited battery life, higher requirements are placed on the power consumption of various components in mobile devices. Dynamic Random Access Memory (DRAM) is an indispensable component in mobile devices. Therefore, DRAM is also in urgent need. Achieve lower operating voltage and lower energy consumption. Among them, the comparator is an important device for reading and writing DRAM data, and the existing comparator cannot meet the current use requirements.

Contents of the invention

The present application provides a comparator and a decision feedback equalization circuit, aiming at improving the response rate of the comparator and reducing the power consumption of the comparator.

In a first aspect, the present application provides a comparator, which is provided with four input terminals and two output terminals, including:

The first input circuit is provided with two input terminals and two output terminals, and the two input terminals are used as the input terminals of the comparator for generating the first differential signal according to the first input signal and the first reference signal in the sampling stage ;

a first positive feedback circuit connected to the two output terminals of the first input circuit for speeding up the difference between the first differential signals;

The second input circuit is provided with two input terminals and two output terminals, and its two input terminals are used as the input terminals of the comparator, and its two output terminals are connected with the two output terminals of the first input circuit for The sampling stage generates a second differential signal according to the second input signal and the second reference signal;

a second positive feedback circuit connected to the two output terminals of the second input circuit for speeding up the difference between the second differential signals;

An output circuit, which is provided with two input terminals and two output terminals, the two output terminals of which are the output terminals of the comparator, and the two input terminals of which are connected with the two output terminals of the first input circuit, for use in the regeneration stage The voltage signal at the output end of the first input circuit and the voltage signal at the output end of the second input circuit are amplified and latched to output a comparison result.

In a second aspect, the present application provides a decision feedback equalization circuit, which is characterized in that it includes four comparators involved in the first aspect, which are sequentially marked as the first comparator, the second comparator, the third comparator and the fourth comparator. Comparators;

The first comparator, its first input end is used to receive the first input signal, its second input end is used to receive the first reference signal, its third input end is connected to the first output end of the fourth comparator, and its second input end is used to receive the first reference signal. The four input terminals are connected to the second output terminal of the fourth comparator;

The second comparator, its first input terminal is used to receive the first input signal, its second input terminal is used to receive the first reference signal, its third input terminal is connected to the first output terminal of the first comparator, and its second input terminal is used to receive the first reference signal. The four input terminals are connected to the second output terminals of the first comparator;

The third comparator, its first input terminal is used to receive the first input signal, its second input terminal is used to receive the first reference signal, its third input terminal is connected to the first output terminal of the second comparator, and its second input terminal is used to receive the first reference signal. The four input terminals are connected to the second output terminals of the second comparator;

In the fourth comparator, its first input terminal is used to receive the first input signal, its second input terminal is used to receive the first reference signal, its third input terminal is connected to the first output terminal of the third comparator, and its second input terminal is used to receive the first reference signal. The four input terminals are connected with the second output terminal of the third comparator.

The present application provides a comparator and a decision feedback equalization circuit. The comparator includes a first input circuit, a second input circuit, a first positive feedback circuit, a second positive feedback circuit and an output circuit. The first input circuit is used for Generate the first differential signal according to the first input signal and the first reference signal, the second input circuit is used to generate the second differential signal according to the second input signal and the second reference signal in the sampling stage, and the first positive feedback circuit is used to accelerate the first differential signal The difference between a differential signal, the second positive feedback circuit is used to accelerate the difference between the second differential signal, and the output circuit is used to compare the voltage signal of the output terminal of the first input circuit and the voltage of the output terminal of the second input circuit in the regeneration phase The signal is amplified and latched to output the comparison result. When any one or both of the first reference signal and the second reference signal are inappropriate, it takes a long time to generate a differential signal with a large difference in the corresponding input circuit, and the positive feedback circuit in the corresponding input circuit is input There is a slight difference between the two output terminals of the circuit, and then the difference is accelerated through the positive feedback mechanism, shortening the time of the sampling stage, thereby improving the response rate of the comparator and reducing the power consumption of the comparator.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description serve to explain the principles of the application.

Fig. 1 is the concrete circuit diagram of a kind of comparator provided by the present application;

Fig. 2 is the working timing diagram of the comparator provided by the present application;

Fig. 3 is a structural block diagram of a comparator provided by the present application;

FIG. 4 is a specific circuit diagram based on one of the comparators provided in FIG. 3;

Fig. 5 is a specific circuit diagram based on another comparator provided in Fig. 3;

FIG. 6 is a structural block diagram of a comparator provided by the present application;

FIG. 7 is a specific circuit diagram based on one of the comparators provided in FIG. 6;

FIG. 8 is a specific circuit diagram of the controllable positive feedback module in the comparator provided in FIG. 7;

FIG. 9 is a specific circuit diagram based on another comparator provided in FIG. 6;

FIG. 10 is a specific circuit diagram of the controllable positive feedback module in the comparator provided in FIG. 9;

FIG. 11 is a structural block diagram of a decision feedback equalization circuit provided by the present application;

FIG. 12 is a schematic diagram of the effect of the decision feedback equalization circuit provided by the present application;

FIG. 13 is a working timing diagram of the decision feedback equalization circuit provided by the present application.

By means of the above drawings, specific embodiments of the present application have been shown, which will be described in more detail hereinafter. These drawings and text descriptions are not intended to limit the scope of the concept of the application in any way, but to illustrate the concept of the application for those skilled in the art by referring to specific embodiments.

Detailed ways

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numerals in different drawings refer to the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with aspects of the present application as recited in the appended claims.

As shown in FIG. 1 , the comparator includes an input circuit 101 , an output circuit 102 and a reset circuit 106 . Wherein, the output end of the input circuit 101 is connected to the input end of the output circuit 102 . The reset circuit 106 is also connected to the output circuit 102 .

The input circuit 101 includes a transistor N1, a transistor N2 and a transistor N3, the transistor N1 and the transistor N2 form a differential transistor pair, the gate of the transistor N1 and the gate of the transistor N2 form the first input terminal IP and the second input terminal IN of the input circuit, The drain of transistor N1 and the drain of transistor N2 form two output terminals of the input circuit.

The output circuit 102 includes a transistor P1, a transistor P2, a transistor N4, and a transistor N5. The four transistors form a cross-coupled transistor pair. The drains of the transistor P1 and the transistor N4 form the first output terminal ON of the output circuit 102. The transistor P2 and the transistor N5 The drain constitutes a second output terminal OP of the output circuit 102 . The reset circuit 106 includes a transistor P3 and a transistor P4.

The working process of the comparator is divided into four stages, which are reset stage, sampling stage, regeneration stage and decision stage. The working process of the comparator shown in Figure 1 is described below in conjunction with Figure 2:

In the reset phase, that is, from time t0 to time t1, the clock signal is at low level, the transistor N3 is disconnected, the input circuit and the output circuit stop working, the transistor P3 and transistor P4 are closed, the reset circuit works, and the drain of the transistor N4 and the The drain voltage of transistor N5 is pulled to high level.

In the sampling phase, that is, from time t1 to time t2, the clock signal is at a high level, the transistor P3 and the transistor P4 are disconnected, and the reset circuit stops working. The transistor N3 is closed, the input circuit collects the input signal through the first input terminal IP, the input circuit collects the reference signal through the second input terminal IN, the input signal pulls down the drain voltage of the transistor N1, and the reference signal pulls down the drain of the transistor N2 Voltage. The drain of transistor N1 pulls down the drain voltage of transistor N4, and the drain of transistor N2 pulls down the drain voltage of transistor N5. Since the input signal is higher than the reference signal, the input signal pulls the drain voltage of the transistor N1 faster, thereby making the drain voltage of the transistor N4 lower than the drain voltage of the transistor N5.

In the regeneration stage, that is, from time t2 to time t3, the drain voltage of transistor N4 and the drain voltage of transistor N5 reach the flipping voltage, transistor P2 and transistor N4 are turned on, transistor P1 and transistor N5 are gradually turned off, and transistor P2 is pulled up The drain voltage of transistor N5, transistor N4 pulls down the drain voltage of transistor N4.

In the decision-making phase, that is, from time t3 to time t4, transistor P2 and transistor N4 are turned on, transistor P1 and transistor N5 are turned off, and the drain voltage of transistor N5 is continuously pulled up, and the drain voltage of transistor N4 is continuously pulled down, After the drain of transistor N5 is pulled low and the drain voltage of transistor N4 is pulled high, the drain voltages of transistor N4 and transistor N5 are maintained.

When the next working cycle comes, the clock signal becomes low level, and the drain voltages of transistor N4 and transistor N5 are reset to high level by transistor P1 and transistor P2.

However, when the reference signal is not selected properly, the input signal and the reference signal will take a long time to generate a differential signal at the output of the input circuit, which will reduce the response rate of the comparator and increase the power consumption of the comparator. For example, in the comparator shown in Figure 2, when the reference signal is relatively small, the transistor N1 and the transistor N2 need to be turned on for a long time, so that the charging current of the node VP and the node VN drops, and the transistor N1 and the transistor N2 pull the transistor N5 and the transistor N4 The rate decreases, resulting in a decrease in the response rate of the comparator, which also increases the power consumption of the comparator.

As shown in FIG. 3 , an embodiment of the present application provides a comparator, and the comparator is provided with four input terminals and two output terminals. The four input terminals of the comparator are sequentially labeled as a first input terminal, a second input terminal, a third input terminal and a fourth input terminal. The two outputs of the comparator are labeled successively as a first output and a second output. Wherein, the comparator includes a first input circuit 101 , a second input circuit 102 , a first positive feedback circuit 103 , a second positive feedback circuit 104 and an output circuit 105 .

The first input circuit 101 is provided with two input terminals and two output terminals, and the second input circuit 102 is also provided with two input terminals and two output terminals. Wherein, the two output ends of the first input circuit 101 are connected with the two output ends of the second input circuit 102 . The first input terminal of the first input circuit 101 is used as the first input terminal of the comparator for receiving the first input signal. The second input terminal of the first input circuit 101 is used as the second input terminal of the comparator for receiving the first reference signal. The first input terminal of the second input circuit 102 is used as the third input terminal of the comparator for receiving the second reference signal. The second input terminal of the second input circuit 102 is used as the fourth input terminal of the comparator for receiving the second input signal.

The output circuit 105 is also provided with two input ends and two output ends, and the two input ends of the output circuit 105 are connected with the two output ends of the first input circuit 101, and the two input ends of the output circuit 105 are also connected with the second input end. The two output terminals of circuit 102 are connected. The two output terminals of the output circuit 105 serve as the two output terminals of the comparator.

After the two input terminals of the first input circuit 101 receive the first input signal and the first reference signal, they generate a first differential signal according to the first input signal and the first reference signal in the sampling stage. After the two input terminals of the second input circuit 102 receive the second input signal and the second reference signal, they generate a second differential signal according to the second input signal and the second reference signal in the sampling stage.

Wherein, the first differential signal and the second differential signal are a pair of voltage signals, the first positive feedback circuit 103 is used to speed up the difference between the first differential signal, and the second positive feedback circuit 104 is used to speed up the difference between the second differential signal difference between. The first input circuit 101 is also used for outputting the first differential signal after the accelerated processing, and the second input circuit 102 is also used for outputting the second differential signal after the accelerated processing. The output circuit 105 is used for amplifying and latching the voltage signal at the output terminal of the first input circuit 101 and the voltage signal at the output terminal of the second input circuit 102 during the regeneration stage, so as to output the comparison result through the two output terminals.

When the first reference signal is not selected properly, the response time of the first input circuit 101 becomes longer, that is, the first input circuit 101 takes a longer time to present the first differential signal with a relatively large difference at the output terminal. The first positive feedback circuit 103 accelerates the difference between the first differential signals through a positive feedback mechanism, thereby reducing the time during which the first input circuit 101 presents the first differential signal with a relatively large difference at the output terminal, that is, shortening the comparator at The time of the sampling phase, thereby increasing the response rate of the comparator and reducing the power consumption of the comparator.

Similarly, when the selection of the second reference signal is inappropriate, the response time of the second input circuit 102 becomes longer, that is, the second input circuit 102 needs a longer time to present the second differential signal with a relatively large difference at the output terminal. The second positive feedback circuit 104 accelerates the difference between the second differential signals through a positive feedback mechanism, thereby reducing the time during which the second input circuit 102 presents the second differential signal with a relatively large difference at the output terminal, that is, shortening the time when the comparator is at The time of the sampling phase, thereby increasing the response rate of the comparator and reducing the power consumption of the comparator.

In an embodiment, the first positive feedback circuit 103 includes a first feedback unit 1031 and a second feedback unit 1032 , and both the first feedback unit 1031 and the second feedback unit 1032 are provided with a control terminal and a first terminal.

Wherein, the control terminal of the first feedback unit 1031 is connected to the first output terminal of the first input circuit 101 , and the first terminal of the first feedback unit 1031 is connected to the second output terminal of the first input circuit 101 . The control terminal of the second feedback unit 1032 is connected to the second output terminal of the first input circuit 101 , and the first terminal of the second feedback unit 1032 is connected to the first output terminal of the first input circuit 101 .

The first feedback unit 1031 is used to pull the voltage of the second output terminal of the first input circuit 101 according to the voltage of the first output terminal of the first input circuit 101 in the sampling phase, and the second feedback unit 1032 is used to pull the voltage of the second output terminal of the first input circuit 101 according to the voltage of the first input circuit in the sampling phase. The voltage at the second output terminal of 101 pulls the voltage at the first output terminal of the first input circuit 101 .

The direction in which the first feedback unit 1031 pulls the voltage of the second output terminal of the first input circuit 101 is the same as the direction in which the second feedback unit 1032 pulls the voltage of the first output terminal of the first input circuit 101 . When the first feedback unit 1031 pulls up the voltage of the second output terminal of the first input circuit 101 , the second feedback unit 1032 also pulls up the voltage of the first output terminal of the first input circuit 101 . When the first feedback unit 1031 pulls down the voltage of the second output terminal of the first input circuit 101 , the second feedback unit 1032 also pulls down the voltage of the first output terminal of the first input circuit 101 .

In an embodiment, the second positive feedback circuit 104 includes a third feedback unit 1033 and a fourth feedback unit 1034, and the third feedback unit 1033 and the fourth feedback unit 1034 are both provided with a control terminal and a first terminal.

Wherein, the control terminal of the third feedback unit 1033 is connected to the first output terminal of the second input circuit 102 , and the first terminal of the third feedback unit 1033 is connected to the second output terminal of the second input circuit 102 . The control terminal of the fourth feedback unit 1034 is connected to the second output terminal of the second input circuit 102 , and the first terminal of the fourth feedback unit 1034 is connected to the first output terminal of the second input circuit 102 .

The third feedback unit 1033 is used to pull the voltage of the second output terminal of the second input circuit 102 according to the voltage of the first output terminal of the second input circuit 102 during the sampling phase, and the fourth feedback unit 1034 is used to pull the voltage of the second output terminal of the second input circuit 102 according to the voltage of the second input circuit during the sampling phase. The voltage at the second output terminal of 102 pulls the voltage at the first output terminal of the second input circuit 102 .

The direction in which the third feedback unit 1033 pulls the voltage of the second output terminal of the second input circuit 102 is the same as the direction in which the fourth feedback unit 1034 pulls the voltage of the first output terminal of the second input circuit 102 . When the third feedback unit 1033 pulls up the voltage of the second output terminal of the second input circuit 102 , the fourth feedback unit 1034 also pulls up the voltage of the first output terminal of the second input circuit 102 . When the third feedback unit 1033 pulls down the voltage of the second output terminal of the second input circuit 102 , the fourth feedback unit 1034 also pulls down the voltage of the first output terminal of the second input circuit 102 .

The following takes the voltage of the two output terminals of the first input circuit 101 pulled down as an example to illustrate: when the voltage of the first output terminal of the first input circuit 101 is higher than the voltage of the second output terminal of the first input circuit 101, the first feedback The unit 1031 has a strong ability to pull down the voltage of the second output end of the first input circuit 101, and the second feedback unit 1032 has a weak ability to pull down the voltage of the first output end of the first input circuit 101, that is, the voltage of the first output end. The falling rate is lower than that of the second output terminal, so that the voltage difference between the first output terminal voltage and the second output terminal becomes larger and positive feedback is realized.

When the voltage of the first output terminal of the first input circuit 101 is lower than the voltage of the second output terminal of the first input circuit 101, the first feedback unit 1031 has a weak ability to pull down the voltage of the second output terminal of the first input circuit 101, The second feedback unit 1032 has a strong ability to pull down the voltage of the first output terminal of the first input circuit 101, that is, the voltage drop rate of the first output terminal is higher than the drop rate of the second output terminal, thereby making the voltage of the first output terminal and the second output terminal The voltage difference between the two output terminals is getting larger and larger, realizing positive feedback.

The following takes the voltage of the two output terminals of the first input circuit 101 as an example to illustrate: when the voltage of the first output terminal of the first input circuit 101 is higher than the voltage of the second output terminal of the first input circuit 101, the first feedback unit 1031 has a weak ability to pull up the voltage of the second output end of the first input circuit 101, and the second feedback unit 1032 has a strong ability to pull up the voltage of the first output end of the first input circuit 101, that is, the voltage rise rate of the first output end is high. Based on the rising rate of the second output terminal, the voltage difference between the voltage of the first output terminal and the second output terminal becomes larger and larger, realizing positive feedback.

When the voltage of the first output terminal of the first input circuit 101 is lower than the voltage of the second output terminal of the first input circuit 101, the first feedback unit 1031 has a stronger ability to pull up the voltage of the second output terminal of the first input circuit 101, the second The second feedback unit 1032 has a weak ability to pull up the voltage of the first output terminal of the first input circuit 101, that is, the voltage rise rate of the first output terminal is lower than the rise rate of the second output terminal, so that the voltage of the first output terminal and the second output terminal The voltage difference at the end is getting bigger and bigger, and positive feedback is realized.

In the above technical solution, when any one or both of the first reference signal and the second reference signal are inappropriate, it takes a relatively long time to generate a differential signal with a large difference in the corresponding input circuit, and the corresponding input circuit The positive feedback circuit in the circuit accelerates the difference through the positive feedback mechanism after there is a slight difference between the two output terminals of the input circuit, shortens the time of the sampling stage, thereby increasing the response rate of the comparator and reducing the power consumption of the comparator.

Figure 4 is a schematic diagram of the circuit structure of a comparator provided by another embodiment of the present application, as shown in Figure 4, the comparator provided by the present application includes a first input circuit 101, a second input circuit 102, a first positive feedback circuit 103 , a second positive feedback circuit 104 and an output circuit 105 .

Wherein, the first input circuit 101 includes a first input transistor N1, a second input transistor N2 and a third input transistor N3. The control terminal of the first input transistor N1 serves as the first input terminal of the first input circuit 101 , and the first terminal of the first input transistor N1 serves as the first output terminal of the first input circuit 101 . The control terminal of the second input transistor N2 serves as the second input terminal of the first input circuit 101 , and the first terminal of the second input transistor N2 serves as the second output terminal of the first input circuit 101 . The first terminal of the third input transistor N3 is connected to the second terminal of the first input transistor N1 and the second terminal of the second input transistor N2, and the second terminal of the third input transistor N3 is connected to the ground terminal.

The control terminal of the third input transistor N3 receives a clock signal for controlling the working state of the first input circuit 101 . When the third input transistor N3 is closed, the first input circuit 101 works. When the third input transistor N3 is turned off, the first input circuit 101 stops working.

The control terminal of the first input transistor N1 receives the first input signal, the control terminal of the second input transistor N2 receives the first reference signal, and the first input signal and the first reference signal are amplified by the first input transistor N1 and the second input transistor N2 Afterwards, a first differential signal is generated at the first terminal of the first input transistor N1 and the first terminal of the second input transistor N2.

Wherein, the second input circuit 102 includes a fourth input transistor N4, a fifth input transistor N5 and a sixth input transistor N6. The control terminal of the fourth input transistor N4 serves as the first input terminal of the second input circuit 102 , and the first terminal of the fourth input transistor N4 serves as the first output terminal of the second input circuit 102 . The control terminal of the fifth input transistor N5 serves as the second input terminal of the second input circuit 102 , and the first terminal of the fifth input transistor N5 serves as the second output terminal of the second input circuit 102 . The first terminal of the sixth input transistor N6 is connected to the second terminal of the fourth input transistor N4 and the second terminal of the fifth input transistor N5, and the second terminal of the sixth input transistor N6 is connected to the ground terminal.

The control terminal of the sixth input transistor N6 receives a clock signal for controlling the working state of the second input circuit 102 . When the sixth input transistor N6 is closed, the second input circuit 102 works. When the sixth input transistor N6 is turned off, the second input circuit 102 stops working.

The control terminal of the fourth input transistor N4 receives the second reference signal, the control terminal of the fifth input transistor N5 receives the second input signal, and the second reference signal and the second input signal are amplified through the fourth input transistor N4 and the fifth input transistor N5 Then, a second differential signal is generated at the first terminal of the fourth input transistor N4 and the first terminal of the fifth input transistor N5.

The output circuit 105 includes a first output transistor N7, a second output transistor N8, a third output transistor P1, and a fourth output transistor P2 forming a cross-coupled circuit. The first terminal of the first output transistor N7 is connected to the second terminal of the third output transistor P1, and the first terminal of the second output transistor N8 is connected to the second terminal of the fourth output transistor P2. After the control terminal of the first output transistor N7 is connected to the control terminal of the third output transistor P1, it is connected to the second terminal of the fourth output transistor P2. After the control terminal of the second output transistor N8 is connected to the control terminal of the fourth output transistor P2, it is connected to the second terminal of the third output transistor P1.

The second end of the first output transistor N7 is the first input end of the output circuit 105, the second end of the second output transistor N8 is the second input end of the output circuit 105, and the second end of the first output transistor N7 is connected to the first input end of the first output transistor N7. The first terminal of the input transistor N1 is connected, and the second terminal of the second output transistor N8 is connected with the first terminal of the second input transistor N2. The second terminal of the third output transistor P1 serves as the first output terminal of the output circuit 105 , and the second terminal of the fourth output transistor P2 serves as the second output terminal of the output circuit 105 .

The first input transistor N1 and the second input transistor N2 are turned on under the control of the first input signal and the first reference signal, and also pull down the first end of the first output transistor N7 and the first end of the second output transistor N8 voltage. The fourth input transistor N4 and the fifth input transistor N5 are turned on under the control of the second input signal and the second reference signal, and also pull down the first terminal of the first output transistor N7 and the first terminal of the second output transistor N8 voltage. By controlling the magnitudes of the first input signal and the second input signal, the difference between the voltage at the first terminal of the first output transistor N7 and the voltage at the first terminal of the second output transistor N8 can be controlled.

The transistor is turned on when the voltage is pulled down to the flipping voltage. That is, the first output transistor N7 and the fourth output transistor P2 are turned on, or the second output transistor N8 and the third output transistor P1 are turned on. If the first output transistor N7 and the fourth output transistor P2 are turned on, the voltage of the second terminal of the fourth output transistor P2 is pulled up, and the voltage of the second terminal of the third output transistor P1 is pulled down. If the second output transistor N8 and the third output transistor P1 are turned on, the voltage at the second end of the fourth output transistor P2 is pulled down, and the voltage at the second end of the third output transistor P1 is pulled up to realize the output voltage signal to the input circuit Perform amplification and latch processing.

In one embodiment, the first feedback unit 1031 includes a first feedback transistor N9, the control terminal of the first feedback transistor N9 is the control terminal of the first feedback unit 1031, and the first terminal of the first feedback transistor N9 is the first feedback unit 1031 on the first end. The control terminal of the first feedback transistor N9 is connected to the first terminal of the first input transistor N1, and the first terminal of the first feedback transistor N9 is connected to the first terminal of the second input transistor N2. The second end of the first feedback transistor N9 is connected to the second end of the second input transistor N2. The second terminal of the first feedback transistor N9 is also connected to the first terminal of the third input transistor N3.

The control terminal of the second feedback transistor N10 is the control terminal of the second feedback unit 1032 , and the first terminal of the second feedback transistor N10 is the first terminal of the second feedback unit 1032 . The control terminal of the second feedback transistor N10 is connected to the first terminal of the second input transistor N2, and the first terminal of the second feedback transistor N10 is connected to the first terminal of the first input transistor N1. The second terminal of the second feedback transistor N10 is connected to the second terminal of the first input transistor N1, and the second terminal of the second feedback transistor N10 is also connected to the first terminal of the third input transistor N3.

In one embodiment, the first feedback transistor N9, the second feedback transistor N10, the first input transistor N1, and the second input transistor N2 are of the same type, so as to ensure that the first feedback transistor N9 pulls the The direction of the voltage is the same as the direction in which the second feedback transistor N10 pulls the voltage of the first output terminal of the first input circuit 101, which also ensures that the feedback transistor pulls the voltage of the output terminal of the first input circuit 101 and the input transistor pulls the output of the first input circuit 101 The direction of the voltage at the terminals is the same, realizing positive feedback.

When the voltage at the first terminal of the first input transistor N1 is greater, the ability of the first feedback transistor N9 to pull down the voltage at the first terminal of the second input transistor N2 is greater, and the voltage at the first terminal of the second input transistor N2 is greater. The faster the voltage drops, the positive feedback mechanism is realized, and the difference of the differential voltage between the first input transistor N1 and the second input transistor N2 is accelerated.

In one embodiment, the third feedback unit 1033 includes a third feedback transistor N11, the control terminal of the third feedback transistor N11 is the control terminal of the third feedback unit 1033, and the first terminal of the third feedback transistor N11 is the third feedback unit 1033 on the first end. The control terminal of the third feedback transistor N11 is connected to the first terminal of the fourth input transistor N4, and the first terminal of the third feedback transistor N11 is connected to the first terminal of the fifth input transistor N5. The second end of the third feedback transistor N11 is connected to the second end of the fourth input transistor N4. The second terminal of the third feedback transistor N11 is also connected to the first terminal of the sixth input transistor N6.

The control terminal of the fourth feedback transistor N12 is the control terminal of the fourth feedback unit 1034 , and the first terminal of the fourth feedback transistor N12 is the first terminal of the fourth feedback unit 1034 . The control terminal of the fourth feedback transistor N12 is connected to the first terminal of the fifth input transistor N5, and the first terminal of the fourth feedback transistor N12 is connected to the first terminal of the fourth input transistor N4. The second end of the fourth feedback transistor N12 is connected to the second end of the fifth input transistor N5, and the second end of the fourth feedback transistor N12 is also connected to the first end of the sixth input transistor N6.

In an embodiment, the types of the third feedback transistor N11, the fourth feedback transistor N12, the fourth input transistor N4, and the fifth input transistor N5 are the same to ensure that the third feedback transistor N11 pulls the second output terminal of the second input circuit 102 The direction of the voltage is the same as the direction in which the fourth feedback transistor N12 pulls the voltage of the first output terminal of the second input circuit 102, and also ensures that the feedback transistor pulls the voltage of the output terminal of the second input circuit 102 and the input transistor pulls the output of the second input circuit 102 The direction of the voltage at the terminals is the same, realizing positive feedback.

When the voltage of the first terminal of the fourth input transistor N4 is greater, the ability of the third feedback transistor N11 to pull down the voltage of the first terminal of the fifth input transistor N5 is greater, and the voltage of the first terminal of the fifth input transistor N5 is greater. The faster the voltage drops, the positive feedback mechanism is implemented to speed up the difference of the differential voltage between the fourth input transistor N4 and the fifth input transistor N5.

In one embodiment, the types of the first input transistor N1 , the second input transistor N2 , the fourth input transistor N4 and the fifth input transistor N5 are the same.

In one embodiment, the comparator further includes a first reset circuit 1061, the first reset circuit 1061 is connected between the first output terminal of the first input circuit 101 and the second output terminal of the first input circuit 101, the first reset The circuit 1061 is used to reset the voltage of the first output terminal of the first input circuit 101 and the voltage of the second output terminal of the first input circuit 101 .

Wherein, the first reset circuit 1061 includes a first clocked transistor P5 and a second clocked transistor P6, the second terminal of the first clocked transistor P5 is connected to the first output terminal of the first input circuit 101, and the second clocked transistor P6 The second end of the first input circuit 101 is connected to the second output end of the first input circuit 101, the first end of the second clocked transistor P6 is connected to the first end of the first clocked transistor P5 and then connected to a power supply. Both the control terminals of the first clocked transistor P5 and the second clocked transistor P6 receive the clock signal, and are turned on when the clock signal is at a low level, and pull the first output terminal and the second output terminal of the first input circuit 101 to a high level. flat.

In one embodiment, the comparator further includes a second reset circuit 1062 and a third reset circuit 1063, the second reset circuit 1062 is connected to the first output terminal of the output circuit 105, and the third reset circuit 1063 is connected to the first output terminal of the output circuit 105. Two output terminals. The second reset circuit 1062 is used to reset the voltage of the first output terminal of the output circuit 105 . The third reset circuit 1063 is used to reset the voltage of the second output terminal of the output circuit 105 .

Wherein, the second reset circuit 1062 includes a third clocked transistor P3, and the second terminal of the third clocked transistor P3 is connected to the first output terminal of the output circuit 105 . The control end of the third clock control transistor P3 is used to receive the clock signal, and is used to pull the first output end of the output circuit 105 to a high level when the clock signal is at a low level. The third reset circuit 1063 includes a fourth clocked transistor P4 , the second end of the fourth clocked transistor P4 is connected to the second output end of the output circuit 105 . The control end of the fourth clock control transistor P4 is used to receive the clock signal, and is used to pull the second output end of the output circuit 105 to a high level when the clock signal is at a low level.

Compared with the second reset circuit 1062 and the third reset circuit 1063 pulling the voltages of the two output terminals of the first input circuit 101 through the output circuit 105 to reset, by setting the first reset circuit 1061 to directly pull the voltages of the two output terminals of the first input circuit 101 The voltage at the output terminal is reset, and the reset time is shorter, thereby improving the response rate of the comparator.

In one embodiment, the types of the first clocked transistor P5, the second clocked transistor P6, the third clocked transistor P3, and the fourth clocked transistor P4 are the same, so as to realize the two output terminals of the input circuit and the output circuit The two output terminals of 105 are pulled to the same level.

In one embodiment, when the first feedback transistor N9, the second feedback transistor N10, the third feedback transistor N11, the fourth feedback transistor N12, the first input transistor N1, the second input transistor N2, the third input transistor N3, and When the fourth input transistor N4 is an N-type transistor, the drain of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal.

In one embodiment, when both the first output transistor N7 and the second output transistor N8 are N-type transistors, the drain of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal.

When the third output transistor P1 and the fourth output transistor P2 are both P-type transistors, the first clocked transistor P5, the second clocked transistor P6, the third clocked transistor P3, and the fourth clocked transistor P4 are all P-type In the case of a transistor, the source of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal.

In one embodiment, the first feedback transistor N9 and the second feedback transistor N10 have the same size, the first input transistor N1 and the second input transistor N2 have the same size, and the size of the first feedback transistor N9 is smaller than the size of the first input transistor N1 Half. Preventing the first feedback transistor N9 and the second feedback transistor N10 from affecting the sensing of the first input signal and the first reference signal by the first input transistor N1 and the second input transistor N2 , thereby improving the accuracy of the output result of the comparator.

In one embodiment, the size of the third feedback transistor N11 and the fourth feedback transistor N12 are the same, the size of the fourth input transistor N4 and the fifth input transistor N5 are the same, and the size of the third feedback transistor N11 is smaller than the size of the fourth input transistor N4 Half. The third feedback transistor N11 and the fourth feedback transistor N12 are prevented from affecting the sensing of the second input signal and the second reference signal by the fourth input transistor N4 and the fifth input transistor N5, thereby improving the accuracy of the output result of the comparator.

In one embodiment, the ratio of the size of the fourth input transistor N4 to the size of the first input transistor N1 is α, α<0.5, so that the size of the fourth input transistor N4 is smaller than half of the size of the first input transistor N1 one. The ratio of the size of the third feedback transistor N11 to the size of the first feedback transistor N9 is α<0.5, so that the size of the first feedback transistor N9 is smaller than half of the size of the third feedback transistor N11 . The ratio of the size of the sixth input transistor N6 to the size of the third input transistor N3 is α, α<0.5, so that the size of the sixth input transistor N6 is smaller than half of the size of the third input transistor N3. Through the above settings, it is possible to avoid the inversion of the first differential signal caused by the second input circuit 102 having too much influence on the first input circuit 101, for example: the first input signal and the first reference signal make the first input transistor N1 The voltage at one terminal is greater than the voltage at the first terminal of the second input transistor N2, and the first differential signal is reversed due to the intervention of the second differential signal, that is, the voltage at the first terminal of the first input transistor N1 is lower than that of the second input transistor N2 first terminal voltage.

In an embodiment, the second reference signal and the second input signal at the current moment are determined according to the first input signal and the first reference signal at the previous moment. The first input signal at the previous moment is greater than the first reference signal, and the second input signal at the current moment is set to be greater than the second reference signal. The first input signal at the last moment is smaller than the first reference signal, and the second input signal at the current moment is set to be smaller than the second reference signal.

The following describes the working process of the comparator shown in Figure 4 in combination with the four working stages of the comparator:

In the reset phase, the clock signal is at low level, the third input transistor N3 and the sixth input transistor N6 are disconnected, the first input circuit 101 and the second input circuit 102 stop working, the first clock control transistor P5 and the second clock control transistor P5 The transistor P6 is turned on, the first reset circuit 1061 works, and the voltages of the first output terminal and the second output terminal of the first input circuit 101 are pulled up to a high level. The third clocked transistor P3 and the fourth clocked transistor P4 are closed, the second reset circuit 1062 and the third reset circuit 1063 work, and the drain of the third output transistor P1 and the drain of the fourth output transistor P2 are pulled to high voltage level.

In the sampling stage, the clock signal is high level, the first clock control transistor P5, the second clock control transistor P6, the third clock control transistor P3 and the fourth clock control transistor P4 are disconnected, and the first reset circuit 1061 to the third reset Circuit 1063 stops working. The third input transistor N3 and the sixth input transistor N6 are closed, and the first input circuit 101 and the second input circuit 102 work.

The sampling phase will be described below in conjunction with the case that the first input signal and the second input signal take different values.

In the first case: at the current moment, the first input signal is greater than the first reference signal, but at the previous moment, the first input signal was smaller than the first reference signal, according to the difference between the first input signal and the first reference signal at the previous moment The relationship between the second input signal is set to be smaller than the first reference signal, for example: at the last moment, the first input signal was 0.7V, and the first reference signal was 0.8V. At the current moment, the first input signal is 0.9V, the first reference signal is 0.8V, the second input signal is 0V, and the second reference signal is 1.2V.

When there is intersymbol interference, that is, the first input signal at the previous moment will interfere with the first input signal at the current moment, assuming that the amplitude of the first input terminal In1 of the first input circuit 101 is 0.8V, the first The pull-down capability of the input transistor N1 is equal to the pull-down capability of the second input transistor N2, and the drain voltage of the first input transistor N1 is equal to the drain voltage of the second input transistor N2. While the pull-down capability of the fourth input transistor N4 is higher than that of the fifth input transistor N5, under the pull of the fourth input transistor N4 and the fifth input transistor N5, and the first positive feedback circuit 103 and the second positive feedback circuit 104 , the voltage at the second terminal of the first input transistor N1 is lower than the voltage at the second terminal of the second input transistor N2 .

When there is no intersymbol interference, the first input signal and the first reference signal will also make the voltage at the second terminal of the first input transistor N1 smaller than the voltage at the second terminal of the second input transistor N2. That is, through the adjustment of the first input circuit 101 by the second input circuit 102, the intersymbol interference is eliminated. Usually, the pull-down capability of the fourth input transistor N4 and the fifth input transistor N5 is relatively small. When there is a voltage difference between the drains of the fourth input transistor N4 and the fifth input transistor N5, the fourth input transistor N4 is accelerated by two positive feedback circuits. and the drain of the fifth input transistor N5 can shorten the sampling time and reduce power consumption.

In the second case, at the current moment and the last moment, the first input signal is greater than the first reference signal, and the second input signal is set to be greater than the first reference signal, for example: at the last moment, the first input signal is 0.9V, The first reference signal is 0.8V. At the current moment, the first input signal is 0.9V, the first reference signal is 0.8V, the second input signal is 1.2V, and the second reference signal is 0V.

When intersymbol interference exists, that is, the first input signal at the previous moment will interfere with the first input signal at the current moment, assuming that the amplitude of the first input terminal In1 of the first input circuit 101 is still 0.9V, the first The pull-down capability of an input transistor N1 is greater than that of the second input transistor N2, and the drain voltage of the first input transistor N1 is lower than the drain voltage of the second input transistor N2. While the pull-down capability of the fourth input transistor N4 is smaller than that of the fifth input transistor N5, the second input circuit 102 will pull the first input transistor N1 in a direction in which the voltage of the first input transistor N1 is greater than the voltage of the second input transistor N2 voltage and the second input transistor N2, but the pulling ability of the transistor in the second input circuit is α times that of the transistor in the first input circuit, and α is less than 0.5, and the pulling ability of the transistor in the second input circuit is much weaker than that of the first input circuit For the pull-up capability of the transistors in the input circuit, the voltage at the second terminal of the first input transistor N1 is still smaller than the voltage at the second terminal of the second input transistor N2.

In the third case, at the current moment, the first input signal is smaller than the first reference signal, but at the previous moment, the first input signal was greater than the first reference signal, and the second input signal is set to be greater than the first reference signal, for example: in the above At one moment, the first input signal is 0.9V, and the first reference signal is 0.8V. At the current moment, the first input signal is 0.7V, the first reference signal is 0.8V, the second input signal is 1.2V, and the second reference signal is 0V.

In the presence of intersymbol interference, assuming that the amplitude of the first input terminal In1 of the first input circuit 101 is 0.8V, the pull-down capability of the first input transistor N1 is equal to the pull-down capability of the second input transistor N2, and the pull-down capability of the first input transistor N1 The drain voltage is equal to the drain voltage of the second input transistor N2. While the pull-down capability of the fourth input transistor N4 is lower than that of the fifth input transistor N5, under the pull of the fourth input transistor N4 and the fifth input transistor N5, and the first positive feedback circuit 103 and the second positive feedback circuit Under the pull of 104 , the voltage at the second terminal of the first input transistor N1 is greater than the voltage at the second terminal of the second input transistor N2 .

When there is no intersymbol interference, the first input signal and the first reference signal will also make the voltage at the second terminal of the first input transistor N1 greater than the voltage at the second terminal of the second input transistor N2. That is, through the adjustment of the first input circuit 101 by the second input circuit 102, the intersymbol interference is eliminated. Usually, the pull-down capability of the fourth input transistor N4 and the fifth input transistor N5 is relatively small. When there is a voltage difference between the drains of the fourth input transistor N4 and the fifth input transistor N5, the fourth input transistor N4 is accelerated by two positive feedback circuits. and the drain of the fifth input transistor N5 can shorten the sampling time and reduce power consumption.

In the fourth case, at the current moment, the first input signal is smaller than the first reference signal, and at the previous moment, the first input signal was smaller than the first reference signal, and the second input signal is set to be smaller than the first reference signal, for example: in the above At one moment, the first input signal is 0.7V, and the first reference signal is 0.8V. At the current moment, the first input signal is 0.7V, the first reference signal is 0.8V, the second input signal is 0V, and the second reference signal is 1.2V.

When there is intersymbol interference, assuming that the amplitude of the first input terminal In1 of the first input circuit 101 is still 0.7V, the pull-down capability of the first input transistor N1 is smaller than that of the second input transistor N2, and the first input transistor N1 The drain voltage of is greater than the drain voltage of the second input transistor N2. While the pull-down capability of the fourth input transistor N4 is greater than that of the fifth input transistor N5, the second input circuit 102 will pull the first input transistor N1 in a direction in which the voltage of the first input transistor N1 is lower than the voltage of the second input transistor N2 voltage and the second input transistor N2, but the pulling ability of the transistor in the second input circuit is α times that of the transistor in the first input circuit, and α is less than 0.5, and the pulling ability of the transistor in the second input circuit is much weaker than that of the first input circuit For the pull-up capability of the transistors in the input circuit, the voltage at the second terminal of the first input transistor N1 is still greater than the voltage at the second terminal of the second input transistor N2.

In the regeneration stage, due to the pull-down effect of the first input transistor N1, the second input transistor N2, the fourth input transistor N4 and the fifth input transistor N5, the drain voltage of the first output transistor N7 and the drain voltage of the second output transistor N8 When the drain voltage of the first input transistor N1 is higher than the drain voltage of the second input transistor N2, the first output transistor N7 and the fourth output transistor P2 are gradually disconnected, and the second output transistor P1 and the The third output transistor N8 is gradually turned on, and the ability to pull down the drain voltage of the fourth output transistor P2 becomes stronger and stronger, and the ability to pull up the drain voltage of the third output transistor P1 becomes stronger and stronger.

In the decision-making phase, the first output transistor N7 and the fourth output transistor P2 are turned off, the second output transistor P1 and the third output transistor N8 are turned on, and the drain voltage of the fourth output transistor P2 continues to be pulled down, and the third output transistor P2 is pulled up. The drain voltage of the transistor P1, after pulling the drain of the fourth output transistor P2 to a high level, and pulling the drain voltage of the third output transistor P1 to a low level, the third output transistor P1 and the fourth output The drain voltage of transistor P2 is maintained.

When the next working cycle comes, the clock signal becomes low level, and the drain voltages of the third output transistor P1 and the fourth output transistor P2 are reset to high level by the third clock control transistor P5 and the fourth clock control transistor P6.

In the above embodiment, setting the second input signal and the second reference signal at the current time according to the first input signal and the first reference signal received by the first input circuit at the previous time can effectively eliminate the first input signal of the first input circuit. Intersymbol interference at the input improves the accuracy of the comparator. Due to intersymbol interference, the differential signal difference generated by the first input signal and the second input signal at the two input terminals of the first input circuit becomes smaller, and the feedback transistor in the input circuit pulls the voltage at the output terminal of the input circuit at different rates , to speed up the difference between the differential signals at the output, thereby shortening the time that the comparator is in the sampling phase and reducing the power consumption of the comparator. In addition, the first reset circuit directly pulls the voltage of the output terminal of the input circuit to reset, which can shorten the reset time of the output terminal of the input circuit, thereby improving the response rate of the comparator.

Fig. 5 is a schematic diagram of the circuit structure of a comparator provided by another embodiment of the present application. As shown in Fig. 5, the comparator provided by the present application includes a first input circuit 101, a second input circuit 102, a first positive feedback circuit 103 , the second positive feedback circuit 104 , the output circuit 105 , the first reset circuit 1061 , the second reset circuit 1062 and the third reset circuit 1063 .

The first input circuit 101 includes a first input transistor P1, a second input transistor P2 and a third input transistor P3, the second terminal of the first input transistor P1 is connected to the first terminal of the third input transistor P3, and the second terminal of the second input transistor P2 The second terminal is connected to the first terminal of the third input transistor P3, and the second terminal of the third input transistor P3 is connected to the power supply terminal.

The first feedback unit 1031 includes a first feedback transistor P9, the second feedback unit 1032 includes a second feedback transistor P10, the control end of the first feedback transistor P9 is connected to the first end of the first input transistor P1, and the second feedback transistor P9 of the first feedback transistor P9 One terminal is connected to the first terminal of the second input transistor P2, the control terminal of the second feedback transistor P10 is connected to the first terminal of the second input transistor P2, and the first terminal of the second feedback transistor P10 is connected to the first terminal of the first input transistor P1. end. Both the second terminal of the first feedback transistor P9 and the second terminal of the second feedback transistor P10 are connected to the first terminal of the third input transistor P3.

The second input circuit 102 includes a fourth input transistor P4, a fifth input transistor P5 and a sixth input transistor P6, the second end of the fourth input transistor P4 is connected to the first end of the sixth input transistor P6, and the fifth input transistor P5 The second terminal is connected to the first terminal of the sixth input transistor P6, and the second terminal of the sixth input transistor P6 is connected to the power supply terminal.

The third feedback unit 1033 includes a third feedback transistor P11, the fourth feedback unit 1034 includes a fourth feedback transistor P12, the control end of the third feedback transistor P11 is connected to the first end of the fourth input transistor P4, and the third feedback transistor P11 One terminal is connected to the first terminal of the fifth input transistor P5, the control terminal of the fourth feedback transistor P12 is connected to the first terminal of the fifth input transistor P5, and the first terminal of the fourth feedback transistor P12 is connected to the first terminal of the fourth input transistor P4. end. Both the second terminal of the third feedback transistor P11 and the second terminal of the fourth feedback transistor P12 are connected to the first terminal of the sixth input transistor P6.

The output circuit 105 includes a first output transistor P7, a second output transistor P8, a third output transistor N1 and a fourth output transistor N2, the first end of the first output transistor P7 is connected to the second end of the third output transistor N1, the second The first end of the second output transistor P8 is connected to the second end of the fourth output transistor N2. After the control terminal of the first output transistor P7 is connected to the control terminal of the third output transistor N1, it is connected to the second terminal of the fourth output transistor N2. After the control terminal of the second output transistor P8 is connected to the control terminal of the fourth output transistor N2, it is connected to the second terminal of the third output transistor N1.

The first reset circuit 1061 includes a first clocked transistor N5 and a second clocked transistor N6, the second terminal of the first clocked transistor N5 is connected to the first output terminal of the first input circuit 101, and the second terminal of the second clocked transistor N6 The two terminals are connected to the second output terminal of the first input circuit 101, the first terminal of the second clocked transistor N6 is connected to the first terminal of the first clocked transistor N5 and then connected to the power supply. The second reset circuit 1062 includes a third clocked transistor N3 , the second terminal of the third clocked transistor N3 is connected to the first output terminal of the output circuit 105 . The third reset circuit 1063 includes a fourth clocked transistor N4 , the second end of the fourth clocked transistor N4 is connected to the second output end of the output circuit 105 .

In an embodiment, when the first feedback transistor P9, the second feedback transistor P10, the third feedback transistor P11, the fourth feedback transistor P12, the first input transistor P1 to the sixth input transistor P6 are all P-type transistors, P The drain of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal.

In one embodiment, when both the first output transistor P7 and the second output transistor P8 are P-type transistors, the drain of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal.

When the third output transistor N1 and the fourth output transistor N2 are both N-type transistors, the first clocked transistor N5, the second clocked transistor N6, the third clocked transistor N3 and the fourth clocked transistor N4 are all N-type In the case of a transistor, the source of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal.

The following describes the working process of the comparator shown in Figure 5 in combination with the four working stages of the comparator:

The difference from the comparator shown in FIG. 4 is that in the reset phase, after the clock signal is inverted to a high level, it is input to the control terminals of the third input transistor P3 and the sixth input transistor P6, so that the first input circuit 101 and the second input circuit 101 The second input circuit 102 stops working. After the clock signal is inverted to a high level, the first clocked transistor N5 and the second clocked transistor N6 are turned on, and the voltages of the first output end and the second output end of the first input circuit 101 are pulled to a low level. After the clock signal is reversed to a high level, the third clocked transistor N3 and the fourth clocked transistor N4 are turned on, and the drain of the third output transistor N1 and the drain of the fourth output transistor N2 are pulled to a low level. flat.

The difference from the comparator shown in FIG. 4 is that in the sampling phase, the clock signal is inverted to a high level and then input to each clock control transistor, and the third input transistor P3 and the sixth input transistor P6 make the first reset circuit 1061 to the third reset circuit 1063 stop working, and the first input circuit 101 and the second input circuit 102 work.

The sampling phase will be described below in conjunction with the case that the first input signal and the second input signal take different values.

In the first case: at the current moment, the first input signal is greater than the first reference signal, but at the previous moment, the first input signal was smaller than the first reference signal, according to the difference between the first input signal and the first reference signal at the previous moment The relationship between the second input signal is set to be smaller than the first reference signal, for example: at the last moment, the first input signal was 0.2V, and the first reference signal was 0.3V. At the current moment, the first input signal is 0.4V, the first reference signal is 0.3V, the second input signal is 0V, and the second reference signal is 1.2V.

When there is intersymbol interference, that is, the first input signal at the previous moment will interfere with the first input signal at the current moment, assuming that the amplitude of the first input terminal In1 of the first input circuit 101 is 0.3V, the first The pull-up capability of the input transistor P1 is equal to the pull-up capability of the second input transistor P2, and the drain voltage of the first input transistor P1 is equal to the drain voltage of the second input transistor P2. While the pull-up capability of the fourth input transistor P4 is higher than that of the fifth input transistor P5, under the pull of the fourth input transistor P4 and the fifth input transistor P5, and the first positive feedback circuit 103 and the second positive feedback circuit 103 Pulled by the feedback circuit 104 , the voltage at the second terminal of the first input transistor P1 is higher than the voltage at the second terminal of the second input transistor P2 .

When there is no intersymbol interference, the first input signal and the first reference signal also make the voltage at the second terminal of the first input transistor P1 higher than the voltage at the second terminal of the second input transistor P2 . That is, through the adjustment of the first input circuit 101 by the second input circuit 102, the intersymbol interference is eliminated. Usually, the pull-down capability of the fourth input transistor P4 and the fifth input transistor P5 is relatively small. When there is a voltage difference between the drains of the fourth input transistor P4 and the fifth input transistor P5, the fourth input transistor P4 is accelerated by two positive feedback circuits. and the drain of the fifth input transistor P5 can shorten the sampling time and reduce power consumption.

In the second case, at the current moment and the last moment, the first input signal is greater than the first reference signal, and the second input signal is set to be greater than the first reference signal, for example: at the last moment, the first input signal is 0.4V, The first reference signal is 0.3V. At the current moment, the first input signal is 0.4V, the first reference signal is 0.3V, the second input signal is 1.2V, and the second reference signal is 0V.

In the presence of intersymbol interference, assuming that the amplitude of the first input terminal IP1 of the first input circuit 101 is still 0.4V, the pull-up capability of the first input transistor P1 is greater than the pull-up capability of the second input transistor P2, and the first input The drain voltage of the transistor P1 is greater than the drain voltage of the second input transistor P2. While the pull-up capability of the fourth input transistor P4 is smaller than the pull-up capability of the fifth input transistor P5, the second input circuit 102 will pull the first input transistor P1 in a direction that makes the voltage of the first input transistor P1 smaller than the voltage of the second input transistor P2. The voltage of the transistor P1 and the second input transistor P2, but the pulling capacity of the transistor in the second input circuit 102 is α times that of the corresponding transistor in the first input circuit 101, and α is less than 0.5, and the transistor in the second input circuit 101 The pull-up capability of the transistor in the first input circuit 102 is much weaker than that of the transistors in the first input circuit 102, and the voltage at the second terminal of the first input transistor P1 is still greater than the voltage at the second terminal of the second input transistor P2.

In the third case, at the current moment, the first input signal is smaller than the first reference signal, but at the previous moment, the first input signal was greater than the first reference signal, and the second input signal is set to be greater than the first reference signal, for example: in the above At one moment, the first input signal is 0.4V, and the first reference signal is 0.3V. At the current moment, the first input signal is 0.2V, the first reference signal is 0.3V, the second input signal is 1.2V, and the second reference signal is 0V.

In the presence of intersymbol interference, assuming that the amplitude of the first input terminal In1 of the first input circuit 101 is 0.3V, the pull-up capability of the first input transistor P1 is equal to the pull-up capability of the second input transistor P2, and the first input transistor The drain voltage of P1 is equal to the drain voltage of the second input transistor P2. While the pull-up capability of the fourth input transistor P4 is lower than the pull-up capability of the fifth input transistor P5, under the pull of the fourth input transistor P4 and the fifth input transistor P5, and the first positive feedback circuit 103 and the second positive feedback circuit 103 Pulled by the feedback circuit 104 , the voltage at the second terminal of the first input transistor P1 is lower than the voltage at the second terminal of the second input transistor P2 .

In the fourth case, at the current moment, the first input signal is smaller than the first reference signal, and at the previous moment, the first input signal was smaller than the first reference signal, and the second input signal is set to be smaller than the first reference signal, for example: in the above At one moment, the first input signal is 0.2V, and the first reference signal is 0.3V. At the current moment, the first input signal is 0.2V, the first reference signal is 0.3V, the second input signal is 0V, and the second reference signal is 1.2V.

When intersymbol interference exists, assuming that the amplitude of the first input terminal In1 of the first input circuit 101 is still 0.2V, the pull-up capability of the first input transistor P1 is smaller than the pull-up capability of the second input transistor P2, and the first input The drain voltage of the transistor P1 is lower than the drain voltage of the second input transistor P2. While the pull-up capability of the fourth input transistor P4 is greater than the pull-up capability of the fifth input transistor P5, the second input circuit 102 will pull the first input transistor P1 to a direction in which the voltage of the first input transistor P1 is greater than the voltage of the second input transistor P2. The voltage of transistor P1 and the second input transistor P2, but the pulling ability of the transistor in the second input circuit is α times that of the transistor in the first input circuit, α is less than 0.5, and the pulling ability of the transistor in the second input circuit is far weaker Due to the pull-up capability of the transistors in the first input circuit, the voltage at the second terminal of the first input transistor P1 is still smaller than the voltage at the second terminal of the second input transistor P2.

In the regeneration stage, due to the pull-down effect of the first input transistor P1, the second input transistor P2, the fourth input transistor P4 and the fifth input transistor P5, the drain voltage of the first output transistor P7 and the drain voltage of the second output transistor P8 When the pole voltage reaches the flipping voltage, when the drain voltage of the first input transistor P1 is higher than the drain voltage of the second input transistor P2, the first output transistor P7 and the fourth output transistor N2 are gradually turned on, and the second output transistor N1 and The third output transistor N2 is gradually turned off, and the ability to pull down the drain voltage of the fourth output transistor N2 becomes stronger and stronger, and the ability to pull up the drain voltage of the third output transistor N1 becomes stronger and stronger.

In the decision-making phase, the first output transistor N7 and the fourth output transistor N2 are turned on, the second output transistor N1 and the third output transistor N8 are turned off, and the drain voltage of the fourth output transistor N2 continues to be pulled down, and the third output transistor N2 is pulled up. The drain voltage of the transistor N1, after pulling the drain of the fourth output transistor N2 to a low level, and pulling the drain voltage of the third output transistor N1 to a high level, the third output transistor N1 and the fourth output The drain voltage of transistor N2 is maintained.

When the next working cycle comes, the clock signal becomes low level, and the drain voltages of the third output transistor N1 and the fourth output transistor N2 are reset to low level by the third clock control transistor N3 and the fourth clock control transistor N4.

In the above technical solution, setting the second input signal and the second reference signal at the current time according to the first input signal and the first reference signal received by the first input circuit at the previous time can effectively eliminate the first input signal of the first input circuit. Intersymbol interference at the input improves the accuracy of the comparator.

FIG. 6 is a structural block diagram of a comparator provided by the present application. As shown in FIG. 6, the comparator includes a first input circuit 101, a second input circuit 102, a first positive feedback circuit 103, and a second positive feedback circuit 104. and an output circuit 105 .

The second input circuit includes at least one controllable input module, each input module includes a fourth input transistor, a fifth input transistor, and a sixth input transistor, the control terminal of the fourth input transistor is used to receive the second reference signal, and the fifth input The control terminal of the transistor is used to receive the second input signal, and the first terminal of the sixth input transistor is connected with the second terminal of the fourth input transistor and the second terminal of the fifth input transistor. The sixth input transistor is used to receive a clock control signal, and the clock control signal can control the working state of the controllable input module, and then control the number of working controllable input modules.

The second positive feedback circuit 104 includes at least one controllable positive feedback module 1040 , wherein each controllable positive feedback module includes a third feedback unit 1041 , a fourth feedback unit 1042 , a first switch 1043 and a second switch 1044 . Both the third feedback unit 1041 and the fourth feedback unit 1042 are provided with a control terminal and a first terminal.

Wherein, the control terminal of the third feedback unit 1041 is connected to the first output terminal of the second input circuit 102 through the first switch 1043 , and the first terminal of the third feedback unit 1041 is connected to the second output terminal of the second input circuit 102 . The control terminal of the fourth feedback unit 1042 is connected to the second output terminal of the second input circuit 102 through the second switch 1044 , and the first terminal of the fourth feedback unit 1042 is connected to the first output terminal of the second input circuit 102 .

The first switch 1043 is used to control whether the third feedback unit 1041 generates positive feedback, and the second switch 1044 is used to control whether the fourth feedback unit 1042 generates positive feedback. By controlling the on and off of the first switch 1043 and the second switch 1044, it is possible to control whether the controllable positive feedback module 1040 generates positive feedback. When both the first switch 1043 and the second switch 1044 are closed, the controllable positive feedback module 1040 can accelerate the difference between the second differential signals at the output terminals of the second input circuit through a positive feedback mechanism. When both the first switch 1043 and the second switch 1044 are turned off, the controllable positive feedback module 1040 is disconnected from the second input circuit, and the positive feedback mechanism cannot be generated at the output end of the second input circuit.

When the comparator is working, the number of controllable positive feedback modules that generate positive feedback can be controlled, thereby controlling the ability of the second positive feedback circuit to pull the difference between the second differential signals. Therefore, on the one hand, the time during which the comparator is in the sampling phase is controlled to ensure the response rate of the comparator. On the other hand, the ability of the second positive feedback circuit to pull the voltage of the output terminal of the second input circuit and the ability of the second input signal and the second reference signal to pull the voltage of the output terminal of the second input circuit can be balanced, so as to avoid the second positive feedback circuit Affecting the polarity of the second differential signal generated at the output of the second input circuit. It is also possible to control the number of working controllable input modules, and control the number of controllable positive feedback modules that generate positive feedback based on the number of working controllable input modules, so that the first differential signal and the second differential signal are added to the signal pole The polarity is the same as that of the first differential signal, and the second differential signal only serves to adjust the first differential signal to ensure that the comparator can accurately output the comparison result according to the first input signal and the first reference signal.

Figure 7 and Figure 8 are one of the specific circuit diagrams based on the comparator shown in Figure 6, wherein the structures of the first input circuit 101, the second input circuit 102 and the output circuit 105 are the same as those of the comparator shown in Figure 4, here I won't repeat them here. The comparator also includes a first reset circuit 1061 , a second reset circuit 1064 and a third reset circuit 1065 . The three reset circuits have also been described in detail in the embodiment shown in FIG. 4 , and will not be repeated here.

The specific circuit structure of each controllable positive feedback module in the positive feedback circuit will be described below with reference to FIG. 7 and FIG. 8 . The third feedback unit 1041 includes a third feedback transistor N11, the control terminal of the third feedback transistor N11 is used as the control terminal of the third feedback unit 1041, and the first terminal of the third feedback transistor N11 is the second terminal of the third feedback unit 1041.

The control terminal of the third feedback transistor N11 is connected to the first terminal of the third feedback transistor N11 through the first switch 1045 . The first switch 1043 includes a first transmission gate G1, and the first transmission gate G1 is controlled by a first enable signal EN1. produce.

The fourth feedback unit 1042 includes a fourth feedback transistor N12 , the control terminal of the fourth feedback transistor N12 is the control terminal of the fourth feedback unit 1042 , and the first terminal of the fourth feedback transistor N12 is the second terminal of the fourth feedback unit 1042 .

The control terminal of the fourth feedback transistor N12 is connected to the first terminal of the fourth feedback transistor N12 through the second switch 1044 . The second switch 1044 includes a second transmission gate G2, the second transmission gate G2 is controlled by a second enable signal EN2, and the second enable signal EN2 is configured according to the operating frequency of the comparator, the input common mode range of the comparator and the test mode signal. produce.

The switching state of the first transmission gate G1 and the second transmission gate G2 is controlled by the enable signal, thereby controlling whether the third feedback transistor N11 and the fourth feedback transistor N12 provide a positive feedback mechanism, and then the controllable positive feedback participating in the positive feedback can be adjusted number of modules.

In one embodiment, the second positive feedback circuit 104 further includes a first zero switch K10 and a zeroth zero switch K00, the control terminal of the third feedback unit 1041 is also connected to the ground terminal through the first zero switch K10, and the first zero switch K10 It is used for turning on when the first transmission gate G1 is closed, so that the transistor in the third feedback unit 1041 is not floating, and reduces the interference of external interference on the comparator. The control terminal of the fourth feedback unit 1042 is also connected to the ground terminal through the zeroth zero switch K00, the zeroth zero switch K00 is used to conduct when the second transmission gate G2 is closed, so that the transistor in the fourth feedback unit 1042 is not floating, Reduce the interference of external interference to the comparator.

In one embodiment, if the third feedback transistor N11, the fourth feedback transistor N12, the first zero switch K10 and the zeroth zero switch K00 are N-type transistors, the drain of the N-type transistor is the first terminal, and the source of the N-type transistor is It is the second end, and the gate of the N-type transistor is the control end. The first terminal of the first zero switch K10 is connected to the control terminal of the third feedback transistor N11, the first terminal of the zeroth zero switch K00 is connected to the control terminal of the fourth feedback transistor N12, the first terminal of the first zero switch K10 and the zeroth zero switch K00 The second terminal is grounded, so as to pull down the third feedback transistor N11 to low level when the first transmission gate G1 is closed, and pull down the fourth feedback transistor N12 to low level when the second transmission gate G2 is closed.

Figure 9 and Figure 10 are one of the specific circuit diagrams based on the comparator shown in Figure 6, wherein the structures of the first input circuit 101, the second input circuit 102 and the output circuit 105 are the same as those of the comparator shown in Figure 5, here I won't repeat them here. The connection relationship between the third feedback unit 1041, the fourth feedback unit 1042, the first switch 1043 and the second switch 1044 of each controllable positive feedback module 1040 in the second positive feedback circuit 104 has been described when describing the structure of FIG. 8 , I won't repeat them here.

It should be noted here that if the third feedback transistor P11, the fourth feedback transistor P12, the first zero switch K10 and the zeroth zero switch K00 are P-type transistors, the drain of the P-type transistor is the first terminal, and the drain of the P-type transistor The source is the second terminal, the gate of the P-type transistor is the control terminal, and the second terminals of the first zero switch K10 and the zeroth zero switch K00 are connected to the power supply terminal.

In the above embodiment, the first input circuit includes a plurality of controllable input modules, and the second positive feedback circuit includes a plurality of controllable positive feedback modules. By controlling the number of controllable positive feedback modules that provide a positive feedback mechanism, the second The ability of the positive feedback circuit to pull the voltages of the two output terminals of the second input circuit, thereby controlling the time when the comparator is in the sampling phase, and can also balance the positive feedback circuit, the input signal, and the reference signal's ability to pull the output terminals of the second input circuit, Improve the response rate and accuracy of the comparator. By controlling the number of controllable input modules, the ability of the second input circuit to pull the voltage of the output terminal of the first input circuit can be adjusted, so as to avoid the polarity of the differential signal at the output terminal of the first input circuit being affected by the pull capability of the second input circuit being too strong , and then set the second input signal and the second reference signal at the current time according to the first input signal and the first reference signal received by the first input circuit at the previous time, which can effectively eliminate the code gap at the first input terminal of the first input circuit interference, thereby improving the accuracy of the comparator.

As shown in FIG. 11 , a decision feedback equalization circuit provided by an embodiment of the present application includes the four comparators described in the above embodiments, which are sequentially marked as the first comparator 100 , the second comparator 200 , and the third comparator 300 and the fourth comparator 400 .

Wherein, the third input terminal Vref2 of the first comparator 100 is connected with the first output terminal P270B of the fourth comparator 400, the fourth input terminal In2 of the first comparator 100 is connected with the second output terminal P270B of the fourth comparator 400 connect. The third input terminal Vref2 of the second comparator 200 is connected to the first output terminal P0B of the first comparator 100 , and the fourth input terminal In2 of the second comparator 200 is connected to the second output terminal P0 of the first comparator 100 . The third input terminal Vref2 of the third comparator 300 is connected to the first output terminal P90B of the second comparator 200 , and the fourth input terminal In2 of the third comparator 300 is connected to the second output terminal P90 of the second comparator 200 . The third input terminal Vref2 of the fourth comparator 400 is connected to the first output terminal P270B of the third comparator 300 , and the fourth input terminal In2 of the fourth comparator 400 is connected to the second output terminal P270 of the third comparator 300 .

The first input terminal In1 of the first comparator 100 to the fourth comparator 400 all receive the first input signal, and the second input terminal Vref1 of the first comparator 100 to the fourth comparator 400 all receive the first reference signal.

Assume that when the first input signal was greater than the first reference signal at the last moment, the fourth register 400 output a digital "1", at the current moment, the third input terminal Vref2 of the first register 100 receives a low level, the first register 100 The fourth input terminal In2 of the system receives a high level, that is, the signal of the third input terminal Vref2 is smaller than the signal of the fourth input terminal In2, assuming that the first input signal is also greater than the first reference signal at the current moment, the intersymbol interference will still make The first input signal is greater than the first reference signal, and the first register 100 still outputs a digital "1".

Assuming that when the first input signal was greater than the first reference signal at the previous moment, the fourth register 400 output a digital "1", at the current moment, the signal of the third input terminal Vref2 of the first register is smaller than the signal of the fourth input terminal In2, Assuming that the first input signal is smaller than the first reference signal at the current moment, if the intersymbol interference makes the first input signal equal to or slightly larger than the first reference signal, since the signal at the third input terminal Vref2 is smaller than the signal at the fourth input terminal In2, there will still be The first register 100 still outputs the number "0".

Assume that when the first input signal was smaller than the first reference signal at the previous moment, the fourth register 400 output a digital "0", at the current moment, the signal of the third input terminal Vref2 of the first register 100 is greater than the signal of the fourth input terminal In2 , assuming that the first input signal is also smaller than the first reference signal at the current moment, the intersymbol interference will still cause the first input signal to be smaller than the first reference signal, and the first register 100 will still output a digital “0”.

Assuming that when the first input signal was smaller than the first reference signal at the previous moment, the fourth register 400 output a digital "0", at the current moment, the signal Vref2 of the third input terminal of the first register 100 is greater than the signal of the fourth input terminal In2, Assuming that the first input signal is greater than the first reference signal at the current moment, if intersymbol interference makes the first input signal equal to or slightly smaller than the first reference signal, since the signal at the third input terminal is greater than the signal at the fourth input terminal, the first register 100 will still The number "1" is still output.

The working principle of the second register 200 to the fourth register 400 is the same as that of the first register 100 , and will not be repeated here.

The decision feedback equalization circuit shown in FIG. 11 is a first-order circuit, and in order to better eliminate intersymbol interference, a multi-stage circuit is usually used. FIG. 12 is a schematic diagram of the effect of the fourth-order decision feedback equalization circuit, and tap1 to tap4 represent the first-order decision feedback equalization circuit to the fourth-order decision feedback equalization circuit in sequence. As shown in Figure 12, the actual waveform of the first input signal under intersymbol interference is shown in curve 1. When the first input signal switches from high level to low level, the falling edge is relatively gentle, that is, there is an error in identifying the first input signal. signal is high. The fourth-order decision feedback equalization circuit can effectively eliminate intersymbol interference, so that the equivalent waveform of the first input signal input to the decision feedback equalization circuit is shown in curve 2, and the falling edge becomes steeper.

In one embodiment, the phase of the first clock signal of the first comparator 100 is 90° earlier than the phase of the second clock signal of the second comparator 200, and the phase of the first clock signal of the first comparator 100 is earlier than that of the third The phase of the second clock signal of the comparator 300 is 180° earlier, and the phase of the first clock signal of the first comparator 100 is 270° earlier than the phase of the second clock signal of the fourth comparator 400 .

In one embodiment, the voltage inversion times T _FB of the output terminals of the first comparator 100 to the fourth comparator 400 are all less than the time interval 1U1 between the first clock signal and the second clock signal, as shown in FIG. 13 , when When the inversion time of the output voltage of the fourth comparator 400 is less than 1U1, 1UI represents the time interval between the first clock signal and the second clock signal, which can ensure that when the clock signal of the first comparator 100 arrives, the fourth comparator 400 has output the comparison result stably, and the fourth comparator 400 keeps the comparison result, so that the first comparator 100 can eliminate the intersymbol interference according to the comparison result of the fourth comparator 400 .

In an embodiment, the decision feedback equalization circuit further includes four registers, which are marked as a first register 500 , a second register 600 , a third register 700 and a fourth register 800 in sequence. The input end of the first register 500 is connected with the two output ends of the first comparator 100, the input end of the second register 600 is connected with the two output ends of the second comparator 200, the input end of the third register 700 is connected with the third The two output terminals of the comparator 300 are connected, and the input terminal of the fourth register 800 is connected with the two output terminals of the fourth comparator 400 . The four registers are respectively used to store the comparison results output by four corresponding comparators, D0 is the result output by the first register 500, D90 is the result output by the second register 600, D180 is the result output by the third register 700, and D270 is The result output by the fourth register 800 .

In the above technical solution, the two output terminals of the fourth register are connected with the two input terminals of the first register, the two output terminals of the first register are connected with the two input terminals of the second register, and so on, forming In the decision feedback equalization circuit, the other two input terminals of the four registers receive the first input signal and the first reference signal. Under the control of the output terminal signals of the four registers, it can effectively eliminate the resulting in intersymbol interference.

Other embodiments of the present application will be readily apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the application, these modifications, uses or adaptations follow the general principles of the application and include common knowledge or conventional technical means in the technical field not disclosed in the application . The specification and examples are to be considered exemplary only, with a true scope and spirit of the application indicated by the following claims.

It should be understood that the present application is not limited to the precise constructions which have been described above and shown in the accompanying drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims (23)

1. A comparator, characterized in that it is provided with four inputs and two outputs, comprising:

the first input circuit is provided with two input ends and two output ends, the two input ends of the first input circuit are used as the input ends of the comparator, and the first input circuit is used for generating a first differential signal according to a first input signal and a first reference signal in a sampling stage;

the first positive feedback circuit is connected with two output ends of the first input circuit and used for accelerating the difference between the first differential signals;

the second input circuit is provided with two input ends and two output ends, the two input ends of the second input circuit are used as the input ends of the comparator, and the two output ends of the second input circuit are connected with the two output ends of the first input circuit and used for generating a second differential signal according to a second input signal and a second reference signal in a sampling stage;

the second positive feedback circuit is connected with the two output ends of the second input circuit and used for accelerating the difference between the second differential signals;

and the output circuit is provided with two input ends and two output ends, the two output ends are the output ends of the comparator, and the two input ends of the output circuit are connected with the two output ends of the first input circuit and used for amplifying and latching the voltage signal of the output end of the first input circuit and the voltage signal of the output end of the second input circuit in a regeneration stage so as to output a comparison result.

2. The comparator of claim 1, wherein the first positive feedback circuit comprises:

a first feedback unit, a control end of which is connected with a first output end of the first input circuit, and a first end of which is connected with a second output end of the first input circuit;

and the control end of the second feedback unit is connected with the second output end of the first input circuit, and the first end of the second feedback unit is connected with the first output end of the first input circuit.

3. The comparator of claim 2, wherein:

the first feedback unit includes: a first feedback transistor, a control terminal of which is a control terminal of the first feedback unit, and a first terminal of which is a first terminal of the first feedback unit;

the second feedback unit includes: and a control end of the second feedback transistor is a control end of the second feedback unit, and a first end of the second feedback transistor is a first end of the second feedback unit.

4. The comparator of claim 3, wherein the first input circuit comprises:

a first input transistor, a control terminal of which is used for receiving the first input signal, a first terminal of which is used as a first output terminal of the first input circuit, and a first terminal of which is connected with a first terminal of the first feedback transistor;

a second input transistor, a control terminal of which is used for receiving the first reference signal, a first terminal of which is used as a second output terminal of the first input circuit, and a first terminal of which is connected with a first terminal of the second feedback transistor;

and a control terminal of the third input transistor is used for receiving a clock signal, a first terminal of the third input transistor is connected with the second terminal of the first input transistor, the second terminal of the second input transistor, the second terminal of the first feedback transistor and the second terminal of the second feedback transistor, and a second terminal of the third input transistor is connected with a ground terminal or a power supply terminal.

5. The comparator of claim 1, wherein the second positive feedback circuit comprises:

a third feedback unit, a control end of which is connected with the first output end of the second input circuit, and a first end of which is connected with the second output end of the second input circuit;

and the control end of the fourth feedback unit is connected with the second output end of the second input circuit, and the first end of the fourth feedback unit is connected with the first output end of the second input circuit.

6. The comparator of claim 5, wherein:

the third feedback unit includes: a third feedback transistor, a control terminal of which is a control terminal of the third feedback unit, and a first terminal of which is a first terminal of the third feedback unit;

the fourth feedback unit includes: and a control end of the fourth feedback transistor is a control end of the fourth feedback unit, and a first end of the fourth feedback transistor is a first end of the fourth feedback unit.

7. The comparator of claim 6, wherein the second input circuit comprises:

a fourth input transistor, a control terminal of which is used for receiving the second reference signal, a first terminal of which is used as a first output terminal of the second input circuit, and a first terminal of which is connected with a first terminal of the third feedback transistor;

a fifth input transistor, a control terminal of which is used for receiving the second input signal, a first terminal of which is used as a second output terminal of the second input circuit, and a first terminal of which is connected with a first terminal of the fourth feedback transistor;

a sixth input transistor, having a control terminal for receiving a clock signal, a first terminal connected to the second terminal of the fourth input transistor, the second terminal of the fifth input transistor, the second terminal of the third feedback transistor, and the second terminal of the fourth feedback transistor, and a second terminal connected to a ground terminal or a power terminal.

8. The comparator as claimed in claim 7, wherein the first to fourth feedback transistors and the first to sixth input transistors are of the same type.

9. The comparator of claim 8, wherein:

the sizes of the first feedback transistor and the second feedback transistor are the same, the sizes of the first input transistor and the second input transistor are the same, and the size of the first feedback transistor is smaller than one half of the size of the first input transistor;

the sizes of the third feedback transistor and the fourth feedback transistor are the same, the sizes of the fourth input transistor and the fifth input transistor are the same, and the size of the third feedback transistor is smaller than one half of the size of the fourth input transistor;

the size of the fourth input transistor is less than one-half of the size of the first input transistor.

10. The comparator of claim 9, wherein:

when the first to fourth feedback transistors and the first to sixth input transistors are all N-type transistors, the drain electrode of the N-type transistor is a first end, and the grid electrode of the N-type transistor is a control end;

when the first to fourth feedback transistors and the first to sixth input transistors are P-type transistors, the drain of the P-type transistor is a first end, and the gate of the P-type transistor is a control end.

11. The comparator according to claim 1, further comprising:

a first reset circuit connected between a first output terminal of the first input circuit and a second output terminal of the first input circuit, for resetting a voltage of the first output terminal of the first input circuit and a voltage of the second output terminal of the first input circuit;

the second reset circuit is connected to the first output end of the output circuit and is used for resetting the voltage of the first output end of the output circuit;

and the third reset circuit is connected to the second output end of the output circuit and is used for resetting the voltage of the second output end of the output circuit.

12. The comparator of claim 11, wherein the first reset circuit comprises:

a first clocked transistor whose control terminal receives a clock signal and whose second terminal is connected to a first output terminal of the first input circuit;

a second clocked transistor having a control terminal receiving the clock signal, a second terminal connected to the second output terminal of the first input circuit, and a first terminal connected to the first terminal of the first clocked transistor;

the second reset circuit includes: a third clock transistor, the control end of which receives the clock signal, and the second end of which is connected with the first output end of the output circuit;

the third reset circuit includes: and a fourth clocked transistor having a control terminal receiving the clock signal and a second terminal connected to the second output terminal of the output circuit.

13. The comparator of claim 12, wherein the first, second, third, and fourth clocked transistors are of the same type.

14. The comparator of claim 1, wherein the output circuit comprises:

a first output transistor, a second end of which is a first input end of the output circuit;

a second output transistor, a second terminal of which is a second input terminal of the output circuit;

a third output transistor, a control end of which is connected with the control end of the first output transistor, a control end of which is also connected with a second end of a fourth output transistor, a second end of which is connected with the first end of the first output transistor, and a second end of which is used as a first output end of the output circuit;

and the control end of the fourth output transistor is connected with the control end of the second output transistor, the control end of the fourth output transistor is also connected with the second end of the third output transistor, the second end of the fourth output transistor is connected with the first end of the second output transistor, and the second end of the fourth output transistor is used as the second output end of the output circuit.

15. The comparator of claim 14, wherein:

the first output transistor and the second output transistor are both N-type transistors, the drain electrode of each N-type transistor is a first end, and the grid electrode of each N-type transistor is a control end;

the third output transistor and the fourth output transistor are both P-type transistors, the first clock-controlled transistor to the fourth clock-controlled transistor are all P-type transistors, the source electrode of each P-type transistor is a first end, and the grid electrode of each P-type transistor is a control end;

or

The first input transistor and the second output transistor are both P-type transistors, the drain electrode of each P-type transistor is a first end, and the grid electrode of each P-type transistor is a control end;

the third output transistor and the fourth output transistor are both N-type transistors, the first clock-controlled transistor to the fourth clock-controlled transistor are both N-type transistors, a source electrode of each N-type transistor is a first end, and a grid electrode of each N-type transistor is a control end.

16. The comparator of claim 1, wherein the second positive feedback circuit comprises at least one controllable positive feedback module; wherein, every controllable positive feedback module includes:

a control end of the third feedback unit is connected with the first output end of the second input circuit through the first switch, and a first end of the third feedback unit is connected with the second output end of the second input circuit;

and the control end of the fourth feedback unit is connected with the second output end of the second input circuit through a second switch, and the first end of the fourth feedback unit is connected with the first output end of the second input circuit.

17. The comparator of claim 16, wherein:

the third feedback unit includes: a third feedback transistor, a control terminal of which is a control terminal of the third feedback unit, and a first terminal of which is a first terminal of the third feedback unit;

the third feedback unit includes: and a control end of the third feedback transistor is a control end of the third feedback unit, and a first end of the third feedback transistor is a first end of the third feedback unit.

18. The comparator of claim 16, wherein:

the first switch comprises a first transmission gate controlled by a first enable signal generated according to the operating frequency of the comparator, the input common mode range of the comparator and a test mode signal;

the second switch includes a second transmission gate controlled by a second enable signal generated according to an operating frequency of the comparator, an input common mode range of the comparator, and a test mode signal.

19. The comparator as claimed in claim 16, wherein the control terminal of the third feedback unit is further connected to a ground terminal or a power terminal through a first zero switch; the control terminal of the fourth feedback unit is further connected to a ground terminal or a power supply terminal through a zeroth switch.

20. A decision feedback equalizer circuit comprising four comparators as claimed in any one of claims 1 to 19, labeled first, second, third and fourth comparators in sequence;

a first input end of the first comparator is used for receiving a first input signal, a second input end of the first comparator is used for receiving a first reference signal, a third input end of the first comparator is connected with a first output end of the fourth comparator, and a fourth input end of the first comparator is connected with a second output end of the fourth comparator;

a first input end of the second comparator is used for receiving a first input signal, a second input end of the second comparator is used for receiving a first reference signal, a third input end of the second comparator is connected with a first output end of the first comparator, and a fourth input end of the second comparator is connected with a second output end of the first comparator;

a first input end of the third comparator is used for receiving a first input signal, a second input end of the third comparator is used for receiving a first reference signal, a third input end of the third comparator is connected with a first output end of the second comparator, and a fourth input end of the third comparator is connected with a second output end of the second comparator;

the first input end of the fourth comparator is used for receiving the first input signal, the second input end of the fourth comparator is used for receiving the first reference signal, the third input end of the fourth comparator is connected with the first output end of the third comparator, and the fourth input end of the fourth comparator is connected with the second output end of the third comparator.

21. The decision feedback equalization circuit of claim 20 wherein:

the phase of the first clock signal of the first comparator is 90 ° earlier than the phase of the second clock signal of the second comparator;

the phase of the first clock signal of the first comparator is 180 ° earlier than the phase of the third clock signal of the third comparator;

the phase of the first clock signal of the first comparator is 270 ° earlier than the phase of the fourth clock signal of the fourth comparator.

22. The decision feedback equalization circuit of claim 21 wherein:

the voltage reversal time of the output end of the first comparator to the voltage reversal time of the output end of the fourth comparator is smaller than the time interval between the first clock signal and the second clock signal.

23. The decision feedback equalization circuit according to any of claims 20-22, further comprising: the four registers are sequentially marked as a first register, a second register, a third register and a fourth register;

the input end of the first register is connected with two output ends of the first comparator;

the input end of the second register is connected with two output ends of the second comparator;

the input end of the third register is connected with two output ends of the third comparator;

and the input end of the fourth register is connected with two output ends of the fourth comparator.

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