CN115421795B

CN115421795B - A multi-port storage acceleration system with software and hardware collaboration

Info

Publication number: CN115421795B
Application number: CN202211000470.9A
Authority: CN
Inventors: 郑俊飞; 吴睿振
Original assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Current assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Priority date: 2022-08-19
Filing date: 2022-08-19
Publication date: 2025-09-23
Anticipated expiration: 2042-08-19
Also published as: CN115421795A

Abstract

The present invention proposes a multi-port storage acceleration system with software and hardware collaboration, comprising: a host, an acceleration device, and a storage disk. The host is used to provide an operating environment for system software and is connected to the acceleration device through a virtual protocol host end inside the host. The acceleration device includes a hardware unit and a firmware unit. The hardware unit is used to provide a configuration register for the physical cable connection relationship between different types of controllers and device ports. The firmware unit is used to provide multiple storage disk controller drivers and storage protocols, and provides a virtual protocol device end interface that communicates with the virtual protocol host end inside the host, and is used to merge the storage protocol interfaces of different types of storage disks into a unified storage protocol interface. The storage disk is connected to a hardware bus hanging under the acceleration device port and serves as a terminal device to store data sent by the host, effectively improving the processor utilization rate, overall system performance and system portability in the multi-port storage acceleration system.

Description

Multi-port storage acceleration system with cooperation of software and hardware

Technical Field

The invention relates to the field of server storage, in particular to a multi-port storage acceleration system with cooperation of software and hardware.

Background

The method fully utilizes the parallelism of hardware circuits and the flexibility of software, divides service functions according to the characteristics of processing flows, and gives modules which are suitable for parallel execution and irrelevant to services to hardware implementation, thereby improving transmission performance and reducing CPU utilization rate, being suitable for serial execution, and giving modules with larger difference of different services to software implementation, thereby customizing the software flow according to actual services and designing the optimal software and hardware interfaces by reasonably dividing the software and hardware modules.

With the development of information technologies such as artificial intelligence, the internet of things and cloud computing, more and more intelligent hardware are emerging, the business data volume related to the intelligent hardware also rises exponentially, the storage capacity requirement of a data center server is also higher and higher, and in order to improve the data storage capacity of a system, researchers design a plurality of multi-port-based storage systems, so that parallel data transmission can be performed on a plurality of storage disks based on reading ports, and the data transmission performance of the system is improved, and the storage capacity of the system is also improved.

The current common design method of the multi-port memory system is that a plurality of hardware ports are designed on a main board of a host, or a plurality of ports are designed on an expansion board of the main board, then the expansion board is connected to the main board of the host, then a plurality of memory disks are respectively inserted into different ports, an open source operating system such as Linux is operated after the system is powered on, and then memory disk controller drivers of various interfaces and corresponding memory protocol software are loaded, so that the large-capacity data storage and the parallel data transmission are realized based on the plurality of memory ports.

This approach can effectively design a multi-port memory system, but still has the following problems:

The processor has higher utilization rate; because all storage disk drives and storage protocols are operated in the host operating system, when the types of storage interfaces integrated by the host motherboard are more, for example, an integrated AHCI (Advanced Host Controller Interface ) is a hardware interface standard based on PCI, in PCI BAR (address mapping register of configuration space, software maps the device custom register space to chip processor address space by writing the register, then software reads and writes the processor address to configure or read the device custom register), a local native queue is realized on the basis of the hardware read and write address of the processor, hardware conforming to the interface standard has a universal memory structure such as device control, status, command table and the like), PCIe (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, a high-speed serial computer expansion bus standard, a communication protocol of tree topology is realized at a hardware level, and the hardware interface is divided into a transaction layer, a data link layer, a physical layer, a link training layer, functions such as data transmission, flow control, power management, interrupt control and the like), the host needs to operate a corresponding bus drive and SATA (SERIAL ADVANCED Technology Attachment, a hardware driver interface, a storage protocol based on AHCI interface, a storage protocol (physical layer) and a memory interface (including a physical layer, a data link layer (Me) and a serial interface) are responsible for generating a serial interface (communication protocol) based on a read-write command layer, a serial interface (communication layer, a serial interface) is provided, a serial interface (a host interface is more reliable, a data link layer is more) is ensured, and a frame interface is generated by a host interface (a host interface is more interface layer, a host interface is required to be responsible for a host interface, and a host interface is required to be a host interface, and a host interface is required to be operated, and a host interface and can be configured and a host, commands such as refreshing, resetting, managing namespaces, and the like, ensuring high-performance data transmission in the form of a single management queue and a plurality of input/output queues), and the like, and when the data transmission capacity is large, the utilization rate of a host processor is high;

Because the data storage of the host occupies higher processor utilization rate, other software and hardware modules on the system such as network protocol stack package/unpacking, audio encoding and decoding, graphic image rendering, artificial intelligence algorithm, compression erasure algorithm and the like, the overall performance of the system is lower because of low data transmission or calculation performance caused by insufficient processor resources;

because of needing to develop different driving software for different storage interfaces, when the host computer is an embedded bare metal without an operating system, the complete storage controller driver and corresponding storage protocol need to be developed from scratch, the skill requirement on software developers is higher, the quick construction of a software system prototype is not facilitated, and the development iteration period of software and hardware products is increased;

In order to enable the same storage controller interface to be suitable for chip hardware of different manufacturers in a traditional mode, each manufacturer often adopts an open source operating system such as Linux and integrates respective drivers into the operating system, and the code multiplexing is facilitated, but the code is complicated and confused and is deeply coupled with the system call of the operating system;

Because different memory controller interfaces need to develop different controller drivers, and the controller interface configuration such as PCIe port width and the like can not be changed along with the scene of a user, when the hardware scheme is changed due to the change of the system requirement, the controller driver software needs to be correspondingly modified and memory protocol software is transplanted, so that the portability of the system software is poor;

Because the hardware aiming at a specific scene is not specially optimized, and a bottom half interrupt mechanism of an open source operating system such as Linux is generally adopted, the system interrupt processing flow is generally put into the bottom half interrupt execution of the system with lower execution speed, and when a device hot plug or a device abnormal state interrupt event occurs, the real-time performance of the system on the corresponding event processing is poor;

Because there is not a unified memory controller driving model, different controllers have different driving software, and the bus devices hung under different controllers are not numbered in a unified way, a specific network topology display interface is needed based on the driving of a specific controller, and when multiple types of interfaces are mixed, the system can not provide a unified mixed bus topology display interface;

Because the system has no reserved debugging and testing interface, when the system fails, the system has no effective means for positioning, a great deal of manpower and material resources are consumed for positioning the system problems, and the development and maintenance cost of the system is indirectly increased.

In order to solve the problems, the invention provides a multi-port storage acceleration system with cooperation of software and hardware, which solves part or all of the problems.

Disclosure of Invention

The invention innovatively provides a multi-port storage acceleration system with cooperation of software and hardware, which aims to solve the problems of high utilization rate of a processor, low overall performance of the system, high development difficulty of system application and poor portability of the system in the multi-port storage acceleration system caused by the prior art, and effectively improves the utilization rate of the processor, the overall performance of the system and the portability of the system in the multi-port storage acceleration system, and reduces the development difficulty of the system application.

The invention provides a multi-port storage acceleration system with cooperation of software and hardware, which comprises a host, acceleration equipment and a storage disk, wherein the host is used for providing an operation environment of system software and is in communication connection with the acceleration equipment through a virtual protocol host end in the host, the acceleration equipment comprises a hardware unit and a firmware unit, the hardware unit is used for providing configuration registers of physical cable connection relations of different types of controllers and equipment ports, the firmware unit is used for providing various storage disk controller driving and storage protocols and providing a virtual protocol equipment end interface communicated with the virtual protocol host end in the host, the storage protocol interfaces of different types of storage disks are combined into a unified storage protocol interface, and the storage disk is connected to a hardware bus hung under the acceleration equipment port and used as terminal equipment for storing data issued by the host.

Optionally, the system software comprises an application system, a configuration tool, a debugging tool and a virtual protocol host end, wherein the configuration tool is used for providing a configuration interface driven by the application system, a storage protocol and a storage disk controller, the debugging tool is used for providing a debugging and testing interface driven by the application system, the storage protocol and the storage disk controller, the application system is an application system facing different industries, and the virtual protocol host end is in communication connection with the virtual protocol device end in the firmware unit through a virtual protocol device end interface provided by the firmware unit and is used for transmitting host data to the storage disk.

Optionally, the hardware unit includes a controller, a crossbar, a port and a Flash chip, where the controller is configured to provide configuration space register access, link management, DMA transmission, status detection, and interrupt control for the bus device, the crossbar is configured to provide a configuration register interface for a physical cable connection relationship between the controller and the port, the port is a device connectable port of the hardware bus, different transmission performances are provided according to a width of a port cable, and the Flash chip is configured to store configuration parameters provided by a configuration tool.

The firmware unit comprises a physical layer driver, a virtual protocol device end, a storage disk controller driver and a storage protocol module, wherein the physical layer driver is used for configuring a cross switch in a hardware unit to realize connection of physical cables between a controller and device ports and construct device ports with different widths, the virtual protocol device end is used for packaging storage protocols of storage disks with different types into a unified storage interface and for transmitting data to the disk in batches at a later stage by using a cache space, the storage protocol module is used for providing a command interface of the storage disk based on the data storage protocol realized by a certain storage disk controller driver, the controller driver is used for driving a corresponding hardware controller to realize connection relation of the storage disk devices on a controller down-hanging bus by configuring a controller register, and bus addresses are allocated for the storage disk devices based on the connection relation of the storage disk devices on the controller down-hanging bus.

The physical layer driver further comprises a configuration module for reading or writing configuration parameters provided by the configuration tool through the physical layer driver from the Flash chip, a first initialization module for configuring the physical cable connection relationship between the controller and the port, a callback interface for registering the storage protocol module for notifying the storage protocol module when corresponding hardware events occur, and initializing all bus controllers.

The controller driver comprises a second initialization module, a disk control module, an interrupt processing module and a regulating module, wherein the second initialization module is used for detecting connection relations of all storage disk devices on a bus hung under the controller, notifying a storage protocol disk to be inserted into a port and start to read and write the storage disk when the insertion of the storage disk devices is detected, the disk control module is used for reading and writing a storage disk register and a port register connected with the storage disk, removing the disk from the bus, rescanning the disk to enable the disk to be hung on the bus, resetting the storage disk on the bus to enable the storage disk to be restored to a default state, the interrupt processing module is used for obtaining connection relations of hardware storage disk devices on the bus, reading and writing the storage disk register, resetting the storage disk, inquiring the working state of the storage disk, inquiring the state of hardware storage disk, simulating the behavior of the hardware storage disk, and testing the functions and performance of the driving software.

Further, the initializing of the first initializing module in the physical layer driver specifically includes:

reading module configuration parameters from a Flash chip;

configuring a cross switch according to module configuration parameters read from a Flash chip, and determining the connection relation between a controller and a port cable;

Initializing a controller descriptor table, wherein the index of an item in the controller descriptor table is a controller number, and each item in the controller descriptor table comprises a controller type, a device descriptor and a topology printing interface, wherein the device descriptor comprises whether the item is allocated to the controller, the device type, a bus address, a father device pointer, a child device linked list and a right brother pointer;

And controlling all controllers to initialize, and transmitting a controller descriptor pointer for recording the controller descriptor table information and a callback interface for storing the protocol module.

Further, in the initialization stage of the controller descriptor table, the device descriptor corresponding to each controller is configured to be allocated to the controller, the controller role, the bus address space reserved by the controller chip, the parent device pointer being empty, the child device linked list being empty, and the right sibling pointer being empty.

Optionally, the initializing of the second initializing module in the controller driver specifically includes:

Initializing a device descriptor table according to a controller descriptor pointer and a callback interface of a storage protocol module;

initializing a disk descriptor table according to the device descriptor table, wherein each table entry in the disk descriptor table comprises whether the table entry is allocated to a storage disk, a disk device pointer and a port device pointer;

Enumerating a bus topology with a depth-first algorithm;

And traversing the disk descriptor table, and for each non-empty table item of the port device pointer, executing a disk insertion callback interface, inputting a disk number, and recording the disk device descriptor pointer of the disk descriptor table information, wherein the disk device descriptor pointer is used for informing a storage protocol module to start reading and writing the disk.

Further, initializing the device descriptor table is specifically to configure each device descriptor to be unassigned to a storage disk, type 0, bus address 0, parent device pointer null, child device pointer null, right sibling pointer null.

Optionally, the disk descriptor table is initialized with a disk device pointer that is null and a port device pointer that is not assigned to the storage disk.

Optionally, enumerating the bus topology with a depth-first algorithm specifically includes:

fetching a device descriptor from a controller descriptor table pointed to by a controller descriptor pointer, fetching an address space of the whole bus from the device descriptor, and distributing bus addresses from the address space by all devices on the bus;

Distributing a device descriptor for each detected bus device from a device descriptor table, and updating the information such as the device type, the father device pointer, the child device pointer, the right brother pointer and the like of the device descriptor according to the bus topology;

allocating an entry for each port from a disk descriptor table, wherein the entry index is a disk number;

And allocating and enabling a hot plug interrupt vector number for each port, allocating an item for each port from a preset interrupt mapping table according to the hot plug interrupt vector number, establishing a mapping between the hot plug interrupt number and a disk number based on the hot plug interrupt vector number, and acquiring the hot plug disk number by inquiring the table when the subsequent interrupt occurs.

Further, the interrupt processing of the hot plug in the interrupt processing module specifically comprises interrupt processing of disk pull-out and interrupt processing of disk plug-in, wherein the interrupt processing of the disk pull-out specifically comprises:

determining an interrupt number of disk pull-out according to the hot plug interrupt vector number and the interrupt state register;

Searching a disc number corresponding to a disc-pulled interrupt number in a preset interrupt mapping table, and searching a corresponding disc descriptor in a disc descriptor table according to the searched disc number;

determining a corresponding disk device pointer and a port device pointer according to the disk descriptor, and setting a sub device chain of the device descriptor pointed by the port device pointer to be empty;

calling an execution disc pull-out callback interface, and transmitting a disc number and a disc equipment pointer;

if the link state machine enters the idle state, ending the interrupt processing of disk pulling, otherwise, calling a disk link abnormality callback interface and transmitting a disk number and a disk equipment pointer, informing a storage protocol module that the storage disk is abnormal, and ending the interrupt processing of disk pulling;

the interrupt processing of disk insertion specifically includes:

Waiting for a hardware link state machine to start to enter a working state; if the link state machine enters the working state, determining a corresponding disk device pointer and a port device pointer according to a disk descriptor, and configuring address mapping from a disk register to a processor in acceleration equipment according to equipment descriptor information pointed by the disk device pointer;

adding a disk device pointer to a child device linked list of port device descriptors;

And calling the execution disk to insert a callback interface and transmitting a disk device pointer to inform the storage protocol module to start reading and writing the disk.

Optionally, the read-write storage disk register and the port register to which the storage disk is connected specifically include:

acquiring a disk number and an offset address;

Searching a disk device pointer and a port device pointer corresponding to the disk number in a disk descriptor table;

Searching bus addresses corresponding to a storage disk register and a port register in the disk device descriptor and the port device descriptor respectively;

and reading and writing the corresponding storage disk register according to the bus address and the offset address corresponding to the storage disk register, and reading and writing the corresponding port register according to the bus address and the offset address corresponding to the port register.

Optionally, resetting the storage disk on the bus to a default state specifically includes:

acquiring a disk number;

Searching a disk device pointer corresponding to the disk number in a disk descriptor table, and a port device pointer corresponding to the disk number and storing a port connected with the disk;

And triggering and resetting the reset register corresponding to the storage disk at the bus address corresponding to the storage disk register, and triggering and resetting the reset register corresponding to the port connected with the storage disk at the bus address corresponding to the port register.

The technical scheme adopted by the invention comprises the following technical effects:

1. The multi-port storage acceleration system comprises a host, acceleration equipment and a storage disk, wherein the host is used for providing an operation environment of system software, the acceleration equipment comprises a hardware unit and a firmware unit, the hardware unit is used for providing configuration registers of physical cable connection relations of different types of controllers and equipment ports, the firmware unit is used for providing various storage disk controller driving and storage protocols and providing a virtual protocol equipment end interface communicated with a virtual protocol host end inside the host, the storage protocol interfaces of different types of storage disks are combined into a unified storage protocol interface, the storage disk is connected to a hardware bus hung under the acceleration equipment port and used as a terminal equipment for storing data issued by the host, the interfaces such as a unified controller driving frame, a virtual storage protocol interface, a hardware cross switch and the like are used for shielding the differences of the controllers and the storage protocols, the driving and protocol development quantity of the host is reduced, the problems that the utilization rate of a processor in the multi-port storage acceleration system is high, the overall performance of the system is low, the system application development difficulty is high, the system portability is poor, the utilization rate of the multi-port storage acceleration system is effectively improved, and the system portability is effectively improved, and the system application performance in the multi-port storage acceleration system is lowered.

2. In the technical scheme of the invention, all storage disk drives and storage protocols are operated on the acceleration equipment, when the types of storage interfaces integrated by the system are more, such as multiple controller interfaces integrated with AHCI, PCIe and the like, a host does not need to operate bus drives, SATA, NVMe and other storage protocols, and when the data transmission quantity is large, the utilization rate of a host processor is greatly reduced.

3. In the technical scheme of the invention, because the data storage of the host occupies lower processor utilization rate, other software and hardware modules of the system such as network protocol stack processing, audio encoding and decoding, graphic image rendering, artificial intelligence algorithm and compression erasure algorithm have more processor resources, so that the data transmission or calculation performance is correspondingly improved, and the overall performance of the system is higher.

4. In the technical scheme of the invention, because different driving software is not required to be developed for different storage controllers, when an operating system such as an embedded bare metal is not used by a host, application software is only required to be developed based on a simple virtual protocol interface, a complete controller driving and storage protocol is not required to be developed from scratch, the requirements on the skills of the developers are lower, and the rapid construction of a system prototype is facilitated.

5. According to the technical scheme, different driving software is not required to be developed for different storage controllers, and the connection relation between the controllers and the ports can also be modified along with a user scene, when the hardware scheme is changed due to the change of the system software requirement, configuration files corresponding to the application system, the storage protocol and the configuration interface driven by the storage disk controller are only required to be modified through the configuration tool, and the controller driving and the storage protocol software is not required to be modified, so that the portability of the software is good.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.

Drawings

For a clearer description of embodiments of the invention or of the solutions of the prior art, reference will be made to the accompanying drawings, which are used in the description of the embodiments or of the prior art, and it will be obvious to those skilled in the art that other drawings can be obtained from these without inventive labour.

FIG. 1 is a schematic diagram of a system according to an embodiment of the present invention;

FIG. 2 is a diagram of the functional use provided by the physical layer driver and the controller driver in a system according to an embodiment of the present invention;

FIG. 3 is a block diagram of a software and hardware design of an acceleration device in a system according to an embodiment of the present invention;

FIG. 4 is a flow chart of the physical layer initialization in a system according to an embodiment of the present invention;

FIG. 5 is a flow chart of the initialization of the controller in the system according to the embodiment of the invention;

FIG. 6 is a schematic diagram of a disc numbering scheme in a system according to an embodiment of the present invention;

FIG. 7 is a flowchart illustrating a process of a disk hot plug interrupt in a system according to an embodiment of the present invention;

fig. 8 is a flow chart of port/disk register read-write and disk reset in a system according to an embodiment of the present invention.

Detailed Description

In order to clearly illustrate the technical features of the present solution, the present invention will be described in detail below with reference to the following detailed description and the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different structures of the invention. In order to simplify the present disclosure, components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and processes are omitted so as to not unnecessarily obscure the present invention.

Example 1

As shown in FIG. 1, the invention provides a multi-port storage acceleration system with cooperative software and hardware, which divides the whole system into 3 layers of a host machine, an acceleration device and a storage disk according to functions, namely, the system comprises the host machine (S001), the acceleration device (S007), the storage disk (type 1 disk or type 2 disk), the host machine is used for providing an operation environment of system software (S002), the system is in communication connection with the acceleration device (S007) through a virtual protocol host end (S006) inside the host machine, the acceleration device (S007) comprises a hardware unit (S013) and a firmware unit (S008), the hardware unit (S013) is used for providing a configuration register of physical cable connection relation between different types of controllers (S014, the controller 1 or the controller 2) and the device port (S016), the firmware unit (S008) is used for providing various storage disk controller drivers (S012, the controller 1 driver or the controller 2 driver), the storage protocol (S011, the storage protocol 1 and the storage protocol 2) and providing a virtual protocol host end (S010) interface which is in communication with a virtual protocol host end inside the host machine, the hardware unit (S010) is used for connecting different types of controllers (S013) to the storage disk interface, namely, the storage disk interface (S016) is used as a unified storage disk interface, and the storage disk interface is connected to the storage device (S016).

The system software (S002) in the host (S001) comprises an application system (S005), a configuration tool (S003), a debugging tool (S004) and a virtual protocol host end (S006), wherein the configuration tool (S003) is used for providing configuration interfaces of the application system (S005), a storage protocol (S011, a storage protocol 1 and a storage protocol 2), a storage disk controller driver (S012, a controller driver 1 and a controller driver 2), the debugging tool (S004) is used for providing debugging and testing interfaces of the application system (S005), the storage protocol (S011), the storage protocol 1 and the storage protocol 2), the storage disk controller driver (S012, the controller driver 1 and the controller driver 2), the application system (S005) is an application system facing different industries, and the virtual protocol host end (S006) is in communication connection with the virtual protocol device end (S010) in the firmware unit (S008) through the virtual protocol device end (S010) interface provided by the firmware unit (S008) and is used for transmitting host (S001) data to the storage disk.

The hardware unit (S013) includes a controller (S014, a controller 1 and a controller 2), a crossbar switch (S015), a port (S016) and a Flash chip (not shown in fig. 1, as shown in fig. 3), where the controller (S014, the controller 1 and the controller 2) are used to provide configuration space register access, link management, DMA transfer, status detection and interrupt control of the bus device, and the controller in this embodiment is a controller (such as AHCI and PCIe) of a specific hardware bus, that is, a hardware adapter module, which is used to implement a data transfer protocol based on the specific bus, simplify a register configuration flow of the device on the hardware bus, reduce coding complexity of software, and does not need software to implement the bus transfer protocol again. The crossbar switch (S015) is used for providing a configuration register interface of a physical cable connection relation between the controller (S014) and the port (S016), the port (S016) is a device connectable port of a hardware bus and provides different transmission performances according to the width of a port cable, and the Flash chip is used for storing configuration parameters provided by a configuration tool (S003).

Specifically, the firmware unit (S008) includes a physical layer driver (S009), a virtual protocol device side (S010), a storage disk controller driver (S012, i.e., a controller 1 driver and a controller driver 2), a storage protocol module (S011, i.e., a storage protocol 1 and a storage protocol 2), and the physical layer driver (S009) is used to configure a crossbar switch (S015) in the hardware unit (S013), to implement connection of physical cables between the controller and the device ports, and to construct device ports (S016) with different widths; the virtual protocol device side (S010) is used for packaging the storage protocols of different types of storage disks into a unified storage interface, and transmitting data to the disks in batches at a later stage by using a buffer space to buffer the data, the storage protocol module ((S011, namely the storage protocol 1 and the storage protocol 2)) is used for providing a command interface of the storage disks based on the data storage protocol realized by a certain storage disk controller driver, the storage protocol module (storage protocol) in the embodiment is particularly a software adapter module and is used for packaging a software and hardware communication protocol based on a controller register, so that the simple device read-write interface and the reliability/security management of a link are realized, the coding complexity of application software is simplified, the controller driver (S012) is used for driving a corresponding hardware controller (S014), the connection relation of the storage disk devices on the controller (S014) down-hanging buses is realized based on the connection relation of the storage disk devices on the controller (S014) down-hanging buses, a bus address of a memory bus (S017) is allocated to the disk device.

Specifically, as shown in fig. 2-3, the physical layer driver includes a configuration module and a first initialization module, where the configuration module is configured to read or write configuration parameters provided by the configuration tool through the physical layer driver from the Flash chip, the first initialization module is configured to configure a physical cable connection relationship between the controller and the port, register a callback interface of the storage protocol module, notify the storage protocol module when a corresponding hardware event occurs, and initialize all bus controllers.

The controller driver comprises a second initialization module, a disk control module, an interrupt processing module and a regulating and testing module, wherein the second initialization module is used for detecting connection relation of all storage disk devices on a controller down-hanging bus, notifying a storage protocol disk that a port is inserted to start reading and writing the storage disk when the insertion of the storage disk device is detected, the disk control module is used for reading and writing a storage disk register and a port register connected with the storage disk, removing the disk from the bus, rescanning the disk to enable the disk to be hung on the bus, resetting the storage disk on the bus to enable the storage disk to be restored to a default state, the interrupt processing module is used for completing data transmission of the storage disk, hardware state abnormality and hot plug interrupt processing, and the regulating and testing module is used for obtaining connection relation of the hardware storage disk devices on the bus, reading and writing the storage disk register, resetting the storage disk, inquiring working state of the storage disk, inquiring the state of driving software, simulating the behavior of the hardware storage disk, and testing functions and performances of the driving software.

Specifically, the physical layer driver and the controller driver provide the following functions:

1. And (5) disc control. The method is further divided into:

(1) Disk/port register reads and writes. Reading and writing a register of a storage disk and a port connected with the storage disk;

(2) And (5) performing topology enumeration. The device connection relation on the down-hanging bus of the detection controller builds a bus topological graph, and allocates bus addresses for the devices (namely maps the device register space to the processor physical address space of the acceleration device);

(3) Disc removal/rescanning. Removing the disk from the bus, rescanning the disk to be attached to the bus;

(4) The disk is reset and the disk on the bus is reset to restore it to the default state.

2. Asynchronous processing. The method is further divided into:

(1) The disc transfer completion processing. The data transmission of the disk completes interrupt processing;

(2) Disk exception handling. Processing abnormal interrupt of hardware state of disk;

(3) And (5) performing hot plug processing on the disk. Hot plug interrupt handling of disks.

3. And (5) configuring a module. The method is further divided into:

and (5) writing configuration parameters. Writing module configuration parameters into the Flash chip;

and (5) reading configuration parameters. And reading module configuration parameters from the Flash chip.

4. And (5) module adjustment and measurement. The method is further divided into:

Topology acquisition. Acquiring a hardware equipment connection relation on a bus;

And (5) disc control. A read-write disk register, a reset disk, etc.;

and (5) inquiring the state. Inquiring the working state of the disk, inquiring the state of driving software such as global variable value, etc.;

Piling test. And simulating hardware behaviors such as disk hot plug and the like, and testing the functions and the performances of the driving software.

In order to realize the above functions, the acceleration device is implemented in two parts, namely, hardware (hardware unit) and software (firmware unit).

The hardware provides the following functions:

1. Flash chip. The method is further divided into parameter configuration, and a parameter configuration interface of acceleration equipment, such as a read-write EEPROM chip i2c bus interface, can be provided.

2. A controller and an underhung bus. The method is further divided into:

(1) And a crossbar providing a physical cable connection relationship configuration register interface for the controller and the device ports.

(2) Address mapping-mapping bus device internal space (e.g., PCIe configuration space, BAR space registers) registers to the accelerator device processor address space for the accelerator device firmware to access the bus device registers through the processor addresses.

(3) Link training, namely providing the functions of bus equipment discovery, bandwidth negotiation of equipment at two ends of a link, maintenance of a link state machine and the like.

(4) DMA transfer-providing DMA transfer configuration functionality between host memory and device internal memory.

(5) State detection, namely detecting the hardware state of the device on the bus, such as whether a link is abnormal, whether hot plug occurs or not, and the like.

(6) Interrupt control, namely triggering an interrupt signal when detecting that the link state is abnormal or the DMA transmission between the host and the device is completed.

The software provides the following functions:

1. physical layer driving. The method is further divided into:

(1) And (5) configuration. The method is further divided into parameter reading, namely reading configuration parameters of the module from the Flash chip, and parameter writing, namely writing the configuration parameters of the module into the Flash chip.

(2) Initializing. The method is further divided into:

1) Configuring a physical cable connection relationship between a controller and a port;

2) Registering a callback interface of a storage protocol, such as a callback interface for completing data transmission, abnormal equipment state and hot plug notification of equipment, and notifying the storage protocol when a corresponding hardware event occurs;

3) Initializing the controller, namely initializing all bus controllers;

2. a controller (e.g., PCIe RC) driver. The method is further divided into:

(1) Initializing. The method is further divided into:

1) And (5) performing topology enumeration. Detecting the connection relation of all devices on a lower hanging bus of the controller;

2) The disc insertion is notified. Notifying the storage protocol disk to be inserted into the port, and starting to read and write the disk;

An example flow of software and hardware module interactions is shown in FIG. 3:

the configuration tool writes module configuration parameters (such as user scene identifiers describing the physical cable connection relation of the controller and the port, and the like) into the Flash chip through a parameter writing interface provided by the physical layer driver;

The physical layer driving initialization module calls a parameter reading interface to read module configuration parameters from the Flash chip, and then registers callback interfaces of a storage protocol such as data transmission completion, equipment state abnormality, equipment hot plug notification and the like;

the physical layer driving initialization module calls a controller initialization interface to initialize all hardware bus controllers;

The controller initialization module calls a topology enumeration interface, accesses a device configuration space register through an address mapping mechanism, detects whether devices corresponding to a specific bus number and a device number exist or not, and accordingly confirms connection relations of the devices on the bus;

when the existence of the storage disk is detected, a storage protocol callback interface is called to inform the storage protocol that the disk can be read and written;

The hardware triggers an interrupt signal to inform firmware when detecting that the state of a disk link is abnormal, DMA transmission is completed and disk hot plug is performed, and the firmware calls a corresponding callback interface to inform a storage protocol after preprocessing (such as clearing an interrupt state register);

The dispatching tool invokes a dispatching interface (topology acquisition, disk control, state inquiry and piling test) to execute dispatching;

The debug interface calls a disk control interface (read/write port/disk register, disk removal/rescan/reset, etc.) to control the disk;

and the adjusting interface returns the execution result of the adjusting interface to the adjusting tool.

Further, as shown in fig. 4, the initialization of the first initialization module in the physical layer driver specifically includes:

Reading module (physical layer) configuration parameters from a Flash chip, wherein the specific configuration parameters comprise:

1. Scene identification, namely, identifying different user scenes, wherein each user scene represents a specific connection relationship between a controller and a port cable;

2. the controller bus address space, i.e., the bus address space of each controller, includes:

(1) Types of controllers such as AHCI, PCIe, etc.;

(2) Starting/ending address, namely the address space of the processor of the acceleration device, which can be mapped by all devices of the controller down-hanging bus;

(3) An address unit, namely a maximum processor address space which can be mapped by each device of the controller down-hanging bus;

Initializing a controller descriptor table, wherein the index of an item in the controller descriptor table is a controller number, each item in the controller descriptor table comprises a controller type (controller type such as AHCI, PCIe and the like), a device descriptor, a topology printing interface (topology printing interface of a specific controller), a device descriptor, wherein the device descriptor comprises whether the item is allocated to the controller (indicating whether the item is allocated to a certain controller), a device type (indicating a device role, including a type 1 controller (controller of a certain interface such as PCIe), a type 2 controller, a cascade device (devices for expanding the number of bus ports such as PCIE SWITCH), a port (devices for connecting discs), a type 1 disc (discs of a certain interface and corresponding to the type 1 controller), a type 2 disc, and a device can have multiple roles such as a root bus device of a direct connection disc which is both the controller and the port), a bus address (an accelerating device processor physical address which can be mapped to a device parent register, after establishing an address mapping, firmware can indirectly read and write the device register) a pointer of the device (bus line of the device), a pointer of the device on the upper level (bus of the same bus), a pointer of the device on the bus (bus of the same bus, a pointer of the device on the bus of the device of the same level (bus descriptor of the device of the bus side of the device of the bus descriptor of the device);

Specifically, the initializing of the second initializing module in the controller driver specifically includes:

Initializing a disk descriptor table from the device descriptor table, wherein each table entry in the disk descriptor table comprises whether the table entry has been allocated to a storage disk (indicating whether the table entry is allocated to a disk), a disk device pointer (a device descriptor pointer of the storage disk for recording disk device information, whether or not a disk is inserted into a port, whether or not the disk is allocated and filled with disk device descriptors, a device descriptor pointer of the disk is added to a child device linked list of the device descriptor of the port when the disk is inserted into the port, indicating that the disk is a child device of the port, or not added to the child device linked list), a port device pointer (a device descriptor pointer of a port to which the disk is connected, a device descriptor pointer of the port device information is recorded, and a port device pointer of a certain disk number corresponds to the table entry is empty, indicating that the port is not present, such as unconnected PCIE SWITCH);

Enumerating a bus topology with a depth-first algorithm;

Further, the disk descriptor table is initialized, specifically, the disk is not allocated to the storage disk, the disk device pointer is null, and the port device pointer is null.

Specifically, enumerating the bus topology with a depth-first algorithm specifically includes:

allocating an entry from the disk descriptor table for each port, wherein the entry index is a disk number, and the disk number rule is shown in fig. 6;

And allocating and enabling a hot plug interrupt vector number for each port, allocating an item for each port from a preset interrupt mapping table according to the hot plug interrupt vector number, establishing a mapping between the hot plug interrupt number (for example, the hot plug interrupt number can be the hot plug interrupt vector number plus an interrupt state register bit number) and a disk number based on the hot plug interrupt vector number, and acquiring the disk number of the hot plug by querying the table when the interrupt occurs subsequently.

Further, as shown in fig. 7, the interrupt processing of the hot plug in the interrupt processing module specifically includes interrupt processing of disk pull out and interrupt processing of disk insert, where the interrupt processing of disk pull out specifically includes:

Determining an interrupt number of disk pulling according to the hot plug interrupt vector number and the interrupt state register, wherein each bit in the interrupt state register represents that one port disk is pulled out or inserted, the interrupt number can be the interrupt vector number plus the interrupt state register bit number, namely, the interrupt number can be the sum of the interrupt vector number and the interrupt state register bit number, and the bit numbers of the interrupt vector number and the interrupt state register bit number can be directly added, and the invention is not limited in this regard;

searching a disc number (disc_num) corresponding to a disc-pulled-out interrupt number in a preset interrupt mapping table, and searching a corresponding disc descriptor in a disc descriptor table according to the searched disc number;

Determining a corresponding disk device pointer and a port device pointer according to the disk descriptor, and setting a sub device chain of the device descriptor pointed by the port device pointer to be empty (namely, indicating that the port has no external disk);

calling an executing disc pull-out callback interface, inputting a disc number and a disc equipment pointer, and informing a storage protocol to stop reading and writing the disc;

The method comprises the steps that a hardware link state machine is waited to enter an idle state, wherein the hardware link state machine is related to a controller, for example, a PCIe controller can configure a space register through a query port, if the link state machine enters the idle state, the interrupt processing of disk pulling is ended, otherwise, a disk link abnormal callback interface is called and a disk number and a disk equipment pointer are transmitted, a storage protocol module is informed that the storage disk is abnormal, and the interrupt processing of disk pulling is ended;

the interrupt processing of disk insertion specifically includes:

If the link state machine enters the working state, determining a corresponding disk device pointer and a port device pointer according to a disk descriptor, and configuring address mapping from a disk register to a processor in acceleration equipment according to the device descriptor information pointed by the disk device pointer (according to the device descriptor information pointed by the disk device pointer, such as a bus address, etc., an address mapping register from a write bus address to a disk configuration space, such as a PCIe BAR register, realizes mapping of a disk custom register space to a processor address space of acceleration equipment, and firmware can read and write the disk custom register through the processor address space subsequently);

adding a disk device pointer to a child device linked list of the port device descriptor, i.e., a child device that indicates that the disk is a port;

Further, as shown in fig. 8, the read/write disk register and the port register to which the disk is connected include:

acquiring a disk number and an offset address;

Resetting a storage disk on a bus to restore the storage disk to a default state specifically includes:

acquiring a disk number;

The multi-port storage acceleration system comprises a host, acceleration equipment and a storage disk, wherein the host is used for providing an operation environment of system software, the acceleration equipment comprises a hardware unit and a firmware unit, the hardware unit is used for providing configuration registers of physical cable connection relations of different types of controllers and equipment ports, the firmware unit is used for providing various storage disk controller driving and storage protocols and providing a virtual protocol equipment end interface communicated with a virtual protocol host end inside the host, the storage protocol interfaces of different types of storage disks are combined into a unified storage protocol interface, the storage disk is connected to a hardware bus hung under the acceleration equipment port and used as a terminal equipment for storing data issued by the host, the interfaces such as a unified controller driving frame, a virtual storage protocol interface, a hardware cross switch and the like are used for shielding the differences of the controllers and the storage protocols, the driving and protocol development quantity of the host is reduced, the problems that the utilization rate of a processor in the multi-port storage acceleration system is high, the overall performance of the system is low, the system application development difficulty is high, the system portability is poor, the utilization rate of the multi-port storage acceleration system is effectively improved, and the system portability is effectively improved, and the system application performance in the multi-port storage acceleration system is lowered.

In the technical scheme of the invention, all storage disk drives and storage protocols are operated on the acceleration equipment, when the types of storage interfaces integrated by the system are more, such as multiple controller interfaces integrated with AHCI, PCIe and the like, a host does not need to operate bus drives, SATA, NVMe and other storage protocols, and when the data transmission quantity is large, the utilization rate of a host processor is greatly reduced.

In the technical scheme of the invention, because the data storage of the host occupies lower processor utilization rate, other software and hardware modules of the system such as network protocol stack processing, audio encoding and decoding, graphic image rendering, artificial intelligence algorithm and compression erasure algorithm have more processor resources, so that the data transmission or calculation performance is correspondingly improved, and the overall performance of the system is higher.

In the technical scheme of the invention, because different driving software is not required to be developed for different storage controllers, when an operating system such as an embedded bare metal is not used by a host, application software is only required to be developed based on a simple virtual protocol interface, a complete controller driving and storage protocol is not required to be developed from scratch, the requirements on the skills of the developers are lower, and the rapid construction of a system prototype is facilitated.

According to the technical scheme, different driving software is not required to be developed for different storage controllers, and the connection relation between the controllers and the ports can also be modified along with a user scene, when the hardware scheme is changed due to the change of the system software requirement, configuration files corresponding to the application system, the storage protocol and the configuration interface driven by the storage disk controller are only required to be modified through the configuration tool, and the controller driving and the storage protocol software is not required to be modified, so that the portability of the software is good.

According to the technical scheme of the invention, the controller drivers of the same class are not required to be integrated into the same operating system such as Linux (firmware unit in acceleration equipment) in order to adapt the controller drivers of different factories, and the controller drivers are developed based on a specific programming language such as GNU C and do not depend on any operating system interface, so that codes are concise and decoupled from the operating system, and therefore, the software redundancy is lower.

In the technical scheme of the invention, as a bottom half interrupt mechanism of an open source operating system such as Linux is not adopted, the system interrupt processing flow is not put into the system bottom half interrupt with lower execution speed, but is executed by an interrupt processing module in a controller drive, when hot plug or abnormal equipment state interrupt occurs, the interrupt processing module can rapidly process the interrupt such as disk read-write completion/hot plug/abnormal link and the like by inquiring an interrupt mapping table, a disk descriptor table based on the interrupt mapping table, a disk descriptor table, an equipment descriptor table, a disk read-write completion/hot plug/abnormal link callback interface and the unified disk number of various controller buses, so that the real-time performance of the system interrupt processing is better.

In the technical scheme of the invention, as different types of controllers have a unified controller driving framework (controller driving internal function modules), and devices of all buses are uniformly numbered, the topology display interface of a specific controller is uniformly registered in the controller descriptor corresponding to the specific controller, and when multiple types of controllers are mixed, the bus topology of all the controllers can be displayed by using the uniform interface.

In the technical scheme of the invention, because the system is reserved with the debugging and testing interfaces, the debugging tool is arranged in the host, when the system fails, the system failure problem positioning can be realized, a great amount of manpower and material resources are not consumed in the system failure positioning, and the system development and maintenance cost is indirectly reduced.

While the foregoing description of the embodiments of the present invention has been presented in conjunction with the drawings, it should be understood that it is not intended to limit the scope of the invention, but rather, it is intended to cover all modifications or variations within the scope of the invention as defined by the claims of the present invention.

Claims

1. The multi-port storage acceleration system with the cooperation of software and hardware is characterized by comprising a host, acceleration equipment and a storage disk, wherein the host is used for providing an operating environment of system software and is in communication connection with the acceleration equipment through a virtual protocol host end in the host; the acceleration device comprises a hardware unit and a firmware unit, wherein the hardware unit is used for providing physical cable connection relation of different types of controllers and device ports, the firmware unit is used for providing various storage disk controller drivers and storage protocols, providing a virtual protocol device end interface communicated with a virtual protocol host end inside a host, combining the storage protocol interfaces of the different types of storage disks into a unified storage protocol interface, the storage disk is connected to a hardware bus hung under the acceleration device port and used as terminal equipment for storing data issued by the host, the firmware unit comprises a physical layer driver, a virtual protocol device end, a storage disk controller driver and a storage protocol module, the physical layer driver is used for configuring a cross switch in the hardware unit, realizing connection of physical cables between the controllers and the device ports, constructing device ports with different widths, the virtual protocol device end is used for packaging the storage protocols of the different types of storage disks into the unified storage interface and buffering data by using a buffering space, the storage protocol module is used for storing data which are hung on the disk in a later stage in a batch mode, the storage protocol module is used for storing the data which is realized on the basis of a certain storage disk controller driver, the physical layer driver is used for providing data which is hung on the controller, the controller is used for realizing the connection relation of the physical cable connection of the physical cable, the physical cable is used for realizing the hardware connection of the controller, the hardware unit is connected with the device port, the physical cable is connected with the device is connected with the hardware unit, and is connected with the device port, and is connected with the device and used for realizing the control device and has functions, and is connected with the device and is connected with. And distributing bus addresses for the storage disk devices based on the connection relation of the storage disk devices on the controller down-hanging bus.

2. The multi-port storage acceleration system with cooperation of software and hardware according to claim 1, wherein the system software comprises an application system, a configuration tool, a debugging tool and a virtual protocol host end, the configuration tool is used for providing configuration interfaces driven by the application system, a storage protocol and a storage disk controller, the debugging tool is used for providing debugging and testing interfaces driven by the application system, the storage protocol and the storage disk controller, the application system is an application system facing different industries, and the virtual protocol host end is in communication connection with the virtual protocol device end in the firmware unit through a virtual protocol device end interface provided by the firmware unit and used for transmitting host data to the storage disk.

3. The multi-port memory acceleration system of claim 1, wherein the hardware unit comprises a controller, a crossbar, a port and a Flash chip, the controller is used for providing configuration space register access, link management, DMA transmission, state detection and interrupt control of a bus device, the crossbar is used for providing a configuration register interface of a physical cable connection relationship between the controller and the port, the port is a device connectable port of a hardware bus and provides different transmission performances according to the width of a port cable, and the Flash chip is used for storing configuration parameters provided by a configuration tool.

4. The multi-port memory acceleration system of claim 1, wherein the physical layer driver comprises a configuration module and a first initialization module, wherein the configuration module is used for reading or writing configuration parameters provided by the configuration tool through the physical layer driver from the Flash chip, the first initialization module is used for configuring a physical cable connection relationship between the controller and the port, registering a callback interface of the memory protocol module, notifying the memory protocol module when a corresponding hardware event occurs, and initializing all bus controllers.

5. The multi-port memory acceleration system with cooperation of software and hardware according to claim 1, wherein the controller driver comprises a second initialization module, a disk control module, an interrupt processing module and a debugging module, wherein the second initialization module is used for detecting connection relations of all memory disk devices on a down-hanging bus of the controller, notifying that a memory protocol disk is inserted into a port to start reading and writing the memory disk when the insertion of the memory disk devices is detected, the disk control module is used for reading and writing a memory disk register and a port register connected with the memory disk, removing the disk from the bus and rescanning the disk to enable the disk to be hung on the bus, resetting the memory disk on the bus to enable the memory disk to be restored to a default state, and the interrupt processing module is used for completing data transmission of the memory disk, hardware state abnormality and hot plug interrupt processing, and the debugging module is used for obtaining connection relations of the hardware memory disk devices on the bus, reading and writing the memory disk register and resetting the memory disk, inquiring the working state of the memory disk and the state of driving software, simulating the behavior of the hardware memory disk and testing functions and performance of the driving software.

6. The system for acceleration of multi-port memory with coordination of software and hardware according to claim 5, wherein the initializing of the first initializing module in the physical layer driver specifically comprises:

reading module configuration parameters from a Flash chip;

7. The multi-port memory acceleration system of claim 6, wherein the device descriptor table is initialized to configure the device descriptor for each controller to be assigned to the controller, the role of the controller, the reserved bus address space of the controller chip, the parent device pointer being empty, the child device linked list being empty, and the right sibling pointer being empty.

8. The system for acceleration of multi-port memory with coordination of software and hardware according to claim 5, wherein the initializing of the second initializing module in the controller driver specifically comprises:

Enumerating a bus topology with a depth-first algorithm;

9. The multi-port memory acceleration system of claim 8, wherein initializing the device descriptor table is characterized by configuring each device descriptor to be unassigned to a memory disk, to be 0 in type, to have a bus address of 0, to have a parent pointer null, to have a child pointer null, and to have a right sibling pointer null.

10. The system of claim 8, wherein the initialization disk descriptor table is a disk that is not assigned to a disk, the disk device pointer is null, and the port device pointer is null.

11. The system of claim 8, wherein enumerating the bus topology with a depth-first algorithm comprises:

12. The multi-port memory acceleration system of claim 11, wherein the interrupt handling of hot plug in the interrupt handling module comprises a disk unplugged interrupt handling and a disk plugged interrupt handling, wherein the disk unplugged interrupt handling comprises:

the interrupt processing of disk insertion specifically includes:

13. The system of claim 11, wherein the read/write disk registers and the port registers to which the disk is connected comprise:

acquiring a disk number and an offset address;

14. The multi-port memory acceleration system of claim 11, the method is characterized in that resetting the storage disk on the bus to restore the storage disk to a default state specifically comprises the following steps:

acquiring a disk number;