CN115458398A - Semiconductor structure and its preparation method - Google Patents

Abstract

The present disclosure relates to a semiconductor structure and a method of fabricating the same. A method for fabricating a semiconductor structure, comprising the steps of: providing a substrate, wherein a sacrificial oxide layer is formed on the upper surface of the substrate, a shallow trench isolation structure is formed in the substrate, the shallow trench isolation structure extends upwards from the inside of the substrate and is provided with a protruding part protruding out of the substrate; the shallow trench isolation structure isolates a plurality of active regions arranged at intervals in the substrate; removing the sacrificial oxide layer; forming a dielectric layer on the side wall of the protrusion part; forming a gate oxide layer, wherein the gate oxide layer covers the upper surface of the active region; and forming a gate material layer, wherein the gate material layer covers the upper surface of the gate oxide layer, the exposed surface of the dielectric layer and the top surface of the bulge. According to the preparation method of the semiconductor structure, the dielectric layer is formed on the side wall of the protruding part, so that the thickness of the gate oxide layer on the corner of the active region is effectively increased, the problem of non-uniformity of the gate oxide layer is solved, the reliability of a semiconductor device is improved, and the failure rate of a chip is reduced.

Description

Semiconductor structure and its preparation method

technical field

The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof.

Background technique

With the continuous development of semiconductor processing technology, semiconductor devices are being used more and more in the fields of electronics and communications due to their smaller size, higher performance, and higher conversion efficiency.

However, with the reduction in the size of semiconductor devices, the reliability of the gate oxide layer has always been the focus and difficulty in the development of various chip process platforms. In the manufacturing process of small-sized semiconductor devices, when removing the sacrificial oxide layer, it is easy to cause the corners of the shallow trench isolation structure to be recessed, thus resulting in a thinner gate oxide layer formed on the corners of the active region. During reliability testing of semiconductor devices, the gate oxide layer on the corner of the active region is easily broken down.

Therefore, how to increase the thickness of the gate oxide layer on the corners of the active region to solve the problem of uneven gate oxide layer and improve the reliability of semiconductor devices is an urgent problem to be solved.

Contents of the invention

Based on this, it is necessary to provide a semiconductor structure and its preparation method to effectively increase the thickness of the gate oxide layer at the corner of the active region, thereby solving the problem of uneven gate oxide layer, and further improving the reliability of the semiconductor device.

An embodiment of the present application provides a method for preparing a semiconductor structure, including the following steps: providing a substrate, a sacrificial oxide layer is formed on the upper surface of the substrate, a shallow trench isolation structure is formed in the substrate, and the shallow trench isolation structure is formed from The substrate extends upwards and has a protruding part protruding from the substrate; the shallow trench isolation structure isolates a plurality of active regions arranged at intervals in the substrate; the sacrificial oxide layer is removed; on the side of the protruding part The wall forms a dielectric layer; forms a gate oxide layer, and the gate oxide layer covers the upper surface of the active region; forms a gate material layer, and the gate material layer covers the upper surface of the gate oxide layer, the exposed surface of the dielectric layer and the top of the protrusion noodle.

In the method for preparing the above semiconductor structure, after the sacrificial oxide layer is removed, a dielectric layer is formed on the sidewall of the protruding portion of the shallow trench isolation structure protruding from the substrate, so as to fill the protruding portion caused by the process of removing the sacrificial oxide layer Depression in the side wall. After the dielectric layer is formed on the sidewall of the protruding part, a gate oxide layer is formed on the upper surface of the active region to effectively increase the thickness of the gate oxide layer on the corner of the active region, thereby solving the problem of uneven gate oxide layer, and further improving Improve the reliability of semiconductor devices and reduce the failure rate of chips.

Optionally, after removing the sacrificial oxide layer, a groove is formed on the lower sidewall of the protrusion; the dielectric layer covers the sidewall of the protrusion and fills up the groove.

In the preparation method of the above semiconductor structure, a dielectric layer is formed to cover and fill the groove of the lower side wall of the protruding part, so as to prevent the gate oxide layer formed on the corner of the active region from being too thin, thereby solving the problem of uneven gate oxide layer.

Optionally, forming the dielectric layer on the sidewall of the protrusion includes: forming a first dielectric material layer, the first dielectric material layer covering the upper surface of the active region, the sidewall of the protrusion and the top surface of the protrusion; Etching and thinning the first dielectric material layer to form a second dielectric material layer; removing the second dielectric material layer located on the upper surface of the active region and the top surface of the protrusion, and retaining the second dielectric material on the side wall of the protrusion The layer is the medium layer.

Optionally, a dry etching process is used to etch and thin the first dielectric material layer; a wet etching process is used to remove the second dielectric material layer located on the upper surface of the substrate and the top surface of the protrusion.

Optionally, in the process of etching and thinning the first dielectric material layer, the thickness of the first dielectric material layer removed by etching is greater than the thickness of the second dielectric material layer.

Optionally, the thickness range of the first dielectric material layer includes: 500 angstroms to 550 angstroms; the thickness range of the second dielectric material layer includes: 100 angstroms to 120 angstroms.

Optionally, the thickness of the second dielectric material layer located on the sidewall of the protrusion is greater than the thickness of the second dielectric material layer located on the upper surface of the substrate and the top surface of the protrusion.

Optionally, a wet etching process is used to remove the sacrificial oxide layer.

Optionally, the dielectric layer is in contact with the gate oxide layer.

Based on the same inventive concept, an embodiment of the present application also provides a semiconductor structure, including: a substrate with a shallow trench isolation structure inside the substrate, the shallow trench isolation structure extends upward from the substrate, and has a The protruding part on the bottom; the shallow trench isolation structure isolates a plurality of active regions arranged at intervals in the substrate; the dielectric layer, the dielectric layer covers the sidewall of the protruding part; the gate oxide layer, the gate oxide layer covers The upper surface of the source region; the gate material layer, the gate material layer covers the upper surface of the gate oxide layer, the exposed surface of the dielectric layer and the top surface of the protrusion.

In the above-mentioned semiconductor structure, the dielectric layer covers and fills the groove of the sidewall of the protruding part of the shallow trench isolation structure protruding from the substrate, so that the problem of thinner gate oxide layer covering the corner of the active region can be effectively avoided , to effectively increase the thickness of the gate oxide layer on the corner of the active region, thereby solving the problem of uneven gate oxide layer, thereby improving the reliability of semiconductor devices and reducing the failure rate of chips.

Optionally, the dielectric layer is in contact with the gate oxide layer.

Optionally, the thickness range of the dielectric layer includes: 100 angstroms-120 angstroms.

Optionally, the dielectric layer includes a silicon oxide layer.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those skilled in the art, other drawings can also be obtained based on these drawings without creative effort.

Fig. 1 is the electron microscope picture of a kind of semiconductor structure provided in the prior art;

FIG. 2 is a flowchart of a method for preparing a semiconductor structure provided in an embodiment of the present application;

3 is a schematic cross-sectional structure diagram of a structure obtained after providing a substrate in a semiconductor structure preparation method provided in an embodiment of the present application;

4 is a schematic cross-sectional structure diagram of a structure obtained after removing a sacrificial oxide layer in a method for preparing a semiconductor structure provided in an embodiment of the present application;

5 is a flow chart of a method for forming a dielectric layer on the sidewall of a protrusion in a method for preparing a semiconductor structure provided in an embodiment of the present application;

6 is a schematic cross-sectional structure diagram of a structure obtained after forming a first dielectric material layer in a method for preparing a semiconductor structure provided in an embodiment of the present application;

7 is a schematic cross-sectional structure diagram of a structure obtained after forming a second dielectric material layer in the semiconductor structure preparation method provided in an embodiment of the present application;

8 is a schematic cross-sectional structure diagram of a structure obtained after forming a first gate oxide material layer in a semiconductor device manufacturing method provided in an embodiment of the present application;

9 is a schematic cross-sectional structure diagram of a structure obtained after forming a dielectric layer in a semiconductor device manufacturing method provided in an embodiment of the present application;

FIG. 10 is a schematic cross-sectional structure diagram of a structure obtained after forming a gate material layer in a semiconductor device manufacturing method provided in an embodiment of the present application.

Explanation of reference signs:

1-substrate; 10-active region; 11-shallow trench isolation structure; 12-groove; sacrificial oxide layer 20;

300A—first dielectric material layer; 300B—second dielectric material layer; 30—dielectric layer; 40—gate oxide layer; 500—gate material layer.

detailed description

In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the related drawings. Embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the present disclosure will be thorough and complete.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms used herein in the description of the present disclosure are for the purpose of describing specific embodiments only, and are not intended to limit the present disclosure.

It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to" or "coupled to" another element or layer, it can be directly on the other element or layer. A layer may be on, adjacent to, connected to, or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. Floor. It will be understood that, although the terms first, second, third etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial terms such as "below", "below", "below", "under", "on", "above", etc., in This may be used to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" can encompass both an orientation of above and below. In addition, the device may be otherwise oriented (eg, rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

When used herein, the singular forms "a", "an" and "the/the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "consists of" and/or "comprising" are used in this specification, the presence of said features, integers, steps, operations, elements and/or parts can be determined, but does not exclude one or more other The presence or addition of features, integers, steps, operations, elements, parts and/or groups. Also, when used herein, the term "and/or" includes any and all combinations of the associated listed items.

As used herein, the "deposition" process includes, but is not limited to, physical vapor deposition (Physical Vapor Deposition, referred to as PVD), chemical vapor deposition (Chemical Vapor Deposition, referred to as CVD) or atomic layer deposition (Atomic Layer Deposition, referred to as ALD).

Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention such that variations in the shapes shown as a result, for example, of manufacturing techniques and/or tolerances are contemplated. Thus, embodiments of the invention should not be limited to the particular shapes of regions shown herein but are to include deviations in shapes that result, for example, from manufacturing techniques. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation was performed. Thus, the regions shown in the figures are schematic in nature and their shapes do not indicate the actual shape of a region of a device and are not intended to limit the scope of the invention.

With the continuous development of semiconductor processing technology, semiconductor devices are being used more and more in the fields of electronics and communications due to their smaller size, higher performance, and higher conversion efficiency.

However, with the reduction in the size of semiconductor devices, the reliability of the gate oxide layer has always been the focus and difficulty in the development of various chip process platforms. In the manufacturing process of small-sized semiconductor devices, when removing the sacrificial oxide layer, it is easy to cause the corners of the shallow trench isolation structure to be recessed, thus resulting in a thinner gate oxide layer formed on the corners of the active region. During reliability testing of semiconductor devices, the gate oxide layer on the corner of the active region is easily broken down.

Taking the thickness of the gate oxide layer as 0.15 μm as an example, as shown in Figure 1, the wet etching process after the sacrificial oxide layer is likely to cause depressions at the corners of the shallow trench isolation structure, resulting in the formation of gates at the corners of the active region. The oxide layer is thinner, only 72.8 angstroms, while the gate oxide layer at the center of the active area is 133.5 angstroms, that is, the gate oxide layer formed on the corner of the active area is 60 angstroms less than the center position, so the reliability test process The gate oxide layer formed on the corner of the active area becomes the easiest point of breakdown.

Therefore, how to increase the thickness of the gate oxide layer on the corners of the active region to solve the problem of uneven gate oxide layer and improve the reliability of semiconductor devices is an urgent problem to be solved.

In view of the above-mentioned deficiencies in the prior art, the purpose of this application is to provide a semiconductor structure and its preparation method, which aims to effectively increase the thickness of the gate oxide layer on the corner of the active region, thereby solving the problem of uneven gate oxide layer, and further improving the semiconductor structure. device reliability.

Please refer to FIG. 2, the embodiment of the present application provides a method for preparing a semiconductor structure, including the following steps:

S10: Provide a substrate, a sacrificial oxide layer is formed on the upper surface of the substrate, a shallow trench isolation structure is formed in the substrate, the shallow trench isolation structure extends upward from the substrate, and has a protrusion protruding from the substrate part; the shallow trench isolation structure isolates a plurality of active regions arranged at intervals in the substrate.

S20: removing the sacrificial oxide layer.

S30: forming a dielectric layer on the sidewall of the protruding portion.

S40: forming a gate oxide layer, the gate oxide layer covering the upper surface of the active region.

S50: forming a gate material layer, the gate material layer covering the upper surface of the gate oxide layer, the exposed surface of the dielectric layer and the top surface of the protrusion.

In the method for preparing the above semiconductor structure, after the sacrificial oxide layer is removed, a dielectric layer is formed on the sidewall of the protruding portion of the shallow trench isolation structure protruding from the substrate, so as to fill the protruding portion caused by the process of removing the sacrificial oxide layer Depression in the side wall. After the dielectric layer is formed on the sidewall of the protruding part, a gate oxide layer is formed on the upper surface of the active region to effectively increase the thickness of the gate oxide layer on the corner of the active region, thereby solving the problem of uneven gate oxide layer, and further improving Improve the reliability of semiconductor devices and reduce the failure rate of chips.

The semiconductor structure manufacturing method provided by the embodiment of the present application will be described in detail below with reference to FIG. 3 to FIG. 10 .

In step S10, referring to step S10 in FIG. 2 and FIG. 3, a substrate 1 is provided, a sacrificial oxide layer 20 is formed on the upper surface of the substrate 1, a shallow trench isolation structure 11 is formed in the substrate 1, and the shallow trench The trench isolation structure 11 extends upward from the substrate 1 and has a protruding portion protruding from the substrate 1 ; the shallow trench isolation structure 11 isolates a plurality of active regions 10 arranged at intervals in the substrate 10 .

In some examples, the substrate 1 may include, but not limited to, a silicon substrate. Of course, in other examples, the material of the substrate 1 can also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate 10 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. end.

Specifically, taking the substrate 1 as a silicon substrate as an example, a silicon oxide layer may be formed on the upper surface of the substrate 1 as the sacrificial oxide layer 20 by using but not limited to a thermal oxidation process.

Specifically, the thickness of the sacrificial oxide layer 20 can be set according to actual needs.

In an optional embodiment, before the sacrificial oxide layer 20 is formed on the upper surface of the substrate 1, a step of cleaning the substrate 1 may also be included. By cleaning, the impurities on the surface of the substrate 1 can be removed to avoid damage to the subsequent The process has an impact, thereby ensuring the performance of the device.

Specifically, the substrate 1 may be cleaned with a cleaning solution, and the substrate 1 may be placed in a cleaning tank storing the cleaning solution for cleaning; of course, the substrate 1 may also be cleaned by spraying. The specific cleaning solution and cleaning process used to clean the substrate 1 are known to those skilled in the art, and will not be repeated here.

It should be noted that after the substrate 1 is cleaned, a step of drying the substrate 1 is also included. The method of drying the substrate 1 is well known to those skilled in the art and will not be repeated here.

In step S20 , referring to step S20 in FIG. 2 and FIG. 4 , the sacrificial oxide layer 20 is removed.

Optionally, the sacrificial oxide layer 20 is removed using a wet etching process.

In some examples, after removing the sacrificial oxide layer 20 , the lower sidewall of the protrusion is formed with the groove 12 .

In step S30 , referring to step S30 in FIG. 2 and FIGS. 4 to 9 , a dielectric layer 30 is formed on the sidewall of the protrusion.

In some examples, the dielectric layer 30 covers the sidewall of the protrusion and fills the groove 12 .

In the preparation method of the above-mentioned semiconductor structure, the dielectric layer 30 is formed to cover and fill the groove 12 of the lower side wall of the protruding part, so as to prevent the gate oxide layer formed on the corner of the active region 10 from being too thin, thereby solving the problem of insufficient gate oxide layer. Even problem.

Optionally, referring to FIG. 5 , forming the dielectric layer 30 on the sidewall of the protrusion includes:

S31 : forming a first dielectric material layer, the first dielectric material layer covering the upper surface of the active region, the sidewall of the protruding part and the top surface of the protruding part.

S32: Etching and thinning the first dielectric material layer to form a second dielectric material layer.

S33: removing the second dielectric material layer located on the upper surface of the active region and the top surface of the protrusion, and the second dielectric material layer remaining on the sidewall of the protrusion is the dielectric layer.

In step S31, referring to step S31 in FIG. 5 and FIG. 6, a first dielectric material layer 300A is formed, and the first dielectric material layer 300A covers the upper surface of the active region 10, the sidewall of the protruding portion and the protruding portion. top surface.

Optionally, the thickness range of the first dielectric material layer 300A includes: 500 Ř550 Å. For example, the thickness of the first dielectric material layer can be 500 angstroms, 510 angstroms, 520 angstroms, 530 angstroms, 540 angstroms or 550 angstroms and so on.

In some examples, the first dielectric material layer 300A may be formed using, but not limited to, a deposition process.

In step S32 , referring to step S32 in FIG. 5 and FIG. 7 , the first dielectric material layer 300A is etched and thinned to form a second dielectric material layer 300B.

Optionally, the thickness range of the second dielectric material layer 300B includes: 100 Ř120 Å. For example, the thickness of the second dielectric material layer 300B can be 100 angstroms, 105 angstroms, 110 angstroms, 115 angstroms or 120 angstroms, etc.

In some examples, a dry etching process is used to etch and thin the first dielectric material layer 300A.

Optionally, the gas used in the dry etching process includes fluorocarbon gas, one or more of HBr and Cl ₂ and a carrier gas, and the fluorocarbon gas includes CF ₄ , CHF ₃ , CH ₂ F ₂ or CH ₃ F, the carrier gas is an inert gas such as He.

Optionally, in the process of etching and thinning the first dielectric material layer 300A, the thickness of the first dielectric material layer 300A removed by etching is greater than the thickness of the second dielectric material layer 300B.

Specifically, the thickness of the second dielectric material layer 300B located on the sidewall of the protrusion is greater than the thickness of the second dielectric material layer 300B located on the upper surface of the substrate 1 and the top surface of the protrusion.

In step S33, referring to step S33 in FIG. 5 and FIG. 8, the second dielectric material layer 300B located on the upper surface of the active region 10 and the top surface of the protrusion is removed, and the second dielectric material layer 300B remaining on the side wall of the protrusion is removed. The material layer 300B is the dielectric layer 30 .

Optionally, taking the substrate 1 as an example of a silicon substrate, the dielectric layer 30 may include but not limited to a silicon oxide layer.

Optionally, the dielectric layer 30 is in contact with the gate oxide layer 40 . In this way, the gate oxide layer formed on the corner of the active region 10 can be prevented from being too thin, thereby solving the problem of uneven gate oxide layer.

In some examples, taking the substrate 1 as an example of a silicon substrate, both the dielectric layer 30 and the gate oxide layer 40 include but are not limited to a silicon oxide layer.

In some examples, a wet etching process is used to remove the second dielectric material layer 300B located on the upper surface of the substrate 1 and the top surface of the protrusion.

In step S40 , referring to step S40 in FIG. 2 and FIG. 9 , a gate oxide layer 40 is formed, and the gate oxide layer 40 covers the upper surface of the active region 10 .

In step S50, referring to step S50 in FIG. 2 and FIG. 10, a gate material layer 500 is formed, and the gate material layer 500 covers the upper surface of the gate oxide layer 40, the exposed surface of the dielectric layer 30 and the top of the protrusion. noodle.

Optionally, after forming the gate material layer 500 , further includes: etching the gate material layer 500 to form a gate (not shown).

Based on the same inventive concept, the embodiment of the present application also provides a semiconductor structure, please refer to FIG. 1 extending upwards, with a protruding portion protruding from the substrate 1; the shallow trench isolation structure 11 isolates a plurality of active regions 10 arranged at intervals in the substrate 1; the dielectric layer 30, the dielectric layer 30 covers The sidewall of the protrusion; the gate oxide layer 40, the gate oxide layer 40 covers the upper surface of the active region 10; the gate material layer 500, the gate material layer 500 covers the upper surface of the gate oxide layer 40, and the exposed dielectric layer 30 surface and the top surface of the protrusion.

In the above semiconductor structure, the dielectric layer 30 covers and fills the groove 12 of the sidewall of the protruding part of the shallow trench isolation structure 11 protruding from the substrate 1, so that the gate oxidation on the corner of the covering active region 10 can be effectively avoided. The problem of thinner layer 40 is to effectively increase the thickness of the gate oxide layer on the corner of the active region 10, thereby solving the problem of unevenness of the gate oxide layer 40, thereby improving the reliability of the semiconductor device and reducing the failure rate of the chip.

In some examples, the substrate 1 may include, but not limited to, a silicon substrate. Of course, in other examples, the material of the substrate 1 can also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate 10 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. end.

Optionally, the thickness range of the dielectric layer 30 includes: 100 angstroms-120 angstroms. For example, the thickness of the dielectric layer 30 can be 100 angstroms, 105 angstroms, 110 angstroms, 115 angstroms or 120 angstroms and so on.

Optionally, taking the substrate 1 as an example of a silicon substrate, the dielectric layer 30 includes a silicon oxide layer.

Optionally, the dielectric layer 30 is in contact with the gate oxide layer 40 .

In some examples, taking the substrate 1 as an example of a silicon substrate, both the dielectric layer 30 and the gate oxide layer 40 include but are not limited to a silicon oxide layer.

In the above semiconductor structure, the dielectric layer 30 is in contact with the gate oxide layer 40 . In this way, the gate oxide layer 40 formed on the corner of the active region 10 can be prevented from being too thin, thereby solving the problem of unevenness of the gate oxide layer 40 .

In the description of this specification, the technical features of the above-mentioned embodiments can be combined arbitrarily. For the sake of brevity, all possible combinations of the technical features of the above-mentioned embodiments are not described. There is no contradiction in the combination, and all should be regarded as within the scope described in this specification.

The above-mentioned embodiments only express several implementation modes of the present disclosure, and the description thereof is relatively specific and detailed, but should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the scope of protection of the disclosed patent should be based on the appended claims.

Claims (13)

1. A method for fabricating a semiconductor structure, comprising:

providing a substrate, wherein a sacrificial oxide layer is formed on the upper surface of the substrate, a shallow trench isolation structure is formed in the substrate, the shallow trench isolation structure extends upwards from the inside of the substrate and is provided with a protruding part protruding out of the substrate; the shallow trench isolation structure isolates a plurality of active regions arranged at intervals in the substrate;

removing the sacrificial oxide layer;

forming a dielectric layer on the side wall of the protruding part;

forming a gate oxide layer, wherein the gate oxide layer covers the upper surface of the active region;

and forming a grid electrode material layer, wherein the grid electrode material layer covers the upper surface of the grid oxide layer, the exposed surface of the dielectric layer and the top surface of the bulge.

2. The method according to claim 1, wherein after the removing of the sacrificial oxide layer, a recess is formed on a lower sidewall of the protrusion; the dielectric layer covers the side wall of the protruding portion and fills the groove.

3. The method of claim 1, wherein forming a dielectric layer on sidewalls of the protrusion comprises:

forming a first dielectric material layer, wherein the first dielectric material layer covers the upper surface of the active region, the side wall of the bulge part and the top surface of the bulge part;

etching and thinning the first dielectric material layer to form a second dielectric material layer;

and removing the second dielectric material layer on the upper surface of the active region and the top surface of the protrusion part, wherein the second dielectric material layer remained on the side wall of the protrusion part is the dielectric layer.

4. The method for manufacturing a semiconductor structure according to claim 3, wherein the first dielectric material layer is etched and thinned by a dry etching process; and removing the second dielectric material layer on the upper surface of the substrate and the top surface of the protruding part by adopting a wet etching process.

5. The method for manufacturing a semiconductor structure according to claim 3, wherein in the process of etching and thinning the first dielectric material layer, the thickness of the first dielectric material layer removed by etching is greater than the thickness of the second dielectric material layer.

6. The method of claim 5, wherein the thickness of the first dielectric material layer is in a range comprising: 500 to 550 angstroms; the thickness range of the second medium material layer comprises: 100 to 120 angstroms.

7. The method of claim 3, wherein the thickness of the second dielectric material layer on the sidewall of the protrusion is greater than the thickness of the second dielectric material layer on the top surface of the substrate and the top surface of the protrusion.

8. The method of claim 1, wherein the sacrificial oxide layer is removed by a wet etching process.

9. The method of claim 1, wherein the dielectric layer is in contact with the gate oxide layer.

10. A semiconductor structure, comprising:

the substrate is internally provided with a shallow trench isolation structure, the shallow trench isolation structure extends upwards from the inside of the substrate and is provided with a protruding part protruding out of the substrate; the shallow trench isolation structure isolates a plurality of active regions arranged at intervals in the substrate;

the dielectric layer covers the side wall of the protruding part;

the gate oxide layer covers the upper surface of the active region;

and the grid material layer covers the upper surface of the grid oxide layer, the exposed surface of the dielectric layer and the top surface of the bulge.

11. The semiconductor structure of claim 10, wherein the dielectric layer is in contact with the gate oxide layer.

12. The semiconductor structure of claim 10, wherein the dielectric layer has a thickness in a range comprising: 100 to 120 angstroms.

13. The semiconductor structure of claim 10, wherein the dielectric layer comprises a silicon oxide layer.

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