CN115458498A - Semiconductor devices and lead frames - Google Patents
Semiconductor devices and lead frames Download PDFInfo
- Publication number
- CN115458498A CN115458498A CN202110638860.8A CN202110638860A CN115458498A CN 115458498 A CN115458498 A CN 115458498A CN 202110638860 A CN202110638860 A CN 202110638860A CN 115458498 A CN115458498 A CN 115458498A
- Authority
- CN
- China
- Prior art keywords
- chip
- semiconductor device
- positioning area
- support portion
- base island
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73221—Strap and wire connectors
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
本申请提供一种半导体器件和用于构建所述半导体器件的引线框架,所述半导体器件包括至少一半导体芯片,贴附至一基岛;其中,一金属件贴附于所述半导体芯片的表面;至少一支撑部位于与所述基岛间隔的位置,并具有至少一定位区;其中,所述金属件从所述半导体芯片的表面延伸至所述支撑部的所述定位区内,以固定于所述支撑部的所述定位区内。
The present application provides a semiconductor device and a lead frame for constructing the semiconductor device, the semiconductor device includes at least one semiconductor chip attached to a base island; wherein a metal part is attached to the surface of the semiconductor chip ; at least one supporting part is located at a position spaced from the base island, and has at least one positioning area; wherein, the metal piece extends from the surface of the semiconductor chip into the positioning area of the supporting part to fix in the positioning area of the supporting part.
Description
技术领域technical field
本申请涉及半导封装领域,特别涉及一种半导体器件及用于构建所述半导体器件的引线框架。The present application relates to the field of semiconductor packaging, in particular to a semiconductor device and a lead frame used to construct the semiconductor device.
背景技术Background technique
封装产品通常是将芯片贴装于引线框架上,以焊线导电连接芯片与引线框架,最后以封装材料封装而获得。Packaged products are usually obtained by mounting the chip on the lead frame, electrically connecting the chip and the lead frame with bonding wires, and finally packaging it with packaging materials.
图1所示的是本领域中一种常规半导体器件1000的结构示意图。如图1所示,所述半导体器件1000包括贴附于第一基岛1011的第一芯片1021和第三芯片1023,以及贴附于第二基岛1012的第二芯片1022。复数个引线指1013围绕第一基岛1011及第二基岛1012设置。如图1所示,所述第三芯片1023及所述第二芯片1022的焊盘分别通过一引线103与一引线指1013电性连接,而所述第一芯片1021与所述第二芯片1022则通过一金属件104电性连接。在图1所示的常规半导体器件1000中,所述金属件104的一端固定于一支撑部1014上。所述金属件104用于电性连接第一芯片1021和第二芯片1022,同时也可用于实现散热功能,通常为由金属铜或含铜合金制成的片状。FIG. 1 is a schematic structural diagram of a
在如图1所示的常规半导体器件1000中,所述金属件104通常以回流焊方式固定,在回流焊过程中,金属件104会在流态锡膏的上方漂浮,发生漂移、甚至旋转的情况,导致最终的焊接成品的精度不够高。而在以黏贴熔融固定所述金属件104的过程中,金属件104也容易发生偏移旋转等导致精度偏差的问题。In the
因此,有必要提供一种新的半导体器件,以克服上述缺陷。Therefore, it is necessary to provide a new semiconductor device to overcome the above defects.
发明内容Contents of the invention
本申请的目的在于提供一种半导体器件以及用于制备半导体器件的引线框架,通过设置用于金属件的定位区,从而解决金属件设置过程中产生的偏移旋转等导致精度偏差的问题。The purpose of the present application is to provide a semiconductor device and a lead frame used for manufacturing the semiconductor device. By setting the positioning area for the metal part, the problem of deviation in precision caused by the offset and rotation generated during the installation of the metal part is solved.
为了达到上述目的,根据本申请的一方面,提供一种半导体器件,包括至少一半导体芯片,贴附至一基岛;其中,一金属件贴附于所述半导体芯片的表面;至少一支撑部位于与所述基岛间隔的位置,并具有至少一定位区;其中,所述金属件从所述半导体芯片的表面延伸至所述支撑部的所述定位区内,以固定于所述支撑部的所述定位区内。In order to achieve the above object, according to one aspect of the present application, a semiconductor device is provided, including at least one semiconductor chip attached to a base island; wherein, a metal part is attached to the surface of the semiconductor chip; at least one supporting portion Located at a position spaced from the base island, and having at least one positioning area; wherein, the metal piece extends from the surface of the semiconductor chip into the positioning area of the support part, so as to be fixed on the support part within the location zone of the .
在一些实施例中,所述定位区为所述支撑部去除至少部分厚度而形成。In some embodiments, the positioning area is formed by removing at least part of the thickness of the support portion.
在一些实施例中,所述支撑部具有一第一表面,所述定位区为所述支撑部的第一表面去除部分厚度而形成;其中,所述支撑部的所述第一表面为所述支撑部朝向所述金属件的一侧表面。In some embodiments, the support portion has a first surface, and the positioning area is formed by removing part of the thickness from the first surface of the support portion; wherein, the first surface of the support portion is the The supporting portion faces one side surface of the metal piece.
在一些实施例中,所述金属件包括贴附于所述半导体芯片的表面的第一部、固定于所述支撑部的所述定位区内的第二部,以及连接所述第一部与所述第二部的连接部;其中,所述金属件的所述第二部表面贴附于所述定位区内。In some embodiments, the metal part includes a first part attached to the surface of the semiconductor chip, a second part fixed in the positioning area of the support part, and a connection between the first part and the The connection part of the second part; wherein, the surface of the second part of the metal part is attached to the positioning area.
在一些实施例中,所述定位区为设置于所述支撑部的贯穿孔。In some embodiments, the positioning area is a through hole disposed on the supporting part.
在一些实施例中,所述金属件包括贴附于所述半导体芯片的表面的第一部、固定于所述支撑部的所述定位区内的第二部,以及连接所述第一部与所述第二部的连接部;其中,所述金属件的所述第二部延伸进入所述贯穿孔内。In some embodiments, the metal part includes a first part attached to the surface of the semiconductor chip, a second part fixed in the positioning area of the support part, and a connection between the first part and the A connecting portion of the second portion; wherein, the second portion of the metal member extends into the through hole.
在一些实施例中,所述金属件的所述连接部的部分表面贴附于所述支撑部上。In some embodiments, a part of the surface of the connecting portion of the metal piece is attached to the supporting portion.
在一些实施例中,所述支撑部具有一第一表面,并具有至少一第一定位区和至少一第二定位区;其中,所述第一定位区为所述支撑部的第一表面去除部分厚度而形成,所述第二定位区为设置于所述支撑部的贯穿孔。In some embodiments, the support portion has a first surface, and has at least one first positioning area and at least one second positioning area; wherein, the first positioning area is removed from the first surface of the support portion part of the thickness, and the second positioning area is a through hole provided in the supporting part.
在一些实施例中,所述金属件包括贴附于所述半导体芯片的表面的第一部、延伸进入所述第二定位区内的第二部,以及连接所述第一部与所述第二部的连接部;其中,所述金属件的所述连接部的部分表面贴附于所述第一定位区内。In some embodiments, the metal member includes a first portion attached to the surface of the semiconductor chip, a second portion extending into the second positioning area, and a connection between the first portion and the second positioning area. The connecting part of the two parts; wherein, a part of the surface of the connecting part of the metal part is attached to the first positioning area.
在一些实施例中,所述金属件朝向所述半导体芯片的一侧表面上设有至少一个凸起,所述半导体芯片通过导电材料与所述凸起贴合。In some embodiments, at least one protrusion is provided on the surface of the metal part facing the semiconductor chip, and the semiconductor chip is bonded to the protrusion through a conductive material.
在一些实施例中,所述半导体器件还包括复数个引线指,每一引线指通过一引线与所述半导体芯片连接。In some embodiments, the semiconductor device further includes a plurality of lead fingers, and each lead finger is connected to the semiconductor chip through a lead.
在一些实施例中,所述半导体器件还包括一第二芯片,所述第二芯片贴附至一第二基岛上;其中,所述第二芯片与所述半导体芯片通过所述金属件电性连接。In some embodiments, the semiconductor device further includes a second chip, and the second chip is attached to a second base island; wherein, the second chip and the semiconductor chip are electrically connected through the metal member. sexual connection.
在一些实施例中,所述金属件朝向所述半导体芯片及所述第二芯片的一侧表面上设有多个凸起,所述半导体芯片及所述第二芯片分别通过导电材料与所述凸起贴合。In some embodiments, a plurality of protrusions are provided on the surface of the metal part facing the semiconductor chip and the second chip, and the semiconductor chip and the second chip are respectively connected to the semiconductor chip and the second chip through a conductive material. Raised fit.
在一些实施例中,所述半导体器件还包括复数个引线指,所述半导体芯片及所述第二芯片分别通过引线与一引线指连接。In some embodiments, the semiconductor device further includes a plurality of lead fingers, and the semiconductor chip and the second chip are respectively connected to a lead finger through a lead.
根据本申请的另一方面,提供一种引线框架,用于一半导体器件;所述引线框架包括至少一封装单元,每一封装单元包括:至少一基岛,用于接收一半导体芯片;至少一支撑部,与所述基岛相间隔,并具有至少一定位区;以及,复数个引线指,围绕所述基岛设置,用于接收引线;其中,所述定位区为所述支撑部去除至少部分厚度而形成。According to another aspect of the present application, a lead frame is provided for a semiconductor device; the lead frame includes at least one package unit, each package unit includes: at least one base island for receiving a semiconductor chip; at least one The support part is spaced from the base island and has at least one positioning area; and a plurality of lead fingers are arranged around the base island for receiving leads; wherein, the positioning area removes at least one positioning area from the support part. part thickness.
根据本申请的一方面,提供所述支撑部具有一第一表面,所述定位区为所述支撑部的第一表面去除部分厚度而形成;其中,所述支撑部的所述第一表面为所述支撑部用于接收一金属件的表面。According to an aspect of the present application, it is provided that the support portion has a first surface, and the positioning area is formed by removing part of the thickness from the first surface of the support portion; wherein, the first surface of the support portion is The supporting portion is used for receiving a surface of a metal piece.
根据本申请的一方面,提供所述定位区为设置于所述支撑部的贯穿孔。According to an aspect of the present application, the positioning area is provided as a through hole disposed on the support portion.
根据本申请的一方面,提供所述支撑部具有一第一表面,并包括至少一第一定位区和至少一第二定位区;其中,所述第一定位区为所述支撑部的第一表面去除部分厚度而形成,所述第二定位区为设置于所述支撑部的贯穿孔。According to an aspect of the present application, it is provided that the supporting part has a first surface and includes at least one first positioning area and at least one second positioning area; wherein, the first positioning area is the first positioning area of the supporting part. The surface is formed by removing part of the thickness, and the second positioning area is a through hole provided in the supporting part.
在本申请中,通过在用于固定金属件的支撑部形成不同的定位区,同时配合经过调整的金属件用于固定的位置处的结构,从而使得金属件与支撑部两者之间形成了相对固定的对应位置关系,进而解决了金属件设置过程中产生的偏移旋转等导致精度偏差的问题。In this application, by forming different positioning areas on the support part used to fix the metal part, and at the same time cooperate with the adjusted structure of the metal part for fixing, so that a gap is formed between the metal part and the support part. The relatively fixed corresponding positional relationship further solves the problem of precision deviation caused by offset rotation generated during the setting of metal parts.
附图说明Description of drawings
图1是现有技术中一种半导体器件1000的结构示意图;FIG. 1 is a schematic structural diagram of a
图2A是集成到半导体器件1的第一芯片、第二芯片、第一基岛、第二基岛、引线指及引线的俯视图;2A is a top view of the first chip, the second chip, the first base island, the second base island, lead fingers and leads integrated into the
图2B是图2A中半导体器件1去除金属件的结构示意图;FIG. 2B is a schematic structural view of the
图2C和图2D为图2A中2C-2C’处的截面图;Fig. 2C and Fig. 2D are the sectional view at 2C-2C ' place among Fig. 2A;
图3A是集成到半导体器件2的第一芯片、第二芯片、第一基岛、第二基岛、引线指及引线的俯视图;3A is a top view of the first chip, the second chip, the first base island, the second base island, lead fingers and leads integrated into the
图3B和图3C为图3A中2B-2B’处的截面图;Fig. 3B and Fig. 3 C are the sectional view at 2B-2B' place among Fig. 3A;
图4A是集成到半导体器件3的第一芯片、第二芯片、第一基岛、第二基岛、引线指及引线的俯视图;4A is a top view of the first chip, the second chip, the first base island, the second base island, lead fingers and leads integrated into the
图4B为图4A中4B-4B’处的截面图;图4C为图4A中4C-4C’处的截面图;Fig. 4B is a sectional view at 4B-4B' place among Fig. 4A; Fig. 4C is a sectional view at 4C-4C' place among Fig. 4A;
图5A是集成到半导体器件4的第一芯片、第二芯片、第一基岛、第二基岛、引线指及引线的俯视图;5A is a top view of the first chip, the second chip, the first base island, the second base island, lead fingers and leads integrated into the semiconductor device 4;
图5B为图4A中5B-5B’处的截面图;Figure 5B is a cross-sectional view at 5B-5B' in Figure 4A;
图6A为根据本申请一实施例的引线框架100的结构示意图,图6B为图6A中6B-6B’处的截面图;Fig. 6A is a schematic structural view of a
图7A为根据本申请一实施例的引线框架200的结构示意图,图7B为图7A中7B-7B’Fig. 7A is a schematic structural diagram of a
处的截面图;cross-sectional view at
图8A为根据本申请一实施例的引线框架300的结构示意图,图8B为根据本申请一实施例的引线框架400的结构示意图。FIG. 8A is a schematic structural diagram of a
具体实施方式detailed description
以下,结合具体实施方式,对本申请的技术进行详细描述。应当知道的是,以下具体实施方式仅用于帮助本领域技术人员理解本申请,而非对本申请的限制。Hereinafter, the technology of the present application will be described in detail in combination with specific implementation manners. It should be understood that the following specific embodiments are only used to help those skilled in the art understand the present application, rather than limiting the present application.
实施例1半导体器件1
在本实施例中,提供一种半导体器件1。如图2A和图2B所示,本实施例的所述半导体器件1包括贴附于第一基岛111的第一芯片121和第三芯片123,以及贴附于第二基岛112的第二芯片122。本实施例的所述半导体器件1还包括复数个引线指113,所述第三芯片123及所述第二芯片122的焊盘分别通过一引线13与一引线指113电性连接,而所述第一芯片121与所述第二芯片122通过一金属件14电性连接。所述金属件14分别贴附于所述第一芯片121及所述第三芯片123的表面。In this embodiment, a
如图2B和图2C所示,在位于与所述第一基岛111(和/或第二基岛112)间隔的位置设有一支撑部114,用以固定所述金属件14。为了在制程中更好地定位所述金属件14,所述支撑部114具有一定位区1141。As shown in FIG. 2B and FIG. 2C , a
本领域技术人员可以理解的是,所述半导体器件1还包括用于塑封所述第一基岛111、第二基岛112、引线指113、第一芯片121、第二芯片122、第三芯片123、引线13和金属件14的封装材料EM。Those skilled in the art can understand that the
具体地,如图2C所示,所述金属件14包括贴附于所述第一芯片121(以及图2A中所述第二芯片122)的表面的第一部141,固定于所述支撑部114的所述定位区1141内的第二部142,以及连接所述第一部141与所述第二部142的连接部143。此外,所述金属件140朝向所述第一芯片121(以及图2A中所述第二芯片122)的一侧表面上设有与所述第一芯片121(以及图2A中所述第二芯片122)对应的凸起144,所述第一芯片121(以及图2A中所述第二芯片122)通过导电材料与对应的凸起144贴合。Specifically, as shown in FIG. 2C, the
所述支撑部114具有一第一表面114a,该第一表面114a为所述支撑部114朝向所述金属件14的一侧表面,即,第一表面114a为图2C中所述支撑部114的上表面。所述定位区1141为所述支撑部114的第一表面114a去除部分厚度而形成。也就是说,在本实施例中,为了更好地定位所述金属件14,所述支撑部114的第一表面114a去除部分厚度从而在所述第一表面114a上形成了凹槽形态的定位区1141。The supporting
由此,在如图2A所示地贴装所述金属件14后,如图2D所示,所述金属件14从所述第一芯片121(以及图2A中所述第二芯片122)的表面延伸至所述支撑部114的所述定位区1141内,并且使得所述第二部142的表面贴附于所述定位区1141内。Thus, after attaching the
实施例2半导体器件2
在本实施例中,提供一种半导体器件2。本实施例的所述半导体器件2是实施例1的半导体器件1的变形,结构与实施例1的半导体器件1的结构基本相同,区别在于:定位区以及金属件的结构不同。In this embodiment, a
与半导体器件1相似地,如图3A所示,本实施例的所述半导体器件2包括贴附于第一基岛211的第一芯片221和第三芯片223,以及贴附于第二基岛212的第二芯片222。本实施例的所述半导体器件2还包括复数个引线指213,所述第三芯片223及所述第二芯片222的焊盘分别通过一引线23与一引线指213电性连接,而所述第一芯片221与所述第二芯片222通过一金属件24电性连接。所述金属件24分别贴附于所述第一芯片221及所述第三芯片223的表面,并且,所述金属件24固定于一与所述第一基岛211(和/或第二基岛212)间隔的支撑部214。Similar to the
本领域技术人员可以理解的是,所述半导体器件2还包括用于塑封所述第一基岛211、第二基岛212、引线指213、第一芯片221、第三芯片223、第二芯片222、引线23和金属件24的封装材料EM。It can be understood by those skilled in the art that the
与实施例1的所述半导体器件1不同的是,如图3B所示,所述金属件24包括贴附于所述第一芯片221(以及图3A中所述第二芯片222)的表面的第一部241,固定于所述支撑部214的第二部242,以及连接所述第一部241与所述第二部242的连接部243。此外,所述金属件240朝向所述第一芯片221(以及图3A中所述第二芯片222)的一侧表面上设有与所述第一芯片221(以及图3A中所述第二芯片222)对应的凸起244,所述第一芯片221(以及图3A中所述第二芯片222)通过导电材料与对应的凸起244贴合。The difference from the
与实施例1的所述半导体器件1不同的是,如图3A和2B所示,所述支撑部214具有一第一表面214a,该第一表面214a为所述支撑部214朝向所述金属件24的一侧表面,即,第一表面214a为图3B中所述支撑部214的上表面。为了在制程中更好地定位所述金属件24,所述支撑部214具有一定位区2141。The difference from the
与实施例1的所述半导体器件1不同的是,如图3B所示,本实施例中的定位区2141为所述支撑部214的第一表面214a去除全部厚度从而在所述支撑部214形成了贯穿孔形态的定位区2141。The difference from the
由此,在如图3A所示地贴装所述金属件24后,如图3C所示,所述金属件21从所述第一芯片221(以及图2A中所述第三芯片23)的表面延伸至所述支撑部114的所述定位区1141内,并且使得所述第二部242延伸进入定位区2141内。Thus, after mounting the
实施例3半导体器件3
在本实施例中,提供一种半导体器件3。本实施例的所述半导体器件3是实施例1的半导体器件1的变形,结构与实施例1的半导体器件1的结构基本相同,区别在于:定位区以及金属件的结构不同。In this embodiment, a
与半导体器件1相似地,如图4A所示,本实施例的所述半导体器件3包括贴附于第一基岛311的第一芯片321和第二芯片322,以及贴附于第二基岛312的第三芯片323。本实施例的所述半导体器件3还包括复数个引线指313,所述第二芯片322及所述第三芯片323的焊盘分别通过一引线33与一引线指313电性连接,而所述第一芯片321与所述第三芯片323通过一金属件34电性连接。所述金属件34分别贴附于所述第一芯片321及所述第二芯片322的表面,并且,所述金属件34固定于一与所述第一基岛311(和/或第二基岛312)间隔的支撑部314。Similar to the
本领域技术人员可以理解的是,所述半导体器件3还包括用于塑封所述第一基岛311、第二基岛312、引线指313、第一芯片321、第二芯片322、第三芯片323、引线33和金属件34的封装材料EM。Those skilled in the art can understand that the
为了在制程中更好地定位所述金属件34,所述支撑部314具有一定位区3141。与实施例1的所述半导体器件1不同的是,如图4A和3B所示,所述定位区3141为形成于所述支撑部314的多个贯穿孔。In order to better position the
具体地,如图4A和图4B所示,所述支撑部314具有一第一表面314a,该第一表面314a为所述支撑部314朝向所述金属件34的一侧表面,即,第一表面314a为图4B中所述支撑部314的上表面。本实施例中的定位区3141为所述支撑部314的第一表面314a去除全部厚度从而在所述支撑部314形成了多个贯穿孔形态的定位区3141。Specifically, as shown in FIG. 4A and FIG. 4B, the
如图4B和图4C所示,所述金属件34包括贴附于所述第一芯片321及所述第二芯片322的表面的第一部341,延伸进入定位区3141内的第二部342,以及连接第一部341和第二部342的连接部343。如图4C所示,所述连接部343的部分表面贴附于所述支撑部314的第一表面314a上。如图4B,所述金属件34朝向所述第二芯片322的一侧表面上设有与所述第二芯片322对应的凸起344;相似地,如图4C所示,所述金属件34朝向所述第一芯片321的一侧表面上设有与所述第一芯片321对应的凸起344。As shown in FIG. 4B and FIG. 4C, the
实施例4半导体器件4Embodiment 4 Semiconductor device 4
在本实施例中,提供一种半导体器件4。本实施例的所述半导体器件4是实施例3的半导体器件3的变形,结构与实施例3的半导体器件3的结构基本相同,区别在于:定位区地设置不同。In this embodiment, a semiconductor device 4 is provided. The semiconductor device 4 in this embodiment is a modification of the
具体地,与半导体器件3相同地,如图5A所示,本实施例的所述半导体器件4包括贴附于第一基岛411的第一芯片421和第二芯片422,以及贴附于第二基岛412的第三芯片423。本实施例的所述半导体器件4还包括复数个引线指413,所述第二芯片422及所述第三芯片423的焊盘分别通过一引线43与一引线指413电性连接,而所述第一芯片421与所述第三芯片423通过一金属件44电性连接。所述金属件44分别贴附于所述第一芯片421及所述第二芯片422的表面,并且,所述金属件44固定于一与所述第一基岛411(和/或第二基岛312)间隔的支撑部414。Specifically, like the
本领域技术人员可以理解的是,所述半导体器件3还包括用于塑封所述第一基岛311、第二基岛312、引线指313、第一芯片321、第二芯片322、第三芯片323、引线33和金属件34的封装材料EM。Those skilled in the art can understand that the
在本实施例中,与实施例3相同地,为了在制程中更好地定位所述金属件44,所述支撑部414具有定位区。与实施例3的所述半导体器件3不同的是,如图5A所示,在本实施例的所述支撑部414设有第一定位区4141和第二定位区4142,其中,第二定位区4142的设置位置及结构与实施例3中的定位区3414相同,此处不再赘述。此外,本实施例中,所述金属件44的结构与设置于实施例3的金属件34相同,此处不再赘述。In this embodiment, similar to
而如图5B所示,与实施例3相似地,本实施例地所述支撑部414具有一第一表面414a,该第一表面414a为所述支撑部414朝向所述金属件44的一侧表面,即,第一表面414a为图5B中所述支撑部414的上表面。本实施例中的第二定位区4142为所述支撑部414的第一表面414a去除部分厚度从而在所述支撑部414形成的凹槽形态的第二定位区4142。As shown in FIG. 5B , similar to
因此,与图4C中所示的实施例3不同的是,如图5B所示,本实施例的金属件44的连接部443延伸至所述支撑部414第二定位区4142内,并且连接部443的表面贴附于所述第二定位区4142内。Therefore, different from
实施例5引线框架100和引线框架200
本实施例中提供一种用于制备实施例1的半导体器件1的引线框架100。本领域技术人员可以理解的是,引线框架100包括一个或多个以封装线W定义的封装单元,封装单元之间通过外框101连接,图6A所示的是一个封装单元的结构。This embodiment provides a
如图6A所示,在一个封装单元中,所述引线框架100包括第一基岛111、第二基岛112、围绕第一基岛111及第二基岛112的复数个引线指113,以及与第一基岛111及第二基岛112相间隔的支撑部114。本领域技术人员可以理解的是,所述第一基岛111、第二基岛112、引线指113及支撑部114也通过外框101连接,以形成完整的引线框架100。As shown in FIG. 6A, in a package unit, the
如图6B及对应的实施例1的图2C所示,在本实施例中,所述支撑部114具有一第一表面114a,所述支撑部114的第一表面114a去除部分厚度而形成了定位区1141,由此,该定位区1141为从所述支撑部114的表面去除部分厚度而形成的凹槽。As shown in FIG. 6B and the corresponding FIG. 2C of
实施例6引线框架200Embodiment 6
本实施例中提供一种用于制备实施例2的半导体器件2的引线框架200。本领域技术人员可以理解的是,引线框架200包括一个或多个以封装线W定义的封装单元,封装单元之间通过外框201连接,图7A所示的是一个封装单元的结构。This embodiment provides a
如图7A所示,在一个封装单元中,所述引线框架200包括第一基岛211、第二基岛212、围绕第一基岛211及第二基岛212的复数个引线指213,以及与第一基岛211及第二基岛212相间隔的支撑部214。本领域技术人员可以理解的是,所述第一基岛211、第二基岛212、引线指213及支撑部214也通过外框201连接,以形成完整的引线框架200。As shown in FIG. 7A, in a package unit, the
如图7B及对应的实施例2的图3B所示,在本实施例中,所述支撑部214具有一第一表面214a,所述支撑部214的第一表面214a去除全部厚度而形成了定位区2141,由此,该定位区2141为形成于所述支撑部214的贯穿孔。As shown in FIG. 7B and the corresponding FIG. 3B of
实施例7引线框架300和引线框架400Embodiment 7
在本实施例中,分别提供用于制备实施例3的半导体器件3的引线框架300及制备实施例4的半导体器件4的引线框架400。In this embodiment, the
引线框架300包括一个或多个以封装线W定义的封装单元,封装单元之间通过外框301连接,图8A所示的是一个封装单元的结构。如图8A所示,在一个封装单元中,所述引线框架300包括第一基岛311、第二基岛312、围绕第一基岛311及第二基岛312的复数个引线指313,以及与第一基岛311及第二基岛312相间隔的支撑部314。本领域技术人员可以理解的是,所述第一基岛311、第二基岛312、引线指313及支撑部314也通过外框301连接,以形成完整的引线框架300。The
如图8A所示,在本实施例的引线框架300中,所述支撑部314具有两个定位区3141,该定位区3141均为贯穿孔。As shown in FIG. 8A , in the
而如图8B所示,在引线框架400中,包括一个或多个以封装线W定义的封装单元,封装单元之间通过外框401连接,图7B所示的是一个封装单元的结构。如图7B所示,在一个封装单元中,所述引线框架400包括第一基岛411、第二基岛412、围绕第一基岛41及第二基岛412的复数个引线指413,以及与第一基岛411及第二基岛412相间隔的支撑部414。本领域技术人员可以理解的是,所述第一基岛411、第二基岛412、引线指413及支撑部414也通过外框401连接,以形成完整的引线框架400。As shown in FIG. 8B , the
如图7B所示,在本实施例的引线框架400中,所述支撑部414具有两个第一定位区4141和第二定位区4142,其中,第一定位区4141均为贯穿孔,而第二定位区4142则为形成于所述支撑部414的表面上的凹槽。As shown in FIG. 7B, in the
本申请已由上述相关实施例加以描述,然而上述实施例仅为实施本申请的范例。必需指出的是,已公开的实施例并未限制本申请的范围。相反地,包含于权利要求书的精神及范围的修改及均等设置均包括于本申请的范围内。The present application has been described by the above-mentioned related embodiments, but the above-mentioned embodiments are only examples for implementing the present application. It must be pointed out that the disclosed embodiments do not limit the scope of the application. On the contrary, modifications and equivalent arrangements included in the spirit and scope of the claims are included in the scope of the present application.
Claims (18)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110638860.8A CN115458498A (en) | 2021-06-08 | 2021-06-08 | Semiconductor devices and lead frames |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110638860.8A CN115458498A (en) | 2021-06-08 | 2021-06-08 | Semiconductor devices and lead frames |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115458498A true CN115458498A (en) | 2022-12-09 |
Family
ID=84294463
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110638860.8A Pending CN115458498A (en) | 2021-06-08 | 2021-06-08 | Semiconductor devices and lead frames |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115458498A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101425494A (en) * | 2007-10-31 | 2009-05-06 | 万国半导体股份有限公司 | Top solder reinforced semiconductor device and method for low parasitic impedance packaging |
| TW201140791A (en) * | 2010-05-05 | 2011-11-16 | Alpha & Omega Semiconductor | Semiconductor packaging and fabrication method using connecting plate for internal connection |
| CN103545268A (en) * | 2012-07-09 | 2014-01-29 | 万国半导体股份有限公司 | Power device with bottom source electrode and preparation method |
| CN104347568A (en) * | 2013-08-07 | 2015-02-11 | 万国半导体股份有限公司 | Multi-chip mixed packaging type semiconductor device and manufacturing method thereof |
| CN107680951A (en) * | 2013-11-27 | 2018-02-09 | 万国半导体股份有限公司 | A kind of encapsulating structure and its method for packing of multi-chip lamination |
| CN215731684U (en) * | 2021-06-08 | 2022-02-01 | 上海凯虹科技电子有限公司 | Semiconductor device and lead frame |
-
2021
- 2021-06-08 CN CN202110638860.8A patent/CN115458498A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101425494A (en) * | 2007-10-31 | 2009-05-06 | 万国半导体股份有限公司 | Top solder reinforced semiconductor device and method for low parasitic impedance packaging |
| TW201140791A (en) * | 2010-05-05 | 2011-11-16 | Alpha & Omega Semiconductor | Semiconductor packaging and fabrication method using connecting plate for internal connection |
| CN103545268A (en) * | 2012-07-09 | 2014-01-29 | 万国半导体股份有限公司 | Power device with bottom source electrode and preparation method |
| CN104347568A (en) * | 2013-08-07 | 2015-02-11 | 万国半导体股份有限公司 | Multi-chip mixed packaging type semiconductor device and manufacturing method thereof |
| CN107680951A (en) * | 2013-11-27 | 2018-02-09 | 万国半导体股份有限公司 | A kind of encapsulating structure and its method for packing of multi-chip lamination |
| CN215731684U (en) * | 2021-06-08 | 2022-02-01 | 上海凯虹科技电子有限公司 | Semiconductor device and lead frame |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR920008254B1 (en) | Semiconductor device having an advanced lead structure and manufacturing method | |
| TWI409926B (en) | Leadframe | |
| JPH04280462A (en) | Lead frame and semiconductor device using this lead frame | |
| JP2000223622A (en) | Semiconductor device, method of manufacturing the same, and mounting structure using the same | |
| TW381326B (en) | Semiconductor device and lead frame therefor | |
| JP5378643B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN215731684U (en) | Semiconductor device and lead frame | |
| CN115458498A (en) | Semiconductor devices and lead frames | |
| JP3092585B2 (en) | Semiconductor chip suction tool and semiconductor device manufacturing method using the tool | |
| JP2013206965A (en) | Method for manufacturing printed circuit board | |
| JP4976673B2 (en) | Semiconductor device, substrate, and method for manufacturing semiconductor device | |
| JP2646989B2 (en) | Chip carrier | |
| JP2003197681A (en) | Electronic equipment | |
| JP2013093483A (en) | Semiconductor device and manufacturing method of the same | |
| JPH0744018Y2 (en) | Projection electrode structure | |
| JP2000200852A (en) | Semiconductor device, method of manufacturing the same, and method of mounting the same | |
| JP2003007954A (en) | Method for manufacturing resin-encapsulated semiconductor device | |
| JPH0382067A (en) | Resin sealed type semiconductor device | |
| JPH0720925Y2 (en) | Lead frame | |
| CN100536121C (en) | Semiconductor device and preparation method thereof | |
| JP2005303169A (en) | Semiconductor devide and manufacturing method of the same | |
| KR20030080187A (en) | Semiconductor device | |
| JPH0371658A (en) | Semiconductor device | |
| JP2004342712A (en) | Method of manufacturing semiconductor device | |
| JPH09252063A (en) | Lead frame, semiconductor integrated circuit device using the same, and method of manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |