CN115458545A - Back-illuminated CMOS image sensor and manufacturing method thereof - Google Patents

Abstract

The invention relates to a back-illuminated CMOS image sensor and a manufacturing method thereof. The back-illuminated CMOS image sensor comprises a pixel substrate, a back dielectric layer and a metal shielding layer, wherein the back dielectric layer and the metal shielding layer are formed on the back surface of the pixel substrate, the metal shielding layer is formed between a pixel area and a peripheral circuit area on the back surface of the pixel substrate at intervals, the metal shielding layer comprises a transverse shielding part and a longitudinal shielding part, the transverse shielding part is located on one side of the back surface of the pixel substrate and surrounds the pixel area, and the longitudinal shielding part and the transverse shielding part are connected on the back surface of the pixel substrate and are inserted into the pixel substrate. The transverse shielding part and the longitudinal shielding part have the function of shielding light on the periphery of the pixel area from entering the pixel area, and compared with the situation of only arranging the transverse shielding part, the width of the transverse shielding part can be shortened, so that the occupied chip area of the metal shielding layer is reduced, and the requirement of further reducing the chip size is met.

Description

Back-illuminated CMOS image sensor and manufacturing method thereof

technical field

The invention relates to the technical field of semiconductors, in particular to a back-illuminated CMOS image sensor and a manufacturing method thereof.

Background technique

CMOS image sensors (CMOS Image Sensors, CIS) use photosensitive CMOS circuits to convert photons into electrons. According to the light incident direction, CMOS image sensors are divided into front-illuminated (FSI) and back-illuminated (BSI). The light-sensing region (such as a photodiode) in the substrate reduces light loss and can obtain higher photoelectric conversion efficiency. Therefore, most CMOS image sensors currently use a back-illuminated structure.

With the development of technology, the pixel size of the back-illuminated CMOS image sensor is continuously reduced, and the interference of the noise signal around the pixel point on the pixel point is more significant, and these noise signals need to be isolated. Among them, in order to shield the incident When light enters the pixel area, usually a metal shielding area is set on the periphery of the pixel area on the back of the sensor. In order to ensure that the light around the pixel area can be effectively prevented from entering the pixel area, the metal shielding area needs to be far away from the pixel area boundary. The direction of the pixel region extends to a sufficient width, which occupies a large chip area and increases the difficulty of meeting the requirements for further reduction of the chip size.

Contents of the invention

In order to solve the problem that the existing back-illuminated CMOS image sensor has a wide metal shielding area, which increases the difficulty of meeting the needs of further reducing the chip size, the present invention provides a back-illuminated CMOS image sensor, and also provides a back-illuminated CMOS image sensor. A method for fabricating a CMOS image sensor.

In one aspect, the present invention provides a back-illuminated CMOS image sensor, comprising a pixel substrate, a back dielectric layer, and a metal shielding layer; the pixel substrate has opposite front and back surfaces, and the pixel substrate includes a pixel region and a peripheral circuit region , a plurality of light sensing areas are formed in the pixel area, and the light sensing areas are used to sense incident light entering the pixel area from the back side of the pixel substrate; the back dielectric layer is formed on the The back side of the pixel substrate; the metal shielding layer is formed on the back dielectric layer and is located between the pixel region and the peripheral circuit region, the metal shielding layer includes a lateral shielding portion and a vertical shielding portion, and the lateral shielding layer The shielding part is located on the back side of the pixel base and surrounds the pixel area, and the vertical shielding part is connected to the horizontal shielding part on the back side of the pixel base and inserted into the pixel base.

Optionally, the width of the horizontal shielding portion is greater than the width of the vertical shielding portion; in the metal shielding layer, the horizontal shielding portion is connected to one or more vertical shielding portions on the back of the pixel substrate.

Optionally, the vertical shielding portion is a ring structure or a non-ring structure; wherein, the pixel area is surrounded by the vertical shielding portion of the ring structure, and/or, the pixel area is surrounded by a plurality of non-ring structures. Surrounded by the vertical shielding portion.

Optionally, there is an air gap in the vertical shielding portion inserted into the pixel base.

Optionally, the back-illuminated CMOS image sensor further includes a stress isolation groove, the stress isolation groove is located on the inner side and/or the outer side of the longitudinal shielding portion, and the back dielectric layer fills the stress isolation groove.

Optionally, the pixel base includes a substrate, a front dielectric layer disposed on the front of the substrate, and an interconnection structure disposed in the front dielectric layer, and the vertical shielding portion penetrates the substrate.

Optionally, the back-illuminated CMOS image sensor further includes metal wires and TSV via holes, the metal wires are arranged on the back side of the pixel substrate corresponding to the peripheral circuit area, and the TSV via holes correspond to The TSV via hole is arranged in the peripheral circuit area and penetrates through the substrate, the interconnection structure and the metal wire are connected, and the depth of the vertical shielding part is the same as that of the TSV via hole

In one aspect, the present invention provides a method for fabricating a back-illuminated CMOS image sensor, comprising:

A pixel substrate is provided, the pixel substrate has opposite front and back surfaces, the pixel substrate includes a pixel region and a peripheral circuit region, a plurality of photosensitive regions are formed in the pixel region, and the photosensitive regions are used for sensing incident light entering the pixel region from the back of the pixel substrate;

Form a first back dielectric layer on the back of the pixel substrate, and etch the pixel substrate from the back of the pixel substrate to form at least a part of the pixel substrate through the groove, the groove corresponds to the pixel A region between the region and the peripheral circuit region is formed, and then a second back dielectric layer is deposited on the inner wall of the trench;

forming a back metal layer, the back metal layer fills the trench and covers the first back dielectric layer outside the trench, the top surface of the back metal layer is higher than the first back dielectric layer; as well as

performing patterning on the back metal layer, using the back metal layer to form a metal shielding layer located between the pixel region and the peripheral circuit region, the metal shielding layer comprising a lateral shielding portion and a vertical shielding portion, The horizontal shielding portion is formed on the back side of the pixel substrate and surrounds the pixel region, and the vertical shielding portion is formed in the groove and connected to the horizontal shielding portion on the backside of the pixel substrate.

Optionally, the pixel base includes a substrate, a front dielectric layer disposed on the front side of the substrate, and an interconnection structure disposed in the front dielectric layer, and the vertical shielding portion penetrates the substrate; Wherein, in the step of etching the pixel substrate from the back surface of the pixel substrate to form the trench, an opening through the substrate is formed corresponding to the peripheral circuit region, and the opening exposes the interconnect connection structure, and, when forming the back metal layer, the back metal layer also fills the openings to form TSV vias.

Optionally, when patterning the back metal layer, the back metal layer is also used to form a metal grid located in the pixel area and a metal wire located in the peripheral circuit area; the metal grid corresponds to It is arranged in the gap area around each of the photo-sensing areas, and the metal wire is connected to the interconnection structure through the TSV via hole.

Optionally, before patterning the back metal layer, the surface of the back metal layer is also planarized.

Optionally, the part of the second back dielectric layer covering the opening of the sidewall of the trench protrudes from the part covering the sidewall of the trench away from the opening, so that the width of the opening of the trench is smaller than the The groove is far away from the width of the opening, so that there is an air gap in the longitudinal shielding portion formed in the groove.

Optionally, in the step of etching the pixel substrate from the back surface of the pixel substrate to form the trench, a stress barrier groove is formed corresponding to the region between the pixel region and the peripheral circuit region, the The stress isolation groove is located on the inner side and/or the outer side of the groove, and the width of the stress isolation groove is smaller than the width of the groove, so that when the second back dielectric layer is deposited on the inner wall of the groove, the first Two back dielectric layers fill the stress isolation groove to form a stress isolation structure.

The back-illuminated CMOS image sensor provided by the present invention includes a pixel substrate, a back dielectric layer formed on the back of the pixel substrate, and a metal shielding layer. The metal shielding layer is formed on the back dielectric layer and is located between the pixel region and the pixel region. Between the peripheral circuit areas, the metal shielding layer includes a horizontal shielding portion and a vertical shielding portion, the horizontal shielding portion is located on the back side of the pixel substrate and surrounds the pixel area, the vertical shielding portion and the vertical shielding portion The lateral shielding part is connected to the back surface of the pixel base and inserted into the pixel base. Both the horizontal shielding part and the vertical shielding part have the effect of shielding the light around the pixel area from entering the pixel area. Compared with the situation where only the horizontal shielding part is provided, the width of the lateral shielding part can be shortened, so that the chip area occupied by the metal shielding layer It is convenient to meet the demand for further reduction of chip size.

In the manufacturing method of the back-illuminated CMOS image sensor provided by the present invention, after the pixel substrate is obtained, a metal shielding layer located between the pixel region and the peripheral circuit region is formed by performing a backside process, and the metal shielding layer includes a lateral A shielding part and a vertical shielding part, the horizontal shielding part is formed on the back side of the pixel base and surrounds the pixel area, the vertical shielding part is connected to the horizontal shielding part on the back side of the pixel base and inserted into the within the pixel base. Both the horizontal shielding part and the vertical shielding part have the effect of shielding light from the periphery of the pixel area from entering the pixel area. Compared with the situation where only the horizontal shielding part is provided, the width of the horizontal shielding part can be shortened, so that the metal shielding layer occupies The chip area is reduced, which is convenient to meet the demand for further reduction of the chip size.

Furthermore, in the process of manufacturing the metal shielding layer, the metal grid located in the pixel area and the metal wire located in the peripheral circuit area can be fabricated on the back of the pixel substrate at the same time, which can save the process. In addition, an air gap can be formed in the vertical shielding portion and/or a stress isolation structure can be formed inside and/or outside the vertical shielding portion, which can reduce the influence of the vertical shielding portion on the internal stress of the pixel substrate.

Description of drawings

FIG. 1 is a schematic flowchart of a manufacturing method of a back-illuminated CMOS image sensor according to an embodiment of the present invention.

2 to 7 are schematic cross-sectional structure diagrams obtained in multiple steps of the manufacturing method of the back-illuminated CMOS image sensor according to an embodiment of the present invention.

Explanation of reference signs:

100-pixel base; 110-substrate; 120-front dielectric layer; 121-interconnection structure; 130-first back dielectric layer; 131-high dielectric constant layer; 132-buffer oxide layer; 140-second back Dielectric layer; 150-back metal layer; 151-metal shielding layer; 151a-transverse shielding part; 151b-vertical shielding part; 152-metal grid; 153-metal wire; 154-TSV via hole; Material layer; 101-light sensing area; 102-deep trench isolation; 103-groove; 104-opening hole; 105-stress barrier structure; 106-air gap.

detailed description

The back-illuminated CMOS image sensor and its manufacturing method of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be understood that the drawings in the description are all in very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

Embodiments of the present invention firstly relate to a manufacturing method of a back-illuminated CMOS image sensor. The manufacturing method of the back-illuminated CMOS image sensor will be described below with reference to FIG. 1 and FIG. 2 to FIG. 7 .

Referring to FIG. 1 and FIG. 2, the manufacturing method of the back-illuminated CMOS image sensor according to the embodiment of the present invention includes a first step S1: providing a pixel substrate 100, the pixel substrate 100 includes a pixel area I and a peripheral circuit area II, and the pixel A plurality of photo-sensing regions 101 are formed in the region I, and the photo-sensing regions 101 are used for sensing incident light entering the pixel region I from the back surface of the pixel substrate 100 .

Specifically, the pixel base 100 may include a substrate 110 . The substrate 110 is, for example, a silicon substrate, a germanium (Ge) substrate, a silicon germanium substrate, a SOI (Silicon On Insulator, Silicon On Insulator) substrate, or a GOI (Germanium On Insulator, Germanium On Insulator) substrate, etc., The substrate 110 may include doped epitaxial layers, graded semiconductor layers, and semiconductor layers on top of other semiconductor layers of different types (eg, a silicon layer on a silicon germanium layer). The photo-sensing region 101 is formed in the substrate 110 . The pixel substrate 100 also includes a front dielectric layer 120 formed on the substrate 110 and an interconnection structure 121 located in the front dielectric layer 120, the surface of the substrate 110 forming the front dielectric layer 120 is the substrate 110 The front side, the surface opposite to the front side is the back side of the substrate 110 . In this embodiment, the photo-sensing region 101 formed in the substrate 110 is used to sense incident light entering the pixel region I from the back of the pixel substrate 100 (ie, the back of the substrate 110 ). The photosensitive region 101 may include a photodiode. It can be understood that only a partial number of photosensitive regions 101 are shown in the drawings. The interconnect structure 121 may include multiple conductive layers and conductive plugs isolated by the front dielectric layer 120 .

The substrate 110 may be stacked on other substrates, and the other substrates may include semiconductor substrates and electronic components and circuit structures formed based on the corresponding semiconductor substrates, and the electronic components and circuit structures in the other substrates May be interconnected with interconnect structure 121 . The other substrate can also be a carrier substrate.

Both the pixel region I and the peripheral circuit region II in the pixel substrate 100 include part of the front or back surface of the pixel substrate 100 , and extend in the thickness direction of the pixel substrate 100 . The pixel area I is provided with the above-mentioned multiple photo-sensing regions 101, and the peripheral circuit area II is located on the periphery of the pixel area I, and is used for setting peripheral components (such as logic elements) of the sensor. The interconnection structure 121 in the above-mentioned front dielectric layer 120 can span the pixel region I and the peripheral circuit region II, so as to interconnect the pixel region I and the peripheral circuit region II. In order to avoid interference and set up a shielding structure, there is a gap between the pixel area I and the peripheral circuit area II.

Referring to FIG. 1 , FIG. 3 and FIG. 4 , the manufacturing method of the back-illuminated CMOS image sensor according to the embodiment of the present invention includes a second step S2: forming a first back dielectric layer 130 on the back of the pixel substrate 100, and forming the first back dielectric layer 130 from the Etching the pixel substrate 100 on the back side of the pixel substrate 100 to form a groove 103 at least partly through the pixel substrate 100, the groove 103 is formed corresponding to the region between the pixel region I and the peripheral circuit region II, and then The inner wall of the trench 103 forms a second back dielectric layer 140 .

In this embodiment, the back of the substrate 110 has been thinned, and before forming the trench 103, a deep trench isolation 102 (DTI) is formed on the back of the pixel substrate 100 corresponding to the pixel region I. For example, refer to As shown in FIG. 3 , the fabrication of the deep trench isolation 102 includes the following process: performing photolithography and etching processes on the back of the thinned substrate 100 to form a deep trench penetrating part of the substrate 110 corresponding to the pixel region I. The deep trenches are disposed corresponding to the gap regions around each photo-sensing area 101 ; then, a dielectric material is deposited to fill the deep trenches to form deep trench isolations 102 . In this embodiment, when depositing a dielectric material to fill the deep trench, first deposit a high dielectric constant layer 131 (dielectric constant over 3.9, for example) along the back of the substrate 100 and the inner surface of the deep trench. , its material may include Al ₂ O ₃ , Ta ₂ O ₅ , ZrO ₂ , LaO, BaZrO, AlO, HfZrO, HfZrON, HfLaO, HfSiON, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr)TiO ₃ ( At least one of BST), Si ₃ N ₄ , TiO ₂ , oxynitride or other suitable materials. The high dielectric constant layer 131 has the effect of absorbing the charge on the back surface of the pixel substrate, which helps to reduce the "white pixel" defect, and then deposits a buffer oxide layer 132 (such as silicon oxide) on the high dielectric constant layer 131, so that The buffer oxide layer 132 fills the deep trench and covers the high dielectric constant layer 131 outside the deep trench. Here, the stack of the high dielectric constant layer 131 and the buffer oxide layer 132 is referred to as the first back dielectric layer 130 .

The trench 103 can be formed corresponding to the region between the pixel region I and the peripheral circuit region II by performing photolithography and etching processes on the first back dielectric layer 130 . In this embodiment, the groove 103 is used to form a vertical shielding portion for blocking incident light outside the pixel region I from entering the pixel region I. From a cross-sectional view, the groove 103 can be a The annular structure (such as a square ring, a circular ring, or a ring of other shapes) may also be a non-annular structure. In order to form effective shielding, when it is a non-ring structure, a plurality of grooves 103 respectively located in different directions of the pixel region I may be formed to surround the pixel region I. In addition, one or more than two rounds of grooves 103 may be formed on the periphery of the pixel region I.

The depth of the groove 103 can be set as required. In this embodiment, in order to improve the shielding effect, the trench 103 penetrates through the substrate, exposing the front dielectric layer 120 . In order to save steps, optionally, the trench 103 and its filling process can be performed synchronously with the TSV process on the backside of the substrate 100 .

Exemplarily, referring to FIG. 4, the second step S2 may include the following process: coating a photoresist on the first back dielectric layer 130, and performing exposure, development, and one or more etchings, corresponding to the pixel area I A trench 103 is formed in the area between the peripheral circuit area II and an opening 104 penetrating the substrate 110 corresponding to the peripheral circuit area II, and the opening 104 is located at a position where a TSV via hole is to be made; then Deposit the second back dielectric layer 140 along the surface of the first back dielectric layer 130, the inner surface of the trench 103 and the inner surface of the opening 104, so as to isolate the substrate 110 from the subsequent filling in the trench 103 and the opening. The metal material in the hole 104, the second back dielectric layer 140 may include at least one of silicon oxide, silicon nitride and silicon oxynitride; then, use an anisotropic etching process to remove the trench 103 and the The second back dielectric layer 140 on the bottom surface of the opening 104 is etched downwards, so that the depth of the opening 104 increases to expose the interconnection structure 121 in the front dielectric layer 120 (specifically, the interconnection structure 121 The conductive layer in), the trench 103 may not expose the interconnection structure 121 in the front dielectric layer 120 . The etching can remove the second back dielectric layer 140 covering the surface of the first back dielectric layer 130 , and the second back dielectric layer 140 only covers the sidewalls of the trench 103 and the opening 104 . In a direction parallel to the back surface of the pixel substrate 100 , the width of the trench 103 is, for example, close to or equal to the radial dimension of the opening 104 . The width of the trench 103 is, for example, in the range of 500-1200 nm, such as about 1 μm.

In this embodiment, in order to reduce the influence of the stress formed by the metal material subsequently filled in the trench 103 on the pixel substrate 100, when the second back dielectric layer 140 is formed on the inner wall of the trench 103, the process can be adjusted to , so that the part of the second back dielectric layer 140 covering the opening (top) of the sidewall of the trench 103 protrudes (towards the side away from the trench) from the part covering the sidewall of the trench 103 away from the opening. The direction of the wall protrudes), so that after covering the second back dielectric layer 140, the width of the opening of the trench 103 is smaller than the width of the trench 103 away from the opening, that is, the second back dielectric layer on the side wall of the trench 103 The layer 140 forms an overhang topography, the purpose of which is that when the metal material is filled in the trench 103 subsequently, since the opening of the trench 103 is narrower than the inside, when the interior of the trench 103 is not fully filled with the metal material The opening of the groove 103 is sealed so that an air gap is formed in the formed metal post, and the air gap helps to relieve the stress generated by the metal post. For example, the second back dielectric layer 140 may be formed by a chemical vapor deposition (CVD) process.

Referring to FIG. 5 , in another embodiment, in order to reduce the influence of the stress formed by the metal material filled in the trench 103 on the pixel substrate 100 , after etching the pixel substrate 100 and forming the trench 103 In the step, at least one stress isolation groove can be formed corresponding to the pixel region I and the peripheral circuit region II, and the stress isolation groove is located on the inner side and/or the outer side of the groove 103, that is, the stress isolation groove can be located on the Between the trench 103 and the pixel area I, the stress isolation groove may be located between the trench 103 and the peripheral circuit area II. After the dielectric material is filled in the stress isolation trench, a stress is formed. The barrier structure 105 , the stress barrier structure 105 can prevent the conduction of the stress formed by the metal material in the trench 103 . The stress barrier grooves may be filled by the second back dielectric layer 140 and/or other dielectric materials. Optionally, the width of the stress barrier groove is, for example, smaller than the width of the groove 103, so that on the one hand, it avoids affecting the chip size, and on the other hand, when depositing the above-mentioned second back dielectric layer 140, the second back surface can be directly used The dielectric layer 140 fills the stress isolation groove without additional deposition of dielectric material, which saves the process. In practical applications, the stress can be relieved by forming an air gap in the metal column formed in the trench 103 as required, or the stress isolation structure 105 can be formed on both sides of the trench 103 to block stress conduction, or both can be used. methods are adopted. Still based on the structure shown in FIG. 4 , the fabrication method of the back-illuminated CMOS image sensor according to the embodiment of the present invention will be described below.

Referring to FIG. 1 and FIG. 6, the manufacturing method of the back-illuminated CMOS image sensor according to the embodiment of the present invention includes a third step S3: forming a back metal layer 150, the back metal layer 150 fills the trench 103, and covers the For the first back dielectric layer 130 outside the trench 103 , the top surface of the back metal layer 150 is higher than the first back dielectric layer 130 .

The back metal layer 150 adopts a metal material with a light shielding function, such as a single metal (such as copper, nickel, zinc, tin, silver, gold, tungsten, magnesium, tantalum, titanium, molybdenum, platinum, aluminum, hafnium, ruthenium, etc. ) and at least one of alloys (such as copper alloys or aluminum alloys, etc.). In this embodiment, when the back metal layer 150 is formed, the back metal layer 150 is also filled in the opening 104 of the peripheral circuit area II to form a TSV via hole 154, and the back metal layer 150 can be selected from As for the metal material constituting the TSV via hole 154 , for example, the backside metal layer 150 includes tungsten.

In this embodiment, the back metal layer 150 filled in the groove 103 serves as a vertical shielding part to isolate the incident light outside the pixel region I from entering the pixel region I, and, in order to achieve a more comprehensive shielding effect, the A lateral shielding portion is formed on the first back dielectric layer 130 , therefore, the top surface of the deposited back metal layer 150 is higher than the first back dielectric layer 130 . In addition, by making the second back dielectric layer 140 on the sidewall of the trench 103 form an overhang topography and controlling the deposition conditions of the back metal layer 150, the back metal layer 150 filled in the trench 103 can be There is an air gap 106 inside, which helps to relieve the stress of the metal material.

Referring to FIG. 1 and FIG. 7, the manufacturing method of the back-illuminated CMOS image sensor according to the embodiment of the present invention includes a fourth step S4: patterning the back metal layer 150, and using the back metal layer 150 to form a A metal shielding layer 151 between I and the peripheral circuit area II, the metal shielding layer 151 includes a horizontal shielding portion 151a and a vertical shielding portion 151b, the horizontal shielding portion 151a is formed on the back side of the pixel substrate 100 and surrounds the pixel In region I, the vertical shielding portion 151b is formed in the trench 103 and connected to the horizontal shielding portion 151a at the back of the pixel substrate 100 .

It should be noted that although both the TSV via hole 154 and the vertical shielding portion 151b in the metal shielding layer 151 are formed by filling the trench (or opening) in the substrate with metal material, the TSV via hole 154 and the metal shielding layer The vertical shielding portion 151b of the layer 151 is essentially different. The metal shielding layer 151 is located between the pixel region I and the peripheral circuit region II. The substrate 110 region below the metal shielding layer 151 has a dark pixel (dark pixel) for signal black level calibration. , and the TSV via hole 154 is connected to the interconnection structure 121 formed in the front dielectric layer 120 for electrically leading out the interconnection structure 121 .

According to the number and shape of the grooves 103 , in the formed metal shielding layer 151 , the horizontal shielding portion 151 a can be connected to one or more vertical shielding portions 151 b on the back of the pixel substrate 100 . The vertical shielding portion 151b can be in a ring structure or a non-ring structure, so that the pixel area I can be surrounded by the ring-shaped vertical shielding portion 151b, or can be surrounded by a plurality of non-ring-shaped vertical shielding portions 151b.

Optionally, when the backside metal layer 150 is patterned, the backside metal layer 150 can also be used to form a metal grid 152 (Backside Metal Grid, BMG) located in the pixel area I and a metal grid 152 (BMG) located in the peripheral circuit area. II metal wire 153, to save the process.

Specifically, the fourth step S4 may include the following process: First, planarize the surface of the back metal layer 150 to make the thickness of the back metal layer 150 on the first back dielectric layer 130 uniform; Deposit a hard mask material layer 160 (silicon oxide, silicon nitride, or a combination thereof) on the 150; then, use photolithography and etching processes to pattern the hard mask material layer 160, and use the hard mask The material layer 160 is used as a mask, and the metal layer 150 on the back is etched to form a lateral shielding portion 151a between the pixel area I and the peripheral circuit area II. At the same time, the metal grid 152 is formed in the pixel area I and the peripheral circuit area II is formed. The metal wire 153 , the metal grid 152 is disposed corresponding to the gap area around each of the photo-sensing regions 101 , and the metal wire 153 is connected to the interconnection structure 121 through the above-mentioned TSV via hole 154 . The metal grid 152 isolates the light irradiated from the back to each photosensitive region 101 from each other, thereby defining different pixel points of the sensor.

In this embodiment, the horizontal shielding portion 151a is an annular structure surrounding the pixel region I, and covers the surface of the joint between the vertical shielding portion 151b and the horizontal shielding portion 151a. The inner boundary of the lateral shielding portion 151 a is adjacent to the boundary of the pixel region I, for example, located directly above the outermost deep trench isolation 102 of the pixel region I. The width of the lateral shielding portion 151a located on the inner side of the vertical shielding portion 151b (referring to the side facing the pixel region I) is about 5 μm to 15 μm, such as 10 μm. The width of the shielding portion 151a is about 5 μm˜15 μm, for example, 10 μm. Both the horizontal shielding part 151a and the vertical shielding part 151b have the function of shielding the peripheral light (or other noise factors) of the pixel region I from entering the pixel region I. function, while ensuring the shielding effect on the peripheral light of the pixel area I, the width of the lateral shielding portion 151a can be reduced, especially the width of the lateral shielding portion 151a located outside the vertical shielding portion 151b, so that the metal shielding layer 151 The occupied chip area is reduced, which is convenient to meet the requirement of further reducing the chip size. In addition, the vertical shielding portion 151b penetrates through at least part of the substrate 110, and also has a blocking effect on noise from the periphery of the pixel region I inside the substrate 110, thus helping to improve the performance of the sensor.

An embodiment of the present invention also relates to a back-illuminated CMOS image sensor, which can be manufactured using the above-mentioned back-illuminated CMOS image sensor manufacturing method. Referring to FIG. 7, the back-illuminated CMOS image sensor of the embodiment of the present invention includes a pixel substrate 100, a back dielectric layer (this embodiment may include a first back dielectric layer 130 and a second back dielectric layer 140) and a metal shielding layer 151; wherein , the pixel substrate 100 has a front surface and a back surface opposite to each other, the pixel substrate 100 includes a pixel area I and a peripheral circuit area II, and a plurality of photosensitive regions 101 are formed in the pixel region I, and the photosensitive regions 101 are used for For sensing incident light entering the pixel region I from the back of the pixel substrate 100, the back dielectric layer is formed on the back of the pixel substrate 100, and the metal shielding layer 151 is formed on the back dielectric layer and located Between the pixel area I and the peripheral circuit area II, the metal shielding layer 151 includes a horizontal shielding part 151a and a vertical shielding part 151b, the horizontal shielding part 151a is located on the back side of the pixel substrate 100 and surrounds the pixel region I, and the vertical shielding part 151a The shielding portion 151b is connected to the lateral shielding portion 151a at the back of the pixel substrate 100 and inserted into the pixel substrate 100 .

Specifically, the width of the horizontal shielding portion 151a is, for example, greater than the width of the vertical shielding portion 151b; and, in the metal shielding layer 151, the horizontal shielding portion 151a can be connected to one or more vertical shielding portions 151b on the back of the pixel substrate 100 . The vertical shielding portion 151b can be a ring structure or a non-ring structure; wherein, the pixel area I is surrounded by the vertical shielding portion 151b of the ring structure, and/or, the pixel area I is surrounded by a plurality of non-ring structure The longitudinal shielding portion 151b surrounds it.

In some embodiments, there may be an air gap 106 in the vertical shielding portion 151 b inserted into the pixel substrate 100 . The air gap 106 helps to relieve the stress formed by the metal material of the longitudinal shielding portion 151b. In some embodiments (refer to FIG. 5 ), the back-illuminated CMOS image sensor may include a stress isolation groove, and the stress isolation groove is disposed on the inner side (the side facing the pixel region I) and/or the outer side of the vertical shielding portion 151b. (the side away from the pixel area I), the back dielectric layer formed on the back of the pixel substrate 100 (specifically, for example, the second back dielectric layer 140, the second back dielectric layer 140 also covers the area where the vertical shielding portion 151b is located) The side wall of the groove 103) can fill the stress barrier groove, thereby forming the stress barrier structure 105, the stress barrier structure 105 has the function of blocking the stress conduction formed by the metal material of the vertical shielding portion 151b, thus reducing the impact of the vertical shielding portion on The effect of stress within the pixel substrate.

The pixel substrate 100 may include a substrate 110, a front dielectric layer 120 disposed on the front of the substrate 110, and an interconnection structure 121 disposed in the front dielectric layer 120, and the vertical shielding portion in the metal shielding layer 151 151b, for example, penetrates through the substrate 110 (along the thickness direction), and may further penetrate part of the front dielectric layer 120 .

The back-illuminated CMOS image sensor of the embodiment of the present invention may also include a metal wire 153 and a TSV via hole 154 arranged corresponding to the peripheral circuit area II, the metal wire 153 is arranged on the back side of the pixel substrate 100, and the TSV via hole 154 penetrates through the substrate 110 and connects the interconnection structure 121 on the front side of the pixel substrate 100 to the metal wire 153 on the back side of the pixel substrate 100 . The trench 103 where the vertical shielding portion 151b is located and the opening corresponding to the TSV via hole 154 can be formed by the same etching process, so the depth of the vertical shielding portion 151b and the TSV via hole 154 in the pixel substrate 100 can be the same. .

In addition, the back-illuminated CMOS image sensor of the embodiment of the present invention may also include a metal grid 152 and a deep trench isolation 102 arranged corresponding to the pixel region I, and the deep trench isolation 102 corresponds to the gap at the periphery of each photo-sensing region 101 Embedded in the pixel substrate 100 from the back of the pixel substrate 100 , the metal grid 152 is arranged on the back side of the pixel substrate 100 corresponding to the gaps around the periphery of each photo-sensing region 101 and separated from the first back dielectric layer 130 .

The back-illuminated CMOS image sensor described in the embodiment of the present invention includes a pixel substrate 100, a back dielectric layer formed on the back of the pixel substrate 100, and a metal shielding layer 151, and the metal shielding layer 151 is formed on the pixel substrate 100 with the back dielectric layer separated. Between the pixel area I and the peripheral circuit area II on the back, the metal shielding layer 151 includes a horizontal shielding portion 151a and a vertical shielding portion 151b, the horizontal shielding portion 151a is located on the back side of the pixel substrate 100 and surrounds the pixel region I, so The vertical shielding portion 151b is connected to the surface of the horizontal shielding portion 151a facing the pixel substrate 100 and inserted into the pixel substrate 100 . Both the horizontal shielding part 151a and the vertical shielding part 151b have the function of shielding the light around the pixel area I from entering the pixel area I. Compared with the case where only the horizontal shielding part is provided, the width of the horizontal shielding part can be shortened, so that the metal shielding layer The chip area occupied by the 151 is reduced, which is convenient to meet the requirement of further reducing the chip size.

The above description is only a description of the preferred embodiments of the present invention, and is not any limitation to the scope of rights of the present invention. Anyone skilled in the art can use the methods and technical contents disclosed above to analyze the present invention without departing from the spirit and scope of the present invention. Possible changes and modifications are made in the technical solution. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention, which do not depart from the content of the technical solution of the present invention, all belong to the technical solution of the present invention. protected range.

Claims (13)

1. A back-illuminated CMOS image sensor, characterized in that, comprising: A pixel substrate, the pixel substrate has opposite front and back, the pixel substrate includes a pixel region and a peripheral circuit region, a plurality of photosensitive regions are formed in the pixel region, and the photosensitive regions are used for sensing measuring incident light entering the pixel region from the backside of the pixel substrate; and a back dielectric layer formed on the back of the pixel substrate; and a metal shielding layer, formed on the back dielectric layer and located between the pixel region and the peripheral circuit region, the metal shielding layer includes a lateral shielding portion and a vertical shielding portion, and the lateral shielding portion is located at the pixel The back side of the base surrounds the pixel area, and the vertical shielding part is connected to the horizontal shielding part on the back side of the pixel base and inserted into the pixel base. 2. The back-illuminated CMOS image sensor according to claim 1, wherein the width of the horizontal shielding portion is greater than the width of the vertical shielding portion; in the metal shielding layer, the horizontal shielding portion The back surface of the pixel substrate is connected with one or more of the vertical shielding parts. 3. The back-illuminated CMOS image sensor according to claim 2, wherein the vertical shielding portion is a ring structure or a non-ring structure; wherein the pixel region is surrounded by the vertical shielding portion of the ring structure, And/or, the pixel area is surrounded by a plurality of the longitudinal shielding portions of non-ring structure. 4. The back-illuminated CMOS image sensor according to claim 1, wherein there is an air gap in the vertical shield inserted into the pixel substrate. 5. The back-illuminated CMOS image sensor according to claim 1, further comprising: The stress isolation groove is located on the inner side and/or the outer side of the longitudinal shielding portion, and the back dielectric layer fills the stress isolation groove. 6. The back-illuminated CMOS image sensor according to claim 1, wherein the pixel base comprises a substrate, a front dielectric layer disposed on the front side of the substrate, and an interconnect layer disposed in the front dielectric layer. A connecting structure, the vertical shielding portion penetrates through the substrate. 7. The back-illuminated CMOS image sensor according to claim 6, further comprising: a metal wire disposed on the back side of the pixel substrate corresponding to the peripheral circuit area; and A TSV via hole is arranged corresponding to the peripheral circuit area and runs through the substrate, the TSV via hole connects the interconnection structure and the metal wire, and the vertical shielding portion is connected to the TSV via hole same depth. 8. A method for manufacturing a back-illuminated CMOS image sensor, comprising: A pixel substrate is provided, the pixel substrate has opposite front and back surfaces, the pixel substrate includes a pixel region and a peripheral circuit region, a plurality of photosensitive regions are formed in the pixel region, and the photosensitive regions are used for sensing incident light entering the pixel region from the back of the pixel substrate; Form a first back dielectric layer on the back of the pixel substrate, and etch the pixel substrate from the back of the pixel substrate to form at least a part of the pixel substrate through the groove, the groove corresponds to the pixel A region between the region and the peripheral circuit region is formed, and then a second back dielectric layer is deposited on the inner wall of the trench; forming a back metal layer, the back metal layer fills the trench and covers the first back dielectric layer outside the trench, the top surface of the back metal layer is higher than the first back dielectric layer; as well as performing patterning on the back metal layer, using the back metal layer to form a metal shielding layer located between the pixel region and the peripheral circuit region, the metal shielding layer comprising a lateral shielding portion and a vertical shielding portion, The horizontal shielding portion is formed on the back side of the pixel substrate and surrounds the pixel region, and the vertical shielding portion is formed in the groove and connected to the horizontal shielding portion on the backside of the pixel substrate. 9. The manufacturing method according to claim 8, wherein the pixel base comprises a substrate, a front dielectric layer disposed on the front side of the substrate, and an interconnection structure disposed in the front dielectric layer , the vertical shielding portion penetrates the substrate; Wherein, in the step of etching the pixel substrate from the back surface of the pixel substrate to form the trench, an opening through the substrate is formed corresponding to the peripheral circuit region, and the opening exposes the interconnect connection structure, and, when forming the back metal layer, the back metal layer also fills the openings to form TSV vias. 10. The manufacturing method according to claim 9, wherein when the back metal layer is patterned, the back metal layer is also used to form a metal grid located in the pixel area and a metal grid located in the peripheral area. Metal wires in the circuit area; the metal grid is arranged corresponding to the gap area around each of the photo-sensing areas, and the metal wires are connected to the interconnection structure through the TSV via holes. 11 . The manufacturing method according to claim 9 , wherein, before patterning the back metal layer, the surface of the back metal layer is also planarized. 11 . 12. The manufacturing method according to claim 8, wherein the part of the second back dielectric layer covering the opening of the sidewall of the trench protrudes more than the part covering the sidewall of the trench away from the opening , so that the width at the opening of the groove is smaller than the width of the groove away from the opening, so that there is an air gap in the longitudinal shielding portion formed in the groove. 13. The manufacturing method according to claim 8, wherein, in the step of etching the pixel substrate from the back surface of the pixel substrate to form the trench, corresponding to the pixel region and the peripheral circuit The regions between the regions form stress-blocking grooves, the stress-blocking grooves are located on the inside and/or outside of the grooves, and the width of the stress-blocking grooves is smaller than the width of the grooves, so that When the second back dielectric layer is deposited on the inner wall, the second back dielectric layer fills the stress isolation groove to form a stress isolation structure.

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