CN115459554B - Method for Eliminating False Pulses of Secondary-Side Synchronous Rectification Signals in Bidirectional CLLC Resonant Converters - Google Patents
Method for Eliminating False Pulses of Secondary-Side Synchronous Rectification Signals in Bidirectional CLLC Resonant Converters Download PDFInfo
- Publication number
- CN115459554B CN115459554B CN202211161057.0A CN202211161057A CN115459554B CN 115459554 B CN115459554 B CN 115459554B CN 202211161057 A CN202211161057 A CN 202211161057A CN 115459554 B CN115459554 B CN 115459554B
- Authority
- CN
- China
- Prior art keywords
- circuit
- signal
- current
- synchronous rectification
- secondary side
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000001360 synchronised effect Effects 0.000 title claims abstract description 72
- 230000002457 bidirectional effect Effects 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 title claims abstract description 26
- 230000000630 rising effect Effects 0.000 claims abstract description 31
- 238000001514 detection method Methods 0.000 claims abstract description 24
- 238000007493 shaping process Methods 0.000 claims abstract description 6
- 239000003990 capacitor Substances 0.000 claims description 20
- 238000007600 charging Methods 0.000 claims description 5
- 230000003111 delayed effect Effects 0.000 claims description 3
- 238000005070 sampling Methods 0.000 claims description 2
- 230000001960 triggered effect Effects 0.000 claims description 2
- 230000003071 parasitic effect Effects 0.000 abstract description 6
- 230000010355 oscillation Effects 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000008030 elimination Effects 0.000 description 3
- 238000003379 elimination reaction Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000007599 discharging Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004146 energy storage Methods 0.000 description 2
- 230000005284 excitation Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0038—Circuits or arrangements for suppressing, e.g. by masking incorrect turn-on or turn-off signals, e.g. due to current spikes in current mode control
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/01—Resonant DC/DC converters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/22—Conversion of DC power input into DC power output with intermediate conversion into AC
- H02M3/24—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters
- H02M3/28—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC
- H02M3/325—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/3353—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having at least two simultaneously operating switches on the input side, e.g. "double forward" or "double (switched) flyback" converter
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
- Rectifiers (AREA)
Abstract
The invention relates to the field of DC/DC converters, and aims to provide a method for eliminating false pulses of secondary synchronous rectification signals in a bidirectional CLLC resonant converter. The method is realized based on a synchronous rectification control circuit and comprises a current detection circuit, a first current polarity comparator, an error pulse eliminating circuit and a synchronous rectification signal generating circuit which are electrically connected in sequence, wherein the error pulse eliminating circuit comprises a rising edge delay filter circuit, a falling edge PMOS instant triggering circuit and a signal shaping circuit which are sequentially arranged. The invention can be connected behind the secondary side resonance current polarity comparator of the traditional bidirectional CLLC resonance circuit in an electric connection mode, can eliminate the influence of parasitic parameters in current, and realizes the improvement of efficiency on the premise of ensuring the normal operation of the circuit.
Description
Technical Field
The invention relates to the field of DC/DC converters, in particular to a method for eliminating false pulses of secondary synchronous rectification signals in a bidirectional CLLC resonant converter, which is applied to a plurality of occasions such as micro-grid operation, electric automobile charging and discharging, energy storage systems and the like.
Background
The bidirectional CLLC resonant converter (circuit) is a common bidirectional isolation DC/DC conversion topology at present, and has the excellent characteristics of soft switch in full power range, small off current at the moment of switch action and small circulation of a primary bridge arm, thereby meeting the requirements of people on high efficiency and high power density of the electric energy converter, and being applied to the scenes of new energy power generation and electric energy storage, bidirectional charging and discharging of electric automobiles, micro power grids and the like on a large scale. However, the traditional bidirectional CLLC resonant circuit controls the output power of the converter by adjusting the switching frequency, that is, a square wave driving signal with a duty ratio of 0.5 is applied to the primary side switching tube, the secondary side switching tube has no driving signal, and the body diode is used for uncontrolled rectification. However, the bidirectional CLLC resonant circuit generally adopts a MOSFET as a switching tube, and its body diode has a larger conduction voltage drop, and generates a larger loss when passing a larger current, which reduces the efficiency of the converter and causes a heat dissipation problem.
Synchronous rectification technology is a common method for solving the problem of rectifying loss of a MOSFET body diode, and has been applied to various circuits. The synchronous rectification technology transfers the current which originally passes through the MOSFET body diode into a channel, and the conduction loss caused by the channel resistance under the condition of large current is smaller than that of the body diode, so that the work efficiency of the circuit is improved. Because the channel is conducted by applying a driving signal to the MOSFET, the key to the implementation of the synchronous rectification technology is that the channel of the MOSFET is conducted by the driving signal when the body diode is required to be conducted, and the wrong driving signal affects the normal operation of the circuit, so that the occurrence of the error condition needs to be avoided.
Compared with other DC/DC converters adopting PWM duty ratio and phase shift control, in the bidirectional CLLC resonant circuit, the time sequence relation between the on and off moments of the body diode of the secondary side and the driving signal of the MOSFET of the primary side is complex. In order to obtain accurate secondary synchronous rectification on-off signals, the traditional scheme is to sample secondary resonance current, and compare the parts larger than 0 and smaller than 0 to be respectively used as driving signals of upper and lower tubes of a secondary rectifier bridge. However, when the bidirectional CLLC resonant circuit works in an under-resonant mode, that is, when the switching frequency is smaller than the resonant frequency, a section of secondary side resonant cavity does not participate in the interruption condition of primary side resonance under ideal conditions, and the secondary side resonant current is zero. Because passive parameters such as resonance inductance, resonance capacitance, parasitic capacitance of MOSFET, interlayer capacitance between primary side and secondary side of the transformer exist on the secondary side of the bidirectional CLLC resonance circuit, current oscillation can be generated near zero on the secondary side when primary side resonance is not participated. The detection circuit is affected by the oscillation to generate wrong driving signal pulses, so that the secondary rectifying MOSFET is conducted for a plurality of times in one switching period, and extra switching loss is caused.
Therefore, in the bidirectional CLLC resonant converter, the conventional synchronous rectification generating scheme based on current detection is affected by passive parameters in the circuit, and the same efficiency improvement effect as that of other conventional circuits is difficult to achieve. Thus, improvements to existing synchronous rectification techniques are needed.
Disclosure of Invention
The invention aims to solve the technical problem of overcoming the defects in the prior art and providing a method for eliminating false pulses of secondary synchronous rectification signals in a bidirectional CLLC resonant converter.
In order to solve the technical problems, the invention adopts the following solutions:
Firstly, a synchronous rectification control circuit for eliminating false pulses of secondary side synchronous rectification signals in a bidirectional CLLC resonant converter is provided, and comprises a current detection circuit, a first current polarity comparator, a false pulse eliminating circuit and a synchronous rectification signal generating circuit which are electrically connected in sequence, wherein the false pulse eliminating circuit comprises a rising edge time delay filter circuit, a falling edge PMOS instant trigger circuit and a signal shaping circuit which are sequentially arranged.
As a preferred embodiment of the present invention, the false pulse cancellation circuit specifically includes:
one end of the first branch is connected with the output end of the first current polarity comparator, the other end of the first branch is connected with the input end of the second current polarity comparator, and a resistor R is arranged on the first branch;
The system comprises a first current polarity comparator, a second branch, a PNP triode, a diode, a C electrode and a diode anode, wherein one end of the first branch is connected with the output end of the first current polarity comparator, and the other end of the first branch is connected with the G electrode in the PMOS tube;
and one end of the capacitor C is connected to the input end of the second current polarity comparator, and the other end of the capacitor C is grounded.
The invention further provides a bidirectional CLLC resonant converter capable of eliminating false pulses of secondary side synchronous rectification signals, which comprises a power circuit part and a synchronous rectification control circuit, wherein the power circuit part consists of a primary side bridge, a secondary side bridge and a CLLC resonant cavity, and the synchronous rectification control circuit is used for sampling secondary side resonant current and providing secondary side bridge switching tube driving signals, and is characterized in that the specific circuit structure of the synchronous rectification control circuit is as described above.
Further, the invention provides a method for eliminating false pulses of secondary synchronous rectification signals in a bidirectional CLLC resonant converter based on the synchronous rectification control circuit, which comprises the following steps:
(1) Acquiring a polarity signal of the secondary side resonance current
The method comprises the steps of detecting a scaled signal i s of a secondary side resonance current i Lrs by a current detection circuit connected to a secondary side of a bidirectional CLLC resonance converter, comparing the scaled signal i s with a first threshold value by a first current polarity comparator to generate a polarity signal i Pol of the secondary side resonance current, wherein the polarity signal i Pol comprises a correct driving signal and an error pulse signal;
(2) Secondary resonant current polarity signal rising edge delay
When the scaled signal i s of the secondary side resonance current is larger than a first threshold value, the first current polarity comparator outputs a high-level signal, the high-level signal is transmitted to the G pole of the PMOS, the PMOS tube is turned off, the S pole voltage of the PMOS tube charges the capacitor C through the resistor R by the high-level signal output by the first current polarity comparator, and the rising edge rate of the polarity signal is delayed through the charging process;
(3) Instant trigger of secondary side resonance current polarity signal falling edge
When the scaled signal i s of the secondary side resonance current is smaller than a first threshold value, the first current polarity comparator outputs a low-level signal, the low-level signal is transmitted to the G pole of the PMOS, the PMOS tube is conducted, the PMOS tube discharges the charge accumulated on the capacitor C, and the level of the S pole is immediately reduced to 0;
Through the steps (2) and (3), compared with the original secondary side resonance current polarity signal i Pol, the rising edge of the S-pole voltage V PMOS of the PMOS tube is shaped into a slowly rising state, and the falling edge is basically the same as the original signal;
(4) Synchronous rectification driving signal after eliminating false pulse
The output voltage V PMOS of the PMOS tube is compared with a second threshold value by using a second current polarity comparator, the rising edge of V PMOS is slow, the error pulse cannot rise from 0 to the second threshold value within the delay time t d of the rising edge, the second current polarity comparator cannot be triggered to generate high level to be filtered, and the second current polarity comparator outputs a level signal which is used as a synchronous rectification driving signal of a switching tube on a corresponding bridge arm in a secondary side bridge of the bidirectional CLLC resonant converter, so that the error pulse in the secondary side synchronous rectification signal is eliminated.
In the bidirectional CLLC resonant converter, the secondary resonant inductor current required by the synchronous rectification driving signals of the upper tube and the lower tube of the secondary rectifier bridge has opposite polarities, and the control method is the same.
In the preferred embodiment of the present invention, in step (1), the current detection circuit uses a current transformer or rogowski coil for detection.
In a preferred embodiment of the present invention, in the step (1), the scaling of the secondary resonant current i Lrs is determined by the component parameters of the current detection circuit, and the maximum value of the scaling signal i s does not exceed the maximum operating voltage V max of the first current polarity comparator, and the specific value of the maximum operating voltage is determined by the comparator model and the supply voltage.
In a preferred embodiment of the present invention, in the step (1), the theoretical value of the first threshold is 0, and the actual circuit is generally set to a value slightly greater than 0 (typically 0.1).
In the preferred embodiment of the present invention, in the step (2), the value of the capacitor C is determined by the load capacity of the first current polarity comparator, typically 1nF, and the value of the resistor R is determined by the required rising edge delay time T d, and r=t d/3C;td is also the maximum pulse width error that can be eliminated by the pulse error elimination circuit, and typically 5% of the switching period T s.
In the step (4), the value of the second threshold is 95% of the maximum operating voltage V max of the second current polarity comparator.
Compared with the prior art, the invention has the beneficial effects that:
1. In the prior art, a primary side variable frequency control bidirectional CLLC resonant circuit is adopted, and a secondary side resonant inductance and parasitic parameters in an actual circuit of the bidirectional CLLC resonant circuit cause resonant current oscillation. The traditional synchronous rectification scheme based on high-frequency secondary side resonance current detection can generate wrong synchronous rectification driving signals, and the normal operation of the circuit is affected. The false pulse eliminating circuit for the synchronous rectification signal of the secondary side can eliminate the influence of parasitic parameters in current.
2. The invention starts from the secondary side resonance circuit of the bidirectional CLLC resonance circuit, and transmits accurate synchronous rectification signals to the secondary side MOSFET of the bidirectional CLLC resonance circuit through the signal processing of the high-frequency resonance current detection circuit, the synchronous rectification signal trigger circuit and the synchronous rectification misoperation eliminating circuit, thereby realizing the efficiency improvement on the premise of ensuring the normal operation of the circuit.
3. The invention can be connected with the secondary side resonance current polarity comparator of the traditional bidirectional CLLC resonance circuit in a simple electric connection mode. The delay filter circuit is used for delaying the rising rate of the rising edge of the output signal of the secondary side resonance current polarity comparator. The delay filter circuit has the same delay effect on the falling rate of the falling edge of the square wave output by the secondary side resonance current polarity comparator, and the falling edge PMOS instant trigger circuit is used for eliminating the influence. The signal shaping circuit is used for reshaping the signal with the slow rising edge into a square wave signal which is easy to be identified by a later-stage driving chip.
Drawings
FIG. 1 is a diagram of a typical conventional synchronous rectification circuit of a bidirectional CLLC resonant converter based on resonant current detection;
FIG. 2 is a diagram of a synchronous rectification circuit of a bidirectional CLLC resonant converter with false pulse elimination function based on resonant current detection according to the present invention;
Fig. 3 is a waveform of the operation of the secondary side synchronous rectification signal false pulse eliminating circuit applied to the bidirectional CLLC resonant circuit according to the present invention.
Detailed Description
The invention will be further described with reference to specific examples, but the scope of the invention is not limited thereto.
A circuit diagram of a typical conventional bidirectional CLLC resonant converter based on resonant current detection is shown in fig. 1, and is divided into a power circuit part and a synchronous rectification control circuit part. the power circuit part comprises a primary side bridge, The secondary bridge and the CLLC resonant cavity are formed, the power transmission direction from left to right is positive, V p and C p are primary side input voltage and input bus capacitance, and V s and C s are secondary side output voltage and output bus capacitance. The switching tube S 1～S4 forms a primary bridge, S 1 is an upper tube of a first bridge arm of the primary bridge, S 2 is a lower tube of the first bridge arm of the primary bridge, S 3 is an upper tube of a second bridge arm of the primary bridge, and S 4 is a lower tube of the second bridge arm of the primary bridge. The switch tubes S 5～S8 form a secondary bridge, S 5 is an upper tube of a first bridge arm of the secondary bridge, S 6 is a lower tube of the first bridge arm of the secondary bridge, S 7 is an upper tube of a second bridge arm of the secondary bridge, and S 8 is a lower tube of the second bridge arm of the secondary bridge. MOSFETs are commonly used as switching tubes in CLLC circuits. The primary side resonance inductor L rp, the primary side resonance capacitor C rp, the secondary side resonance inductor L rs, the secondary side resonance capacitor C rs and the transformer form a CLLC resonant cavity, wherein L m is the equivalent primary side excitation inductor of the transformer. the synchronous rectification control circuit part comprises a current detection circuit, a current polarity comparator and a synchronous rectification signal generation circuit.
Taking a forward power transmission mode as an example, the controller controls the primary bridge S 1～S4 according to the current circuit state and the circuit working target, the control signal is a square wave signal with the duty ratio of 50%, and the working frequency is determined by the current state of the circuit and the circuit working target, wherein the driving signals of S 1 and S 4 are the same, the driving signals of S 2 and S 3 are the same, and the driving signals of S 1 and S 2 are complementary. The primary side driving signal controls the switching tubes of the primary side bridge to conduct orderly, and square wave voltage V AB with the maximum value of input voltage V p is generated between the points A and B. The square wave voltage V AB as an excitation generates a load dependent current on the resonant cavity and the secondary bridge, i.e. transfers the energy of the primary side to the secondary side. When synchronous rectification control is not adopted to improve the working efficiency of the circuit, the secondary side current passes through the body diode of the secondary side rectifier bridge S 5～S8, wherein the body diodes of S 5 and S 8 are conducted simultaneously, the body diodes of S 6 and S 7 are conducted simultaneously, and the body diodes of S 5 and S 6 are conducted alternately. When synchronous rectification control is adopted, when the body diode of S 5～S8 needs to be conducted, the channel of S 5～S8 replaces the body diode to conduct through a proper driving signal for S 5～S8.
In the scheme shown in fig. 1, the secondary side resonant current i Lrs flowing through the secondary side resonant inductor L rs is subjected to current detection, and then the secondary side resonant current i Lrs is compared with a given threshold value to obtain a current polarity signal, which is a synchronous rectification signal. However, due to the resonant inductance on the secondary side of the bi-directional CLLC resonant converter, the secondary side resonant inductance will oscillate with the parasitic capacitance of the secondary side switching tube S 5～S8. In particular, when the circuit is operated in an under-resonant mode, i.e., the switching frequency f s is less than the resonant frequency f r, the secondary side resonant current oscillates near zero, which can be passed through the comparator to output an erroneous drive signal. The wrong driving signal can cause the secondary side switching tube to act for a plurality of times in one switching period, so that extra switching loss is caused, and the electric energy conversion efficiency is affected.
Fig. 2 is a diagram of a synchronous rectification circuit of a bidirectional CLLC resonant converter with false pulse cancellation based on resonant current detection according to the present invention. Compared with the conventional scheme in fig. 1, a false pulse eliminating circuit is added between the first current polarity comparator and the synchronous rectification signal generating circuit. The output of the first current polarity comparator is split into two branches. The first branch is used for transmitting a G pole driving signal of the PMOS tube, and the PMOS is conducted when the G pole driving signal is in a low level, so that the voltage on the capacitor C is rapidly released through the PMOS tube. The voltage signal on the capacitor C is compared with a second threshold value through a second current polarity comparator, the output waveform of the second current polarity comparator is a reliable synchronous rectification driving signal after the false pulse is eliminated, and the driving signal for driving the switching tube can be obtained through a synchronous rectification signal generating circuit.
Fig. 3 is an operational waveform of the secondary synchronous rectification signal false pulse eliminating circuit applied to the bidirectional CLLC resonant converter proposed in the present invention. G 14 is a driving signal of the primary side switching transistors S 1 and S 4, i s is a scaled signal of the secondary side resonant current, i Pol is a secondary side resonant current polarity signal containing an error pulse generated after the scaled signal of the secondary side resonant current is compared with a first threshold value by a first current polarity comparator, and V PMOS is a voltage waveform of the S pole of PMOS. G 58 is the synchronous rectified drive signal for the secondary side switching tubes S 5 and S 8, and G 67 is the synchronous rectified drive signal for the secondary side switching tubes S 6 and S 7. time t 1 is the on time of the primary side switching tube driving signal, time t 2 is the on time of the secondary side switching tube synchronous rectification driving signal, time interval t d from t 1 to t 2 is rising edge delay time formed by resistor R and capacitor C, time t 3 is the off time of the secondary side switching tube synchronous rectification driving signal, time t 4 is the off time of the primary side switching tube driving signal, and time interval from t 3 to t 4 is a time period when obvious parasitic oscillation exists in a circuit and error pulses are generated.
The specific false pulse eliminating method provided by the invention comprises the following steps:
and step 1, acquiring a polarity signal of the secondary side resonance current.
The current detection circuit connected to the secondary side of the bidirectional CLLC resonant converter is used for obtaining a scaled signal i s of a secondary side resonant current i Lrs, the scaled signal i s of the secondary side resonant current is compared with a first threshold value through a first current polarity comparator to generate a polarity signal i Pol of the secondary side resonant current, and the polarity signal i Pol comprises correct driving signals in the time points t 1 to t 3 and error pulse signals in the time points t 3 to t 4. The scaling of the secondary side resonant current i Lrs is determined by the component parameters of the current detection circuit, the maximum value of the signal i s after the scaling is required to be satisfied does not exceed the maximum operating voltage V max of the comparator, and the maximum operating voltage of the comparator is determined by the type of the comparator and the power supply voltage. The theoretical value of the first threshold is 0, and the actual circuit is generally set to a value slightly greater than 0, typically 0.1.
And 2, delaying the rising edge of the secondary side resonance current polarity signal.
When the scaled signal i s of the secondary side resonant current is greater than the first threshold, the first current polarity comparator outputs a high level signal. The output high-level signal is connected to the G pole of the PMOS, the PMOS is turned off at the moment, the S pole voltage of the PMOS charges the capacitor C through the resistor R by the output high-level signal of the first current polarity comparator, and the charging process delays the rising edge rate of the polarity signal. The value of the capacitor C is determined by the load capacity of the first current polarity comparator, and is typically 1nF. The value of the resistor R is determined by the required rising edge delay time T d, and r=t d/3C.td is also the maximum pulse width error that can be eliminated by the pulse error elimination circuit, and its typical value is 5% of the switching period T s.
And 3, triggering the falling edge of the secondary side resonance current polarity signal in real time.
When the scaled signal i s of the secondary side resonant current is smaller than the first threshold, the first current polarity comparator outputs a low level signal. The output low level signal is connected to the G pole of the PMOS, the PMOS is conducted at this time, the PMOS discharges the charge accumulated on the capacitor C, and the level of the S pole immediately drops to 0.
After steps 2 and 3, the rising edge of the S-pole voltage V PMOS of the PMOS is shaped to be a slow rising state compared with the original secondary side resonant current polarity signal i Pol, and the falling edge is substantially the same as the original signal.
And 4, eliminating the synchronous rectification driving signal after the false pulse.
The PMOS output voltage V PMOS is compared with a second threshold value by a second current polarity comparator, which typically takes a value of 95% of the maximum operating voltage V max of the comparator. Since the rising edge of V PMOS is slow, the false pulses cannot rise from 0 to the second threshold within the rising edge delay time td, and these false pulses cannot trigger the second current polarity comparator to generate a high level to be filtered. The rising edge of the reliable synchronous rectified polarity signal G 58 output by the second current polarity comparator is delayed by a time t d relative to the original secondary side resonant current polarity signal i Pol, and the falling edge is substantially unchanged. G 58 is a synchronous rectification driving signal of the switching tubes S 5 and S 8, G 67 is a synchronous rectification driving signal of the switching tubes S 6 and S 7, the acquisition method of G 67 is similar to that of G 58, only polarity comparison logic is opposite, and redundant description is omitted.
Based on the above, the circuit is sequentially composed of a rising edge delay filter circuit, a falling edge PMOS instant trigger circuit and a signal shaping circuit, and the circuit and the traditional bidirectional CLLC resonant circuit, the traditional high-frequency resonant current detection circuit and the traditional synchronous rectification signal trigger circuit realize the accurate synchronous rectification function of the optimized bidirectional CLLC resonant circuit. The invention is used in a bidirectional CLLC resonance circuit, can eliminate the influence of synchronous rectification false pulse caused by current oscillation in an actual circuit, improves the electric energy conversion efficiency and ensures the stable operation of the circuit.
The secondary synchronous rectification signal false pulse eliminating circuit and method applied to the bidirectional CLLC resonant converter can eliminate the false pulse of the synchronous rectification signal under the condition of not depending on a central digital controller, thereby obtaining a reliable synchronous rectification control signal and further effectively improving the conversion efficiency of the circuit.
Finally, it should also be noted that the above list is merely a few specific embodiments of the present invention. It will be apparent that the invention is not limited to the above embodiments, but may be varied and substituted for similar components. For example, the invention adopts PMOS as the falling edge instant trigger control element, and the PMOS can be replaced by PNP triode with similar performance. All modifications directly derived or suggested to one skilled in the art from the present disclosure should be considered as being within the scope of the present invention.
Claims (9)
1. The synchronous rectification control circuit for eliminating false pulses of secondary synchronous rectification signals in the bidirectional CLLC resonant converter is characterized by comprising a current detection circuit, a first current polarity comparator, a false pulse eliminating circuit and a synchronous rectification signal generating circuit which are electrically connected in sequence, wherein the false pulse eliminating circuit consists of a rising edge time delay filter circuit, a falling edge PMOS instant trigger circuit and a signal shaping circuit which are sequentially arranged;
The false pulse eliminating circuit specifically comprises a first branch, a second branch and a third branch, wherein one end of the first branch is connected with the output end of a first current polarity comparator, the other end of the first branch is connected with the input end of a second current polarity comparator, and a resistor R is arranged on the first branch; one end of the second branch is connected with the output end of the first current polarity comparator, and the other end of the second branch is connected with the G pole in the PMOS tube; the PMOS tube comprises a body diode, a capacitor C, a capacitor and a capacitor, wherein the S electrode and the diode cathode of the body diode are connected to the input end of the second current polarity comparator, and the D electrode and the diode anode are grounded;
The resistor R and the capacitor C form a rising edge delay filter circuit, the PMOS tube forms a falling edge PMOS instant trigger circuit, and the second current polarity comparator forms a signal shaping circuit.
2. A bidirectional CLLC resonant converter capable of eliminating false pulses of secondary side synchronous rectification signals comprises a power circuit part formed by a primary side bridge, a secondary side bridge and a CLLC resonant cavity, and a synchronous rectification control circuit for sampling secondary side resonance current and providing secondary side bridge switching tube driving signals, wherein the specific circuit structure of the synchronous rectification control circuit is as set forth in claim 1.
3. The method for eliminating false pulses of secondary synchronous rectification signals in a bidirectional CLLC resonant converter based on the synchronous rectification control circuit of claim 1, comprising the steps of:
(1) Acquiring a polarity signal of the secondary side resonance current
The method comprises the steps of detecting a scaled signal i s of a secondary side resonance current i Lrs by a current detection circuit connected to a secondary side of a bidirectional CLLC resonance converter, comparing the scaled signal i s with a first threshold value by a first current polarity comparator to generate a polarity signal i Pol of the secondary side resonance current, wherein the polarity signal i Pol comprises a correct driving signal and an error pulse signal;
(2) Secondary resonant current polarity signal rising edge delay
When the scaled signal i s of the secondary side resonance current is larger than a first threshold value, the first current polarity comparator outputs a high-level signal, the high-level signal is transmitted to the G pole of the PMOS, the PMOS tube is turned off, the S pole voltage of the PMOS tube charges the capacitor C through the resistor R by the high-level signal output by the first current polarity comparator, and the rising edge rate of the polarity signal is delayed through the charging process;
(3) Instant trigger of secondary side resonance current polarity signal falling edge
When the scaled signal i s of the secondary side resonance current is smaller than a first threshold value, the first current polarity comparator outputs a low-level signal, the low-level signal is transmitted to the G pole of the PMOS, the PMOS tube is conducted, the PMOS tube discharges the charge accumulated on the capacitor C, and the level of the S pole is immediately reduced to 0;
Through the steps (2) and (3), compared with the original secondary side resonance current polarity signal i Pol, the rising edge of the S-pole voltage V PMOS of the PMOS tube is shaped into a slowly rising state, and the falling edge is basically the same as the original signal;
(4) Synchronous rectification driving signal after eliminating false pulse
The output voltage V PMOS of the PMOS tube is compared with a second threshold value by using a second current polarity comparator, the rising edge of V PMOS is slow, the error pulse cannot rise from 0 to the second threshold value within the delay time t d of the rising edge, the second current polarity comparator cannot be triggered to generate high level to be filtered, and the second current polarity comparator outputs a level signal which is used as a synchronous rectification driving signal of a switching tube on a corresponding bridge arm in a secondary side bridge of the bidirectional CLLC resonant converter, so that the error pulse in the secondary side synchronous rectification signal is eliminated.
4. A method according to claim 3, wherein in the bidirectional CLLC resonant converter, the secondary resonant inductor current required for synchronous rectification driving signals of the upper and lower tubes of the secondary rectifier bridge has opposite polarities and the control method is the same.
5. A method according to claim 3, wherein in step (1) the current detection circuit uses a current transformer or rogowski coil for detection.
6. A method according to claim 3, wherein in step (1), the scaling of the secondary resonant current i Lrs is determined by the component parameters of the current detection circuit, the maximum value of the scaling signal i s does not exceed the maximum operating voltage V max of the first current polarity comparator, the specific value of the maximum operating voltage being determined by the comparator model and the supply voltage.
7. A method according to claim 3, wherein in step (1), the theoretical value of the first threshold is 0, and the actual circuit is set to a value slightly greater than 0.
8. The method of claim 3, wherein in step (2), the capacitor C is determined by the load capacity of the first current polarity comparator, and the resistor R is determined by the required rising edge delay time T d, and r=t d/3C;td is the maximum pulse width that can be eliminated by the pulse cancellation circuit, and is 5% of the switching period T s.
9. A method according to claim 3, wherein in step (4), the second threshold value is 95% of the maximum operating voltage V max of the second current polarity comparator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211161057.0A CN115459554B (en) | 2022-09-22 | 2022-09-22 | Method for Eliminating False Pulses of Secondary-Side Synchronous Rectification Signals in Bidirectional CLLC Resonant Converters |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211161057.0A CN115459554B (en) | 2022-09-22 | 2022-09-22 | Method for Eliminating False Pulses of Secondary-Side Synchronous Rectification Signals in Bidirectional CLLC Resonant Converters |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115459554A CN115459554A (en) | 2022-12-09 |
| CN115459554B true CN115459554B (en) | 2024-12-13 |
Family
ID=84307265
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211161057.0A Active CN115459554B (en) | 2022-09-22 | 2022-09-22 | Method for Eliminating False Pulses of Secondary-Side Synchronous Rectification Signals in Bidirectional CLLC Resonant Converters |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115459554B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118694132A (en) * | 2024-05-29 | 2024-09-24 | 奇瑞汽车股份有限公司 | Control system based on bidirectional CLLC resonant converter |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110838793A (en) * | 2019-10-21 | 2020-02-25 | 浙江大学 | A Synchronous Rectifier Circuit and Control Strategy for Bidirectional CLLC Resonant Converters |
| CN114244126A (en) * | 2021-12-03 | 2022-03-25 | 西安理工大学 | Synchronous rectification method of bidirectional CLLC resonant converter |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5463787B2 (en) * | 2008-12-02 | 2014-04-09 | 富士電機株式会社 | Switching power supply device and switching power supply control circuit |
| CN102355147A (en) * | 2011-10-28 | 2012-02-15 | 上海大学 | Digital control device and method for LLC (logical link control) synchronously-rectified resonant converter |
| CN110768549B (en) * | 2019-09-14 | 2020-11-06 | 浙江大学 | A single-phase zero-voltage soft-switching charger topology and its modulation method |
-
2022
- 2022-09-22 CN CN202211161057.0A patent/CN115459554B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110838793A (en) * | 2019-10-21 | 2020-02-25 | 浙江大学 | A Synchronous Rectifier Circuit and Control Strategy for Bidirectional CLLC Resonant Converters |
| CN114244126A (en) * | 2021-12-03 | 2022-03-25 | 西安理工大学 | Synchronous rectification method of bidirectional CLLC resonant converter |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115459554A (en) | 2022-12-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11264894B2 (en) | Converter and current control system thereof | |
| CN101728958B (en) | Method and control device for controlling isolated converter by tail current | |
| US6937483B2 (en) | Device and method of commutation control for an isolated boost converter | |
| US9906147B2 (en) | Adaptive dead time control apparatus and method for switching power converters | |
| Ruan et al. | Zero-voltage-switching PWM three-level converter with two clamping diodes | |
| CN104320001B (en) | A kind of magnetic isolation feedback circuit | |
| CN101552566B (en) | Synchronous Rectifiers for Resonant Switching Power Converters | |
| US20050248964A1 (en) | Power supply controller and method therefor | |
| US5818704A (en) | Synchronizing/driving circuit for a forward synchronous rectifier | |
| CN104300795A (en) | Flyback converter and control method of flyback converter | |
| CN101902134B (en) | Power source apparatus | |
| US11984813B2 (en) | Synchronous rectification control system and method for quasi-resonant flyback converter | |
| CN108418435A (en) | A Synchronous Rectification Flyback DC-DC Power Conversion Device | |
| CN115459554B (en) | Method for Eliminating False Pulses of Secondary-Side Synchronous Rectification Signals in Bidirectional CLLC Resonant Converters | |
| CN111726011B (en) | Digital isolator circuit comprising integrated isolated DC-DC and digital isolator comprising circuit | |
| CN108667304B (en) | Synchronous rectification flyback DC-DC power supply conversion device and control method | |
| CN102157920A (en) | Synchronous rectification control circuit and control method thereof | |
| US6522109B2 (en) | Power conversion apparatus | |
| CN109845080B (en) | DC voltage converter and method for operating a DC voltage converter | |
| US7113413B1 (en) | Control circuit with tracking turn on/off delay for a single-ended forward converter with synchronous rectification | |
| CN214480290U (en) | Sampling circuit and multi-winding series converter comprising same | |
| EP4005079B1 (en) | A prestart control circuit for a switching power converter comprising a synchronous rectifier switch on the secondary side of an energy storage section | |
| CN114567182A (en) | Synchronous rectification control device, chip and switching power supply | |
| CN113783402A (en) | Self-adaptive control circuit and control method | |
| CN105680707A (en) | Synchronous rectification chip protection method of isolated type synchronous rectification control circuit and synchronous rectification chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |