CN115472498B - Method and device for directional formation of palladium complex center by low temperature oxidation masking PN junction - Google Patents
Method and device for directional formation of palladium complex center by low temperature oxidation masking PN junction Download PDFInfo
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- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 title claims abstract description 148
- 229910052763 palladium Inorganic materials 0.000 title claims abstract description 74
- 238000000034 method Methods 0.000 title claims abstract description 71
- 230000003647 oxidation Effects 0.000 title claims abstract description 69
- 238000007254 oxidation reaction Methods 0.000 title claims abstract description 69
- 230000000873 masking effect Effects 0.000 title claims abstract description 10
- 230000015572 biosynthetic process Effects 0.000 title abstract description 3
- 238000009792 diffusion process Methods 0.000 claims abstract description 40
- 238000011084 recovery Methods 0.000 claims abstract description 31
- 238000005530 etching Methods 0.000 claims abstract description 25
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 15
- 239000001301 oxygen Substances 0.000 claims abstract description 15
- 229910000077 silane Inorganic materials 0.000 claims abstract description 14
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 11
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 claims description 33
- 239000012535 impurity Substances 0.000 claims description 21
- 238000000576 coating method Methods 0.000 claims description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 17
- 239000011248 coating agent Substances 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 15
- 230000006798 recombination Effects 0.000 claims description 13
- 230000001590 oxidative effect Effects 0.000 claims description 12
- PIBWKRNGBLPSSY-UHFFFAOYSA-L palladium(II) chloride Chemical compound Cl[Pd]Cl PIBWKRNGBLPSSY-UHFFFAOYSA-L 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- 238000005245 sintering Methods 0.000 claims description 11
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 9
- 239000007789 gas Substances 0.000 claims description 6
- 238000001459 lithography Methods 0.000 claims description 5
- 239000002904 solvent Substances 0.000 claims description 5
- 238000012545 processing Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- 238000002156 mixing Methods 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 238000007790 scraping Methods 0.000 claims description 3
- 230000001476 alcoholic effect Effects 0.000 claims 1
- 239000003292 glue Substances 0.000 claims 1
- 230000008569 process Effects 0.000 abstract description 34
- 238000004519 manufacturing process Methods 0.000 abstract description 10
- 239000000758 substrate Substances 0.000 abstract description 6
- 239000004065 semiconductor Substances 0.000 abstract description 5
- 238000005516 engineering process Methods 0.000 abstract description 4
- 238000000206 photolithography Methods 0.000 abstract description 3
- 238000005468 ion implantation Methods 0.000 abstract description 2
- 239000002131 composite material Substances 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 64
- 239000000047 product Substances 0.000 description 22
- 238000009826 distribution Methods 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 238000005215 recombination Methods 0.000 description 8
- 238000001259 photo etching Methods 0.000 description 7
- 238000012360 testing method Methods 0.000 description 7
- 239000011521 glass Substances 0.000 description 5
- 238000004528 spin coating Methods 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 238000007650 screen-printing Methods 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 238000003672 processing method Methods 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- GVVPGTZRZFNKDS-JXMROGBWSA-N geranyl diphosphate Chemical compound CC(C)=CCC\C(C)=C\CO[P@](O)(=O)OP(O)(O)=O GVVPGTZRZFNKDS-JXMROGBWSA-N 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 238000012805 post-processing Methods 0.000 description 2
- 238000000748 compression moulding Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000013016 damping Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000007606 doctor blade method Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000009993 protective function Effects 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D8/00—Diodes
- H10D8/01—Manufacture or treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D8/00—Diodes
- H10D8/01—Manufacture or treatment
- H10D8/045—Manufacture or treatment of PN junction diodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D8/00—Diodes
- H10D8/50—PIN diodes
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
Abstract
本发明公开了一种低温氧化掩蔽PN结定向形成钯复合中心的方法及器件，属于半导体器件制造领域。本发明采用LTO(Low Temperature Oxidation)低温氧化工艺技术，超高纯度氧气携源硅烷，于LTO氧化炉内低温环境，在已形成沟槽的普通PIN二极管扩散片晶片表面形成致密的氧化物薄膜。再经过光刻和刻蚀工序后，进行精准的定向钯扩散。从而获得Vf(正向压降)、Trr(反向恢复时间)等参数集中性很好的扩散基片，显著提高扩散片上的芯片利用率，大幅度提升产品品质。而相比采用价格高昂的离子注入机，本发明大幅度降低成本的同时，可获得与离子注入相对接近的参数品质。
The present invention discloses a method and device for directional formation of palladium composite centers by low-temperature oxidation masking PN junctions, and belongs to the field of semiconductor device manufacturing. The present invention adopts LTO (Low Temperature Oxidation) low-temperature oxidation process technology, ultra-high purity oxygen carrying source silane, and forms a dense oxide film on the surface of an ordinary PIN diode diffusion sheet wafer with grooves formed in a low-temperature environment in an LTO oxidation furnace. After the photolithography and etching processes, precise directional palladium diffusion is performed. Thereby, a diffusion substrate with good concentration of parameters such as Vf (forward voltage drop) and Trr (reverse recovery time) is obtained, which significantly improves the chip utilization rate on the diffusion sheet and greatly improves the product quality. Compared with the use of expensive ion implanters, the present invention can greatly reduce costs while obtaining parameter quality relatively close to ion implantation.
Description
Technical Field
The invention belongs to the field of semiconductor device manufacturing, and particularly relates to a method and a device for directionally forming a palladium composite center by masking PN junctions through low-temperature oxidation.
Background
It is well known that the most important property of a diode is unidirectional conductivity. In the circuit, current can only flow in from the anode of the diode and flow out from the cathode of the diode. The types of diodes are very numerous, and among them, fast recovery diodes (collectively referred to as FRDs) are semiconductor diodes with good switching characteristics and short reverse recovery time. The diode is mainly used in high-frequency electronic circuits such as a switching power supply or a frequency converter, and the like, and is used as a high-frequency rectification diode or a damping diode, and can replace a Schottky diode in certain fields.
The internal structure of the fast recovery diode is a typical PIN junction diode, namely a base region I is added between a P-type silicon material and an N-type silicon material to form a PIN silicon chip. The fast recovery diode has shorter reverse recovery time, lower forward voltage drop and higher reverse breakdown voltage (withstand voltage value). However, unlike schottky diodes, PIN-structured fast recovery diodes require the use of a principle of forming a recombination center by doping gold in the manufacturing process to reduce the reverse recovery time, i.e., to achieve a higher switching speed.
Recombination centers refer to certain impurities and defects within the semiconductor structure that promote carrier recombination and are decisive for the length of the non-equilibrium carrier lifetime. The impurities and defects as recombination centers are generally formed by introducing one or more deep energy levels into the forbidden band, which can capture both electrons and holes, thereby facilitating the recombination process. Gold and platinum are the most common recombination centers in semiconductor silicon materials, and the VF and Trr characteristics of the diode obtained by doping gold are better than those of a platinum-doped diode, but the high-temperature reverse leakage current characteristics are worse than those of a platinum-doped diode. While palladium with recombination centers between gold and platinum may be used, if impurity concentration is better controlled. Palladium is doped into the rectifier diode with the common PIN structure, so that the recombination of electrons and holes can be accelerated, and the palladium concentration near the PN junction can also directly determine the reverse recovery time.
Typically, PIN junction rectifier diodes with faster recovery times, collectively known as Fast Recovery Diodes (FRDs). The fast recovery diode FR, the high efficiency rectifier diode HER, and the ultrafast recovery diode SF can be classified according to the recovery time.
According to the relation formula of the stored charge and the forward voltage:
The reverse recovery time is the time required for the stored charge to be depleted, so that Vf/. Alpha.trr can be derived, and the forward voltage drop is inversely proportional to the reverse recovery time. It is well known that excessive forward voltage drop results in higher power loss in high frequency circuits, and thus for fast recovery diode products, it is important to precisely control the range of reverse recovery time Trr.
Because Vf is inaccurate before the chip is packaged into a finished product, whether Vf of the product meets the requirement can only be determined in advance according to the rule of summarizing Trr from experience accumulated for many years, and the typical distribution of Trr is summarized as shown in the following table 1:
TABLE 1 common typical classifications of fast recovery diode FRDs
| Model number | Voltage distribution | Typical range of Trr |
| Ultrafast recovery diode SF | Whole series | 22~35ns |
| High-efficiency rectifier diode HER | <1000V | 30~48ns |
| High-efficiency rectifier diode HER | >1000V | 48~72ns |
| Fast recovery diode FR | <500V | 75~150ns |
| Fast recovery diode FR | 500~1000V | 90~250ns |
| Fast recovery diode FR | >1000V | 180~450ns |
From the above classification table, it can be seen that the lower Trr diode chip has a higher standard deviation. In other words, the smaller the deviation of the palladium impurity concentration within each silicon wafer, the better.
The ion implanter used in the manufacture of integrated circuits is extremely expensive, cumbersome in process and low in production efficiency, and therefore, cannot be used in the diode manufacturing process. The traditional process mode of the diode is that diffusion is carried out, namely, after PN junction diffusion of a silicon wafer is formed, source coating is directly carried out, palladium impurities are diffused, and therefore a composite center is introduced into the PN junction. The uniformity of the palladium impurity concentration on the wafer surface is difficult to ensure by the traditional coating source, and the final Trr deviation of the product is caused, and particularly for a 5-inch substrate or even a 6-inch substrate, the difference of the inner and outer ring concentration can reach 50 percent.
Therefore, how to ensure the uniformity of the palladium impurity concentration when the composite center is formed inside the diode diffusion sheet is a technical problem to be solved in the present day.
Disclosure of Invention
The invention aims to solve the problem of uneven palladium impurity concentration when a composite center is formed in a diode diffusion sheet in the prior art, and provides a method for directionally forming a palladium composite center by masking PN junctions through low-temperature oxidation.
The specific technical scheme adopted by the invention is as follows:
in a first aspect, the present invention provides a method for orientating a low temperature oxidation masked PN junction to form a palladium recombination center, comprising:
S1, adopting a PIN diode diffusion sheet wafer which is formed with PN junctions and is etched and grooved as a material, firstly carrying silane by pure oxygen to form a first oxidation atmosphere, carrying out low-temperature oxidation at 500-800 ℃, and then carrying out dry oxygen oxidation at 500-800 ℃ continuously by pure oxygen to form a second oxidation atmosphere, so that an oxide film is formed on the surface of the wafer;
S2, forming a patterned mask on the wafer with the oxide film through photoresist uniformization lithography, so that the center of each chip mesa is exposed out of an oxide etching window, and the mask surrounding the oxide etching window is still reserved at the peripheral edge positions of the chip mesas and the grooves among the chip mesas;
s3, coating a palladium source on the surface of the wafer, and then carrying out directional palladium diffusion through sintering to diffuse palladium impurities into the wafer to form a composite center.
As a preferable mode of the first aspect, the processing method of the PIN diode diffusion chip wafer with PN junction formed and etched slot comprises the steps of forming a wafer with a rectifier diode PIN structure after impurity diffusion of a silicon wafer, and obtaining the wafer with a chip pattern structure through photoresist uniformization photoetching and etched slot.
Preferably, in the first aspect, the first oxidizing atmosphere is obtained by mixing high-purity oxygen and silane at a gas flow ratio of (1 to 3): 1 and continuously introducing the mixture into a low-temperature oxidizing environment.
As a preferable aspect of the above-mentioned first aspect, in forming the oxide film on the wafer surface, the oxide film formed by low-temperature oxidation in the first oxidizing atmosphere has a thickness ofThe above is preferablyThe above is more preferablePreferably, the oxide film formed by dry oxidation in the second oxidizing atmosphere has a thickness not exceeding
The palladium source is preferably an alcohol solution of palladium chloride, preferably an isopropanol solution of 5-20% by mass of palladium chloride, and preferably the palladium source is coated on the surface of the wafer and then sintered after the isopropanol solvent is volatilized.
Preferably, the low-temperature oxidation and the dry-oxygen oxidation are performed in a fully automatic program-controlled furnace, and the directional palladium diffusion is performed in the fully automatic program-controlled furnace.
Preferably, in the first aspect, the sintering temperature for performing directional palladium diffusion is 750 to 1000 ℃.
As a preferable mode of the first aspect, the method of applying the palladium source to the wafer surface is a dispensing method or a knife scraping method.
In a second aspect, the present invention provides a diode device obtained by processing a wafer produced by the method according to any one of the first aspects.
As preferable of the above second aspect, the diode device types include a fast recovery diode FR, an ultrafast recovery diode SF, a high efficiency rectifier diode HER.
Compared with the prior art, the invention has the following beneficial effects:
The invention adopts LTO (Low Temperature Oxidation) low-temperature oxidation technology, ultra-high purity oxygen carries source silane, and a compact oxide film is formed on the surface of a common PIN diode diffusion sheet wafer with grooves formed in a low-temperature environment in an LTO oxidation furnace. And performing accurate directional palladium diffusion after photoetching and etching processes. Therefore, a diffusion substrate with good parameter set such as Vf (forward pressure drop), trr (reverse recovery time) and the like is obtained, the chip utilization rate on the diffusion substrate is obviously improved, and the product quality is greatly improved. Compared with the ion implanter with high price, the invention greatly reduces the cost and can obtain the parameter quality relatively close to the ion implantation.
Drawings
FIG. 1 is an example of a wafer with a chip pattern after a second photoresist etch and oxide etch;
FIG. 2 shows a state of palladium chloride in which a dilute isopropanol solution is blade-coated and infiltrated into the surface of a chip;
FIG. 3 shows Trr distribution ranges before products of S42-S59 specifications are adopted by the invention;
FIG. 4 shows Trr distribution ranges of S42-S59 products after the invention is adopted;
FIG. 5 shows Trr distribution ranges before the S95-S110 specification products are adopted by the invention;
FIG. 6 shows the Trr distribution range of the S95-S110 specification product after the invention is adopted.
Detailed Description
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to the appended drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may be embodied in many other forms than described herein and similarly modified by those skilled in the art without departing from the spirit of the invention, whereby the invention is not limited to the specific embodiments disclosed below. The technical features of the embodiments of the invention can be combined correspondingly on the premise of no mutual conflict.
In the description of the present invention, it should be understood that the terms "first" and "second" are used solely for the purpose of distinguishing between the descriptions and not necessarily for the purpose of indicating or implying a relative importance or implicitly indicating the number of features indicated.
In a preferred embodiment of the present invention, a method for forming palladium recombination centers by low temperature oxidation masking PN junction orientation is provided, comprising the steps of:
S1, adopting a PIN diode diffusion sheet wafer which is formed with PN junctions and is etched and grooved as a material, firstly carrying silane by pure oxygen to form a first oxidation atmosphere, carrying out low-temperature oxidation at 500-800 ℃, and then carrying out dry oxygen oxidation at 500-800 ℃ continuously by pure oxygen to form a second oxidation atmosphere, so that an oxide film is formed on the surface of the wafer.
S2, forming a patterned mask on the wafer with the oxide film through photoresist uniformization lithography, so that the center of each chip mesa is exposed out of the oxide etching window, but the mask surrounding the oxide etching window is still reserved at the peripheral edge positions of the chip mesas and the grooves among the chip mesas, and then performing oxide etching on the wafer to remove the oxide film in the range of each oxide etching window, thereby obtaining the source attaching window for attaching the palladium source.
S3, coating a palladium source on the surface of the wafer, and then carrying out directional palladium diffusion through sintering to diffuse palladium impurities into the wafer to form a composite center.
The processing method of the PIN diode diffusion wafer with PN junction and etched slot comprises the steps of diffusing impurities on a silicon wafer to form a wafer with a rectifier diode PIN structure, and carrying out photoresist homogenizing lithography and etching slot to obtain the wafer with the chip pattern structure. The impurity diffusion mode, photoresist homogenizing photoetching and etching grooving processes of the silicon wafer all belong to the prior art.
As a preferred implementation manner of the embodiment of the invention, the first oxidizing atmosphere is obtained by mixing high-purity oxygen and silane according to a gas flow ratio (1-3): 1 and continuously introducing the mixture into a low-temperature oxidizing environment. In practical application, in order to facilitate the switching control of the first oxidation atmosphere and the second oxidation atmosphere, the high-purity oxygen source and the silane source can be respectively connected into the air inlet pipeline, both the two gas sources are opened when the first oxidation atmosphere is required to be formed, the respective flow rates are controlled according to the corresponding flow rate ratio, and when the second oxidation atmosphere is required to be formed, the silane source can be closed, and only the pure oxygen source is opened.
In order to avoid the introduction of impurities, the high purity oxygen used in the present invention is preferably ultra-high purity oxygen having a purity of more than 99.999%.
The silane in the present invention is monosilane SiH 4.
The invention is different from the conventional process of diffusing palladium and then etching, and adopts the wafer with the chip pattern after etching grooving to conduct directional palladium diffusion so as to obtain the wafer with good uniformity and consistency.
And since PN junctions in the wafer with the chip patterns after the grooves are etched are exposed after the grooves are etched, the PN junctions must be protected before palladium diffusion. Therefore, an oxidation process is needed to form a silicon dioxide film to mask the whole trench, especially the PN junction. The traditional oxidation process is to oxidize at a temperature above 1100 ℃ and form a thicknessThe above, dense oxide film. However, for wafers after the completion of the diffusion of PN junctions (e.g., boron and phosphorus), high temperatures above 1100 ℃ can lead to dopant redistribution that reduces the reverse breakdown voltage of the product. According to different oxidation time, the voltage decay can reach 50-100V. In the process method, the oxidation is carried out in a low-temperature environment with the temperature of 500-800 ℃.
In the LTO process in the conventional glass packaging GPP process, the temperature of the glass layer needs to be controlled to be 250-500 ℃ in consideration of protection, so that the thickness of the oxide layer is thinner and is not more thanThe invention does not carry out glass sintering, so that the concern of glass temperature does not exist, and the oxidation process is completed by combining the LTO low-temperature oxidation process technology with the process temperature of 500-800 ℃. The thickness of the oxide layer can be ensured, and the secondary distribution of boron and phosphorus impurities can be avoided.
In addition, if the process of diffusing palladium and then etching is adopted, then the carried source oxidation is adopted, the palladium source is separated out from the vicinity of the PN junction, so that the Trr parameter which seriously affects the product is raised by tens of times, and meanwhile, the reverse leakage Ir is greatly improved. The common PIN junction diode can be unaffected, a silicon dioxide oxidation film is formed at the process temperature of combining low-temperature LTO with 500-800 ℃ in a first oxidation atmosphere, then a silane source is closed, and the compactness of the surface oxidation film is increased by a pure oxygen dry-oxygen oxidation process in a second oxidation atmosphere. Otherwise, the compactness of an oxide layer formed by the low-temperature LTO in the previous step is insufficient, and in the process of combining a palladium composite center in the subsequent step, redundant palladium sources in the groove enter the vicinity of a PN junction through the non-compact oxide layer at high temperature, so that the final reverse leakage IR and high-temperature leakage HTIR of the product can be seriously influenced, and the final reverse leakage IR failure in a high-temperature reverse bias (HTRB) reliability test can be directly caused, even the normal-temperature reverse leakage IR failure in a conventional electrical test is directly caused
In the present invention, the thickness of the oxide film formed during the two-stage oxidation process needs to be reasonably controlled. As a preferred implementation manner of the embodiment of the invention, in the process of forming the oxide film on the surface of the wafer, the thickness of the oxide film formed by low-temperature oxidation under the first oxidation atmosphere is as followsThe above is preferablyThe above is more preferableEven if not allThe above. While the thickness of the oxide film formed by dry oxidation in the second oxidizing atmosphere preferably does not exceedThe formation of a dense layer sufficient to achieve the protective function is subject to.
And (2) after the wafer in the step (S1) is oxidized, performing secondary spin coating and secondary photoetching on the surface of the oxidized wafer in the step (S2), and etching an oxide layer to obtain a source attached window of the palladium source. As shown in fig. 1, an example of a wafer with a chip pattern after a second photoresist bake and oxide etch is shown. Taking a common S130mil chip as an example, each box in fig. 1 is a chip mesa of one chip, where a square area denoted by a is an oxide layer etching window formed by photolithography, and a square annular area denoted by B is a remaining silicon dioxide mask, that is, a portion outside the window of the black area is protected by a silicon dioxide oxide film mask. And (3) after the oxide layer etching window is etched, removing the internal oxide layer to expose the silicon crystal face, so that an attached source window for attaching a palladium source is formed. The additional source window is filled during the subsequent palladium source solution coating process.
In the present invention, the palladium source to be specifically used may be selected according to the actual process. As a preferred implementation manner of the embodiment of the invention, the palladium source can be selected from alcohol solutions of palladium chloride, and preferably isopropanol solutions of 5% -20% of palladium chloride by mass. Preferably, when an isopropanol solution of palladium chloride is used as the palladium source, the surface of the wafer is coated with the palladium source and then sintered after the isopropanol solvent is volatilized.
It should be noted that, the above oxidation process of S1, the photolithography and oxide layer etching process of S2, and the directional palladium diffusion process of S3 may all be related devices in the prior art, which is not the focus of the present invention. In order to facilitate the automatic control of the whole process, the low-temperature oxidation and the dry-oxygen oxidation in the S1 can be performed in a full-automatic program-controlled furnace, the directional palladium diffusion in the S3 can be performed in the full-automatic program-controlled furnace, the full-automatic program-controlled oxidation furnace can be adopted in the S1, and the full-automatic program-controlled diffusion furnace can be adopted in the S3.
In addition, the specific process of directional palladium diffusion on the wafer can be the same as in the prior art, and the specific sintering temperature and sintering time can be optimized according to the actual process conditions. As a preferred implementation of the embodiment of the present invention, the sintering temperature used in the directional palladium diffusion of the wafer is 750-1000 ℃.
In addition, the method of applying the palladium source to the wafer surface may be selected according to the actual application, so that the palladium source can be uniformly applied. Generally, the coating modes which can be selected are divided into two modes, one is that a silicon wafer is placed on a rotary sucker to be subjected to spin coating in a dropping mode or a brush type, and the other is that the silicon wafer is placed under a screen plate to be subjected to blade coating by adopting a scraper.
The spin coating has the advantages that the application range is wide, the low-viscosity solution can be brushed by a brush pen in a rotating way, the high-concentration solution can be spun by a dropper at a high rotating speed, but the defects are obvious, namely the uniformity of the solution is difficult to control. Generally, a gradient concentration difference is formed radially from the center to the outer ring, and the concentration decreases toward the outer ring. This phenomenon is more pronounced when large-sized diode chips are fabricated, especially for 5-inch and even 6-inch substrates, where the inner and outer concentration differences are as high as 50%. This disadvantage is difficult to avoid with either fully automated or semi-automated/manual equipment. Spin coating is generally suitable for applications where the deviation of the surface coating is not high, such as photoresist, laser protection liquid coating, etc.
The advantages of blade coating are just opposite, and the blade with the diameter larger than that of the silicon wafer is adopted, so that the uniformity of coating on the surface of the silicon wafer after blade coating can be ensured as long as the height and levelness of the screen printing plate are adjusted well, similar to the principle of screen printing. However, the method has strong limitation, and is mainly used for high viscosity situations with good surface tension, such as blade coating of glass paste. The isopropanol solution of palladium chloride is a dilute solution, and the viscosity is low, so that the palladium chloride cannot be coated on the surface of a silicon wafer by a scraper, and therefore, the conventional process can only rely on spin coating for coating.
However, in the present invention, since the oxidized film is formed in advance around the source-attached window before the palladium source is coated, the problem of non-uniformity in the thin solution coating process can be solved. Since, referring to fig. 1, the black area indicated by each a is an additional source window obtained after etching the oxide layer, and the white area indicated by the surrounding B is a thicker oxide layer area, the surface tension of the isopropyl alcohol solution on the surface of the chip is quite high due to the greater hydrophobicity generated by the compactness of the silicon oxide layer, and after the solution is permeated to the wafer through the grid by a doctor blade method, droplets as shown in fig. 2 are formed on each black window, so that the isopropyl alcohol solution can be uniformly dispersed on each chip mesa.
As a preferred implementation of the embodiment of the present invention, the doctor blade apparatus is a conventional apparatus for screen printing, in which a doctor blade is used to draw the solution back and forth onto the wafer surface. After the machine level is ensured, the concentration of the palladium source on each chip table surface of the wafer can be kept consistent as long as a uniform isopropanol solution of palladium chloride is adopted. After the blade coating is finished, the wafer is required to be placed in a hot plate or an oven in time, and the wafer can be sintered at the temperature of 750-1000 ℃ after the solvent isopropanol volatilizes, so that the palladium impurity diffusion process is completed.
The method of S1-S3 can be used for obtaining the corresponding silicon core wafer in the process of generating the diode device, and performing post-processing technology on the silicon core wafer to form the silicon diode. Specific post-processing techniques include photoresist stripping, sawing, soldering, cleaning, mesa passivation, compression molding, packaging, etc., and may be selected based on the actual diode processing technique.
The invention is applicable to all diode diffusion sheets which need to form a composite center by introducing impurity palladium and improve the switching speed, such as a fast recovery diode FR, an ultrafast recovery diode SF and a high-efficiency rectifying diode HER.
In order to show the effect achieved by the method S1 to S3 of the present invention, the following is shown by a specific practical application case.
Examples
In this embodiment, the chip manufacturing of the two specification ranges (S42-S59 and S95-S130 respectively) of the ultra-fast recovery diode SF chip with the most demanding parameter requirements is taken as an example. In this embodiment, a diffusion wafer with a PIN structure with a finished voltage range of 600-800V is selected for manufacturing, wherein a PN junction required by a rectifier diode is formed by impurity diffusion, and the following processing method is as follows:
Firstly, grooving is carried out through a photoetching station and an etching station according to a normal chip circulation program, and wafers with chip pattern structures with corresponding sizes are manufactured respectively. After the wafer is cleaned again, the wafer is sent into a full-automatic program-controlled furnace, ultra-pure oxygen with purity higher than 99.999% is introduced into the furnace with silane carried by the gas flow ratio of 1:1 to form an oxidizing atmosphere, the wafer is subjected to LTO low-temperature oxidation for 80 minutes in the furnace at 550 ℃, then the silane gas is closed, ultra-pure oxygen is continuously introduced as the oxidizing atmosphere, and the oxidizing atmosphere is oxidized for 20 minutes by pure oxygen to improve the compactness of an oxide layer. Oxidized wafer, oxide layer thickness was measured to be about
And then, the wafer is sent to a photoetching station and an etching station again for secondary photoetching and oxide layer etching (the same as the conventional chip circulation process), and palladium Jin Kuosan auxiliary source windows (the auxiliary source windows are controlled to be positioned at the center of the chip table top and smaller than the chip table top by 20-30 mils) are respectively obtained, as shown in fig. 1. After the conventional oxide sheet cleaning flow is carried out again, the isopropanol solution of palladium chloride with the mass ratio of 1:10 is uniformly coated on each chip table surface by adopting a knife scraping method in screen printing. After the blade coating is finished, the wafer is required to be placed in a hot plate or an oven in time, and after the solvent isopropanol volatilizes, the wafer is sintered for 30 minutes according to the diffusion sintering temperature requirements (S45-S59 mil:800 ℃ and S95-S130 mil:820 ℃) corresponding to the production process, so that palladium impurities are diffused into the vicinity of the silicon PN junction to form a composite center. And then completing the production and test of the single chip according to the conventional GPP process flow.
The invention adopts the computer to automatically collect the online test data of the final product, and compares the online test data after the computer is fitted, so that the product can be found that the distribution from the center to the outer ring of the product is obviously converged after the process method is used, the qualification rate is greatly improved, and the economic benefit is obviously improved. Specific results are shown below:
For small-size chips, the center position, the half position of the radius and the 1-3 mm position of the outermost ring of each chip are selected, and the 3 positions are counted by randomly using a computer in thousands of chips tested on line, wherein 10000 chips Trr data are respectively extracted. As shown in table 1 below and fig. 3 and 4, it is evident that the Trr normal distribution of the chip is more convergent after the use of the present invention. Meanwhile, according to the self-control requirement, 237 chips of the product are out of the range of 22-36 ns, and the product accounts for 0.79% of the total number. After the invention is adopted, all the extracted 3 ten thousand chips are qualified.
Table 1S42 to S59 specification products with Trr distribution (granularity) of chips before and after the invention is adopted
* Ten thousand chips are randomly extracted from three area data of a wafer by a computer in an on-line test
For the middle and large-size chips, the center position, the half radius position and the 1-3 mm outermost position of each chip are selected, and the 3 positions are counted by randomly using a computer in thousands of chips tested on line, wherein 5000 chips Trr data are extracted respectively. As shown in table 2 below and fig. 5 and 6, the Trr normal distribution of the chip is more convergent after the present invention is also applied.
According to the self-control requirement, although the product parameters are qualified for the products before and after the invention is adopted, the Trr concentration of the products after the invention is adopted is better. The formula of the relationship between the stored charge and the forward voltage shows that the Vf forward voltage can be smaller through process improvement (namely, the Trr value is accurately controlled to be close to the upper limit parameter), which is more beneficial to reducing the power consumption in the switch circuit, so that the final packaged diode product is more efficient and energy-saving.
Table 2S 95-S110 specification products with Trr distribution (granularity) of chips before and after the invention is adopted
* 5000 Chips are randomly extracted from three area data of a wafer by a computer in an on-line test
The above embodiment is only a preferred embodiment of the present invention, but it is not intended to limit the present invention. Various changes and modifications may be made by one of ordinary skill in the pertinent art without departing from the spirit and scope of the present invention. Therefore, all the technical schemes obtained by adopting the equivalent substitution or equivalent transformation are within the protection scope of the invention.
Claims (14)
1. A method for orientating a masked PN junction to form a palladium recombination center by low temperature oxidation, comprising:
S1, adopting a PIN diode diffusion sheet wafer which is formed with PN junctions and is etched and grooved as a material, forming a chip pattern structure on the surface of the wafer after the etching and grooving are finished, firstly forming a first oxidation atmosphere by pure oxygen carrying silane and carrying out low-temperature oxidation at 500-800 ℃, and then continuously carrying out dry oxygen oxidation at 500-800 ℃ by pure oxygen to form a second oxidation atmosphere, so that an oxide film is formed on the surface of the wafer;
S2, forming a patterned mask on the wafer with the oxide film through photoresist uniformization lithography, so that the center of each chip mesa is exposed out of an oxide etching window, and the mask surrounding the oxide etching window is still reserved at the peripheral edge positions of the chip mesas and the grooves among the chip mesas;
s3, coating a palladium source on the surface of the wafer, and then carrying out directional palladium diffusion through sintering to diffuse palladium impurities into the wafer to form a composite center.
2. The method for directionally forming a palladium composite center by low-temperature oxidation masking PN junction according to claim 1, wherein the method for processing the PIN diode diffusion chip wafer which is provided with PN junction and is etched and grooved is characterized in that a silicon wafer is diffused by impurities to form a wafer with a rectifier diode PIN structure, and then the wafer with a chip pattern structure is obtained by photoresist lithography and etching and grooving.
3. The method for directionally forming a palladium composite center by masking a PN junction by low-temperature oxidation according to claim 1, wherein the first oxidation atmosphere is obtained by mixing high-purity oxygen and silane according to a gas flow ratio of (1-3): 1 and continuously introducing the mixture into a low-temperature oxidation environment.
4. The method of claim 1, wherein the thickness of the oxide film formed by low-temperature oxidation in the first oxidation atmosphere is 3000 a or more and the thickness of the oxide film formed by dry oxidation in the second oxidation atmosphere is not more than 500 a.
5. The method of orientating a masked PN junction to form a palladium recombination center of claim 4 wherein the thickness of the oxide film formed by low temperature oxidation in a first oxidizing atmosphere is greater than 5000A.
6. The method of claim 5, wherein the oxide film formed by low temperature oxidation in the first oxidizing atmosphere has a thickness of 6000 a to 9000 a.
7. The method for orientating a masked PN junction to form a palladium recombination center of claim 1 wherein said palladium source is an alcoholic solution of palladium chloride.
8. The method for orientating a masked PN junction to form a palladium composite center of claim 7, wherein the palladium source is an isopropyl alcohol solution of 5% -20% by mass of palladium chloride.
9. The method for directionally forming a palladium composite center on a low temperature oxidation masked PN junction of claim 7, wherein after the palladium source is coated on the wafer surface, sintering is performed after the isopropanol solvent is evaporated.
10. The method for directionally forming a palladium composite center by masking a PN junction by low-temperature oxidation according to claim 1, wherein the low-temperature oxidation and the dry-oxygen oxidation are performed in a fully-automatic program-controlled furnace, and the directional palladium diffusion is performed in the fully-automatic program-controlled furnace.
11. The method for directionally forming a palladium composite center by low-temperature oxidation masking PN junction according to claim 1, wherein the sintering temperature for directional palladium diffusion is 750-1000 ℃.
12. The method for orientating a masked PN junction to form a palladium composite center according to claim 1, wherein the method for coating the palladium source on the surface of the wafer is a glue dropping method or a knife scraping method.
13. A diode device obtained by processing a wafer produced by the method according to any one of claims 1 to 12.
14. The diode device of claim 13, wherein the diode device types include fast recovery diode FR, ultrafast recovery diode SF, high efficiency rectifier diode HER.
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| CN104201102A (en) * | 2014-08-28 | 2014-12-10 | 苏州启澜功率电子有限公司 | Fast recovery diode FRD chip and production process for same |
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| US8669554B2 (en) * | 2006-05-10 | 2014-03-11 | Ho-Yuan Yu | Fast recovery reduced p-n junction rectifier |
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| CN104201102A (en) * | 2014-08-28 | 2014-12-10 | 苏州启澜功率电子有限公司 | Fast recovery diode FRD chip and production process for same |
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