CN115473946B - Cross-protocol chip data transmission equipment and method - Google Patents
Cross-protocol chip data transmission equipment and method Download PDFInfo
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Abstract
The application discloses a cross-protocol chip data transmission device and a method. Wherein the inter-protocol-chip data transfer device includes a first die and a second die electrically connected to each other. The first die splits a first data beat received by the first interface module into a plurality of second data beats through the first conversion module, then the plurality of second data beats are sent to the second die through the first cross-core module, the second die receives the second data sent by the first die through the second cross-core module, and the plurality of second data beats are recombined into the first data beat through the second cross-core module.
Description
Technical Field
The present application relates to the field of chip transmission, and in particular, to a cross-protocol chip data transmission device and method.
Background
Currently, with the development of the semiconductor industry, the chip size is becoming more and more extreme. In a super-large chip, along with the expansion of the chip size, a plurality of dies (die) are integrated in more and more super-large chips, and the need for transmission and interaction of data streams of different protocols across the dies is more and more vigorous. However, various protocols, such as a scheme for transmitting data streams of a trusted eXtensible Stream (CXS) protocol across a core, do not exist in the market at present, so that most CXS protocol data streams cannot be transmitted across the core.
Disclosure of Invention
The embodiment of the application provides cross-protocol chip data transmission equipment, which can enable CXS protocol data streams to be transmitted across a pipe core.
In a first aspect, an embodiment of the present application provides an inter-protocol chip data transmission device, where the inter-protocol chip data transmission device includes a first die and a second die.
The first die includes:
the first interface module is used for receiving the first data beat.
And the first conversion module is electrically connected with the first interface module and is used for splitting the first data beat received by the first interface module into a plurality of second data beats.
And the first cross-core module is respectively in electrical signal connection with the first conversion module and the second die and is used for receiving a plurality of second data beats split by the first conversion module and sending the plurality of second data beats to the second die.
The second die includes:
and the second cross core module is electrically connected with the first cross core module and is used for receiving a plurality of second data beats sent by the first cross core module.
And the second conversion module is electrically connected with the second cross core module and is used for combining the second data beat received by the second cross core module into the first data beat.
And the second interface module is in electrical signal connection with the second conversion module and is used for shooting the first data combined by the second conversion module.
In the embodiment of the application, after the first die splits the first data beat received by the first interface module into a plurality of second data beats through the first conversion module, the plurality of second data beats are sent to the second die through the first cross-core module, the second die receives the second data sent by the first die through the second cross-core module, and the plurality of second data beats are recombined into the first data beat through the second cross-core module.
In one possible implementation, the first conversion module includes: the first slave submodule is in electrical signal connection with the first cross-core module and is used for splitting the first data beat received by the first interface module into a plurality of second data beats and sending the second data beats to the second die through the first cross-core module; and the first main sub-module is respectively in electric signal connection with the first interface module and the first slave sub-module, and is used for receiving the first data beat received by the first interface module and distributing the first data beat to the first slave sub-module.
In this embodiment, the first conversion module adopts a distributed structure such as Flink, hbase, mySQL, and the like, receives data through the first master sub-module and distributes the data to the first slave sub-module, and the first slave sub-module splits the first data beat to obtain a plurality of second data beats.
In a possible implementation manner, the first master sub-module is further configured to generate first check information according to the first data beat, and send the first check information to the first slave sub-module, so that the first slave sub-module determines whether the plurality of split second data beats are incorrect according to the first check information.
In this embodiment, after the first check information is generated in the first master sub-module, the first check information is sent to the first slave sub-module, so that the first slave sub-module can compare and check the plurality of split second data beats with the first check information, the accuracy and integrity of the second data beats are determined in time, and the second data beats with errors in splitting are prevented from being sent to the second die, which affects the subsequent processing flow.
In one possible implementation, the first slave sub-module includes: the first storage unit is electrically connected with the first main body sub-module and is used for storing a first data beat distributed by the first main body sub-module; and the first conversion unit is respectively in electrical signal connection with the first storage unit and the first cross-core module, and is used for splitting the first data beat stored in the first storage unit into a plurality of second data beats according to a first preset format and sending the second data beats to the second die through the first cross-core module.
In this embodiment, the first slave sub-module splits the first data beat through the first converting unit, and stores the first data beat through the first storing unit, so as to reduce the processing pressure of the first converting unit, avoid data accumulation, and avoid data loss.
In one possible implementation, the first slave sub-module further includes: and the first logic unit is respectively in electric signal connection with the first storage unit and the first main sub-module, and is used for responding to the state information of the first storage unit and sending a first control signal to the first main sub-module, so that the first main sub-module responds to the first control signal and sends the first data beat to the first slave sub-module.
In this embodiment, the first logic unit sends the control signal to control the data transmission of the first master sub-module to the first slave sub-module, so as to avoid the situation that the processing pressure of the first slave sub-module is too high, which results in a crash.
In one possible implementation, the second conversion module includes: the second main body sub-module is electrically connected with the second cross-core module and is used for combining a plurality of second data beats received by the second cross-core module into a first data beat according to a second preset format; and the second slave sub-module is respectively in electric signal connection with the second main sub-module and the second interface module and is used for sending the first data beat combined by the second main sub-module out through the second interface module.
In this embodiment, the second conversion module adopts a distributed structure such as Flink, hbase, mySQL, and the like, receives the plurality of second data beats through the second master sub-module, combines the plurality of second data beats into one first data beat, and distributes the first data beat to the second slave sub-module, and the second data beat is processed by the second slave sub-module and then sent out through the second interface module, so that the distributed structure improves throughput of data, reduces delay, and improves performance.
In a possible implementation manner, the second master sub-module is further configured to generate second check information according to the second data beat, and send the second check information to the second slave sub-module, so that the second slave sub-module determines whether the merged multiple first data beats thereof are incorrect according to the second check information.
In this embodiment, after the second check information is generated in the second master submodule, the second check information is sent to the second slave submodule, so that the second slave submodule can compare and check a plurality of first data beats merged by the second master submodule with the second check information, the accuracy and integrity of the first data beats are determined in time, and the first data beats with errors in splitting are prevented from being sent out through the second interface module, and the subsequent processing flow is prevented from being influenced.
In one possible implementation, the second main sub-module includes: the second conversion unit is electrically connected with the second cross-core module and is used for combining a plurality of second data beats received by the second cross-core module into a first data beat according to a preset format; and the second storage unit is respectively in electric signal connection with the second conversion unit and the second slave submodule and is used for storing the first beat of data combined by the second conversion unit so as to send out the first beat of data through the second slave submodule.
In this embodiment, the second slave sub-module splits the second beat of data through the second converting unit, and stores the second beat of data through the second storage unit, so as to reduce the processing pressure of the second converting unit, avoid data accumulation, and avoid data loss.
In one possible implementation manner, the second conversion module further includes: and the second logic unit is respectively in electric signal connection with the second storage unit and the second slave submodule and is used for responding to the state information of the second slave submodule and sending a second control signal to the second storage unit so that the second storage unit can send the first data beat to the second slave submodule in response to the second control signal.
In this embodiment, the second logic unit sends the control signal to control the data transmission from the second master sub-module to the second slave sub-module, so as to avoid the situation that the processing pressure of the second slave sub-module is too high, which results in a crash.
In a possible implementation manner, the second conversion unit is further configured to send a resource query instruction to the second storage unit, and the second storage unit sends a cross-core control signal to the first die in response to the resource query instruction, so that the first die determines whether to send the second beat of data to the second die according to the cross-core control signal.
In this embodiment, the second storage unit determines the amount of the remaining storage resources of the second storage unit through the resource query instruction, and sends the cross-core control signal according to the amount of the remaining storage resources, so as to control data transmission from the first core to the second core, avoid data accumulation, cause an excessive data processing pressure of the second core, cause a crash, and simultaneously avoid data loss caused by excessive data.
In a second aspect, an embodiment of the present application provides a cross-protocol chip data transmission method, which is applied to the above-mentioned cross-protocol chip data transmission device, where the cross-protocol chip data transmission method includes: receiving an original first data beat through the first interface module, wherein the bit width of the original first data beat is a first bit width; splitting the original first data beat into a plurality of second data beats through the first conversion module, wherein the bit width of the second data beats is a second bit width, and the second bit width is smaller than the first bit width; cross-core transmitting, by the first cross-core module, the plurality of second beats of data to the second cross-core module; merging, by the second conversion module, the plurality of second data beats received by the second cross-core module into a target first data beat, the target first data beat having the same data and format as the original first data beat; and shooting the first target data through the second interface module.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a cross-protocol-chip data transmission device according to an embodiment of the present application.
Fig. 2 is a schematic structural diagram of a first conversion module and a second conversion module of the cross-protocol-chip data transmission device provided in fig. 1.
Fig. 3 is a schematic structural diagram of a first slave sub-module and a second master sub-module of the cross-protocol chip data transmission device provided in fig. 2.
Fig. 4 is a schematic structural diagram of a first slave sub-module of the cross-protocol-chip data transmission device provided in fig. 2.
Fig. 5 is a schematic structural diagram of a second main sub-module of the cross-protocol chip data transmission device provided in fig. 2.
Fig. 6 illustrates an example of a cross-protocol-chip data transmission method provided by an embodiment of the present application.
100. A first die; 200. a second die; 110. a first interface module; 120. a first conversion module; 130. a first cross-core module; 121. a first body sub-module; 122. a first slave sub-module; 1221. a first storage unit; 1222. a first conversion unit; 1223. a first logic unit; 210. a second interface module; 220. a second conversion module; 230. a second cross-core module; 221. a second body submodule; 222. a second slave sub-module; 2211. a second storage unit; 2212. a second conversion unit; 2213. a second logic unit.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the invention, are given by way of illustration and explanation only, and are not intended to limit the scope of the invention. In the present application, unless indicated to the contrary, the use of the directional terms "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, and more particularly to the orientation of the figures of the drawings; while "inner" and "outer" are with respect to the outline of the device.
The embodiments of the present application provide a cross-protocol chip data transmission device, which are described in detail below. It should be noted that the following description of the embodiments is not intended to limit the preferred order of the embodiments.
The application provides a cross-protocol chip data transmission device which can be a mobile phone, a tablet computer, a computer device, a server, a wearable device, an automobile and other devices needing chip control.
Referring to fig. 1, in an embodiment of the present application, a cross-protocol chip data transmission apparatus includes a first die 100 and a second die 200, and the first die 100 and the second die 200 are electrically connected to transmit cross-die data to each other. In practical applications of the present application, the first die 100 may transfer large-bit-wide CXS data across the dies to the second die 200, and the second die 200 may also transfer large-bit-wide CXS data across the dies to the first die 100. In the embodiment of the present application, the first die 100 is taken as a transmitting end, and the second die 200 is taken as a receiving end, for example, to describe.
The first die 100 as a transmitting end includes a first interface module 110, a first conversion module 120, and a first cross-core module 130. The first conversion module 120 is electrically connected to the first interface module 110 and the first cross-core module 130 respectively, and the electrical signal connection method generally connects the two modules through traces on the chip substrate.
In the first die 100, after receiving the first beat of data, the first interface module 110 transmits the first beat of data to the first conversion module 120, the first conversion module 120 splits the first beat of data received by the first interface module 110 into a plurality of second beats of data, and then sends the split plurality of second beats of data to the first cross-core module 130, and sends the split plurality of second beats of data to the second die 200 through the first cross-core module 130, thereby completing the cross-die transmission.
The first interface module 110 may be various types of interfaces, such as a Peripheral Component Interconnect (PCI) interface, an Industry Standard Architecture (ISA) interface, an Accelerated Graphics Port (AGP), and the like, for receiving a first beat of data transmitted from other electronic devices outside the first die 100 or a first beat of data transmitted from a functional unit inside the first die 100 to the second die 200.
The first cross-core module 130 is a cross-die transmission module for transmitting cross-die (die to die) data, and specifically, it sends the received multiple second beats of data split by the first conversion module 120 to the second die 200.
The first conversion module 120 is configured to split a first data beat received by the first interface module 110 into a plurality of second data beats, where a protocol format of the first data beat is different from a protocol format of cross-core transmission of the first cross-core module 130, and a bit width of the first data beat is greater than a bit width of the second data beat, so that the first conversion module 120 may split the first data beat into the plurality of second data beats according to a first predetermined format, and when a bit width of one data beat cannot be filled by a last second data beat in a splitting process, invalid data may be filled, and the invalid data may be uniformly distributed in each second data beat. The first predetermined format is to split the first beat of data with the first bit width into a plurality of second beats of data with the second bit width, the predetermined position of each second beat of data is a serial number identifier of the second beat of data, and the transmission is completed only when the second die 200 receives the plurality of second beats of data in sequence of serial numbers. The predetermined location may be arbitrary, and is generally located at the beginning of the second beat of data.
Referring to fig. 2, the first conversion module 120 specifically includes a first main sub-module 121 and a first sub-module 122, the first main sub-module 121 is electrically connected to the first interface module 110 and the first sub-module 122, and the first sub-module 122 is electrically connected to the first main sub-module 121 and the first core cross module 130.
In the embodiment of the application, the sub-modules in the first conversion module 120 adopt a distributed structure of Master-Slave (Master-Slave) architectures such as Flink, hbase, mySQL, and the like, receive data through the first Master sub-module 121 and distribute the data to the first Slave sub-module 122, and the first Slave sub-module 122 splits the first data beat to obtain a plurality of second data beats, and the Master-Slave interfaces improve throughput of data, reduce delay, and improve performance.
In the first conversion module 120, after receiving the first beat of data from the first interface module 110, the first master sub-module 121 distributes the first beat of data to the first slave sub-module 122, and the first slave sub-module 122 splits the first beat of data into a plurality of second beats of data, and sends the second beats of data to the second die 200 through the first cross core module 130.
In an embodiment of the present application, after the first body submodule 121 receives the first beat of data, the first verification information is generated according to the first beat of data. The first master sub-module 121 sends the first beat of data to the first slave sub-module 122, and additionally sends the first verification information to the first slave sub-module 122. After the first data beat is split into a plurality of second data beats, the first slave sub-module 122 compares the split plurality of second data beats with the first check information to check, and determines whether the data of each second data beat is correct and complete and whether the split data is incorrect. The first check information can help to determine the accuracy and integrity of the second data beat in time, and the second data beat with a wrong split is prevented from being sent to the second die 200, so that the subsequent processing flow is prevented from being influenced. And the first slave module is used for verifying so that the verification data transmission link is shortest, thereby saving the bandwidth of data transmission on one hand and improving the timeliness of data verification on the other hand.
Referring to fig. 3 and 4, the first slave sub-module 122 includes a first storage unit 1221, a first conversion unit 1222, and a first logic unit 1223. The first storage unit 1221 is electrically connected to the first conversion unit 1222, the first logic unit 1223, and the first body submodule 121, respectively. The first conversion unit 1222 is electrically connected to the first core module 130 in addition to the first storage unit 1221. The first logic unit 1223 is electrically connected to the first body submodule 121, in addition to the first storage unit 1221.
In the first slave sub-module 122, after receiving the first beat of data distributed from the first master sub-module 121, the first storage unit 1221 stores the first beat of data, and then splits the first beat of data into a plurality of second beats of data according to a first predetermined format by the first conversion unit 1222. The first cross-core module 130 sends the plurality of second beats of data to the second die 200.
In this embodiment, the first slave sub-module 122 splits the first beat of data by the first converting unit 1222, and stores the first beat of data by the first storing unit 1221, so as to reduce the processing pressure of the first converting unit 1222, avoid data accumulation, and avoid data loss.
In some embodiments, each time before receiving a first beat of data, the first converting unit 1222 sends a status inquiry signal, i.e., a first status inquiry signal, to the first storing unit 1221. The first storage unit 1221 sends its state information to the first logic unit 1223 in response to the first query state signal. The first logic unit 1223 sends a first control signal to the first master sub-module 121 in response to the status information, so that the first master sub-module 121 sends a first beat of data to the first slave sub-module 122 in response to the first control signal.
Specifically, when the first storage unit 1221 has a remaining space, the first logic unit 1223 transmits a first control signal to the first body submodule 121 in response to the state information having the remaining space. The first master sub-module 121 sends a first beat of data to the first slave sub-module 122 in response to the first control signal.
When the first storage unit 1221 has no remaining space, the first logic unit 1223 stops transmitting the first control signal to the first main sub-module 121 in response to the state information having the remaining space. The first master sub-module 121 does not receive the first control signal, and stops sending the first beat of data to the first slave sub-module 122.
In this embodiment, the flow control method is used to control the data transmission from the first master sub-module 121 to the first slave sub-module 122, so that the data transmission can be stopped and used at any time, and the situation that the first slave sub-module 122 receives and processes the first data beat continuously, so that the processing pressure is too high and the data is broken down can be avoided.
With continued reference to fig. 1, the second die 200 as a receiving end includes a second interface module 210, a second conversion module 220, and a second cross-core module 230. The second conversion module 220 is electrically connected to the second interface module 210 and the second cross-core module 230 respectively, and the electrical signal connection generally connects the two modules through traces on the chip substrate.
In the second die 200, after the second cross-core module 230 receives the multiple second data beats sent by the first cross-core module 130, the multiple second data beats are transmitted to the second conversion module 220, the multiple second data beats received by the second cross-core module 230 are combined into the first data beat by the second conversion module 220, and then the combined first data beat is sent out by the second conversion module 220, thereby completing the cross-die transmission of the first data beat.
The second cross-core module 230 is a cross-die transmission module for transmitting cross-die (die to die) data, and in particular, it sends a plurality of second beats of data received from the first die 100 to the second conversion module 220.
The second conversion module 220 is used to combine the second beat of data received by the second cross-core module 230 into the first beat of data,
the protocol format of the first beat of data is different from the protocol format of the second cross-core module 230 for cross-core transmission, and the bit width thereof is greater than the bit width of the second beat of data, so the second conversion module 220 can combine a plurality of second beats of data into the first beat of data according to a second predetermined format. The second predetermined format is opposite to the first predetermined format, and is to merge a plurality of second beats of data with a second bit width ordered in sequence number order into a first beat of data with a first bit width.
With continued reference to fig. 2, the second conversion module 220 includes a second main sub-module 221 and a second sub-module 222, the second main sub-module 221 is electrically connected to the second core spanning module 230 and the second sub-module 222, and the second sub-module 222 is electrically connected to the second main sub-module 221 and the second interface module 210.
In the embodiment of the present application, the sub-modules in the second conversion module 220 adopt a distributed structure of Master-Slave (Master-Slave) architectures such as Flink, hbase, mySQL, and the like, the second Master sub-module 221 receives the plurality of second data beats, combines the plurality of second data beats into one first data beat, and distributes the first data beat to the second Slave sub-module 222, and the second Slave sub-module 222 processes the second data beat and then sends the second data beat through the second interface module 210, so that the distributed structure improves data throughput, reduces delay, and improves performance.
In the second conversion module 220, after receiving the plurality of second data beats from the second trans-core module 230, the second master sub-module 221 merges the plurality of second data beats into a first data beat according to a predetermined format, and the second slave sub-module 222 sends the first data beat out through the second interface module 210.
In an embodiment of the present application, after the second main sub-module 221 receives the plurality of second data beats, second verification information is generated according to the plurality of second data beats. The second master sub-module 221 transmits the merged first beat of data to the second slave sub-module 222, and additionally transmits second parity information to the second slave sub-module 222. The second slave sub-module 222 compares and verifies the merged first beat of data with the second verification information, and determines whether the data of the first beat of data is correct and complete, and whether the merging is incorrect. The second check information can help to determine the accuracy and integrity of the first data beat in time, and the first data beat with the wrong split is prevented from being sent out to influence the subsequent processing flow. And the second slave module is used for verifying so that the verification data transmission link is shortest, thereby saving the bandwidth of data transmission on one hand and improving the timeliness of data verification on the other hand.
Meanwhile, under the combined action of the first check information and the second check information, cross-core transmission of the check information can be avoided, cross-core transmission bandwidth can be saved, and errors and even breakdown of the cross-core transmission due to blocking can be avoided.
Referring to fig. 3 and 5, the second main sub-module 221 includes a second storage unit 2211, a second conversion unit 2212 and a second logic unit 2213. The second storage unit 2211 is electrically connected to the second conversion unit 2212, the second logic unit 2213 and the second slave sub-module 222, respectively. The second conversion unit 2212 is electrically connected to the second trans-core module 230 in addition to the second storage unit 2211. The second logic unit 2213 is electrically connected to the second slave sub-module 222 in addition to the second memory unit 2211.
In the second main sub-module 221, after the second conversion unit 2212 receives the plurality of geothermal data beats from the second trans-core module 230, the plurality of second data beats are combined into a first data beat, and then the first data beat is stored in the second storage unit 2211. When the condition is met, the second storage unit 2211 sends the first beat of data stored in the second storage unit to the second slave sub-module 222, so that the first beat of data is sent out through the second slave sub-module 222.
In this embodiment, the second slave sub-module 222 splits the second beat of data through the second converting unit 2212, and stores the second beat of data through the second storing unit 2211, so as to reduce the processing pressure of the second converting unit 2212, avoid data accumulation, and avoid data loss.
In some embodiments, before each second data beat is received, the second logic unit 2213 receives status information from the second slave sub-module 222, and the second logic unit 2213 sends a second control signal to the second storage unit 2211 in response to the status information, so that the second storage unit 2211 sends the first data beat to the second slave sub-module 222 in response to the second control signal.
In this embodiment, the second logic unit 2213 sends a control signal to control the data transmission of the second master sub-module 221 to the second slave sub-module 222, so as to avoid the situation that the processing pressure of the second slave sub-module 222 is too high, which results in a breakdown.
Meanwhile, before the second main sub-module 221 receives the second beat of data from the first die 100, the second conversion unit 2212 sends a resource query instruction to the second storage unit 2211. The second storage unit 2211 sends a cross-core control signal to the first die 100 in response to the resource query instruction, so that the first die 100 determines whether to send the second beat of data to the second die 200 according to the cross-core control signal.
Specifically, when the second storage unit 2211 has the remaining space, the cross-core control signal is sent to the first die 100. The first die 100 sends a second beat of data to the second die 200 in response to the cross-die control signal. In the first die 100, the cross-core control signal is received by the first switch unit 1222, and the first switch unit 1222 transmits the cross-core control signal to the first logic unit 1223 when sending the first status query signal to the first memory unit 1221. Only when the cross-core control signal is received and the first storage unit 1221 has the remaining space, the first logic unit 1223 sends the first control signal to the first main sub-module 121 in response to the state information having the remaining space. The first master sub-module 121 sends a first beat of data to the first slave sub-module 122 in response to the first control signal.
In this embodiment, the second storage unit 2211 determines the remaining amount of storage resources of itself through the resource query instruction, and sends a cross-core control signal according to the remaining amount of storage resources, so as to control data transmission from the first die 100 to the second die 200, avoid data accumulation, and avoid a situation that data processing pressure of the second die 200 is too large, resulting in a crash, and also avoid data loss due to too much data.
In the embodiment of the application, after the first die 100 splits the first data beat received by the first interface module 110 into a plurality of second data beats through the first conversion module 120, the plurality of second data beats are sent to the second die 200 through the first cross-core module 130, the second die 200 receives the second data sent by the first die 100 through the second cross-core module 230, and the plurality of second data beats are recombined into the first data beat through the second cross-core module 230, cross-core transmission of the first data beat is realized only by internal structures of the two dies, which is helpful for reducing the size of a chip, simplifying a device structure, and saving device space.
Referring to fig. 6, an embodiment of the present application further provides a cross-protocol chip data transmission method, which is applied to the above-mentioned cross-protocol chip data transmission device, and the cross-protocol chip data transmission method includes:
step S100, receiving an original first data beat through the first interface module, where a bit width of the original first data beat is a first bit width.
Step S200, splitting the original first beat of data into a plurality of second beats of data through the first conversion module, where a bit width of the second beats of data is a second bit width, and the second bit width is smaller than the first bit width.
Step S300, cross-core transmitting the plurality of second data beats to the second cross-core module through the first cross-core module.
Step S400, merging the multiple second data beats received by the second cross-core module into a target first data beat through the second conversion module, where the data and format of the target first data beat are the same as the original first data beat.
And S500, shooting out the first target data through the second interface module.
In an embodiment of the present application, the first die 100 first receives an original first beat of data through the first interface module 110, then splits the original first beat of data into a plurality of second beats of data through the first conversion module 120, and finally cross-transmits the plurality of second beats of data to the second cross-core module 230 through the first cross-core module 130. After the second die 200 receives the multiple second data beats through the second cross-core module 230, the multiple second data beats received by the second cross-core module 230 are merged into a target first data beat through the second conversion module 220, and then the target first data beat is sent out through the second interface module 210, thereby completing the cross-core transmission of the first data beat.
In an embodiment of the present application, the first beat of data includes an original first beat of data and a target first beat of data, a protocol format of the first beat of data is different from a protocol format of cross-core transmission of the first cross-core module 130, and a bit width of the first beat of data is greater than a bit width of the second beat of data, so the first conversion module 120 may split the original first beat of data into a plurality of second beats of data according to a first predetermined format, and when a last second beat of data cannot fill up a bit width of one beat of data in a splitting process, the first beat of data may be filled with invalid data, and the invalid data may be uniformly distributed in each second beat of data. The first predetermined format is to split an original first data beat with a first bit width into a plurality of second data beats with a second bit width, a predetermined position of each second data beat is a serial number identifier, and transmission is completed only when the second die 200 receives the plurality of second data beats in the sequence of serial numbers. The predetermined location may be arbitrary, and is generally located at the beginning of the second beat of data.
Meanwhile, after receiving the plurality of second data beats, the second conversion module 220 may combine the plurality of second data beats into the target first data beat according to a second predetermined format. The second predetermined format is opposite to the first predetermined format, and is to merge a plurality of second beats of data with a second bit width ordered in sequence number order into a target first beat of data with a first bit width.
In the embodiment of the application, the cross-core transmission of the first data beat is realized only by the internal structures of the two tube cores, so that the chip size is reduced, the equipment structure is simplified, and the equipment space is saved.
The above-described embodiments are merely preferred embodiments of the present application, and are not intended to limit the scope of the present application, and various modifications and improvements made to the technical solutions of the present application by those skilled in the art without departing from the design spirit of the present application should fall within the protection scope defined by the claims of the present application.
Claims (10)
1. An inter-protocol chip data transmission device, characterized in that the inter-protocol chip data transmission device comprises a first die and a second die;
the first die includes:
the first interface module is used for receiving a first data beat;
the first conversion module is electrically connected with the first interface module and is used for splitting the first data beat received by the first interface module into a plurality of second data beats;
the first cross-core module is respectively in electrical signal connection with the first conversion module and the second die and is used for receiving a plurality of second data beats split by the first conversion module and sending the plurality of second data beats to the second die;
the second die includes:
the second cross-core module is electrically connected with the first cross-core module and is used for receiving a plurality of second data beats sent by the first cross-core module;
the second conversion module is electrically connected with the second cross-core module and is used for combining the second data beats received by the second cross-core module into the first data beats;
and the second interface module is in electrical signal connection with the second conversion module and is used for shooting the first data combined by the second conversion module.
2. The inter-protocol-chip data transmission device of claim 1, wherein the first conversion module comprises:
the first slave submodule is in electrical signal connection with the first cross-core module and is used for splitting a first data beat received by the first interface module into a plurality of second data beats and sending the second data beats to the second die through the first cross-core module;
and the first main sub-module is respectively in electric signal connection with the first interface module and the first slave sub-module, is used for receiving the first data beat received by the first interface module and distributing the first data beat to the first slave sub-module.
3. The inter-protocol-chip data transmission device of claim 2, wherein the first master sub-module is further configured to generate first check information according to the first data beat, and send the first check information to the first slave sub-module, so that the first slave sub-module determines whether there is an error in the split second data beats according to the first check information.
4. The inter-protocol-chip data transmission device of claim 2, wherein the first slave sub-module comprises:
the first storage unit is electrically connected with the first main body sub-module and is used for storing a first data beat distributed by the first main body sub-module;
and the first conversion unit is respectively in electrical signal connection with the first storage unit and the first cross-core module, and is used for splitting the first data beat stored in the first storage unit into a plurality of second data beats according to a first preset format and sending the second data beats to the second die through the first cross-core module.
5. The inter-protocol-chip data transmission device of claim 4, wherein the first slave sub-module further comprises:
and the first logic unit is respectively in electric signal connection with the first storage unit and the first main sub-module, and is used for responding to the state information of the first storage unit and sending a first control signal to the first main sub-module, so that the first main sub-module responds to the first control signal and sends the first data beat to the first slave sub-module.
6. The inter-protocol-chip data transmission device of claim 1, wherein the second conversion module comprises:
the second main body sub-module is electrically connected with the second cross-core module and is used for combining a plurality of second data beats received by the second cross-core module into a first data beat according to a second preset format;
and the second slave sub-module is respectively in electric signal connection with the second main sub-module and the second interface module and is used for sending the first data beat combined by the second main sub-module out through the second interface module.
7. The cross-protocol-chip data transmission device according to claim 6, wherein the second master sub-module is further configured to generate second check information according to the second data beat, and send the second check information to the second slave sub-module, so that the second slave sub-module determines whether the plurality of merged first data beats of the second master sub-module are wrong according to the second check information.
8. The inter-protocol-chip data transmission device of claim 6, wherein the second body sub-module comprises:
the second conversion unit is electrically connected with the second cross-core module and is used for combining a plurality of second data beats received by the second cross-core module into a first data beat according to a preset format;
and the second storage unit is respectively in electric signal connection with the second conversion unit and the second slave submodule and is used for storing the first beat of data combined by the second conversion unit so as to send out the first beat of data through the second slave submodule.
9. The inter-protocol-chip data transmission device of claim 8, wherein the second conversion module further comprises:
and the second logic unit is respectively in electric signal connection with the second storage unit and the second slave submodule and is used for responding to the state information of the second slave submodule and sending a second control signal to the second storage unit so that the second storage unit can send the first data beat to the second slave submodule in response to the second control signal.
10. A cross-protocol-chip data transmission method applied to the cross-protocol-chip data transmission device according to any one of claims 1 to 9, the cross-protocol-chip data transmission method comprising:
receiving an original first data beat through the first interface module, wherein the bit width of the original first data beat is a first bit width;
splitting the original first data beat into a plurality of second data beats through the first conversion module, wherein the bit width of the second data beats is a second bit width, and the second bit width is smaller than the first bit width;
transmit, by the first cross-core module, the plurality of second data beats cross-core to the second cross-core module;
merging, by the second conversion module, the plurality of second data beats received by the second cross-core module into a target first data beat, the target first data beat having the same data and format as the original first data beat;
and shooting the first target data through the second interface module.
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| CN108255761A (en) * | 2016-12-28 | 2018-07-06 | 英特尔公司 | Interface bridge between integrated circuit dies |
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