CN115497830A - Method for manufacturing semiconductor device and semiconductor device - Google Patents

Abstract

The present application discloses a manufacturing method of a semiconductor device and a semiconductor device, wherein the manufacturing method of the semiconductor device includes providing a substrate; forming a gate structure on the substrate; forming a field plate covering the upper surface of the gate structure and the upper surface of the substrate film layer; forming a photoresist layer with a preset pattern on a predetermined area of the field plate film layer; using the photoresist layer with a preset pattern as a mask to etch the field plate film layer to obtain a field plate, field plate and substrate The contact surface is flat. The solution can improve the performance of the semiconductor device.

Description

Manufacturing method of semiconductor device and semiconductor device

technical field

The present application relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor device and the semiconductor device.

Background technique

The BCD (Bipolar-CMOS-DMOS) process combines bipolar (Bipolar) devices, complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) devices and double-diffusion metal-oxide semiconductor (Double-diffusion Metal Oxide Semiconductor, DMOS) devices simultaneously Produced on the same chip, it combines the advantages of high transconductance, strong load driving capability of bipolar devices, high integration and low power consumption of CMOS, so that they can learn from each other and give full play to their respective advantages. Among them, the DMOS device is the core of the BCD circuit. In order to better process integration with the mature integrated circuit (Integrated Circuit, IC) process, a horizontal DMOS, namely LDMOS (Lateral Double-diffusion Metal Oxide Semiconductor) is generally used. Among them, the field plate is the core of LDMOS. In order to meet the requirements of LDMOS withstand voltage, it is necessary to use a thermal oxide layer as a field plate.

However, the contact surface between the field plate and the substrate obtained by the prior art is uneven, which leads to an increase in the on-resistance of the LDMOS, thereby degrading the performance of the LDMOS.

Contents of the invention

The present application provides a method for manufacturing a semiconductor device and the semiconductor device, which can improve the performance of the semiconductor device.

The application provides a method for manufacturing a semiconductor device, comprising:

provide a base;

forming a gate structure on the substrate;

forming a field plate film covering the upper surface of the gate structure and the upper surface of the substrate;

forming a photoresist layer with a predetermined pattern on a predetermined region of the field plate film layer;

The field plate film layer is etched by using the photoresist layer with a preset pattern as a mask to obtain a field plate, and the contact surface between the field plate and the substrate is flat.

In the method for manufacturing a semiconductor device provided in the present application, the field plate film layer is etched using the photoresist layer with a preset pattern as a mask to obtain a field plate, including:

Using the photoresist layer as a mask to sequentially perform first etching on the field plate film layer;

removing the photoresist layer, and performing a second etching on the first etched field plate film layer to obtain the field plate.

In the method for manufacturing a semiconductor device provided in this application, the field plate film layer includes a first film layer, a second film layer, and a third film layer that are sequentially stacked, and the first film layer is located near the base of the substrate. On one side, the thickness of the first film layer is 100Å-800Å, the thickness of the second film layer is 200Å-600Å, and the thickness of the third film layer is 100Å-500Å.

In the manufacturing method of the semiconductor device provided in the present application, the field plate film layer after the first etching includes a first film layer and a second film layer, and the residual thickness of the second film layer is 50Ř200Å.

In the manufacturing method of the semiconductor device provided in the present application, the thickness of the second etched field plate film layer in the non-preset area is 0, and the residual thickness of the second film layer of the field plate is 30Ř200Å.

In the method for manufacturing a semiconductor device provided in the present application, the material of the first film layer is silicon oxide, the material of the second film layer is silicon nitride, and the material of the third film layer is silicon oxide.

In the manufacturing method of the semiconductor device provided in the present application, after the field plate film layer is etched using the photoresist layer as a mask to obtain the field plate, it further includes:

forming a crystallized layer covering the upper surface of the substrate and the upper surface of the gate structure;

forming a dielectric layer covering the upper surface of the substrate, the upper surface of the gate structure and the upper surface of the field plate;

forming a first contact hole, a second contact hole, a third contact hole and a fourth contact hole penetrating through the dielectric layer;

A first metal structure, a second metal structure, a third metal structure and a fourth metal structure are formed on the dielectric layer, and the first metal structure, the second metal structure and the third metal structure pass through the first metal structure respectively A contact hole, the second contact hole and the third contact hole are connected to the crystallized layer, and the fourth metal structure is connected to the field plate through the fourth contact hole.

In the manufacturing method of the semiconductor device provided in the present application, the material of the photoresist layer is a KrF type positive photoresist, the thickness of the photoresist layer is 5000Å~20000Å, and the critical dimension of the photoresist layer is 0.15um~ 0.8um.

In the method for manufacturing a semiconductor device provided in the present application, the first etching is a dry etching process, and the second etching is a wet etching process.

The present application provides a semiconductor device, the semiconductor device is made by the above-mentioned manufacturing method of the semiconductor device, and the semiconductor device includes:

base;

a gate structure, the gate structure is disposed on the substrate;

The field plate is arranged on the substrate, and the contact surface between the field plate and the substrate is a plane.

In summary, the method for manufacturing a semiconductor device provided by the present application includes: providing a substrate; forming a gate structure on the substrate; forming a field plate film covering the upper surface of the gate structure and the upper surface of the substrate; A photoresist layer with a preset pattern is formed on a preset region of the field plate film layer; the field plate film layer is etched using the photoresist layer with a preset pattern as a mask to obtain a field plate, and the The contact surface between the field plate and the substrate is plane. Through this solution, a field plate with a flat contact surface with the substrate can be obtained, thereby avoiding an increase in the on-resistance of the semiconductor device due to an uneven contact surface between the field plate and the substrate. That is, this solution can reduce the on-resistance of the semiconductor device, thereby increasing the performance of the semiconductor device.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can also be obtained based on these drawings without any creative effort.

FIG. 1 is a schematic flowchart of a manufacturing method of a semiconductor device provided in the present application.

2-6 are structural schematic diagrams of the middleware of the semiconductor device provided by the present application.

FIG. 7 is a schematic structural diagram of a semiconductor device provided in the present application.

FIG. 8 is a layout of a semiconductor device provided in the prior art.

FIG. 9 is a layout of a semiconductor device provided by the present application.

detailed description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numerals in different drawings refer to the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with aspects of the present application as recited in the appended claims.

It should be noted that, in this document, the term "comprising", "comprising" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article or apparatus comprising a set of elements includes not only those elements, It also includes other elements not expressly listed, or elements inherent in the process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a..." does not exclude the existence of other identical elements in the process, method, article, or device that includes the element. In addition, different implementations of the present application Components, features, and elements with the same name in the example may have the same meaning, or may have different meanings, and the specific meaning shall be determined based on the explanation in the specific embodiment or further combined with the context in the specific embodiment.

It should be understood that the specific embodiments described here are only used to explain the present application, and are not intended to limit the present application.

In the following description, the use of suffixes such as 'module', 'part' or 'unit' for denoting elements is only for facilitating the description of the present application and has no specific meaning by itself. Therefore, 'module', 'part' or 'unit' may be mixedly used.

The embodiments involved in the present application are described in detail below. It should be noted that the description order of the embodiments in the present application is not used as a limitation on the priority order of the embodiments.

The technical solutions shown in this application will be described in detail below through specific embodiments. It should be noted that the order of description of the following embodiments is not intended to limit the order of priority of the embodiments.

Field plate is the core of LDMOS. In order to meet the requirements of LDMOS withstand voltage, it is necessary to use a thermal oxide layer as a field plate. At present, the formation method of the field plate is generally to generate a pad oxide layer and a pad silicon nitride layer as a liner through two thermal oxidation processes, and then define the growth area and shape of the field plate by photolithography, and then obtain the field plate by thermal growth. Finally, the pad oxide layer and the pad silicon nitride layer are removed.

However, a "bird's beak" will be formed between the field plate formed in the above way, the gate, and the substrate, and the electric field lines in multiple directions will be concentrated in the "bird's beak" area, making the electric field strength in this area stronger and prone to breakdown. Therefore, due to the existence of the "bird's beak", the breakdown voltage of LDMOS is low.

Moreover, due to the unevenness of the contact surface between the field plate and the substrate, the on-resistance of the LDMOS will increase, thereby reducing the performance of the LDMOS.

Based on this, the present application provides a method for manufacturing a semiconductor device, please refer to FIG. 1 , which is a schematic flowchart of the method for manufacturing a semiconductor device provided in the present application. The specific flow of the manufacturing method of the semiconductor device can be as follows:

101. Provide a substrate 10.

In some embodiments, the base 10 may be a semiconductor substrate. In another embodiment, the base 10 may include a semiconductor substrate, a buried layer and an epitaxial layer. Wherein, the buried layer and the epitaxial layer are sequentially stacked on the semiconductor substrate.

In some embodiments, after the substrate 10 is formed, ion implantation into the drift region, the channel region, the source region, the drain region, and the deep well region may be performed on the substrate 10 . It should be noted that when the base 10 is a semiconductor substrate, the drift region, channel region, source region, drain region, deep well region and other ion implantation regions are located in the semiconductor substrate. When the base 10 includes a semiconductor substrate, a buried layer and an epitaxial layer, the drift region, the channel region, the source region, the drain region, the deep well region and the plasma implantation region are located in the semiconductor substrate and in the epitaxial layer.

In some embodiments, the channel region may be a first conductivity type channel region, the drift region may be a second conductivity type drift region, the source region may be a second conductivity type source region, and the drain region may be a second conductivity type. For the conductivity type drain region, the buried layer may be a first conductivity type buried layer, and the epitaxial layer may be a second conductivity type epitaxial layer. It should be noted that the first conductivity type is P type and the second conductivity type is N type; or the first conductivity type is N type and the second conductivity type is P type.

In a specific implementation process, the buried layer may be formed by performing ion implantation of the first conductivity type on the upper surface layer of the semiconductor substrate. For example, Sb ion implantation can be performed on the upper surface layer of the semiconductor substrate to obtain the buried layer. There are many methods for forming the epitaxial layer, such as physical vapor deposition, chemical vapor deposition or other suitable methods.

Among them, the material of the semiconductor substrate can be single crystal silicon, silicon carbide, gallium arsenide, indium phosphide or silicon germanium, etc. The semiconductor substrate can also be a germanium silicon substrate, a III-V element compound substrate, Silicon substrate or its laminated structure, or silicon-on-insulator structure, also can be diamond substrate or other semiconductor material substrates known to those skilled in the art, for example, can implant P atoms in single crystal silicon to form N-type conductive The semiconductor substrate can also be implanted with B atoms in single crystal silicon to form a P-type conductive semiconductor substrate.

It can be understood that the surface of the substrate 10 may have a natural oxide layer, surface particles, metal ions, etc., resulting in an uneven surface of the substrate 10 . In order to solve the above problems, the substrate 10 may be cleaned by a wet cleaning process after ion implantation. For example, chemical reagents are used to clean the substrate 10 to remove the natural oxide layer, surface particles, metal ions, etc. on the surface of the substrate 10 .

Wherein, the chemical reagent may include one or a combination of sulfuric acid, hydrochloric acid, nitric acid, and hydrofluoric acid. That is to say, the acidic solution may include any one of the above-mentioned various solutions, or may also include a combination of any two or more of the above-mentioned various solutions, which is not limited in this embodiment .

102 . Form a gate structure 20 on the substrate 10 .

Wherein, the gate structure 20 shown in FIG. 2 may include a gate layer and a gate spacer. Gate spacers are located on both sides of the gate layer.

In this embodiment, the material of the gate layer is polysilicon. In other embodiments, the material of the gate layer may be amorphous silicon, silicon carbide, and the like. The material of the gate spacer may include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbonitride.

103 , forming a field plate film layer 30 covering the upper surface of the gate structure 20 and the upper surface of the substrate 10 .

Wherein, the field plate film layer 30 includes a first film layer, a second film layer and a third film layer stacked in sequence, and the first film layer is located on a side close to the substrate 10 .

In this embodiment, the thickness of the first film layer is 100Å-800Å, the thickness of the second film layer is 200Å-600Å, and the thickness of the third film layer is 100Å-500Å. The material of the first film layer is silicon oxide, the material of the second film layer is silicon nitride, and the material of the third film layer is silicon oxide.

In some embodiments, the structure shown in FIG. 3 can be obtained by sequentially depositing a first film layer, a second film layer and a third film layer on the substrate 10 by chemical vapor deposition.

104 . Form a photoresist layer 40 with a predetermined pattern on the predetermined region 31 of the field plate film layer 30 .

Wherein, the field plate film layer 30 may include a preset region 31 and a non-preset region. It can be understood that the non-predetermined region is the region of the field plate film 30 except the predetermined region 31 .

Specifically, a photoresist material may be coated on the predetermined region 31 of the field plate film layer 30 to form the photoresist layer 40 . Then, photolithography is performed on the photoresist layer 40 to obtain the photoresist layer 40 with a predetermined pattern. Wherein, performing photolithography on the photoresist layer 40 may include: coating a photoresist layer on the photoresist layer 40; exposing and developing the photoresist layer to form a preset pattern; using the photoresist layer as mask, etch the photoresist layer 40 along a preset pattern, so as to obtain the photoresist layer 40 with a preset pattern; finally, remove the photoresist layer.

In some embodiments, after forming the photoresist layer 40 with a predetermined pattern, the photoresist layer 40 may be cured. For example, the photoresist layer 40 is cured by ultraviolet rays, the photoresist layer 40 is cured by a baking process, and the like.

In the embodiment of the present application, the material of the photoresist layer 40 is KrF (light source 248nm) type positive photoresist. The thickness of the photoresist layer 40 is 5000Ř20000Å. The critical dimension (Critical Dimension, CD) of the photoresist layer 40 is 0.15um~0.8um.

105 . Etching the field plate film layer 30 by using the photoresist layer 40 with a predetermined pattern as a mask to obtain the field plate 32 . The contact surface between the field plate 32 and the substrate 10 is a plane.

In some embodiments, the field plate film layer 30 can be etched by using the photoresist layer 40 as a mask directly by using a dry etching process or a wet etching process, and then the photoresist layer 40 is removed to obtain contact with the substrate 10. The face is a flat field plate 32 . Please refer to Figure 4-Figure 5 for details.

However, directly using a dry etching process (anisotropic etching) is likely to damage the wafer and cause leakage. Directly adopting the wet etching process (isotropic etching) will form oblique protrusions on the sidewall of the field plate 32 to increase the interlayer capacitance. Therefore, in this embodiment, in order to avoid the above situation, the field plate film layer 30 is etched in a manner of cooperating with a dry etching process and a wet etching process in this embodiment.

Specifically, the first etching can be performed on the field plate film layer 30 by using the photoresist layer 40 as a mask; then, the photoresist layer 40 is removed, and the second etching is performed on the field plate film layer 30 after the first etching to obtain the field plate film layer 30. plate 32.

Wherein, the first etching is a dry etching process. In some embodiments, the field plate film layer 30 can be dry-etched by using the photoresist layer 40 as a mask and using carbon tetrafluoride as an etching gas.

Wherein, the second etching is a wet etching process. In some embodiments, after removing the photoresist layer 40, hydrofluoric acid can be used as an etchant to perform a wet etching process on the first etched field plate film layer 30, so that the contact surface with the substrate 10 is flat. The field plate 32.

It can be understood that the second etched field plate film layer 30 is the field plate 32 . In some embodiments, the photoresist layer 40 may be removed by an ashing process.

To sum up, this embodiment can avoid the leakage caused by directly using the dry etching process to damage the wafer, and effectively avoid the beveled protrusions formed on the sidewall of the field plate by directly using the wet etching process, thereby reducing the interlayer capacitance.

It should be noted that after the first etching, the third film layer is completely etched, and the second film layer is not etched or partially etched. That is, the first etched field plate film layer 30 includes a first film layer and a second film layer. It should be noted that, after the second etching, the remaining thickness of the second film layer is 50Ř200Å.

After the second etching, the field plate film layer 30 in the non-predetermined area is completely etched, and the second film layer of the field plate 32 is not etched or partially etched. Specifically, after the second etching, the loss of the second film thickness of the field plate 32 is 0Ř20Å. That is, after the second etching, the residual thickness of the second film layer of the field plate 32 is 30Ř200Å.

In this embodiment, the substrate 10 is not consumed during the formation of the field plate 32 , and the substrate 10 is a plane. Therefore, the contact surface of the field plate 32 and the substrate 10 is a plane. Therefore, the semiconductor device provided by this embodiment does not have a "bird's beak", thereby avoiding the problem in the prior art that the breakdown voltage of the semiconductor device is low due to the existence of the "bird's beak". That is, this embodiment can increase the breakdown voltage of the semiconductor device and improve the reliability of the semiconductor device.

Moreover, compared with the prior art, since the contact surface between the field plate 32 and the substrate 10 is flat, the conduction path of the current of the semiconductor device can be reduced, thereby reducing its on-resistance and improving the performance of the semiconductor device.

In addition, compared with the prior art, the embodiment of the present application reduces the formation process of the pad oxide layer and the pad silicon nitride layer. That is, the embodiment of the present application can reduce two thermal oxidation processes, thereby reducing the manufacturing cost and time cost of the semiconductor device.

In some embodiments, as shown in FIGS. 6-7 , after the field plate 32 is formed, it may further include:

forming a crystallized layer 50 covering the upper surface of the substrate 10 and the upper surface of the gate structure 20;

forming a dielectric layer 60 covering the upper surface of the substrate 10, the upper surface of the gate structure 20 and the upper surface of the field plate 32;

forming a first contact hole 61 , a second contact hole 62 , a third contact hole 63 and a fourth contact hole 64 penetrating through the dielectric layer 60;

A first metal structure 71, a second metal structure 72, a third metal structure 73 and a fourth metal structure 74 are formed on the dielectric layer 60, and the first metal structure 71, the second metal structure 72 and the third metal structure 73 pass through the first metal structure 73 respectively. A contact hole 61 , a second contact hole 62 and a third contact hole 63 are connected to the crystallized layer 50 , and the fourth metal structure 74 is connected to the field plate 32 through the fourth contact hole 64 .

It should be noted that the upper surface of the substrate 10 refers to the surface of the substrate 10 close to the gate structure 20 . The upper surface of the gate structure 20 refers to the surface of the gate structure 20 facing away from the substrate 10 .

It should be noted that the crystallization layer 50 covering the upper surface of the substrate 10 is respectively located on the source region and the drain region, and the field plate 32 is located on part of the drift region and part of the drain region. That is, the first metal structure 71 can be connected to the source region through the first contact hole 61, the second metal structure 72 can be connected to the gate structure 20 through the second contact hole 62, and the third metal structure 73 can be connected to the gate structure 20 through the third contact hole. The hole 63 is connected to the drain region. The fourth metal structure 74 may be connected to the drift region through the fourth contact hole 64 .

That is, in the semiconductor device provided in the present application, a voltage can be directly applied to the field plate 32 through the fourth metal structure 74 and the fourth contact hole 64 to form a field plate capacitance and deplete the drift region. In some embodiments, the second metal structure 72 can be electrically connected to the fourth metal structure 74, so that the second metal structure 72 and the fourth metal structure 74 apply a voltage to the field plate 32 at the same time, thereby increasing the depletion of the semiconductor device. ability.

Please refer to FIG. 8-FIG. 9, FIG. 8 is a layout of a semiconductor device provided in the prior art, and FIG. 9 is a layout of a semiconductor device provided in the present application. Wherein, 1 is a polycrystalline layer, 2 is a field plate, 3 is a crystallization layer, and 4 is a contact hole. It should be noted that, in FIGS. 8-9 , O1≈O2, L1+W1>L2+W2.

O2 of the semiconductor device provided by the present application is approximately equal to O1 in the prior art, therefore, the field plate capacitance of the semiconductor device provided by the present application is almost equal to the field plate capacitance of the prior art. Moreover, since there is no overlapping portion between the field plate and the polysilicon in the semiconductor device provided by the present application, L1+W1 is much smaller than L2+W2. That is, compared with the prior art, the size of the semiconductor device provided by the present application can be greatly reduced.

In summary, the method for manufacturing a semiconductor device provided by the present application includes providing a substrate 10; forming a gate structure 20 on the substrate 10; forming a field plate film layer 30 covering the upper surface of the gate structure 20 and the upper surface of the substrate 10; A photoresist layer 40 with a preset pattern is formed on the preset region 31 of the film layer 30; the field plate film layer 30 is etched with the photoresist layer 40 having a preset pattern as a mask to obtain a field plate 32, and the field plate 32 The contact surface with the substrate 10 is a plane. The solution can improve the reliability and performance of the semiconductor device. Also, it is possible to reduce the size of the semiconductor device.

Referring to FIG. 5 , the present application provides a semiconductor device, which includes a substrate 10 and a field plate 32 . Wherein, the field plate 32 is disposed on the substrate 10 . The contact surface of the field plate 32 and the substrate 10 is a plane.

In this embodiment, the substrate 10 is not consumed during the formation of the field plate 32 , and the substrate 10 is a plane. Therefore, the contact surface of the field plate 32 and the substrate 10 is a plane. Therefore, the semiconductor device provided by this embodiment does not have a "bird's beak", thereby avoiding the problem in the prior art that the breakdown voltage of the semiconductor device is low due to the existence of the "bird's beak". That is, this embodiment can increase the breakdown voltage of the semiconductor device and improve the reliability of the semiconductor device.

Moreover, compared with the prior art, since the contact surface between the field plate 32 and the substrate 10 is flat, the conduction path of the current of the semiconductor device can be reduced, thereby reducing its on-resistance and improving the performance of the semiconductor device.

In addition, compared with the prior art, the embodiment of the present application reduces the formation process of the pad oxide layer and the pad silicon nitride layer. That is, the embodiment of the present application can reduce two thermal oxidation processes, thereby reducing the manufacturing cost and time cost of the semiconductor device.

For the specific manufacturing process of the semiconductor device, reference may be made to the various embodiments in the above-mentioned manufacturing method of the semiconductor device, which will not be repeated here. It should be noted that the meanings of the nouns are the same as those in the above-mentioned manufacturing method of the semiconductor device, and for specific implementation details, reference may be made to the description in the method embodiments.

The manufacturing method of the semiconductor device and the semiconductor device provided by the application have been introduced in detail above. The principles and implementation methods of the application have been explained by using specific examples in this paper. The description of the above embodiments is only used to help understand the application. core idea; at the same time, for those skilled in the art, according to the idea of this application, there will be changes in the specific implementation and application scope. In summary, the content of this specification should not be construed as limiting the application.

Claims (10)

1. A method of manufacturing a semiconductor device, comprising:

providing a substrate;

forming a gate structure on the substrate;

forming a field plate film layer covering the upper surface of the grid structure and the upper surface of the substrate;

forming a photoresist layer with a preset pattern on a preset region of the field plate film layer;

and etching the field plate film layer by using the photoresist layer with a preset pattern as a mask to obtain a field plate, wherein the contact surface of the field plate and the substrate is a plane.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the etching the field plate film layer by using the photoresist layer with a predetermined pattern as a mask to obtain a field plate comprises:

sequentially carrying out first etching on the field plate film layer by taking the photoresist layer as a mask;

and removing the photoresist layer, and performing second etching on the field plate film layer after the first etching to obtain the field plate.

3. The method of manufacturing a semiconductor device of claim 2, wherein the field plate film layer comprises a first film layer, a second film layer, and a third film layer that are sequentially stacked, the first film layer being located on a side proximate to the substrate, the first film layer having a thickness of 100A-800A, the second film layer having a thickness of 200A-600A, and the third film layer having a thickness of 100A-500A.

4. The method of manufacturing a semiconductor device of claim 2, wherein the first etched field plate film layer comprises a first film layer and a second film layer, and the second film layer has a residual thickness of 50A-200A.

5. The method of manufacturing a semiconductor device according to claim 2, wherein the thickness of the second etched field plate film layer in the non-predetermined region is 0, and the residual thickness of the second film layer of the field plate is 30A-200A.

6. The method for manufacturing a semiconductor device according to claim 3, wherein the first film layer is made of silicon oxide, the second film layer is made of silicon nitride, and the third film layer is made of silicon oxide.

7. The method for manufacturing a semiconductor device according to claim 1, wherein after the etching the field plate film layer using the photoresist layer as a mask to obtain a field plate, the method further comprises:

forming a crystallization layer covering the upper surface of the substrate and the upper surface of the gate structure;

forming a dielectric layer covering the upper surface of the substrate, the upper surface of the grid structure and the upper surface of the field plate;

forming a first contact hole, a second contact hole, a third contact hole and a fourth contact hole which penetrate through the dielectric layer;

and forming a first metal structure, a second metal structure, a third metal structure and a fourth metal structure on the dielectric layer, wherein the first metal structure, the second metal structure and the third metal structure are respectively connected with the crystallization layer through the first contact hole, the second contact hole and the third contact hole, and the fourth metal structure is connected with the field plate through the fourth contact hole.

8. The method for manufacturing a semiconductor device according to claim 1, wherein a material of the light-blocking layer is a KrF-type positive photoresist, the thickness of the light-blocking layer is from 5000A to 20000A, and the critical dimension of the light-blocking layer is from 0.15um to 0.8um.

9. The method for manufacturing a semiconductor device according to claim 2, wherein the first etching is a dry etching process, and the second etching is a wet etching process.

10. A semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 9, comprising:

a substrate;

the grid structure is arranged on the substrate;

the field plate is arranged on the substrate, and the contact surface of the field plate and the substrate is a plane.

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