CN115497879B

CN115497879B - Method for manufacturing semiconductor structure

Info

Publication number: CN115497879B
Application number: CN202110677055.6A
Authority: CN
Inventors: 吴柏翰; 蔡百钧; 欧阳自明; 李书铭
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2021-06-18
Filing date: 2021-06-18
Publication date: 2025-04-18
Anticipated expiration: 2041-06-18
Also published as: CN115497879A

Abstract

The invention discloses a manufacturing method of a semiconductor structure, which comprises the steps of forming a material laminated layer on a substrate and covering an array area and a peripheral area of the substrate, forming a first patterning mask layer on the material laminated layer, transferring patterns of the first patterning mask layer to the material laminated layer to form a first array pattern and a first peripheral pattern in the array area and the peripheral area, providing a second patterning mask layer above the first array pattern and the first peripheral pattern, staggering the patterns of the second patterning mask layer and the first patterning mask layer, transferring the patterns of the second patterning mask layer downwards to form a first sacrificial pattern and a second sacrificial pattern in the array area and the peripheral area, and simultaneously transferring the patterns of the first array pattern, the first sacrificial pattern, the first peripheral pattern and the second sacrificial pattern to form a second array pattern and a second peripheral pattern in the array area and the peripheral area respectively. The manufacturing method of the semiconductor structure provided by the invention can simplify the process steps and reduce the cost.

Description

Method for manufacturing semiconductor structure

Technical Field

The present invention relates to a method for manufacturing a semiconductor structure, and more particularly, to a method for manufacturing a material layer for patterning an array region and a peripheral region of a semiconductor structure.

Background

In recent years, as the technology for manufacturing dynamic random access memory (Dynamic Random Access Memory, DRAM) devices continues to advance toward the miniaturization of device dimensions, many challenges are presented. For example, the patterning process is performed separately on the material layers of the array region and the peripheral region of the semiconductor structure, and multiple precise steps are required to perform the patterning process in response to the reduced device size, which is also relatively expensive and has long process time. Accordingly, there remains a need for improved methods of fabricating dynamic random access memory devices, and in particular, for overcoming various problems that may occur when patterning processes are performed with reduced device dimensions.

Disclosure of Invention

The invention provides a manufacturing method of a semiconductor structure, which comprises the steps of forming a first material layer above a substrate, wherein the substrate comprises an array region and a peripheral region, the first material layer covers the array region and the peripheral region, the first material layer comprises a first pattern transfer layer and a second pattern transfer layer, forming a first pattern mask layer on the first material layer of the array region and the peripheral region, the first pattern mask layer exposes part of the top surface of the first material layer, removing a part of the first material layer by taking the first pattern mask layer as a mask to transfer the pattern of the first pattern mask layer to a second pattern transfer layer, forming a first array pattern and a first peripheral pattern in the array region and the peripheral region respectively, providing a second pattern mask layer corresponding to the array region and the peripheral region above the first array pattern and the first peripheral pattern, wherein the pattern of the second pattern mask layer is staggered with the pattern of the first pattern mask layer (for example in a first direction), transferring the second pattern mask layer as a pattern transfer layer in the first direction, and the peripheral pattern in the first array region and the peripheral region simultaneously, and forming a second array pattern in the first array region and the peripheral region.

In addition, in one embodiment, after the second array pattern and the second peripheral pattern are formed, the method further includes forming a second material layer over the second array pattern and the second peripheral pattern, forming a third patterned mask layer over the second material layer in the array region and the peripheral region, and performing a self-aligned double patterning process according to the pattern of the third patterned mask layer to form a patterned material layer, wherein the patterned material layer includes the third array pattern formed in the array region.

In addition, in one embodiment, after forming the third array pattern, the method further includes forming a fourth patterned mask layer to cover the peripheral region and the third array pattern exposing the array region, and removing the exposed portion of the underlying material layer and the corresponding portion of the second array pattern with the fourth patterned mask layer and the third array pattern as masks to convert the second array pattern into a final array pattern.

The embodiment of the invention defines the pattern of the array region along the first direction while defining the pattern of the peripheral region, and compared with the traditional process of separately manufacturing the array pattern and the peripheral pattern, the manufacturing method of the semiconductor structure provided by the invention can simplify the process steps and reduce the cost. In addition, since the present invention can produce high-density array patterns by using only one SADP process, the present invention can greatly reduce the production cost compared with the conventional method in which multiple (e.g. more than four) complex and expensive SADP processes are used to produce array patterns with the same density.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. In the drawings:

FIGS. 1A, 1B, 2-5, 6A, 6B, 7A, 7B, 8-15, 16A, 16B, 17 are schematic views of a semiconductor structure at various stages of fabrication according to an embodiment of the present invention, wherein FIG. 1B is a schematic cross-sectional view taken along line B-B in the schematic top view of FIG. 1A;

FIG. 6B is a schematic cross-sectional view taken along line B-B of the schematic top view of FIG. 6A, respectively;

FIG. 7B is a schematic cross-sectional view taken along line B-B of the schematic top view of FIG. 7A, respectively;

fig. 16B is a schematic cross-sectional view taken along line B-B in the schematic plan view of fig. 16A, respectively.

Reference numerals and signs

10 Substrate

11 Cover layer (cap layer)

12 Target Material layer

12-1 Tungsten nitride layer

12-2 Tungsten layer

120A target array pattern

120B target peripheral pattern

13 Carbide layer

14,18 Dielectric layer

15,150 Nitrogen-containing layer

16,160,21,210,34,340 Polysilicon layer

17,22,220,25,250,31,310,35,350 Carbonaceous layer

21A first array pattern

21B first peripheral pattern

211,212,241,242,271,272,291,292,371,372 Openings of

23,230,26,260,36 Antireflection layer

24,27,37,46 Patterning a mask layer

24A,24b,27a,27b,37a,37b: mask pattern

25S sacrificial pattern layer

25S-a first sacrificial pattern

25S-b second sacrificial pattern

29,290 Polysilicon pattern layer

29A second array pattern

29B second perimeter pattern (final perimeter pattern)

290A final array pattern

32,320 Nitride layer

32A first nitrided pattern

32B second nitrided pattern

33,330 Silicon oxide layer

38 Core Pattern layer

38A first core pattern

38B second core pattern

41,410 Spacer material layer

42,420,42R planarization layer

43 Patterning the stack layer

43A first stack

43B second stack

43' Patterning a stack of materials

43A': first material stack (third array pattern)

43B' second material stack

A1 array region

A2 peripheral region

B-B line

D1, D2, D3, dc: direction

ML-1 first material lamination

ML-2 second material lamination

L1, L2, L3 Pattern transfer layer

Detailed Description

Referring to fig. 1A and 1B, a substrate 10 and a first material stack ML-1 are provided, the substrate 10 including an array region A1 and a peripheral region A2. In one embodiment, the material of the substrate 10 may comprise a semiconductor material. In one embodiment, the substrate 10 is comprised of silicon, gallium arsenide, gallium nitride, germanium silicide, other suitable materials, or combinations of the foregoing. In one embodiment, the substrate 10 is a silicon-on-insulator (silicon on insulator) substrate. Various components, such as buried word lines, isolation structures, bit lines, etc., may be formed within the substrate 10 and above the substrate 10, and such components are omitted from the drawings herein for simplicity of illustration and description.

The first material layer ML-1 is formed over the substrate 10 and covers the array region A1 and the peripheral region A2. The first material layer ML-1 comprises a plurality of materials, such as a dielectric layer 14, a pattern transfer layer L1, a dielectric layer 18, and a pattern transfer layer L2, which are sequentially formed over the substrate 10. In one embodiment, the method for forming the plurality of material layers included in the first material layer ML-1 may include Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), spin coating, other suitable processes, or combinations thereof. In one embodiment, dielectric layer 14 and dielectric layer 18 are comprised of an insulating material, such as silicon nitride (SiN). In one example, the thickness of dielectric layer 18 is about, but not limited to, 30nm and the thickness of dielectric layer 14 is about, but not limited to, 70nm.

In one embodiment, the pattern transfer layer L1 includes a nitrogen-containing layer 15, a polysilicon layer 16, and a carbon-containing layer 17 sequentially formed over the dielectric layer 14. The nitrogen-containing layer 15 is, for example, a material different from that of the dielectric layer 14. In this example, the nitrogen-containing layer 15 is an oxygen-rich silicon oxynitride (O-rich SiON). The carbon-containing layer 17 comprises a carbide, such as diamond-like carbon, amorphous carbon film, a highly selective transparent carbon-containing layer, and may be, but is not limited to, about 70nm to about 100nm thick. In this example, carbon-containing layer 17 is a high-selectivity transparent carbon-containing layer. Here, the pattern transferring layer L1 is described as including the nitrogen-containing layer 15, the polysilicon layer 16, and the carbon-containing layer 17, but the present invention is not limited thereto, and in other embodiments, the pattern transferring layer L1 may be a combination of other material layers suitable for pattern transferring.

In one embodiment, the pattern transfer layer L2 includes a polysilicon layer 21, a carbon-containing layer 22, and an anti-reflective layer 23 sequentially formed over the dielectric layer 18. The carbon-containing layer 22 includes, for example, a carbide such as diamond-like carbon, an amorphous carbon film, a high selectivity transparent carbon-containing layer. In this example, the carbon-containing layer 22 is a spin-on carbon layer. The material of the anti-reflection layer 23 includes, for example, an organic polymer, carbon, silicon oxynitride, or the like. Here, the pattern transferring layer L2 is described as including the nitrogen-containing layer 15, the polysilicon layer 16, and the carbon-containing layer 17, but the present invention is not limited thereto, and in other embodiments, the pattern transferring layer L2 may be a combination of other material layers suitable for pattern transferring.

In one embodiment, the target material layer 12 and other material layers are further disposed between the substrate 10 and the first material layer ML-1 to cover the array area A1 and the peripheral area A2. For example, a cap layer 11, a target material layer 12, and a carbide layer 13, which are sequentially formed over the substrate 10, are further included between the substrate 10 and the first material layer ML-1. Methods of forming the cap layer 11, the target material layer 12, and the carbide layer 13 may include PVD, CVD, ALD, spin coating, other suitable processes, or combinations of the foregoing, for example.

The cap layer 11 is, for example, a silicon nitride layer or other suitable insulating material. The target material layer 12 is, for example, a single layer or multiple layers of conductive material. In one embodiment, the target material layer 12 may comprise tungsten, tungsten nitride, copper, aluminum copper alloy, polysilicon, silicon germanium, other suitable conductive materials, or a combination of the foregoing. In this example, the target material layer 12 may include, for example, a tungsten nitride layer 12-1 and a tungsten layer 12-2. The carbide layer 13 includes, for example, diamond-like carbon, an amorphous carbon film, and a high-selectivity transparent carbon-containing layer (HIGHLY SELECTIVE TRANSPARENT carbon-containing layer). In this example, carbide layer 13 is a high-selectivity transparent carbon-containing layer.

Referring again to fig. 1A and 1B, a patterned mask layer 24 (e.g., a patterned photoresist) is provided over the first material layer ML-1, wherein the patterned mask layer 24 exposes a portion of the top surface of the first material layer ML-1. The patterned mask layer 24 includes a mask pattern 24a and a mask pattern 24b, which are respectively formed on the anti-reflective layer 23 of the array region A1 and the peripheral region A2, and expose a portion of the top surface of the anti-reflective layer 23. Further, an opening 241 is included in the mask pattern 24a, and an opening 242 is included in the mask pattern 24 b.

Next, referring to fig. 1A-1B, fig. 2-5, fig. 6A, and fig. 6B, the present invention defines a final peripheral pattern (e.g., the second peripheral pattern 29B shown in fig. 6A and fig. 6B) in the peripheral area A2 and defines a line pattern (e.g., the second array pattern 29a shown in fig. 6A and fig. 6B) along a specific direction in the array area A1 by a two-stage photolithography process. Generally, the first array pattern 21A and the first peripheral pattern 21B (fig. 3) with larger line widths are formed by a first stage photolithography process (as illustrated in fig. 1A-1B and fig. 2-3), and then the second array pattern 29a and the second peripheral pattern 29B (fig. 6A-6B) are formed by further increasing the pattern density of the first array pattern 21A and the first peripheral pattern 21B by a second stage photolithography process (as illustrated in fig. 4-5 and fig. 6A-6B).

Referring to fig. 1A-1B and fig. 2, the patterned mask layer 24 is used as a mask to remove the pattern transfer layer L2 not covered by the patterned mask layer 24. In one embodiment, the portions of the anti-reflective layer 23 and the underlying carbon-containing layer 22 and polysilicon layer 21 exposed by the openings 241 and 242 are removed, for example, by a dry etching process. As shown in fig. 2, after etching, the pattern of the patterned mask layer 24 is transferred to the underlying pattern transfer layer L2 to form an anti-reflective layer 230, a carbon-containing layer 220, and a polysilicon layer 210. In this exemplary step, dielectric layer 18 may act as an etch stop layer.

Thereafter, as shown in fig. 3, the patterned masking layer 24, the carbon-containing layer 220, and the anti-reflective layer 230 are removed, leaving the polysilicon layer 210. The polysilicon layer 210 includes a first array pattern 21a in the array region A1 and a first peripheral pattern 21b in the peripheral region A2. Further, the first array pattern 21a includes openings 211 therein, and the first peripheral pattern 21b includes openings 212 therein. The openings 211 and 212 are portions of the top surface of the dielectric layer 18 exposed. In one embodiment, the first array pattern 21a and, for example, extends along the direction D2. Further, the first array pattern 21a and the first peripheral pattern 21b are separated in the direction D1, for example.

Next, as shown in fig. 4, a carbon-containing layer 25 and an anti-reflective layer 26 are sequentially formed over the polysilicon layer 210. Methods of forming carbon-containing layer 25 and antireflective layer 26 may include PVD, CVD, ALD, spin coating, other suitable processes, or a combination of the foregoing. The carbon-containing layer 25 completely covers the first array pattern 21a and the first peripheral pattern 21b, and fills the openings 211 and 212. The carbon-containing layer 25 includes, for example, a carbide such as diamond-like carbon, an amorphous carbon film, a high-selectivity transparent carbon-containing layer. In this example, carbon-containing layer 25 is a spin-on carbon layer. The antireflective layer 26 is, for example, composed of an organic polymer, carbon, silicon oxynitride, or the like.

Referring to fig. 4 again, a patterned mask layer 27 (e.g. a patterned photoresist layer) is formed on the anti-reflective layer 26, wherein the patterned mask layer 27 includes a mask pattern 27a and a mask pattern 27b respectively formed on the anti-reflective layer 26 of the array region A1 and the peripheral region A2, and a portion of the top surface of the anti-reflective layer 26 is exposed. Further, an opening 271 is included in the mask pattern 27a, and an opening 272 is included in the mask pattern 27 b. Furthermore, the patterning mask layer 27 is offset from the pattern of the polysilicon layer 210 (i.e., the pattern of the patterning mask layer 24), for example, in the direction D1. For example, as shown in fig. 4, the openings 271 of the mask pattern 27a correspond to the first array pattern 21a of the underlying polysilicon layer 210, and the openings 272 of the mask pattern 27b correspond to the first peripheral pattern 21b of the underlying polysilicon layer 210. In one embodiment, the extending direction of the mask pattern 24a is substantially the same as the extending direction of the mask pattern 27 a.

It should be noted that, in fig. 4, the mask pattern 27b of the peripheral area A2 only shows one example pattern adjacent to the array area A1, and the peripheral area A2 may also increase the density of the peripheral pattern in other areas not shown, such as the pattern staggering at the array area A1, so the actual pattern of the mask pattern 27b depends on the application design.

Next, as shown in fig. 5, the anti-reflection layer 26 and the carbon-containing layer 25 not covered by the patterned mask layer 27 are removed using the patterned mask layer 27 as a mask. In one embodiment, the portions of the anti-reflective layer 26 and the underlying carbon-containing layer 25 exposed by the openings 271 and 272 are removed, for example, by a dry etching process. After etching, the pattern of patterned masking layer 27 is transferred to the underside to form carbon-containing layer 250 and anti-reflective layer 260, as shown in fig. 5. In this exemplary step, dielectric layer 18 may act as an etch stop layer. Thereafter, the patterned masking layer 27 is removed, for example, by an ashing process.

As shown in fig. 5, the stacked carbon-containing layer 250 and the anti-reflection layer 260 constitute a sacrificial pattern layer 25S. And the sacrificial pattern layer 25S includes a first sacrificial pattern 25S-a in the array region A1 and a second sacrificial pattern 25S-b in the peripheral region A2. In one embodiment, the first sacrificial pattern 25S-a extends along the direction D2, for example. Furthermore, the first sacrificial pattern 25S-a and the second sacrificial pattern 25S-b are separated in the direction D1, for example. Further, in this example, the first sacrificial patterns 25S-a and the first array patterns 21a in the array region A1 are staggered on the dielectric layer 18. The second sacrificial pattern 25S-b in the peripheral area A2 is not limited in this aspect, and may cover a part of the first peripheral pattern 21b or be offset from a part of the first peripheral pattern 21b depending on the peripheral pattern to be formed finally.

Next, as shown in fig. 6A and 6B, the dielectric layer 18 and the pattern transfer layer L1, which are not covered by the sacrificial pattern layer 25S and the polysilicon layer 210, are removed using the sacrificial pattern layer 25S and the polysilicon layer 210 as masks. In one embodiment, for example, a dry etching process is used to remove the dielectric layer 18 exposed by the openings of the sacrificial pattern layer 25S and the polysilicon layer 210 and the portions of the carbon-containing layer 17, the polysilicon layer 16 and the nitrogen-containing layer 15 that are located below. After etching, the patterns of the sacrificial pattern layer 25S and the polysilicon layer 210 are transferred to the underlying dielectric layer 18 and the pattern transfer layer L1 to form a remaining dielectric layer (not shown), a remaining carbon-containing layer (not shown), the polysilicon layer 160 and the nitrogen-containing layer 150. In this exemplary step, dielectric layer 14 serves as an etch stop layer.

Thereafter, the sacrificial pattern layer 25S, the polysilicon layer 210, the remaining dielectric layer 18, and the remaining carbon-containing layer 17 may be removed by one or more steps including an ashing process, an etching process, and the like. As shown in fig. 6B, the polysilicon layer 160 and the nitrogen-containing layer 150 constitute the polysilicon pattern layer 29. The polysilicon pattern layer 29 includes a second array pattern 29a in the array region A1 and a second peripheral pattern 29b in the peripheral region A2. Further, the second array pattern 29a includes an opening 291 therein, and the second peripheral pattern 29b includes an opening 292 therein. Openings 291 and 292 are portions of the top surface of dielectric layer 14 that are exposed.

The present invention has thus far defined the final peripheral pattern (i.e., the second peripheral pattern 29 b) in the peripheral area A2 by the two-stage photolithography process, and defines the pattern (the second array pattern 29 a) extending in a specific direction in the array area A1 while defining the final peripheral pattern 29b in the peripheral area A2. Next, referring to fig. 7A, 7B, and 8-13, the present invention defines a pattern extending along another direction in the array region A1 (e.g., the third array pattern 43a' of fig. 13) by a self-aligned double pattern (self-aligned double patterning; SADP) process.

Referring to fig. 7A and 7B, a second material stack ML-2 is formed over the polysilicon pattern layer 29. The second material layer ML-2 includes various materials, for example, a carbon-containing layer 31, a nitride layer 32, a silicon oxide layer 33, and a pattern transfer layer L3, which are sequentially formed over the polysilicon pattern layer 29. The second material layer ML-2 may be formed by any of a variety of methods, including PVD, CVD, ALD, spin coating, other suitable processes, or a combination thereof. The carbon-containing layer 31 completely covers the second array pattern 29a and the second peripheral pattern 29b, and fills the openings 291 and 292. The carbon-containing layer 31 includes, for example, diamond-like carbon, amorphous carbon film, high-selectivity transparent carbon-containing layer. In this example, the carbon-containing layer 31 is a spin-on carbon layer. Nitride layer 32 is, for example, a material that is different from dielectric layer 14. In this example, the nitride layer 32 may comprise, for example, nitrogen-rich silicon oxynitride (N-rich SiON). The silicon oxide layer 33 may comprise, for example, a layer of tetraethyl orthosilicate (TETRAETHYL ORTHOSILICATE, TEOS).

In one embodiment, the pattern transfer layer L3 includes a polysilicon layer 34, a carbon-containing layer 35, and an anti-reflective layer 36 sequentially formed over the silicon oxide layer 33. The carbon-containing layer 35 includes, for example, a carbide such as diamond-like carbon, an amorphous carbon film, a high-selectivity transparent carbon-containing layer. In this example, carbon-containing layer 35 is a spin-on carbon layer. The material of the anti-reflection layer 36 includes, for example, an organic polymer, carbon, silicon oxynitride, or the like. Here, the pattern transferring layer L3 is described as including the polysilicon layer 34, the carbon-containing layer 35, and the anti-reflection layer 36, but the present invention is not limited thereto, and in other embodiments, the pattern transferring layer L3 may be a combination of other material layers suitable for pattern transferring.

Referring to fig. 7A and 7B, a patterned mask layer 37 (e.g., a patterned photoresist) is formed on the second material layer ML-2, wherein the patterned mask layer 37 exposes a portion of the top surface of the second material layer ML-2. The patterned mask layer 37 includes a mask pattern 37a and a mask pattern 37b, which are respectively formed on the anti-reflective layer 36 of the array region A1 and the peripheral region A2, and expose a portion of the top surface of the anti-reflective layer 36. Further, an opening 371 is included in the mask pattern 37a, and an opening 372 is included in the mask pattern 37 b.

As shown in fig. 7A, 7B, the mask pattern 37A includes line patterns that are spaced apart in the direction D1 and extend along the direction Dc. The direction Dc has an angle of more than 0 degrees and less than 90 degrees with the direction D1, for example, but the present invention is not limited thereto, and in other embodiments, the mask pattern 37a may also include a line pattern that is separated in the direction D2 and extends substantially along the direction D1.

Next, referring to fig. 8, the pattern transfer layer L3 uncovered by the patterned mask layer 37 is removed using the patterned mask layer 37 as an etching mask. In one embodiment, portions of the anti-reflective layer 36 and the underlying carbon-containing layer 35 and polysilicon layer 34 exposed by the openings 371 and 372 are removed, for example, by a dry etching process. After etching, the pattern of the patterned masking layer 37 is transferred to the underlying pattern transfer layer L3 to form the remaining anti-reflective layer 36 (not shown), the carbon-containing layer 350 and the polysilicon layer 340. In this exemplary step, the silicon oxide layer 33 serves as an etch stop layer.

Thereafter, the patterned masking layer 37 and the remaining anti-reflective layer 36 may be removed by including an ashing process, an etching process, and the like. As shown in fig. 8, the carbon-containing layer 350 and the polysilicon layer 340 constitute the core pattern layer 38. The core pattern layer 38 includes a first core pattern 38a in the array region A1 and a second core pattern 38b in the peripheral region A2.

Next, as shown in fig. 9, a spacer material layer 41 is deposited over the silicon oxide layer 33 and the core pattern layer 38. The spacer material layer 41 conformally covers the core pattern layer 38. For example, the spacer material layer 41 covers the top surfaces and sidewalls of the first and second core patterns 38a and 38b, and covers the exposed portions of the silicon oxide layer 330. The spacer material layer 41 may comprise, for example, an oxide, and the forming method may comprise PVD, CVD, ALD, spin coating, other suitable processes, or a combination thereof. The spacer material layer 41 may comprise the same or a different material than the silicon oxide layer 33. In this example, the spacer material layer 41 is a tetraethyl orthosilicate (TEOS) layer.

Thereafter, as shown in fig. 10, a planarization layer 42 is formed over the spacer material layer 41. The planarization layer 42 completely covers the spacer material layers 41 and fills the gaps between the spacer material layers 41. Planarization layer 42 comprises, for example, an organic dielectric layer, such as diamond-like carbon, amorphous carbon film, highly selective transparent carbon-containing layer, or other suitable material, and may be formed by a method including PVD, CVD, ALD, spin coating, other suitable process, or a combination of the foregoing. In this example, the planarizing layer 42 is a spin-on carbon layer.

Next, as shown in fig. 11, a portion of the planarization layer 42 and a portion of the spacer material layer 41 are removed until the top surface of the core pattern layer 38 is exposed. The method of removing a portion of the planarization layer 42 and a portion of the spacer material layer 41 may include, for example, an etch back process or a chemical mechanical polishing process. After this removal step, the remaining planarization layer 42R is filled between the remaining spacer material layers 41, and the top surface of the planarization layer 42R is substantially flush with the top surface of the spacer material layer 41.

Then, referring to fig. 12, using the planarization layer 42R and the core pattern layer 38 as masks, the spacer material layer 41 and the silicon oxide layer 33 not covered by the planarization layer 42R and the core pattern layer 38 are removed to form a patterned stack layer 43. In one embodiment, the spacer material layer 41 and the silicon oxide layer 33 not covered by the planarization layer 42R and the core pattern layer 38 are removed, for example, by a dry etching process, until the nitride layer 32 is exposed. In this exemplary step, nitride layer 32 may act as an etch stop layer.

As shown in fig. 12, patterned stack 43 is formed after etching to include a stack of two three layers of material in an alternating arrangement. The first three-layer material stack comprises, from top to bottom, a carbon-containing layer 350, a polysilicon layer 340, and a silicon oxide layer 330, and the other three-layer material stack comprises, from top to bottom, a planarization layer 420, a spacer material layer 410, and a silicon oxide layer 330. Furthermore, if the formed regions are distinguished, the patterned stack layer 43 includes a plurality of first stacks 43a in the array region A1 and a plurality of second stacks 43b in the peripheral region A2.

Referring to fig. 13, the carbon-containing layer 350 and the planarization layer 420 are then removed to form a patterned material stack 43'. Patterning material stack 43' includes a first material stack 43a ' in array region A1 and a second material stack 43b ' in peripheral region A2. In this example, the first material stack 43a' may serve as a third array pattern. In this example, the third array pattern 43a' includes a line pattern that is spaced apart in the direction D1 and extends along the direction Dc (as shown in fig. 7A). In other embodiments, the mask pattern 37a may also include a line pattern that is spaced apart in the direction D2 and extends substantially along the direction D1.

To this end, the present invention defines a pattern (i.e., a third array pattern 43 a') extending in another direction in the array region A1 by using the SADP process described above. Referring to fig. 13-15, 16A and 16B, the present invention then etches the underlying material layer by an etching process using the third array pattern 43a' as an etching mask to convert the underlying second array pattern 29a into a final array pattern (e.g., the final array pattern 290a shown in fig. 16A and 16B).

Referring again to fig. 13, a patterned masking layer 46 (e.g., a patterned photoresist) is formed over the second material stack 43b' of the peripheral region A2 and the nitride layer 32. The patterned masking layer 46 covers the second material stacks 43b ' and fills the openings between the second material stacks 43b ', exposing the third array patterns 43a ' of the array region A1. In one embodiment, the patterned masking layer 46 may further cover a portion of the array region A1 adjacent to the peripheral region A2 (as shown in fig. 13). However, the present invention is not limited thereto, and whether the patterned masking layer 46 covers a portion of the array area A1 adjacent to the boundary can be determined according to the target pattern to be formed at the boundary between the subsequent corresponding array area A1 and the peripheral area A2.

Next, referring to fig. 14, using the patterned mask layer 46 and the third array pattern 43a' as a mask, the exposed portions of the underlying material layer are removed, for example, the exposed portions of the nitride layer 32 are etched away, until the carbon-containing layer 31 is exposed, and the remaining nitride layer 32 forms a nitride layer 320. Patterning mask layer 46 and patterning material stack 43' may then be removed by one or more steps including an ashing process, an etching process, and the like. In this example, after removal of patterned masking layer 46, patterned material stack 43' is removed, leaving nitride layer 320. As shown in fig. 14, the nitride layer 320 includes a first nitride pattern 32a in the array region A1 and a second nitride pattern 32b in the peripheral region A2.

Next, as shown in fig. 15, the carbon-containing layer 31 and the polysilicon pattern layer 29, which are not covered by the nitride layer 320, are removed by using the nitride layer 320 as a mask, thereby forming a carbon-containing layer 310 and a polysilicon pattern layer 290. In one embodiment, for example, a dry etching process is used to remove portions of the carbon-containing layer 31 not covered by the first nitride pattern 32a and the corresponding underlying second array pattern 29a, thereby forming the nitride layer 320, the carbon-containing layer 310, and the final array pattern 290a. In this exemplary step, dielectric layer 14 may act as an etch stop layer.

Referring to fig. 16A and 16B, the nitride layer 320 and the carbon-containing layer 310 may be removed by one or more steps including an ashing process, an etching process, and the like, thereby exposing the polysilicon pattern layer 290. In one embodiment, a portion of dielectric layer 14 may also be removed during this removal step. As shown in fig. 16A and 16B, the polysilicon pattern layer 290 includes a final array pattern 290a and a second peripheral pattern (final peripheral pattern) 29B. Specifically, the present invention defines a high-density target array pattern after undergoing the two-stage photolithography etching steps illustrated in fig. 1A, 1B, 2-3 and 4-5, 6A, and 6B, and the SADP step illustrated in fig. 7A, 7B, and 8-15. Since the SADP process is only needed once, the invention only needs to use one high-order immersion lithography (immersion lithography) technique, thus greatly reducing the manufacturing cost.

Next, referring to fig. 17, an etching process may be used to transfer the pattern of the polysilicon pattern layer 290 into the target material layer 12. For example, in this example, the underlying material layers, such as dielectric layer 14, carbide layer 13, target material layer 12, and cap layer 11 are etched using polysilicon pattern layer 290 as a mask. After etching, the final array pattern 290a and the second peripheral pattern 29b of the polysilicon pattern layer 290 are transferred to the target material layer 12, thereby forming the target array pattern 120a and the target peripheral pattern 120b in the target material layer 12, respectively. In a DRAM device application, the target array pattern 120a may correspond to the pattern of the capacitive contact pad capacitor contact pad.

According to the method for fabricating a semiconductor structure according to an embodiment of the present invention, a final peripheral pattern of the peripheral area A2 and a line pattern of the array area A1 along a first direction are defined by two-stage photolithography and etching processes illustrated in fig. 1A, 1B, 2-3 and 4, 6A and 6B. Next, after defining the line pattern of the array area A1 along a second direction by the SADP process illustrated in fig. 7A, 7B, and 8 to 15, the line pattern of the array area A1 along the first direction is etched by using the line pattern of the second direction as an etching mask, so as to obtain a final array pattern of the array area A1. And finally, simultaneously transferring the final array pattern and the final peripheral pattern to the target material layer to form the target array pattern and the target peripheral pattern of the invention on the target material layer.

In summary, since the pattern of the peripheral area A2 is defined and the pattern of the array area A1 along the first direction is defined, the method for manufacturing the semiconductor structure according to the present invention can simplify the process steps and reduce the cost compared with the conventional process of separately manufacturing the array pattern and the peripheral pattern. In addition, since the present invention can produce high-density array patterns by using only one SADP process, the present invention can greatly reduce the production cost compared with the conventional method in which multiple (e.g. more than four) complex and expensive SADP processes are used to produce array patterns with the same density.

Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but rather may be modified or altered somewhat without departing from the spirit and scope of the present invention.

Claims

1. A method of fabricating a semiconductor structure, comprising:

forming a first material layer over a substrate, the substrate comprising an array region and a peripheral region, wherein the first material layer covers the array region and the peripheral region, and the first material layer comprises a first pattern transfer layer and a second pattern transfer layer;

forming a first patterned masking layer on the first material layer of the array region and the peripheral region, wherein the first patterned masking layer exposes a portion of the top surface of the first material layer;

Removing a part of the first material lamination layer by taking the first patterning mask layer as a mask so as to transfer the pattern of the first patterning mask layer to the second pattern transfer layer, and forming a first array pattern and a first peripheral pattern in the array region and the peripheral region respectively;

Providing a second patterned mask layer above the first array pattern and the first peripheral pattern, corresponding to the array region and the peripheral region, wherein the pattern of the second patterned mask layer is staggered with the pattern of the first patterned mask layer;

Using the second patterned mask layer as a mask to transfer the pattern of the second patterned mask layer downwards to form a first sacrificial pattern and a second sacrificial pattern in the array region and the peripheral region, and

And performing pattern transfer on the first array pattern and the first sacrificial pattern to form a second array pattern in the array region, and performing pattern transfer on the first peripheral pattern and the second sacrificial pattern to form a second peripheral pattern in the peripheral region.

2. The method of claim 1, wherein a first dielectric layer is disposed between the substrate and the first pattern transfer layer, and the second array pattern and the second peripheral pattern are formed on the first dielectric layer.

3. The method of claim 2, wherein a second dielectric layer is disposed between the second pattern transfer layer and the first pattern transfer layer, wherein the first array pattern, the first periphery pattern, the first sacrificial pattern, and the second sacrificial pattern are formed on the second dielectric layer.

4. The method of manufacturing a semiconductor structure of claim 1, further comprising, after forming the first array pattern and the first peripheral pattern:

Depositing a carbon-containing layer on the first array pattern and the first peripheral pattern to completely cover the first array pattern and the first peripheral pattern, and

Forming an anti-reflection layer on the carbon-containing layer, wherein the second patterned mask layer is formed on the anti-reflection layer,

When the second patterned mask layer is used as a mask, the pattern of the second patterned mask layer is transferred to the anti-reflection layer and the carbon-containing layer, so that the first sacrificial pattern and the second sacrificial pattern are formed.

5. The method of manufacturing a semiconductor structure of claim 1, further comprising:

Forming a second material layer on the second array pattern and the second peripheral pattern;

Forming a third patterned mask layer on the second material layer of the array region and the peripheral region, and

Performing a self-aligned double patterning process according to the pattern of the third patterned mask layer to form a patterned material stack layer, wherein the patterned material stack layer comprises a third array pattern formed in the array region.

6. The method of manufacturing a semiconductor structure of claim 5, wherein forming the second material stack further comprises:

Depositing a carbon-containing layer on the second array pattern and the second peripheral pattern;

Depositing a nitride layer on the carbon-containing layer;

depositing a silicon monoxide layer on the nitride layer, and

Forming a third pattern transfer layer on the silicon oxide layer,

Wherein the third patterned mask layer is formed on the third pattern transfer layer.

7. The method of manufacturing a semiconductor structure of claim 6, wherein the self-aligned double patterning process comprises:

Transferring the pattern of the third patterned mask layer to the third pattern transfer layer to form a core pattern layer, wherein the core pattern layer comprises a first core pattern and a second core pattern formed in the array region and the peripheral region;

depositing a spacer material layer over the silicon oxide layer and the core pattern layer, wherein the spacer material layer conformally covers the core pattern layer;

forming a planarization layer to completely cover the spacer material layer;

Removing a portion of the planarization layer and a portion of the spacer material layer until a top surface of the core pattern layer is exposed, leaving the planarization layer filled between the remaining spacer material layers;

removing the remained part of the spacer material layer to expose the silicon oxide layer;

removing the spacer material layer and the silicon oxide layer uncovered by the remaining portion of the planarization layer and the core pattern layer with the remaining portion of the planarization layer and the core pattern layer as a mask until the nitride layer is exposed, and

The carbon-containing layer and the remaining planarization layer are removed to form the patterned material stack layer.

8. The method of claim 5, wherein the pattern extension direction of the third patterned masking layer is at an angle of less than 90 degrees to the first direction, or the pattern of the third patterned masking layer extends along the first direction.

9. The method of manufacturing a semiconductor structure of claim 5, further comprising:

Forming a fourth patterned mask layer to cover the peripheral region and expose the third array pattern of the array region, and

And removing the exposed part of the lower material layer and the corresponding part of the second array pattern by taking the fourth patterned mask layer and the third array pattern as masks so as to convert the second array pattern into a final array pattern.

10. The method of claim 9, wherein a target material layer is disposed between the substrate and the first material layer to cover the array region and the peripheral region.

11. The method of manufacturing a semiconductor structure of claim 10, further comprising:

And simultaneously transferring the final array pattern of the array region and the second peripheral pattern of the peripheral region to the target material layer to form a target array pattern and a target peripheral pattern in the array region and the peripheral region respectively.

12. The method of claim 11, wherein the target array pattern is a capacitive contact pad in the array region of a dynamic random access memory device.

13. The method of manufacturing a semiconductor structure of claim 11, wherein between the substrate and the first material stack further comprises:

A carbon-containing layer is formed on the target material layer and covers the array region and the peripheral region,

Wherein the third array pattern is located above the carbon-containing layer, and the second array pattern and the second peripheral pattern are located in the carbon-containing layer.

14. The method of manufacturing a semiconductor structure of claim 13, further comprising:

a first dielectric layer is formed on the target material layer, wherein the first dielectric layer is positioned on the carbon-containing layer,

Wherein the final array pattern of the array region and the second peripheral pattern of the peripheral region are formed on the first dielectric layer after the step of converting the second array pattern into the target array pattern.