CN115498037A - Semiconductor structures and methods of forming them - Google Patents

Abstract

A semiconductor structure and its forming method, the forming method comprising: providing a semiconductor substrate, including a resistance region, a resistance structure material layer is formed on the semiconductor substrate of the resistance region; in the resistance region, forming one or A plurality of parallel grooves, the grooves run through a partial thickness of the resistance structure material layer; after the grooves are formed, the resistance structure material layer is patterned, part of the resistance structure material layer outside the grooves is removed, and part of the resistance structure containing the grooves is retained The structural material layer is used as a resistance structure; a dielectric layer is formed on the semiconductor substrate at the side of the resistance structure, and the dielectric layer is also filled in the groove, and the dielectric layer exposes the top of the resistance structure; along the extension direction of the resistance structure, the resistance structure and Part of the resistance structure at the junction of the dielectric layer forms an opening surrounded by the dielectric layer and the remaining resistance structure; electrodes are formed in the opening. A groove is formed on the top of the resistance structure, which reduces the probability of sunken defects on the top surface of the resistance structure.

Description

Semiconductor structures and methods of forming them

technical field

Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background technique

Integrated circuits usually include active and passive devices. Active devices include MOS transistors, while passive devices include resistors. Resistors are indispensable components in integrated circuit design, and in integrated circuit design, the resistors may be polysilicon resistors or metal resistors.

Among them, in a device with a metal gate structure, a polysilicon resistance structure is usually used. In addition, the size of the polysilicon resistive structures is generally relatively large at present.

Contents of the invention

The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

In order to solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a semiconductor substrate including a resistance region; a resistance structure located on the semiconductor substrate of the resistance region, wherein a top of the resistance structure is formed with one or A plurality of grooves arranged in parallel, the grooves penetrating through the resistance structure in partial thickness; electrodes, located in the resistance region, along the extension direction of the resistance structure, the electrodes are located on both sides of the resistance structure, And connected to the side wall of the resistance structure; a dielectric layer, located on the semiconductor substrate at the side of the resistance structure and the electrode, the dielectric layer is also filled in the trench, and the dielectric layer exposes the resistance top of the structure and electrodes.

Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, including: providing a semiconductor substrate, including a resistance region, a resistance structure material layer is formed on the semiconductor substrate of the resistance region; , forming one or more parallel trenches in the resistive structure material layer, the trenches penetrating part of the thickness of the resistive structural material layer; after forming the trenches, patterning the resistive structural material layer , removing part of the resistive structure material layer outside the trench, retaining part of the resistive structure material layer containing the trench as a resistive structure; forming a dielectric layer on the semiconductor substrate at the side of the resistive structure, the dielectric layer is also filled in the groove, and the dielectric layer exposes the top of the resistance structure; along the extending direction of the resistance structure, part of the resistance structure at the junction of the resistance structure and the dielectric layer is removed , forming an opening surrounded by the dielectric layer and the remaining resistance structure; forming an electrode in the opening.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following advantages:

In the semiconductor structure provided by the embodiment of the present invention, one or more grooves arranged in parallel are formed on the top of the resistance structure; during the process of forming the resistance structure and the dielectric layer, usually including Layer planarization process, and during planarization, if the size of the resistance structure is large, more serious dishing defects are likely to appear on the top surface of the resistance structure, and, in this embodiment, the electrodes are located along the The two sides of the resistance structure in the extension direction of the resistance structure, and the electrodes are only used to electrically connect the resistance structure, the size of the electrodes is relatively small, therefore, the remaining size of the resistance structure Larger, more prone to recessed defects, therefore, by making the top of the resistive structure with grooves, the contact area between the polishing pad and the top surface of the resistive structure is reduced during the planarization process, thereby reducing the resistance of the resistive structure. The probability of sunken defects on the top surface improves the flatness of the top surface of the resistance structure, which is beneficial to ensure the integrity of the resistance structure, thereby reducing the probability of resistance value deviation of the resistance structure, thereby improving the performance of the semiconductor structure.

In the method for forming a semiconductor structure provided by an embodiment of the present invention, one or more parallel grooves are formed in the material layer of the resistance structure; The structure and the dielectric layer are planarized, and when the planarization is performed, if the size of the resistive structure is large, serious dishing defects are likely to appear on the top surface of the resistive structure, and, in this embodiment, the electrode Formed on both sides of the resistance structure along the extension direction of the resistance structure, and the electrodes are only used to electrically connect the resistance structure, the size of the electrodes is small, so the remaining The size of the resistive structure is relatively large, and it is more prone to sink defects. Therefore, by forming a groove on the top of the resistive structure, the contact area between the polishing pad and the top surface of the resistive structure is reduced during the planarization process, thereby reducing the size of the resistive structure. The probability of sunken defects appearing on the top surface of the resistance structure improves the flatness of the top surface of the resistance structure, which is conducive to ensuring the integrity of the resistance structure, thereby reducing the probability that the resistance value of the resistance structure will shift, thereby improving the semiconductor structure. performance.

Description of drawings

1 to 4 are structural schematic diagrams corresponding to each step in a method for forming a semiconductor structure;

5 to 7 are structural schematic diagrams of an embodiment of the semiconductor structure of the present invention;

8 to 20 are structural schematic diagrams corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

detailed description

The performance of current semiconductor structures still needs to be improved. The reason why the performance of the semiconductor structure still needs to be improved is analyzed in combination with a method for forming the semiconductor structure.

Referring to FIG. 1 to FIG. 4 , schematic structural diagrams corresponding to each step in a method for forming a semiconductor structure are shown.

Referring to FIG. 1 , a semiconductor substrate 10 is provided, the semiconductor substrate 10 includes a resistance region 10R and a device region 10H, a resistance structure material layer 20 is formed on the semiconductor substrate 10, and the resistance structure material layer 20 includes a metal barrier layer 22 and a top resistive layer 23 on said barrier metal layer 22 .

Referring to FIG. 2, the resistive structure material layer 20 is patterned, and the remaining resistive structural material layer 20 on the semiconductor substrate 10 in the resistive region 10R is reserved as a resistive structure 30, and in the device region 10H, the remaining resistive structure material layer 20 located in the resistive region 10H is reserved. The remaining top resistive layer 23 on the barrier metal layer 22 is used as the dummy gate layer 31 .

After patterning the resistive structure material layer 20 , in the resistive region 10R, the remaining metal barrier layer 22 is used as a bottom resistive layer in the resistive structure 30 .

Wherein, the extending direction of the resistive structure 30 is the first direction (not shown), and the arrangement direction of the resistive structure 30 and the dummy gate layer 31 is the second direction (shown as the X direction in FIG. 2 ). The first direction is perpendicular to the second direction, and both the first direction and the second direction are parallel to the surface of the semiconductor substrate 10 .

Referring to FIG. 3 , which is a cross-sectional view along the second direction, a dielectric layer 40 is formed on the semiconductor substrate 10 at the side of the resistance structure 30 .

The process of forming the dielectric layer 40 generally includes the process of planarizing the dielectric layer 40, and since the resistance structure 30 has a large line width, after the planarization process, the resistance structure The top of the 30 is prone to more serious sunken defects.

Referring to FIG. 4 , FIG. 4 is a cross-sectional view along a first direction. Along the first direction, a part of the resistance structure 30 at the junction of the resistance structure 30 and the dielectric layer 40 is removed, and the dielectric layer 40 is formed. and the opening surrounded by the remaining resistive structure 30; an electrode 35 is formed in the opening.

In the process of forming the electrode 35, the process of planarizing the electrode 35 is usually included, and the process of planarizing this time will easily make the top surface of the resistance structure 30 further concave, and even lead to the resistance of the resistance structure 30. The top resistance layer 23 in the structure 30 is excessively recessed, thereby exposing the metal barrier layer 22 at the bottom, and since the metal barrier layer 22 has a great influence on the resistance value of the resistance structure 30, it is easy to cause the resistance structure 30 The resistance value shifts.

Moreover, the electrodes 35 are formed on both sides of the resistive structure 30 along the first direction (that is, the extending direction of the resistive structure 30), and the remaining resistive structures 30 are larger in size and are more likely to have recessed defects. .

In order to solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a semiconductor substrate, including a resistance region, and a resistance structure material layer is formed on the semiconductor substrate of the resistance region; In the resistance area, one or more parallel grooves are formed in the resistance structure material layer, and the grooves penetrate part of the thickness of the resistance structure material layer; after forming the grooves, patterning the resistance A structural material layer, removing part of the resistive structure material layer outside the trench, and retaining a part of the resistive structure material layer including the trench as a resistive structure; forming a dielectric layer on the semiconductor substrate at the side of the resistive structure, The dielectric layer is also filled in the groove, and the dielectric layer exposes the top of the resistance structure; along the extension direction of the resistance structure, the portion at the junction of the resistance structure and the dielectric layer is removed The resistance structure is formed to form an opening surrounded by the dielectric layer and the remaining resistance structure; and an electrode is formed in the opening.

In the method for forming a semiconductor structure provided by an embodiment of the present invention, one or more parallel grooves are formed in the material layer of the resistance structure; The structure and the dielectric layer are planarized, and when the planarization is performed, if the size of the resistive structure is large, serious dishing defects are likely to appear on the top surface of the resistive structure, and, in this embodiment, the electrode Formed on both sides of the resistance structure along the extension direction of the resistance structure, and the electrodes are only used to electrically connect the resistance structure, the size of the electrodes is small, so the remaining The size of the resistive structure is relatively large, and it is more prone to sink defects. Therefore, by forming a groove on the top of the resistive structure, the contact area between the polishing pad and the top surface of the resistive structure is reduced during the planarization process, thereby reducing the size of the resistive structure. The probability of sunken defects appearing on the top surface of the resistance structure improves the flatness of the top surface of the resistance structure, which is conducive to ensuring the integrity of the resistance structure, thereby reducing the probability that the resistance value of the resistance structure will shift, thereby improving the semiconductor structure. performance.

In order to make the above objects, features and advantages of the embodiments of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

Referring to FIGS. 5 to 7, a schematic structural view of an embodiment of the semiconductor structure of the present invention is shown, wherein FIG. 5 is a top view of the resistance structure, FIG. 6 is a cross-sectional view of FIG. 5 based on the direction AA, and FIG. 7 is a view based on BB of FIG. Orientation section view.

Wherein, for the convenience of illustration, the device area is not shown in FIG. 7 , and only the resistance area is shown in FIG. 7 .

The semiconductor structure includes: a semiconductor substrate 101 including a resistance region 101R; a resistance structure 301 located on the semiconductor substrate 101 of the resistance region 101R, wherein one or more parallel arrays are formed on the top of the resistance structure 301 groove (not shown), the groove penetrates the resistance structure 301 of partial thickness; the electrode 351 is located in the resistance region 101R, along the extension direction of the resistance structure 301 (as shown in Figure 7 and Figure 9 In the X direction), the electrode 351 is located on both sides of the resistance structure 301 and is connected to the side wall of the resistance structure 301; the dielectric layer 401 is located on the semiconductor substrate at the side of the resistance structure 301 and the electrode 351 101 , the dielectric layer 401 is also filled in the groove, and the dielectric layer 401 exposes the top of the resistive structure 301 and the electrode 351 .

In the semiconductor structure provided by the embodiment of the present invention, one or more trenches arranged in parallel are formed on the top of the resistance structure 301; during the process of forming the resistance structure 301 and the dielectric layer 401, usually including The process of planarizing the structure 301 and the dielectric layer 401, and when planarizing, if the size of the resistive structure 301 is large, serious dishing defects are likely to appear on the top surface of the resistive structure 301, and, in this embodiment , the electrodes 351 are located on both sides of the resistance structure 301 along the extension direction of the resistance structure 301, and the electrodes 351 are only used to electrically connect the resistance structure 301, then the electrodes 351 The size of the resistance structure 301 is smaller, therefore, the remaining resistance structure 301 is larger in size and is more likely to have recessed defects. Therefore, by forming a groove on the top of the resistance structure 301, the friction between the polishing pad and the grinding pad during planarization is reduced. The contact area of the top surface of the resistance structure 301, thereby reducing the probability of sunken defects on the top surface of the resistance structure 301, improving the flatness of the top surface of the resistance structure 301, which is conducive to ensuring the integrity of the resistance structure, thereby reducing the resistance The probability that the resistance of the structure will shift, thereby improving the performance of the semiconductor structure.

The semiconductor substrate 101 provides a process operation basis for the formation process of the semiconductor structure.

In this embodiment, the material of the semiconductor substrate 101 is silicon. In other embodiments, the material of the semiconductor substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide, and gallium indium. One or more, the semiconductor substrate can also be a silicon-on-insulator semiconductor substrate or a germanium-on-insulator semiconductor substrate or other types of semiconductor substrates. The material of the semiconductor substrate 101 may be a material suitable for process requirements or easy to integrate.

In this embodiment, the semiconductor substrate 101 includes a resistance region 101R and a device region 101H. The resistance region 101R is used to form a resistance structure, and the device region 101H is used to form a MOS transistor.

In this embodiment, the device region 101H is a low voltage (LV) device region for forming low voltage devices. As an example, the operating voltage of the low voltage device is less than 2V.

It should be noted that the semiconductor substrate 101 may further include a high-voltage device region (not shown) for forming a high-voltage device. The operating voltage of the high-voltage device is greater than that of the low-voltage device. As an example, high voltage devices operate at voltages greater than 10V.

In this embodiment, the semiconductor structure further includes an isolation structure 111 located in the semiconductor substrate 101 of the resistance region 101R.

The isolation structure 111 is used to isolate the resistance structure 301 on the isolation structure 111 from the semiconductor substrate 101, so as to prevent a short circuit between the resistance structure 301 and a well (well) region in the semiconductor substrate 101, The isolation structure 111 is also used to realize isolation between different devices, for example, in a CMOS manufacturing process, an isolation structure is usually formed between an NMOS transistor and a PMOS transistor. Specifically, the isolation structure 111 is a shallow trench isolation structure (Shallow Trench Isolation, STI).

The material of the isolation structure 111 is insulating material. In this embodiment, the material of the isolation structure 111 includes silicon oxide or silicon oxynitride.

It should be noted that, in this embodiment, the metal gate structure of the second device region 101H is formed by first forming a high-k gate dielectric layer and then forming a metal gate (high k first metal gate last), and the resistance structure 301 and The dummy gate layer of the second device region 101H is formed together. Wherein, the dummy gate layer is used to occupy a spatial position for the gate electrode layer of the second device region 101H.

Therefore, in this embodiment, the semiconductor structure further includes: a gate dielectric layer 211 located on the semiconductor substrate 101 of the device region 101H and the resistance region 101R; a metal barrier layer 221 located on the gate dielectric layer 211; The gate electrode layer 361 is located on the metal barrier layer 221 of the device region 101H.

In this embodiment, in the device region 101H, the gate dielectric layer 211 , the metal barrier layer 221 and the gate electrode layer 361 form a metal gate structure.

The gate dielectric layer 211 is used to isolate the electrode 351 from the semiconductor substrate 101 , and the gate electrode layer 361 from the semiconductor substrate 101 .

The material of the gate dielectric layer 211 includes one or more of HfO ₂ , ZrO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al ₂ O ₃ , SiO ₂ and La ₂ O ₃ . In this embodiment, the gate dielectric layer 211 includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. Wherein, the high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide. Specifically, the high-k dielectric material includes HfO ₂ , ZrO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al ₂ O ₃ .

It should be noted that the gate dielectric layer 211 may further include a gate oxide layer located between the high-k gate dielectric layer and the semiconductor substrate 101 . As an example, the material of the gate oxide layer is silicon oxide.

The metal barrier layer 221 is used to isolate the gate dielectric layer 211 and the electrode 351, and the gate dielectric layer 211 and the gate electrode layer 361 to protect the gate dielectric layer 211, and the metal barrier layer 221 is also used to block the electrode 351 and the gate electrode Easily diffusible ions (for example, Al ions) in the layer 361 diffuse into the gate dielectric layer 211 .

Specifically, the material of the barrier metal layer 221 includes one or both of titanium nitride (TiN) and silicon-doped titanium nitride (TiSiN). In this embodiment, the material of the barrier metal layer 221 is titanium nitride.

The gate electrode layer 361 includes a work function layer (not shown), and an electrode layer (not shown) on the work function layer. Wherein, the work function layer is used to adjust the threshold voltage of the formed transistor, and the electrode layer is used to extract the electricity of the gate electrode layer 361 .

The resistor structure 301 is used as a passive device in an integrated circuit.

In this embodiment, the resistance structure 301 includes the metal barrier layer 221 located in the resistance region 101R, and the top resistance layer 231 located on the metal barrier layer 221, and the metal barrier layer 221 is used as The bottom resistive layer in the resistive structure.

In this embodiment, the resistor structure 301 is located on the isolation structure 111 of the resistor 101R region, so that the resistor structure 301 is insulated from the semiconductor substrate 101 .

In this embodiment, the material of the top resistance layer 231 includes polysilicon.

It should be noted that, since the resistance value of the top resistance layer 231 is much greater than the resistance value of the metal barrier layer 221, the current of the resistance structure 301 mainly flows through the metal barrier layer 221 when the resistance structure 301 is in operation, correspondingly, it is different from the resistance value of the top resistance layer 231. In comparison, the metal barrier layer 221 has a greater influence on the resistance of the resistance structure 301 .

In this embodiment, the groove penetrates through part of the thickness of the resistance structure 301, and retains part of the thickness of the resistance structure 301, so as to keep the resistance of the resistance structure 301 meeting the performance requirements, and protect the resistance located in the resistance structure 301. other layers below.

Specifically, the trench penetrates through a partial thickness of the top resistive layer 231 .

In this embodiment, the extension direction of the plurality of trenches arranged in parallel is the same as the extension direction of the resistance structure 301, which can reduce the number of trenches in the planarization process when a small number of trenches are formed. Under the influence of the contact area between the polishing pad and the top surface of the resistance structure 301 , the process cost is saved, the process complexity is reduced, and the process efficiency is improved.

In this embodiment, the arrangement direction of the plurality of trenches arranged in parallel is perpendicular to the extending direction of the resistive structure 301, then in the direction perpendicular to the extending direction of the resistive structure 301, according to the A sufficient number of grooves are arranged to greatly reduce the contact area with the top surface of the resistance structure 301 during the planarization process, thereby reducing the probability of sunken defects appearing on the top surface of the resistance structure 301 .

It should be noted that the depth h of the groove can neither be too large nor too small. If the depth h of the trench is too large, too many resistive structures 301 will be removed, which will easily affect the resistance of the resistive structure 301, and if the depth h of the trench is too large, the process of forming the trench In the middle, it is easy to cause damage to other film layers below the trench; if the depth h of the trench is too small, the height of the resistance structure 301 protruding around the trench is too small, and the dielectric During the planarization process of the layer 401, it is easy to remove the resistance structure 301 protruding around the trench, so that during the planarization process, it is easy to contact the resistance structure 301 at the bottom of the trench, and it is difficult to Reducing the contact area with the top surface of the resistance structure 301 during the planarization process makes it difficult to reduce the probability of recess defects occurring on the top surface of the resistance structure 301 . Therefore, in this embodiment, the depth h of the trench is 1/4 to 1/3 of the thickness of the resistance structure 301 .

It should be noted that the width w1 of the groove can neither be too large nor too small. If the width w1 of the trench is too large, too many resistive structures 301 will be removed, which will easily affect the resistance of the resistive structure 301. Moreover, during the planarization process, the dielectric layer 401 in the trench will easily appear. The problem of serious top surface depression; if the width w1 of the trench is too small, the line width of the resistance structure 301 protruding around the trench is still large, so it is difficult to reduce the The contact area with the top surface of the resistance structure 301 is small in the planarization process, so it is difficult to reduce the probability of sunken defects on the top surface of the resistance structure 301, and it is also easy to increase the process of the photolithography process adopted when forming the trench. difficulty. Therefore, in this embodiment, the width w1 of the trench is 0.15 μm to 2 μm.

At the same time, it should be noted that the distance w2 between adjacent grooves cannot be too large or too small. If the distance w2 between adjacent trenches is too large, that is to say, the line width of the resistive structures 301 around the trenches is still relatively large, so it is difficult to reduce the The contact area with the top surface of the resistive structure 301 is small in the planarization process, so it is difficult to reduce the probability of sunken defects on the top surface of the resistive structure 301, and the width w1 of the trench is correspondingly too small; If the distance w2 between the trenches is too small, the width w1 of the formed trenches will be too large, and too many resistive structures 301 will be removed, which will easily affect the resistance of the resistive structures 301. Moreover, in During the planarization process, the dielectric layer 401 located in the trench is prone to the problem of severe top surface dishing. Therefore, in this embodiment, the distance w2 between adjacent trenches is 0.15 μm to 2 μm.

In this embodiment, the semiconductor structure further includes: a protection layer 341 located on the sidewall of the trench.

During the process of planarizing the resistive structure 301 and the dielectric layer 401, the protective layer 341 protects the resistive structure 301 on the sidewall of the trench, reducing the probability of over-grinding the resistive structure 301, This further effectively reduces the probability of sunken defects on the top surface of the resistance structure 301, improves the flatness of the top surface of the resistance structure 301, and further improves the performance of the semiconductor structure.

In this embodiment, the protective layer 341 conformally covers the sidewall and bottom of the trench, and the protective layer 341 protects the resistive structure 301 on the sidewall of the trench while protecting the protective layer. The resistance structure 301 at the bottom of 341 plays a protective role.

In this embodiment, the material of the protective layer 341 includes silicon nitride or silicon oxynitride.

The silicon nitride has a relatively high hardness, and can better protect the resistance structure 301 on the sidewall and bottom of the trench during the planarization process.

Along the extension direction of the resistance structure 301, the electrodes 351 are located on both sides of the resistance structure 301 and connected to the side walls of the resistance structure 301, that is, the electrodes 351 and the sides of the resistance structure 301 The ends are connected.

Specifically, the electrodes 351 are located on the metal barrier layer 221 on both sides of the top resistance layer 231 .

The electrodes 351 are used to electrically connect with the conductive plug, so as to realize the electrical connection between the resistance structure 301 and other circuits.

The electrodes 351 are located at ends of the resistive structure 301 . Since the longer the length of the resistive structure 301, the greater the resistance of the resistive structure 301, therefore, by making the electrode 351 at the end of the resistive structure 301, the resistance of the resistive structure 301 can be maximized. The length enables the resistance structure 301 to obtain greater resistance.

In this embodiment, the material of the electrode 351 includes a metal material. The metal material has good electrical conductivity, which is beneficial to improve the electrical connection performance between the resistance structure 301 and the external interconnection structure, thereby improving the electrical performance of the semiconductor structure.

In this embodiment, the electrode 351 has the same material and stacked structure as the gate electrode layer 361 of the MOS transistor, so that the electrode 351 and the gate electrode layer 361 of the MOS transistor can be formed in the same process. For example, the device gate structure used in the low-voltage device region is a metal gate structure, and the use of a metal gate structure is conducive to improving the electrical performance of the MOS transistor and reducing leakage current.

Correspondingly, during the formation of the semiconductor structure, in the step of forming the gate electrode layer 361 , the electrode 351 is formed simultaneously.

In this embodiment, the material of the electrode 351 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN and TiAlC.

In this embodiment, the electrode 351 and the gate electrode layer 361 are made of the same material, so the electrode 351 and the gate electrode layer 361 can be formed in the same step, which improves process efficiency and saves process cost.

The electrode 351 includes a work function layer (not shown), and an electrode layer (not shown) located on the work function layer, and the electrode layer is used to extract electricity from the electrode 351 .

The dielectric layer 401 is used to isolate adjacent devices.

In this embodiment, the dielectric layer 401 is filled in the trench and covers the sidewall of the protective layer 341, which is used to improve the flatness of the top of the resistive structure 301, and provide a better structure for subsequent fabrication. craft platform.

In this embodiment, the material of the dielectric layer 401 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

It should be noted that, generally, the process of forming the dielectric layer 401 includes the process of planarizing the resistance structure 301 and the dielectric layer 401. In this embodiment, a groove is formed on the top of the resistance structure 301, which reduces the During the planarization process, the contact area between the polishing pad and the top surface of the resistance structure 301 is reduced, thereby reducing the probability of sunken defects occurring on the top surface of the resistance structure 301 .

In this embodiment, the semiconductor structure further includes: a covering layer 501 covering the dielectric layer 401 , the resistance structure 301 and the electrode 351 .

In this embodiment, the covering layer 401 also covers the gate electrode layer 361 accordingly.

The covering layer 501 is used to provide a process platform for forming conductive plugs.

The material of the cover layer 501 is an insulating material. In this embodiment, the material of the cover layer 501 includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. one or more.

In this embodiment, the semiconductor structure further includes: a conductive plug 511 penetrating through the covering layer 501 on top of the electrode 351 and electrically connecting the electrode 351 .

The conductive plug 511 is used to realize the electrical connection of the electrode 351 .

In this embodiment, the material of the conductive plug 511 includes tungsten, ruthenium or cobalt.

It should be noted that, generally, the process of forming the electrode 351 includes the process of planarizing the resistance structure 301 and the electrode 351. During the polishing process, the contact area between the polishing pad and the top surface of the resistance structure 301 is reduced, thereby reducing the probability of sunken defects occurring on the top surface of the resistance structure 301 .

It should also be noted that this embodiment improves the flatness of the top surface of the resistance structure 301, thereby improving the formation quality of the electrode 351, thereby improving the reliability of the electrical connection between the conductive plug 511 and the electrode 351, The performance of the semiconductor structure is further improved.

8 to 20 are structural schematic diagrams corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

Referring to FIG. 8 , a semiconductor substrate 100 is provided, including a resistance region 100R, and a resistance structure material layer 200 is formed on the semiconductor substrate 100 of the resistance region 100R.

The semiconductor substrate 100 provides a process operation basis for subsequent processes.

In this embodiment, the material of the semiconductor substrate 100 is silicon. In other embodiments, the material of the semiconductor substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide, and gallium indium. One or more, the semiconductor substrate can also be a silicon-on-insulator semiconductor substrate or a germanium-on-insulator semiconductor substrate or other types of semiconductor substrates. The material of the semiconductor substrate 100 may be a material suitable for process requirements or easy to integrate.

In this embodiment, the semiconductor substrate 100 includes a resistance region 100R, and the resistance region 100R is used to form a resistance structure.

In this embodiment, the semiconductor substrate 100 further includes a device region 100H, and the device region 100H is used to form a MOS transistor. Among them, MOS transistors are used as active devices in integrated circuits.

In this embodiment, the device region 100H is a low-voltage device region for forming low-voltage devices. As an example, the operating voltage of the low voltage device is less than 2V.

It should be noted that the semiconductor substrate 100 may further include a high-voltage device region (not shown) for forming a high-voltage device. The operating voltage of the high-voltage device is greater than that of the low-voltage device. As an example, high voltage devices operate at voltages greater than 10V.

It should also be noted that in this embodiment, the metal gate structure of the second device region 100H is formed by forming a high-k gate dielectric layer first and then forming a metal gate (high kfirst metal gate last) process, and is formed on the resistor The resistance structure of the region 100R is formed together with the dummy gate layer formed in the second device region 100H.

Therefore, in this embodiment, a gate dielectric layer 210 is further formed between the resistance structure material layer 200 and the semiconductor substrate 100, and the resistance structure material layer 200 includes a metal barrier layer 220 and is located on the metal barrier layer 220. The top resistive layer 250.

The gate dielectric layer 210 is used to isolate the subsequently formed electrode from the semiconductor substrate 100 , and the subsequently formed gate electrode layer from the semiconductor substrate 100 .

The material of the gate dielectric layer 210 includes one or more of HfO ₂ , ZrO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al ₂ O ₃ , SiO ₂ and La ₂ O ₃ . In this embodiment, the gate dielectric layer 210 includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. Wherein, the high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide. Specifically, the high-k dielectric material includes HfO ₂ , ZrO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al ₂ O ₃ .

It should be noted that the gate dielectric layer 210 may further include a gate oxide layer located between the high-k gate dielectric layer and the semiconductor substrate 101 . As an example, the material of the gate oxide layer is silicon oxide.

The metal barrier layer 220 is used to isolate the gate dielectric layer 210 and the subsequently formed electrode, and the gate dielectric layer 210 and the subsequently formed gate electrode layer to protect the gate dielectric layer 210, and the metal barrier layer 220 is also used to block the electrode and easily diffusible ions (for example: Al ions) in the gate electrode layer diffuse into the gate dielectric layer 210 .

Specifically, the material of the barrier metal layer 220 includes one or both of titanium nitride (TiN) and silicon-doped titanium nitride (TiSiN). In this embodiment, the material of the barrier metal layer 220 is titanium nitride.

The resistance structure material layer 200 is used to subsequently form a resistance structure, and the metal barrier layer 220 of the resistance region 100R is used to subsequently serve as a bottom resistance layer.

In this embodiment, the material of the top resistance layer 250 includes polysilicon.

In this embodiment, the resistive structure material layer 200 is also formed on the semiconductor substrate 100 in the device region 100H, which is used to prepare for the subsequent formation of a dummy gate layer in the device region 100H. Wherein, the dummy gate layer is used to occupy a space position for the formation of the metal gate structure.

In this embodiment, an isolation structure 110 is further formed in the semiconductor substrate 100 of the resistance region 101R.

Subsequently, a resistance structure is formed on the isolation structure 110, and the isolation structure 110 is used to isolate the resistance structure and the semiconductor substrate 100, so as to prevent a short circuit between the resistance structure and the well region in the semiconductor substrate 100. The isolation structure 110 is also used to achieve isolation between different devices, for example, in a CMOS manufacturing process, an isolation structure is usually formed between an NMOS transistor and a PMOS transistor. Specifically, the isolation structure 110 is a shallow trench isolation structure (Shallow Trench Isolation, STI).

The material of the isolation structure 110 is insulating material. In this embodiment, the material of the isolation structure 110 includes silicon oxide or silicon oxynitride.

Referring to FIG. 9 and FIG. 10 in conjunction, FIG. 10 is a top view of the resistance structure material layer 200 of the resistance region 100R, and FIG. 9 is a cross-sectional view of FIG. 10 based on the AA direction. One or more parallel grooves 230 are formed in the middle, and the grooves 230 penetrate part of the thickness of the resistive structure material layer 200 .

After subsequent patterning of the resistive structure material layer 200 to form a resistive structure located in the resistive region 100R, the trench 230 is located in the resistive structure.

In the process of forming the resistance structure and the dielectric layer, the process of planarizing the resistance structure and the dielectric layer is usually included, and when the planarization is performed, if the size of the resistance structure is large, the top surface of the resistance structure is likely to appear larger. serious dishing defect, and in this embodiment, the electrodes are formed on both sides of the resistance structure along the extension direction of the resistance structure, and the electrodes are only used to If the electrode is electrically connected, the size of the electrode is smaller, therefore, the size of the remaining resistive structure is larger, and it is more likely to have a recess defect. Therefore, by forming the trench 230 on the top of the resistive structure, reducing the During the planarization process, the contact area between the polishing pad and the top surface of the resistance structure reduces the probability of sunken defects on the top surface of the resistance structure, improves the flatness of the top surface of the resistance structure, and is conducive to ensuring the integrity of the resistance structure properties, thereby reducing the probability that the resistance value of the resistance structure will shift, thereby improving the performance of the semiconductor structure.

In this embodiment, the trench 230 penetrates part of the thickness of the resistive structure material layer 200, retaining part of the thickness of the resistive structure material layer 200, thereby maintaining the normal performance and resistance of the subsequent resistive structure, and protecting the The metal barrier layer 220 under the resistance structure material layer 200 is used to reduce or avoid the impact on the resistance value of the resistance structure.

Specifically, the groove 230 penetrates a partial thickness of the top resistive layer 250 .

In this embodiment, one or more parallel trenches 230 are formed by a dry etching process.

The dry etching process has the characteristics of anisotropic etching, so by selecting the dry etching process, it is beneficial to reduce the damage to the remaining resistive structure material layer 200 on the side of the trench 230, and at the same time, The dry etching is more directional, which is beneficial to improving the topography quality and dimensional accuracy of the trench 230 .

In this embodiment, the extension direction of the plurality of trenches 230 arranged in parallel is the same as the extension direction of the resistance structure material layer 200, which can reduce the effect on planarization under the condition of forming a small number of trenches. Under the effect of the contact area with the top surface of the resistance structure 301 during the process, the process cost is saved, the process complexity is reduced, and the process efficiency is improved.

In this embodiment, the arrangement direction of the plurality of trenches 230 arranged in parallel is perpendicular to the extension direction of the resistance structure material layer 200 , then in the direction perpendicular to the extension direction of the resistance structure material layer 200 , According to the width of the resistance structure 300, a sufficient number of grooves 230 are arranged to greatly reduce the contact area with the top surface of the resistance structure during the planarization process, thereby reducing the probability of sunken defects appearing on the top surface of the resistance structure .

It should be noted that the depth h of the groove 230 cannot be too large or too small. If the depth h of the trench 230 is too large, too much material layer 200 of the resistive structure will be removed, which will easily cause damage to the metal barrier layer 220 below the trench 230, thereby affecting the resistance value of the resistive structure 300; if If the depth h of the trench 230 is too small, the height of the resistance structure protruding around the trench 230 is too small, and the trench will be easily distorted during the planarization process of the dielectric layer 401. The protruding resistance structure around the groove 230 is removed, so that during the planarization process, it is easy to contact the resistance structure at the bottom of the trench 230, and it is difficult to reduce the contact area with the top surface of the resistance structure during the planarization process , so it is difficult to reduce the probability of sunken defects appearing on the top surface of the resistance structure. Therefore, in this embodiment, the depth h of the trench 230 is 1/4 to 1/3 of the thickness of the resistance structure material layer 200 .

It should be noted that the width w1 of the groove 230 cannot be too large or too small. If the width w1 of the trench 230 is too large, a dielectric layer will be formed in the trench 230 later, and during the planarization process, the dielectric layer in the trench is likely to have a serious problem of top surface depression; if the If the width w1 of the trench 230 is too small, the line width of the resistance structure protruding around the trench 230 will still be relatively large, so that it is difficult to reduce the contact with the resistance in the planarization process during the planarization process. The contact area of the top surface of the structure makes it difficult to reduce the probability of sunken defects on the top surface of the resistance structure, and it is also easy to increase the process difficulty of the photolithography process and dry etching process used when forming the trench 230 . Therefore, in this embodiment, the width w1 of the trench 230 is 0.15 μm to 2 μm.

At the same time, it should be noted that the distance w2 between adjacent grooves 230 cannot be too large or too small. If the distance w2 between the adjacent trenches 230 is too large, that is to say, the line width of the resistance structure protruding around the trenches 230 is still relatively large, so that it is difficult to Reducing the contact area with the top surface of the resistance structure during the planarization process makes it difficult to reduce the probability of sunken defects on the top surface of the resistance structure, and correspondingly causes the width w1 of the trench 230 to be too small; if adjacent If the distance w2 between the trenches 230 is too small, the width w1 of the formed trenches 230 will be too large, and a dielectric layer will be formed in the trenches 230 later. The dielectric layer in 230 is prone to the problem of severe top surface dishing, and it is also easy to increase the process difficulty of the photolithography process and dry etching process for forming the trench 230 . Therefore, in this embodiment, the distance w2 between adjacent trenches 230 is 0.15 μm to 2 μm.

Referring to FIG. 11 and FIG. 12 in conjunction, FIG. 11 and FIG. 12 are cross-sectional views based on FIG. 9 , after the trench 230 is formed, the resistive structure material layer 200 is patterned, and part of the resistive structure outside the trench 230 is removed. The material layer 200 retains the part of the resistive structure material layer 200 including the groove 230 as the resistive structure 300 .

Reserving part of the resistance structure material layer 200 including the groove 230 as the resistance structure 300, so that in the subsequent planarization process, the contact area between the polishing pad and the top surface of the resistance structure 300 is reduced, thereby reducing the resistance of the resistance structure 300. The probability of concave defects on the top surface improves the flatness of the top surface of the resistance structure 300, which is conducive to ensuring the integrity of the resistance structure 300, and at the same time protects the integrity of the metal barrier layer 220, thereby reducing the resistance of the resistance structure 300. The probability of offset, which in turn improves the performance of the semiconductor structure.

The resistor structure 300 is used as a passive device in an integrated circuit.

In this embodiment, the remaining metal barrier layer 220 and the top resistance layer 250 in the resistance region 100R are used as the resistance structure 300 , and the metal barrier layer 220 is used as the bottom resistance layer in the resistance structure 300 .

In this embodiment, the resistance structure 300 is located on the isolation structure 110 of the resistance 100R region, so that the resistance structure 300 is insulated from the semiconductor substrate 100 .

In this embodiment, the resistive structure material layer 200 directly forms the resistive structure 300 , therefore, the material of the top resistive layer 250 includes polysilicon.

It should be noted that, since the resistance value of the top resistance layer 250 is much greater than the resistance value of the barrier metal layer 220, the current of the resistance structure 300 mainly flows through the barrier metal layer 220 when the resistance structure 300 is in operation, correspondingly, it is different from the barrier metal layer 250. In comparison, the metal barrier layer 220 has a greater influence on the resistance of the resistance structure 300 .

In this embodiment, after forming the trench 230 and before forming a dielectric layer on the semiconductor substrate 100 at the side of the resistance structure 300, it further includes: forming a protective layer 340 on the sidewall of the trench 230 .

During the process of planarizing the resistive structure 300 and the dielectric layer 400, the protective layer 340 protects the resistive structure 300 on the sidewall of the trench, reducing the probability of over-grinding the resistive structure 300, Further effectively reducing the probability of sunken defects on the top surface of the resistance structure 300, improving the flatness of the top surface of the resistance structure 300, and further improving the performance of the semiconductor structure.

In this embodiment, the protection layer 340 is formed before the dielectric layer is formed on the semiconductor substrate 100 at the side of the resistance structure 300, so that the protection layer 340 conformally covers the sidewall and bottom of the trench 230, Therefore, while protecting the resistive structure 300 on the sidewall of the trench 230 , the protective layer 340 also protects the resistive structure 300 at the bottom of the protective layer 340 .

In this embodiment, the material of the protective layer 340 includes silicon nitride or silicon oxynitride.

The silicon nitride has relatively high hardness, and can better protect the resistance structure 300 on the sidewall and bottom of the trench during the planarization process.

Specifically, in this embodiment, before patterning the resistance structure material layer 200, the protection layer 340 is formed, so that the protection layer 340 is also used as an etching mask for patterning the resistance structure material layer 200 Membrane simplifies the process steps.

Referring to FIG. 11 , the step of forming the protective layer 340 includes: forming a protective material layer 240 on the resistive structure material layer 200, the protective material layer 240 conformally covering the bottom and sidewalls of the trench 230, and The top of the resistive structure material layer 200 .

The protective material layer 240 is used to form the protective layer 340 .

In this embodiment, the protective material layer 240 is formed by an atomic layer deposition process.

The thickness uniformity of the protective material layer 240 formed by the atomic layer deposition process is good, and it has good step coverage (step coverage), so that the protective material layer 240 can conformally cover the trench 230 well. The bottom and sidewalls of and the top of the resistive structure material layer 200 .

Referring to FIG. 12 , part of the protective material layer 240 outside the trench 230 is removed to form a protective layer that conformally covers the bottom and sidewalls of the trench 230 and extends to cover part of the top of the resistive material layer 200 340.

The passivation layer 340 is also used as an etching mask for patterning the resistive structure material layer 200 .

In this embodiment, a dry etching process is used to remove part of the protective material layer 240 outside the trench 230 .

The dry etching process has the characteristics of anisotropic etching, so by selecting the dry etching process, it is beneficial to reduce the damage to the resistance structure material layer 200, and at the same time, the dry etching is more The etching directionality is beneficial to improve the topography quality and dimensional accuracy of the sidewalls of the protection layer 340 and the resistance structure 300 .

Continuing to refer to FIG. 12 , the step of patterning the resistance structure material layer 200 includes: using the protection layer 340 as a mask, removing the resistance structure material layer 200 exposed by the protection layer 340 .

Using the protective layer 340 as a mask to form the resistive structure 300 is beneficial to forming the resistive structure 300 with high dimensional accuracy.

In this embodiment, in the step of patterning the resistive structure material layer 200 , part of the top resistive layer 250 on the semiconductor substrate 100 in the device region 100H is reserved as the dummy gate layer 310 .

The dummy gate layer 310 occupies a spatial position for forming a gate electrode layer in a subsequent process.

In this embodiment, the dummy gate layer 310 and the resistance structure 300 are formed in the same step, thereby simplifying the process steps of forming the semiconductor structure. Therefore, the material of the dummy gate layer 310 is the same as that of the top resistor layer 250 .

In this embodiment, after patterning the resistive structure material layer 200 and before subsequently forming a dielectric layer, further include: removing the gate dielectric layer 210 exposed by the resistive structure 300 and the dummy gate layer 310 .

Referring to FIG. 13, a dielectric layer 400 is formed on the semiconductor substrate 100 at the side of the resistance structure 300, the dielectric layer 400 is also filled in the trench 230, and the dielectric layer 400 exposes the resistance structure 300 the top of.

The dielectric layer 400 is used to isolate adjacent devices.

In this embodiment, the dielectric layer 400 is formed by a chemical vapor deposition process.

In this embodiment, the dielectric layer 400 is filled in the trench 230 and covers the sidewalls of the protection layer 340, which is used to improve the flatness of the top of the resistance structure 300, and provide better support for subsequent manufacturing processes. technology platform.

In this embodiment, the dielectric layer 400 exposes the top of the resistive structure 300 to prepare for subsequent removal of part of the resistive structure 300 to form electrodes.

In this embodiment, the dielectric layer 400 also exposes the top of the dummy gate layer 310 to prepare for subsequent removal of the dummy gate layer 310 .

In this embodiment, the material of the interlayer dielectric layer 400 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.

In this embodiment, the step of forming the dielectric layer 400 includes: forming a dielectric material layer (not shown) on the semiconductor substrate 100 covering the resistance structure 300 .

The dielectric material layer is used to form the dielectric layer 400 .

In this embodiment, the material of the interlayer dielectric material layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.

In this embodiment, the step of forming the dielectric layer 400 further includes: planarizing the protective layer 340 and the dielectric material layer on the top of the resistive structure 300, and removing the protective layer higher than the top of the resistive structure 300 340 and dielectric material layer.

By planarizing the protective layer 340 and the dielectric material layer on the top of the resistance structure 300, the top of the resistance structure 300 is exposed, so as to facilitate the subsequent formation of electrodes in the resistance structure 300, and at the same time, the flatness of the top surface is relatively high. The high resistance structure 300 provides a better process platform for subsequent manufacturing.

It should be noted that, in the process of planarizing the top of the dielectric material layer, when the depth of the groove 230 formed is small, or the dielectric material layer is ground too much, the medium in the groove 230 There is a possibility that the layer 400 is removed, so that the protective layer 340 remains in the trench 230 . In this embodiment, the case where the dielectric layer 400 remains in the trench 230 is described.

14 to 16 in combination, FIG. 14 is a top view of the resistance structure 300, FIG. 15 is a sectional view of FIG. 14 based on the direction AA, and FIG. 16 and FIG. 14 are sectional views based on the direction of BB. The portion of the resistive structure 300 at the junction of the resistive structure 300 and the dielectric layer 400 forms an opening 330 surrounded by the dielectric layer 400 and the rest of the resistive structure 300 .

The opening 330 is used to provide a space for subsequent electrode formation.

In this embodiment, the opening 330 is formed by a dry etching process.

In this embodiment, in the step of removing part of the resistive structure 300 at the junction of the resistive structure 300 and the dielectric layer 400, part of the top resistor at the junction of the resistive structure 300 and the dielectric layer 400 is removed. layer 250 to form an opening 330 surrounded by the dielectric layer 400 , metal barrier layer 220 and the remaining top resistance layer 250 , and remove the dummy gate layer 310 to form a gate opening 320 .

The gate opening 320 is used to provide a space position for the subsequent formation of the gate electrode layer.

In this embodiment, the gate opening 320 is formed by a dry etching process.

Referring to FIG. 17 to FIG. 19 together, FIG. 17 is a top view of the resistance structure 300 , FIG. 16 is a cross-sectional view of FIG. 17 based on the direction AA, and FIG. 19 and FIG. 17 are cross-sectional views based on the direction of BB.

In this embodiment, along the extension direction of the resistance structure 300, the electrode 350 is located between the resistance structure 300 and the dielectric layer 400, that is, the end of the electrode 350 and the resistance structure 300 Specifically, the electrodes 350 are located on the barrier metal layer 220 on both sides of the top resistance layer 250 .

The electrodes 350 are located at ends of the resistive structure 300 . Since the longer the resistance structure 300 is, the greater the resistance value of the resistance structure 300 is, the electrode 350 is located at the end of the resistance structure 300, and the length of the resistance structure 300 can be maximized, This makes the resistance structure 300 obtain greater resistance.

The electrodes 350 are used to electrically connect with the conductive plug, so as to realize the electrical connection between the resistance structure 300 and other circuits.

In this embodiment, the material of the electrode 350 includes metal material. The metal material has good electrical conductivity, which is beneficial to improve the electrical connection performance between the resistance structure 300 and the external interconnection structure, thereby improving the electrical performance of the semiconductor structure.

In this embodiment, the electrode 350 has the same material and stacked structure as the gate electrode layer of the MOS transistor, so that the electrode 350 and the gate electrode layer of the MOS transistor can be formed in the same manufacturing process. For example, the device gate structure used in the low-voltage device region is a metal gate structure, and the use of a metal gate structure is conducive to improving the electrical performance of the MOS transistor and reducing leakage current.

Correspondingly, in this embodiment, in the step of forming the gate electrode layer of the MOS transistor, the electrode 350 is formed at the same time, thereby simplifying the process steps of forming the semiconductor structure.

Continuing to refer to FIG. 18 , the step of forming the electrode 350 in the opening 330 further includes: forming a gate electrode layer 360 in the gate opening 320 .

The gate electrode layer 360 is used to control the opening or closing of the channel of the transistor.

In this embodiment, the gate electrode layer 360 and the resistance structure 300 are formed in the same step, thereby simplifying the process steps of forming the semiconductor structure. Therefore, the material of the gate electrode layer 360 is the same as that of the electrode 350 .

In this embodiment, the metal gate structure is formed by forming a high-k gate dielectric layer first and then forming a metal gate (high k first metalgate last). Therefore, the metal gate layer 360 includes The upper work function layer (not shown) and the electrode layer (not shown) on the work function layer. Wherein, the work function layer is used to adjust the threshold voltage of the MOS transistor, and the electrode layer is used to extract the electricity of the gate electrode layer 361 .

In this embodiment, in the device region 100H, the gate dielectric layer 210 , the metal barrier layer 220 and the gate electrode layer 360 form a metal gate structure.

It should be noted that, generally, the process of forming the electrode 350 and the gate electrode layer 360 includes the process of planarizing the resistance structure 300, the electrode 350 and the gate electrode layer 360. In this embodiment, the top of the resistance structure 300 The grooves are formed to reduce the contact area between the polishing pad and the top surface of the resistance structure 300 during the planarization process, thereby reducing the probability of sunken defects on the top surface of the resistance structure 300 .

Referring to FIG. 20 , which is a cross-sectional view based on FIG. 19 , a conductive plug 510 electrically connected to the electrode 350 is formed on the top of the electrode 350 .

The conductive plug 510 is used to realize the electrical connection of the electrode 350 .

In this embodiment, the material of the conductive plug 510 includes tungsten, ruthenium or cobalt.

In this embodiment, before forming the conductive plug 510 , it further includes: forming a covering layer 500 covering the dielectric layer 340 , the resistance structure 300 and the electrode 350 .

The covering layer 500 is used to provide a process platform for forming the conductive plug 510 .

The material of the covering layer 500 is insulating material. In this embodiment, the material of the covering layer 500 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.

In this embodiment, the covering layer 500 also covers the gate electrode layer 360 accordingly.

In this embodiment, the step of forming a conductive plug 510 electrically connected to the electrode 350 on the top of the electrode 350 includes: forming a cover layer 500 penetrating through the top of the electrode 350 and exposing a conductive hole (not shown) of the electrode 350 mark); forming the conductive plug 510 in the conductive hole.

The conductive plug 510 penetrates through the covering layer 500 on the top of the electrode 350 , so as to be electrically connected to the electrode 350 .

It should also be noted that this embodiment improves the flatness of the top surface of the resistance structure 300, thereby improving the formation quality of the electrode 350, thereby improving the reliability of the electrical connection between the conductive plug 510 and the electrode 350, The performance of the semiconductor structure is further improved.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (20)

1. A semiconductor structure, characterized in that, comprising: a semiconductor substrate, including a resistive region; a resistance structure located on the semiconductor substrate in the resistance region, wherein one or more grooves arranged in parallel are formed on the top of the resistance structure, and the grooves penetrate part of the thickness of the resistance structure; electrodes, located in the resistance region, along the extension direction of the resistance structure, the electrodes are located on both sides of the resistance structure, and connected to the side walls of the resistance structure; The dielectric layer is located on the semiconductor substrate at the side of the resistance structure and the electrode, the dielectric layer is also filled in the trench, and the dielectric layer exposes the top of the resistance structure and the electrode. 2. The semiconductor structure according to claim 1, further comprising: a protective layer located on a sidewall of the trench; The dielectric layer is filled in the groove and covers the sidewall of the protection layer. 3. The semiconductor structure of claim 2, wherein the protective layer conformally covers sidewalls and bottom of the trench. 4. The semiconductor structure according to claim 1, wherein the extension direction of the plurality of parallel trenches is the same as the extension direction of the resistance structure; The arrangement direction of the plurality of trenches arranged in parallel is perpendicular to the extension direction of the resistance structure. 5. The semiconductor structure according to claim 1, wherein the semiconductor structure further comprises an isolation structure located in the semiconductor substrate of the resistance region; The resistance structure is located on the isolation structure of the resistance area. 6. The semiconductor structure according to claim 1, wherein the semiconductor substrate further comprises a device region; The semiconductor structure further includes: a gate dielectric layer located on the semiconductor substrate of the device region and the resistance region; a metal barrier layer located on the gate dielectric layer; a gate electrode layer located on the metal barrier layer of the device region on the barrier layer; The resistive structure includes the metal barrier layer in the resistive region, and a top resistive layer on the metal barrier layer, the metal barrier layer is used as a bottom resistive layer in the resistive structure; The electrodes are located on the metal barrier layer on both sides of the top resistance layer, and the materials of the electrodes and the gate electrode layer are the same. 7. The semiconductor structure according to claim 1, wherein the depth of the trench is 1/4 to 1/3 of the thickness of the resistance structure. 8 . The semiconductor structure according to claim 1 , wherein the width of the trench is 0.15 μm to 2 μm, and the distance between adjacent trenches is 0.15 μm to 2 μm. 9. The semiconductor structure according to claim 2, wherein a material of the protective layer comprises silicon nitride or silicon oxynitride. 10. The semiconductor structure according to claim 6, wherein the material of the metal barrier layer comprises one or both of titanium nitride and silicon-doped titanium nitride; the material of the top resistance layer comprises polysilicon. 11. The semiconductor structure according to claim 1, wherein the material of the electrode comprises one or more of TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN and TiAlC. 12. The semiconductor structure according to claim 5, wherein the material of the isolation structure comprises silicon oxide or silicon oxynitride. 13. The semiconductor structure according to claim 6, wherein the material of the gate dielectric layer comprises HfO ₂ , ZrO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al ₂ O ₃ , SiO ₂ and La ₂ One or more of O ₃ . 14. A method for forming a semiconductor structure, comprising: A semiconductor substrate is provided, including a resistance region, and a resistance structure material layer is formed on the semiconductor substrate of the resistance region; In the resistive region, one or more parallel trenches are formed in the layer of resistive structural material, the trenches penetrating part of the thickness of the layer of resistive structural material; After forming the trench, patterning the resistance structure material layer, removing part of the resistance structure material layer outside the trench, and retaining a part of the resistance structure material layer including the trench as a resistance structure; forming a dielectric layer on the semiconductor substrate at the side of the resistance structure, the dielectric layer is also filled in the trench, and the dielectric layer exposes the top of the resistance structure; Along the extension direction of the resistance structure, removing part of the resistance structure at the junction of the resistance structure and the dielectric layer, forming an opening surrounded by the dielectric layer and the remaining resistance structure; Electrodes are formed in the openings. 15. The method for forming a semiconductor structure according to claim 14, further comprising: after forming the trench and before forming a dielectric layer on the semiconductor substrate at the side of the resistance structure: The sidewalls of the trench form a protective layer. 16. The method for forming a semiconductor structure according to claim 15, wherein the protective layer is formed before patterning the resistive structure material layer; The step of forming the protection layer includes: forming a protection material layer on the resistance structure material layer, the protection material layer conformally covering the bottom and sidewalls of the trench and the top of the resistance structure material layer; removing a portion of the protective material layer outside the trench to form a protective layer conformally covering the bottom and sidewalls of the trench and extending to cover a portion of the top of the resistive material layer; The step of patterning the resistance structure material layer includes: using the protection layer as a mask, removing the resistance structure material layer exposed by the protection layer. 17. The method for forming a semiconductor structure according to claim 16, wherein the step of forming the dielectric layer comprises: forming a dielectric material layer covering the resistance structure on the semiconductor substrate; The protective layer and the dielectric material layer on the top of the resistance structure are planarized, and the protective layer and the dielectric material layer higher than the top of the resistance structure are removed. 18. The method for forming a semiconductor structure according to claim 14, wherein in the step of providing a semiconductor substrate, the semiconductor substrate further includes a device region, and the resistance structure material layer is also formed on the On the semiconductor substrate in the device region, the resistance structure material layer includes a metal barrier layer and a top resistance layer on the metal barrier layer, and a gate dielectric layer is also formed between the resistance structure material layer and the semiconductor substrate ; In the step of patterning the resistive structure material layer, the remaining metal barrier layer and top resistive layer in the resistive region serve as a resistive structure, the metal barrier layer is used as a bottom resistive layer in the resistive structure, and Reserving part of the top resistance layer on the semiconductor substrate in the device region as a dummy gate layer; After patterning the resistive structure material layer and before forming the dielectric layer, further include: removing the resistive structure and the gate dielectric layer exposed by the dummy gate layer; In the step of forming the dielectric layer, the dielectric layer also exposes the top of the dummy gate layer; In the step of removing part of the resistance structure at the junction of the resistance structure and the dielectric layer, removing part of the top resistance layer at the junction of the resistance structure and the dielectric layer, forming a The opening surrounded by the barrier layer and the remaining top resistance layer, and the dummy gate layer is also removed to form a gate opening in the device region; In the step of forming an electrode in the opening, it further includes: forming a gate electrode layer in the gate opening. 19. The method for forming a semiconductor structure according to claim 18, wherein the material of the metal barrier layer comprises one or both of titanium nitride and silicon-doped titanium nitride, and the top resistance layer The material includes polysilicon. 20. The method for forming a semiconductor structure according to claim 16, wherein the protective material layer is formed by an atomic layer deposition process.

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