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CN115513017A - Spindt cathode electron source and preparation method and application thereof - Google Patents

Spindt cathode electron source and preparation method and application thereof Download PDF

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CN115513017A
CN115513017A CN202210996108.5A CN202210996108A CN115513017A CN 115513017 A CN115513017 A CN 115513017A CN 202210996108 A CN202210996108 A CN 202210996108A CN 115513017 A CN115513017 A CN 115513017A
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emission
insulating layer
silicon substrate
cone
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CN115513017B (en
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李兴辉
韩攀阳
姜琪
杜婷
蔡军
冯进军
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Beijing Vacuum Electonics Research Institute
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J1/00Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
    • H01J1/02Main electrodes
    • H01J1/30Cold cathodes, e.g. field-emissive cathode
    • H01J1/304Field-emissive cathodes
    • H01J1/3042Field-emissive cathodes microengineered, e.g. Spindt-type
    • H01J1/3044Point emitters
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J9/00Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
    • H01J9/02Manufacture of electrodes or electrode systems
    • H01J9/022Manufacture of electrodes or electrode systems of cold cathodes
    • H01J9/025Manufacture of electrodes or electrode systems of cold cathodes of field emission cathodes

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Abstract

The invention discloses a Spindt cathode electron source and a preparation method and application thereof, wherein the cathode electron source comprises the following structures: the silicon substrate, the insulating layer and the grid are sequentially arranged from bottom to top, and an insulating layer cavity is formed among the silicon substrate, the insulating layer and the grid through hole; an emission sharp cone arranged on the silicon substrate and positioned in the cavity of the insulating layer, wherein the emission sharp cone corresponds to the gate through hole; the coating layer is arranged on the silicon substrate, is positioned in the insulating layer cavity and completely covers the exposed silicon substrate in the insulating layer cavity; the attached oxide layer is positioned between the coating layer and the emission pointed cone and coats the lower side surface of the emission pointed cone; the upper side surface of the emission tip cone is exposed outside the incidental oxide layer. The cathode electron source structure avoids the unexpected electron emission of the three-combination point, thereby effectively preventing the common discharge along the network and the space arc failure caused by the discharge.

Description

一种Spindt阴极电子源及其制备方法和应用A kind of Spindt cathode electron source and its preparation method and application

技术领域technical field

本发明涉及真空电子技术领域。更具体地,涉及一种Spindt阴极电子源及其制备方法和应用。The invention relates to the technical field of vacuum electronics. More specifically, it relates to a Spindt cathode electron source and its preparation method and application.

背景技术Background technique

基于强电场诱发电子逸出原理的场发射电子源,具有无需外能,室温工作,瞬时启动以及大电流密度优势,在真空电子器件中替代传统热阴极电子源,有望保留器件高频率、大功率、耐高温、耐辐射的优点,同时还能实现更小的体积和更轻的重量,具有很好的综合优势。场发射电子源潜在应用,包括各种高端分析仪器、显示器件、X射线发射器、微波功率器件、高能粒子加速器件、空间推进器件等诸多场景。研制高性能场发射电子源,对真空电子器件的发展和进步,具有十分重要的意义。The field emission electron source based on the principle of electron escape induced by a strong electric field has the advantages of no external energy, room temperature operation, instant start and high current density. It can replace the traditional hot cathode electron source in vacuum electronic devices, and it is expected to retain the high frequency and high power of the device. , high temperature resistance, and radiation resistance, and at the same time achieve smaller volume and lighter weight, which has very good comprehensive advantages. Potential applications of field emission electron sources include various high-end analytical instruments, display devices, X-ray emitters, microwave power devices, high-energy particle acceleration devices, space propulsion devices and many other scenarios. The development of high-performance field emission electron sources is of great significance to the development and progress of vacuum electronic devices.

Spindt阴极是开发最早,发展和应用最为成熟的场发射电子源,后期很多场发射电子源研究都曾以此为借鉴。Spindt阴极是一种大量集成微发射单元的阵列式阴极,图1示出了一个其典型单元的结构,图1中各部件标号分别表示为:101-硅基底,201-绝缘层,301-栅极和401-发射尖锥。正常工作时,在101-硅基底和301-栅极施加正向偏压,即可在401-发射尖锥表面产生强电场,导致电子发射。随着栅极偏压的升高,单元发射电流能够呈指数形式迅速增长。微发射单元大量集成,使得Spindt阴极能够同时维持很大电流密度和总电流。The Spindt cathode is the field emission electron source that was developed the earliest and is the most mature in development and application. It was used as a reference for many researches on field emission electron sources in the later period. The Spindt cathode is an array cathode with a large number of integrated micro-emission units. Figure 1 shows the structure of a typical unit. The components in Figure 1 are marked as: 101-silicon substrate, 201-insulating layer, 301-gate pole and 401-emitter tip. When working normally, applying a forward bias voltage on the 101-silicon substrate and the 301-gate can generate a strong electric field on the surface of the 401-emission cone, resulting in electron emission. As the gate bias voltage increases, the cell emission current can rapidly increase exponentially. A large number of micro-emitting units are integrated, so that the Spindt cathode can maintain a large current density and total current at the same time.

然而Spindt阴极电子源,在大电流应用时常会出现电弧失效,影响器件可靠性。相关研究表明,出现电弧失效的最主要诱因,是当301-栅极和101-硅基底之间施加很高电压时,在101-硅基底、201-绝缘层和真空三结合点部位会产生非期望的电子发射,非期望的发射电子在电场作用下,沿201-绝缘层边壁向301-栅极爬升,期间不断碰撞产生电子倍增,继而形成沿络放电,并最终在301-栅极和401-发射尖锥诱发电弧导致损毁。对于这种电弧失效,前期已有两类相关的应对专利技术。However, the Spindt cathode electron source often has arc failure in high current applications, which affects the reliability of the device. Relevant studies have shown that the main cause of arc failure is that when a high voltage is applied between the 301-gate and the 101-silicon substrate, an abnormality will occur at the junction of the 101-silicon substrate, the 201-insulating layer and the vacuum triple junction. The expected electron emission, the undesired electron emission climbs along the side wall of the 201-insulation layer to the 301-gate under the action of the electric field, during which the electrons are multiplied by constant collisions, and then discharge along the network is formed, and finally in the 301-gate and 401-Emitting a cone-induced arc causes damage. For this kind of arc failure, there have been two types of related patented technologies in the early stage.

一类技术是力图阻断电子沿络放电的路径。日本专利JP-A8-321255结构,如图2所示,引入第二种绝缘层材料,这两种绝缘材料构建3层交替的绝缘层201,202和203,实际上也可以构建5层、7层或者更多层结构,利用两种材料不同腐蚀选择比导致的横向腐蚀差异,能够实现总体褶皱结构的绝缘侧壁。这种褶皱结构绝缘侧壁,使得从101-硅基底、201-绝缘层和真空三结合点部位产生电子,沿壁向301-栅极运动及产生沿络放电难度大大增加。美国专利US6075315A结构,如图3所示,同样引入另一种绝缘层材料,但只用其在201-绝缘层和301-栅极之间构建了204-屏蔽层。专门结构设计,使得301-栅极适度回缩,用204-屏蔽层隔绝101-硅基底、201-绝缘层和真空三结合点部位至301-栅极的空间直视,从而使得非期望发射电子难以产生沿络放电到达301-栅极。然而该类技术,并未阻止非期望电子发射,虽然增加了电子沿络放电难度,但未解决根本问题。并且美国专利结构,由于301-栅极回缩,大大降低了相同工作电压下401-发射尖锥表面电场强度,削弱了Spindt阴极电子发射能力。One type of technology is to try to block the path of electron discharge along the network. The structure of Japanese patent JP-A8-321255, as shown in Figure 2, introduces a second insulating layer material, and these two insulating materials construct three alternating layers of insulating layers 201, 202 and 203. In fact, five layers and seven layers can also be constructed. A layer or more layer structure, using the difference in lateral corrosion caused by the different corrosion selection ratios of the two materials, can realize the insulating sidewall of the overall wrinkled structure. This wrinkled structure insulates the sidewall, making it more difficult for electrons to be generated from the three junctions of 101-silicon substrate, 201-insulating layer and vacuum, to move along the wall to the 301-gate and to generate discharge along the network. The US6075315A structure, as shown in FIG. 3 , also introduces another insulating layer material, but only uses it to construct the 204 -shielding layer between the 201 -insulating layer and the 301 -gate. The special structure design makes the 301-gate moderately retracted, and the 204-shielding layer is used to isolate the 101-silicon substrate, 201-insulating layer and vacuum triple junction from the space of the 301-gate, so that the undesired emission of electrons It is difficult to generate discharge along the grid to reach the 301-gate. However, this type of technology does not prevent undesired electron emission. Although it increases the difficulty of electron discharge along the network, it does not solve the fundamental problem. And the U.S. patented structure, due to the retraction of the 301-grid, greatly reduces the surface electric field intensity of the 401-emission cone under the same operating voltage, and weakens the electron emission capability of the Spindt cathode.

另一类技术是力图阻断产生空间电弧的通道。美国专利US6369496B1结构,如图4所示,利用另一种绝缘材料构建205-绝缘环柱,用以包围401-发射尖锥,将其与201-绝缘层和301-栅极隔离,避免空间电弧产生。美国专利US005442193A结构,如图5所示,利用另一种绝缘材料构建206-遮盖层,将201-绝缘层和301-栅极完全敷形遮盖,以期阻断其和401-发射尖锥产生空间电弧。然而这类技术,也未从根本上阻止非期望电子发射,并且前者隔离不彻底,后者由于绝缘遮盖原因会要求更高工作电压,也会导致绝缘击穿以及空间电弧。Another type of technology is trying to block the channel that generates space arc. U.S. Patent US6369496B1 structure, as shown in Figure 4, uses another insulating material to construct 205-insulating ring columns to surround 401-emission cones and isolate them from 201-insulating layers and 301-grids to avoid space arcs produce. The US005442193A structure, as shown in Figure 5, uses another insulating material to construct the 206-covering layer, and completely conformally covers the 201-insulating layer and 301-gate, in order to block it and the 401-emission cone to create a space arc. However, this type of technology does not fundamentally prevent undesired electron emission, and the isolation of the former is not complete, while the latter requires a higher operating voltage due to insulation covering, which will also lead to insulation breakdown and space arcing.

发明内容Contents of the invention

基于以上事实,本发明的目的在于提供一种Spindt阴极电子源及其制备方法和应用,解决了现有技术中不能完全克服非期望电子发射的问题,进而可以有效防止传统结构电子源常见的沿络放电和空间电弧失效。Based on the above facts, the object of the present invention is to provide a Spindt cathode electron source and its preparation method and application, which solves the problem that the undesired electron emission cannot be completely overcome in the prior art, and then can effectively prevent the common edge of the electron source with the traditional structure. Network discharge and space arc failure.

一方面,本发明提供一种Spindt阴极电子源,其结构中包含:On the one hand, the invention provides a kind of Spindt cathode electron source, comprises in its structure:

从下到上依次设置的硅基底、绝缘层和栅极,所述硅基底、绝缘层和栅极透孔间形成绝缘层空腔;A silicon substrate, an insulating layer, and a gate are sequentially arranged from bottom to top, and an insulating layer cavity is formed between the silicon substrate, the insulating layer, and the through hole of the gate;

设置于硅基底上的位于绝缘层空腔中的发射尖锥,所述发射尖锥与栅极透孔相对应;以及,an emission cone disposed on the silicon substrate and located in the cavity of the insulating layer, the emission cone corresponding to the gate through-hole; and,

设置于硅基底上的包被层,所述包被层位于绝缘层空腔中且完全覆盖所述绝缘层空腔中暴露的硅基底;a cladding layer disposed on the silicon substrate, the cladding layer being located in the cavity of the insulating layer and completely covering the silicon substrate exposed in the cavity of the insulating layer;

位于包被层与发射尖锥之间的、且包覆在发射尖锥下侧面的附带氧化层;所述发射尖锥的上侧面暴露于所述附带氧化层外。An incidental oxide layer located between the coating layer and the emitting cone and covering the lower side of the emitting cone; the upper side of the emitting cone is exposed to the incidental oxide layer.

进一步地,所述包被层为由所述硅基底表面经热氧化得到的二氧化硅。Further, the coating layer is silicon dioxide obtained by thermal oxidation of the surface of the silicon substrate.

进一步地,所述包被层厚度为30-100nm。Further, the thickness of the coating layer is 30-100 nm.

进一步地,所述发射尖锥的上侧面暴露于所述附带氧化层外的高度为0.3-0.4μm。Further, the height of the upper side of the emitting cone exposed to the incidental oxide layer is 0.3-0.4 μm.

进一步地,所述发射尖锥的材料选自高熔点、低功函数的纯金属,优选为W或Mo。Further, the material of the emitting cone is selected from pure metals with high melting point and low work function, preferably W or Mo.

进一步地,所述发射尖锥底部直径为0.6-1μm,高度为0.8-2.2μm,顶部曲率半径为20-50nm。Further, the emission cone has a bottom diameter of 0.6-1 μm, a height of 0.8-2.2 μm, and a top curvature radius of 20-50 nm.

进一步地,所述发射尖锥的上侧面暴露于所述附带氧化层外的高度为发射尖锥整体高度的15-50%。Further, the height of the upper side of the emission cone exposed to the incidental oxide layer is 15-50% of the overall height of the emission cone.

进一步地,所述附带氧化层的材质为由发射尖锥下侧面的表面经热氧化得到。Further, the material of the oxidized layer is obtained by thermal oxidation of the surface of the lower side of the emitting cone.

进一步地,所述硅基底选自半导体工艺标准N型掺杂硅片。Further, the silicon substrate is selected from semiconductor process standard N-type doped silicon wafers.

进一步地,所述硅基底电阻率为0.005-5Ω·cm。Further, the resistivity of the silicon substrate is 0.005-5Ω·cm.

进一步地,所述绝缘层材料选自二氧化硅或氮化硅。Further, the insulating layer material is selected from silicon dioxide or silicon nitride.

进一步地,所述绝缘层材料厚度为0.8-2μm。Further, the thickness of the insulating layer material is 0.8-2 μm.

进一步地,所述栅极的材料选自高熔点纯金属,优选为W或Mo;优选地,所述栅极的厚度为100-200nm,所述栅极透孔直径为0.8-1.2μm。Further, the material of the gate is selected from pure metals with high melting point, preferably W or Mo; preferably, the thickness of the gate is 100-200 nm, and the diameter of the through-hole of the gate is 0.8-1.2 μm.

又一方面,本发明提供如上所述的Spindt阴极电子源的制备方法,包括如下步骤:In another aspect, the present invention provides the preparation method of Spindt cathode electron source as described above, comprising the steps:

在硅基底上形成绝缘层;forming an insulating layer on the silicon substrate;

真空镀膜,在所述绝缘层上形成栅极层;vacuum coating, forming a gate layer on the insulating layer;

通过光刻,并依次刻蚀栅极层和绝缘层直至硅基底,形成含有栅极透孔的栅极和绝缘层空腔;Through photolithography, and sequentially etch the gate layer and insulating layer until the silicon substrate, forming a gate and insulating layer cavity containing gate through holes;

旋转基片,采用表面小倾角的方法仅在栅极表面真空镀膜一层牺牲层,缩小栅极透孔;The substrate is rotated, and only a sacrificial layer is vacuum-coated on the surface of the grid by adopting the method of small surface inclination to reduce the through-hole of the grid;

表面垂直真空镀膜一层发射尖锥材料,在空腔内形成发射尖锥;The surface is vertically vacuum-coated with a layer of emitting cone material to form an emitting cone in the cavity;

去除牺牲层及沉积在牺牲层上的发射尖锥材料;removing the sacrificial layer and the emission tip material deposited on the sacrificial layer;

旋转基片,采用表面大倾角的方法仅在栅极表面和发射尖锥上侧面真空镀膜一层保护层;The substrate is rotated, and a protective layer is only vacuum-coated on the surface of the gate and the upper side of the emission cone by adopting the method of large surface inclination;

热氧化硅基底,空腔内硅基底表面形成所述包被层,发射尖锥未保护部分附带受氧化,形成附带氧化层;The silicon substrate is thermally oxidized, the coating layer is formed on the surface of the silicon substrate in the cavity, and the unprotected part of the emission tip is incidentally oxidized to form an incidental oxide layer;

腐蚀去除所述保护层,露出栅极以及发射尖锥上侧面,得到所述Spindt阴极电子源。The protective layer is removed by etching to expose the grid and the upper side of the emission cone to obtain the Spindt cathode electron source.

又一方面,本发明提供如上所述的Spindt阴极电子源在真空电子用器件中的应用。In yet another aspect, the present invention provides the application of the Spindt cathode electron source as described above in devices for vacuum electronics.

本发明的有益效果如下:The beneficial effects of the present invention are as follows:

本发明提供的Spindt阴极电子源,其包被层完全覆盖硅基底,消除了硅基底、绝缘层和真空形成的三结合点结构,杜绝了该结构点产生非期望电子发射。相对于前期阻断电子沿络放电传输路径或者电弧放电路径技术,本发明消除了产生放电和电弧的电子发射源头,可以有效防止传统结构电子源在高电压、大电流工作状态容易出现沿络放电和空间电弧失效,有效提高电子源工作可靠性。In the Spindt cathode electron source provided by the invention, the cladding layer completely covers the silicon substrate, eliminating the triple junction structure formed by the silicon substrate, insulating layer and vacuum, and preventing the undesired electron emission from the structure point. Compared with the previous technology of blocking the transmission path of electron discharge along the network or the path of arc discharge, the present invention eliminates the source of electron emission that generates discharge and arc, and can effectively prevent the traditional electronic source from being prone to discharge along the network under high voltage and high current working conditions. and space arc failure, effectively improving the reliability of the electron source.

本发明提供的Spindt阴极电子源的制作方法,只是在完成传统结构以后,实施发射尖锥保护层制作和基底包被层制作两步工艺,整个制作方法工艺流程简单易实施,兼容性强。The manufacturing method of the Spindt cathode electron source provided by the present invention is only to implement the two-step process of manufacturing the emitting cone protective layer and manufacturing the base coating layer after completing the traditional structure.

附图说明Description of drawings

下面结合附图对本发明的具体实施方式作进一步详细的说明。The specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings.

图1示出示出现有技术中典型结构的Spindt阴极电子源的结构示意图。Fig. 1 shows a schematic structural diagram of a Spindt cathode electron source showing a typical structure in the prior art.

图2示出现有技术中多绝缘层褶皱侧壁结构Spindt阴极电子源的结构示意图。FIG. 2 shows a schematic structural diagram of a Spindt cathode electron source with a multi-insulation layer wrinkled sidewall structure in the prior art.

图3示出现有技术中带栅极屏蔽层Spindt阴极电子源的结构示意图。FIG. 3 shows a schematic structural diagram of a Spindt cathode electron source with a grid shielding layer in the prior art.

图4示出现有技术中带发射尖锥绝缘环柱隔离Spindt阴极电子源的结构示意图。Fig. 4 shows a schematic structural diagram of a Spindt cathode electron source with an emission tip insulating ring column isolation in the prior art.

图5示出现有技术中带遮盖层Spindt阴极电子源的结构示意图。Fig. 5 shows a schematic structural diagram of a Spindt cathode electron source with a covering layer in the prior art.

图6示出本发明一种基底包被的Spindt阴极电子源的结构示意图。Fig. 6 shows a schematic structural view of a substrate-coated Spindt cathode electron source of the present invention.

图7a-图7h示出本发明一种基底包被的Spindt阴极电子源的制作流程图。Fig. 7a-Fig. 7h show a fabrication flow chart of a substrate-coated Spindt cathode electron source of the present invention.

图8a和图8b示出本发明一种带基底包被层的常规高宽比Spindt阴极电子源照片及局部放大照片。Fig. 8a and Fig. 8b show a conventional aspect ratio Spindt cathode electron source photo and partial enlarged photo of the present invention with a base coating layer.

图9a-图9c示出本发明一种带基底包被层的较大高宽比Spindt阴极电子源一次、二次循环制作发射尖锥阵列及最终局部放大发射单元的扫描电子照片。Figures 9a-9c show the scanning electron photographs of a Spindt cathode electron source with a large aspect ratio and a substrate cladding layer in the present invention, which is produced in one cycle and two cycles, and the emission cone array and the final partial enlarged emission unit.

图10a-图10b分别示出本发明实施例1、实施例2所得Spindt阴极电子源发射性能测试曲线。Fig. 10a-Fig. 10b respectively show the emission performance test curves of Spindt cathode electron source obtained in embodiment 1 and embodiment 2 of the present invention.

具体实施方式detailed description

为了更清楚地说明本发明,下面结合优选实施例和附图对本发明做进一步的说明。附图中相似的部件以相同的附图标记进行表示。本领域技术人员应当理解,下面所具体描述的内容是说明性的而非限制性的,不应以此限制本发明的保护范围。In order to illustrate the present invention more clearly, the present invention will be further described below in conjunction with preferred embodiments and accompanying drawings. Similar parts in the figures are denoted by the same reference numerals. Those skilled in the art should understand that the content specifically described below is illustrative rather than restrictive, and should not limit the protection scope of the present invention.

针对现有技术中Spindt阴极电子源,在大电流应用时常会出现电弧失效,影响器件可靠性,以及并没有相关技术能很好的克服该不足的问题,本发明的一个具体实施方式提供了一种Spindt阴极电子源,如图6所示,其结构中包含:In view of the Spindt cathode electron source in the prior art, arc failure often occurs in high current applications, which affects the reliability of the device, and there is no related technology that can well overcome this problem. A specific embodiment of the present invention provides a A kind of Spindt cathode electron source, as shown in Figure 6, comprises in its structure:

从下到上依次设置的硅基底101、绝缘层201和栅极301,所述硅基底101、绝缘层201和栅极透孔间形成绝缘层空腔;A silicon substrate 101, an insulating layer 201, and a gate 301 are sequentially arranged from bottom to top, and an insulating layer cavity is formed between the silicon substrate 101, the insulating layer 201, and the through hole of the gate;

设置于硅基底101上的位于绝缘层空腔中的发射尖锥401,所述发射尖锥401与栅极透孔相对应;以及,An emission cone 401 disposed on the silicon substrate 101 and located in the cavity of the insulating layer, the emission cone 401 corresponding to the gate through hole; and,

设置于硅基底101上的包被层207,所述包被层207位于绝缘层空腔中且完全覆盖所述绝缘层空腔中暴露的硅基底101;A cladding layer 207 disposed on the silicon substrate 101, the cladding layer 207 is located in the cavity of the insulating layer and completely covers the silicon substrate 101 exposed in the cavity of the insulating layer;

位于包被层207与发射尖锥401之间的、且包覆在发射尖锥401下侧面的附带氧化层402;所述发射尖锥401的上侧面暴露于所述附带氧化层402外。An incidental oxide layer 402 located between the coating layer 207 and the emitting cone 401 and covering the lower side of the emitting cone 401 ; the upper side of the emitting cone 401 is exposed to the incidental oxide layer 402 .

本实施方式中,栅极透孔的直径小于绝缘层空腔的直径。In this implementation manner, the diameter of the gate through hole is smaller than the diameter of the cavity of the insulating layer.

通过构建包被层207,消除了传统Spindt阴极电子源由所述硅基底、绝缘层和真空形成的三结合点结构,杜绝了该处产生非期望电子发射,以及由此带来的沿络放电和空间电弧,从而提高了Spindt阴极电子源在高电压、大电流下工作可靠性。By constructing the cladding layer 207, the traditional Spindt cathode electron source is eliminated from the three-junction structure formed by the silicon substrate, insulating layer and vacuum, preventing the generation of undesired electron emission and the resulting discharge along the network. And space arc, thus improving the reliability of Spindt cathode electron source working under high voltage and high current.

包被层207作用是有效遮盖所述硅基底101,要求一定的厚度以耐受电场击穿。所述包被层207位于由所述硅基底101、发射尖锥401和绝缘层201构成的空腔中,完全覆盖所述硅基底101隔离真空,消除了传统结构中硅基底、绝缘层和真空构成的三结合点。综合考量包被层位置及工艺实现,所述207-包被层材料选用热氧化二氧化硅。为有效形成阻隔,所述包被层207厚度优选为30-100nm。The function of the cladding layer 207 is to effectively cover the silicon substrate 101 and requires a certain thickness to withstand electric field breakdown. The cladding layer 207 is located in the cavity formed by the silicon substrate 101, the emission cone 401 and the insulating layer 201, completely covers the silicon substrate 101 and isolates the vacuum, and eliminates the silicon substrate, the insulating layer and the vacuum in the traditional structure. composed of three junctions. In comprehensive consideration of the position of the coating layer and the realization of the process, the material of the 207-coating layer is thermally oxidized silicon dioxide. In order to effectively form a barrier, the thickness of the coating layer 207 is preferably 30-100 nm.

在一些优选示例中,所述包被层为由所述硅基底表面经热氧化得到的二氧化硅。In some preferred examples, the coating layer is silicon dioxide obtained by thermal oxidation of the surface of the silicon substrate.

发射尖锥的功能是发射电子,在一个优选示例中,所述发射尖锥401的材料选自高熔点、低功函数的纯金属,以实现对电子的有效发射。例如,发射尖锥401材料可优选为钼(熔点2620℃,功函数4.2eV)或钨(熔点3420℃,功函数4.5eV),相对于半导体工艺常用硅材料,可以克服逸出功大,化学不稳定,导电、导热差等问题,从而提供大电流稳定电子发射。The function of the emission cone is to emit electrons. In a preferred example, the material of the emission cone 401 is selected from pure metals with high melting point and low work function, so as to achieve effective emission of electrons. For example, the material of the emission tip 401 can preferably be molybdenum (melting point 2620°C, work function 4.2eV) or tungsten (melting point 3420°C, work function 4.5eV), which can overcome the large work function and chemical Instability, poor electrical conductivity, poor thermal conductivity, etc., so as to provide high current and stable electron emission.

所述发射尖锥401形状,影响其表面电场强度进而影响场电子发射。尖锥高度优化位置在栅极上下表面之间,具体由所述绝缘层201和栅极301厚度确定,范围优选在0.8-2.2μm;尖锥顶端曲率半径,具体由所述发射尖锥401高度、栅极透孔301直径以及制作尖锥双方向沉积膜层厚度确定,优化范围在20-50nm;发射尖锥底部直径,由所述栅极301孔直径以及制作尖锥倾斜方向沉积厚度确定,范围在0.6-1μm。The shape of the emission cone 401 affects the strength of its surface electric field and thus affects field electron emission. The optimal position of the height of the cone is between the upper and lower surfaces of the gate, specifically determined by the thickness of the insulating layer 201 and the gate 301, and the range is preferably 0.8-2.2 μm; the curvature radius of the cone tip is specifically determined by the height of the emission cone 401 1. The diameter of the gate through hole 301 and the thickness of the deposited film layer in both directions of the fabrication of the cone are determined, and the optimization range is 20-50nm; the diameter of the bottom of the emission cone is determined by the diameter of the gate 301 hole and the thickness of the deposition in the oblique direction of the fabrication of the cone, The range is 0.6-1μm.

Spindt阴极场发射电子源原理认为,场致电子发射仅存在于发射尖锥401顶端很小面积范围。示例性的,所述发射尖锥的上侧面暴露于所述附带氧化层外的高度为发射尖锥整体高度的15-50%。此条件下,发射尖锥401上侧面(上半部分)保持了原有材料特性,使Spindt阴极电子源保持应有的电子发射性能。发射尖锥401被附带氧化层包覆的下侧面(下半部分)由于位置原因,不影响电子源性能。According to the principle of the Spindt cathode field emission electron source, the field electron emission only exists in a small area at the top of the emission cone 401 . Exemplarily, the height of the upper side of the emission cone exposed to the accompanying oxide layer is 15-50% of the overall height of the emission cone. Under this condition, the upper side (upper part) of the emission cone 401 maintains the original material properties, so that the Spindt cathode electron source maintains proper electron emission performance. The lower side (lower part) of the emitting cone 401 covered by the incidental oxide layer does not affect the performance of the electron source due to the position.

在又一些优选实例中,所述发射尖锥的上侧面暴露于所述附带氧化层外的高度为0.3-0.4μm。In still some preferred examples, the height of the upper side of the emitting cone exposed to the incidental oxide layer is 0.3-0.4 μm.

示例性的,所述附带氧化层的材质为由发射尖锥下侧面的表面经热氧化得到。硅基底同时起承载结构作用,以及适用微加工工艺特点,选用微电子标准尺寸硅片;所述硅基底101承担提供发射电子及阴极导电功能,优选选用半导体工艺标准N型掺杂硅片,电阻率优选为0.005-5Ω·cm。Exemplarily, the material with the oxide layer is obtained by thermal oxidation of the surface of the lower side of the emitting cone. The silicon base plays the role of carrying structure at the same time, and is suitable for the characteristics of micro-machining technology. The standard size silicon chip of microelectronics is selected; the silicon base 101 is responsible for providing the functions of emitting electrons and cathode conduction. The ratio is preferably 0.005-5Ω·cm.

绝缘层201的作用是抵御所述硅基底101和栅极301之间的高工作电压,需要所述绝缘层201有较高的击穿场强和厚度。绝缘层厚度,根据击穿场强以及所述栅极透孔直径和所述发射尖锥401形状综合影响而定,优选范围为0.8-2μm;绝缘层201材料优选自工艺兼容二氧化硅或氮化硅,更优选地,根据工艺实现方法,所述绝缘层201厚度为0.8-1.2μm时,材料选自综合性能更优的热氧化二氧化硅,厚度为1.2-2μm时,材料选自制备工艺更优的化学气相沉积氮化硅。The function of the insulating layer 201 is to resist the high operating voltage between the silicon substrate 101 and the gate 301 , which requires the insulating layer 201 to have a higher breakdown field strength and thickness. The thickness of the insulating layer is determined according to the comprehensive influence of the breakdown field strength and the diameter of the gate through hole and the shape of the emission cone 401, preferably in the range of 0.8-2 μm; the material of the insulating layer 201 is preferably made of process-compatible silicon dioxide or nitrogen More preferably, according to the process implementation method, when the thickness of the insulating layer 201 is 0.8-1.2 μm, the material is selected from thermally oxidized silicon dioxide with better comprehensive performance, and when the thickness is 1.2-2 μm, the material is selected from the prepared Process-optimized chemical vapor deposition of silicon nitride.

栅极的作用是通过加载的高电压,在所述发射尖锥401表面形成强电场以引出电子,本身要承载结构强度以及一定的漏电热功率耗散。所述栅极301的材料,选自高熔点的金属材料,在一个优选示例中,栅极301材料选自钼或钨。所述栅极301厚度,受结构强度和微加工工艺影响,根据实际应用情况,优选为100-200nm。所述栅极透孔直径,在施加电压情况下,影响所述发射尖锥401表面电场强度以及电子发射性能,根据实际应用情况,优选为0.8-1.2μm。The function of the grid is to form a strong electric field on the surface of the emitting cone 401 to extract electrons through the applied high voltage, and it must carry structural strength and certain leakage heat power dissipation. The material of the gate 301 is selected from metal materials with a high melting point. In a preferred example, the material of the gate 301 is selected from molybdenum or tungsten. The thickness of the gate 301 is affected by structural strength and micro-processing technology, and is preferably 100-200 nm according to actual application conditions. The diameter of the gate through-hole affects the surface electric field intensity and electron emission performance of the emitting cone 401 under the condition of applying a voltage, and is preferably 0.8-1.2 μm according to actual application conditions.

根据本发明的又一个具体实施方式,提供一种Spindt阴极电子源的制备方法,其包括如下步骤:According to another specific embodiment of the present invention, a kind of preparation method of Spindt cathode electron source is provided, and it comprises the steps:

1)在硅基底101上形成绝缘层201。1) An insulating layer 201 is formed on the silicon substrate 101 .

绝缘层材料优选热氧化二氧化硅,它由硅片材料直接氧化形成,和硅片具有最佳结合效果;但二氧化硅超过一定厚度后热氧化生长极为缓慢,因而绝缘层较薄时选用热氧化二氧化硅,超过一定厚度后选用化学气相沉积方法的氮化硅。在一个示例中,热氧化二氧化硅绝缘层,厚度范围为0.8-1.2μm;在另一个示例中,化学气相沉积二氧化硅绝缘层,厚度范围为1.2-2μm。化学气相沉积方法,也可沉积氮化硅材料作为绝缘层。The material of the insulating layer is preferably thermally oxidized silicon dioxide, which is formed by direct oxidation of the silicon wafer material and has the best bonding effect with the silicon wafer; however, the thermal oxidation growth of silicon dioxide exceeds a certain thickness is extremely slow, so thermal oxidation is used when the insulating layer is thin. Oxide silicon dioxide, and silicon nitride by chemical vapor deposition method after exceeding a certain thickness. In one example, the thermally oxidized silicon dioxide insulating layer has a thickness in the range of 0.8-1.2 μm; in another example, the chemical vapor deposition silicon dioxide insulating layer has a thickness in the range of 1.2-2 μm. The chemical vapor deposition method can also deposit silicon nitride material as an insulating layer.

2)真空镀膜,在所述绝缘层201上形成栅极层301,如图7a所示。2) Vacuum coating, forming a gate layer 301 on the insulating layer 201, as shown in FIG. 7a.

栅极材料选自高熔点的金属材料,优选W或Mo。栅极301通过真空镀膜技术形成,优选磁控溅射镀膜方法,相对其他镀膜工艺,溅射镀膜能够得到较好的膜层结合力。栅极301厚度可根据实际应用情况进行调整,优选为100-200nm。The gate material is selected from metal materials with high melting point, preferably W or Mo. The gate 301 is formed by vacuum coating technology, preferably magnetron sputtering coating method, compared with other coating processes, sputtering coating can obtain better film bonding force. The thickness of the gate 301 can be adjusted according to actual application conditions, preferably 100-200 nm.

3)通过光刻,并依次刻蚀栅极层301和绝缘层201直至硅基底101,形成含有栅极透孔的栅极301和绝缘层空腔,如图7b所示。3) By photolithography, and sequentially etching the gate layer 301 and the insulating layer 201 until the silicon substrate 101, forming the gate 301 and the insulating layer cavity including gate through holes, as shown in FIG. 7b.

半导体工艺常规光刻技术,用于形成栅极透孔图形的掩蔽层,并可通过后续刻蚀工艺将该掩蔽层上图形复制转移到结构层,本发明中结构层为栅极层。Conventional photolithography technology in semiconductor technology is used to form the masking layer of the gate through-hole pattern, and the pattern on the masking layer can be copied and transferred to the structural layer through a subsequent etching process. The structural layer in the present invention is the gate layer.

透过图形掩蔽层刻蚀栅极301,形成栅极透孔,刻蚀优选反应离子刻蚀方法;反应离子刻蚀是高度各向异性的干法刻蚀方法,能在产生深度方向刻蚀同时基本保持宽度方向尺寸不变。对于本发明中栅极透孔刻蚀,能够完成301-栅极100-200nm深度方向刻蚀,同时维持光刻掩蔽层定义的0.8-1.2μm栅极透孔直径基本不变,得到近似陡直的侧壁。The gate 301 is etched through the pattern masking layer to form gate through-holes, and the etching method is preferably reactive ion etching; reactive ion etching is a highly anisotropic dry etching method, which can produce depth direction etching at the same time Basically keep the dimension in the width direction unchanged. For the gate through-hole etching in the present invention, the 301-gate 100-200nm depth direction etching can be completed, while maintaining the 0.8-1.2 μm gate through-hole diameter defined by the photolithographic masking layer basically unchanged, and obtaining approximately steep side wall.

透过栅极透孔刻蚀绝缘层,形成绝缘层栅控空腔,刻蚀优选反应离子刻蚀和湿法化学腐蚀结合方法;首先反应离子刻蚀实现绝缘层0.8-2μm基本全部深度刻蚀,确保过程中不产生横向的钻蚀,从而避免栅极空悬和绝缘层结合不牢;湿法化学腐蚀用作短时间漂洗刻蚀,确保绝缘层空腔刻蚀直达硅基底。由于湿法化学腐蚀方法具有很好的腐蚀选择比,可以保证该过程只基本针对绝缘层材料,而不伤害硅基底。短时间湿法化学腐蚀过程,会产生轻微的横向钻蚀,使得绝缘空腔横向尺寸略大于0.8-1.2μm栅极透孔直径。Etch the insulating layer through the gate through hole to form a gate-controlled cavity in the insulating layer. The combination of reactive ion etching and wet chemical etching is preferred for etching; first, reactive ion etching realizes the etching of the insulating layer at a depth of 0.8-2 μm. , to ensure that there is no lateral undercutting during the process, so as to avoid the gate being suspended and the insulating layer bonded weakly; the wet chemical etching is used as a short-term rinse etching to ensure that the insulating layer cavity is etched directly to the silicon substrate. Since the wet chemical etching method has a good etching selection ratio, it can be ensured that the process only basically targets the insulating layer material and does not damage the silicon substrate. The short-term wet chemical etching process will produce slight lateral undercutting, making the lateral size of the insulating cavity slightly larger than the diameter of the 0.8-1.2 μm gate through-hole.

4)旋转基片,采用表面小倾角的方法仅在栅极表面真空镀膜一层牺牲层,缩小栅极透孔,如图7c所示。4) The substrate is rotated, and only one layer of sacrificial layer is vacuum-coated on the surface of the gate by adopting the method of a small surface inclination to reduce the through-hole of the gate, as shown in FIG. 7c.

小倾角沉积牺牲层目的,其一在于通过缩小栅极301的孔直径,进而控制4发射尖锥401的底部大小;其二在于完全包裹栅极301,使得后续工艺中制作发射尖锥401所沉积膜层和栅极301形成有效隔离。The purpose of depositing the sacrificial layer at a small inclination angle is to reduce the hole diameter of the gate 301, thereby controlling the size of the bottom of the emission cone 401; The film layer and the gate 301 form an effective isolation.

牺牲层501材料,选自和硅基底101,绝缘层201,栅极301和401发射尖锥401具有腐蚀选择比的材料,优选地选自金属氧化物材料以利于形成晶粒细小均匀膜层。在一个优选例中,选自三氧化二铝。The material of the sacrificial layer 501 is selected from materials having an etch selectivity with the silicon substrate 101, the insulating layer 201, the gates 301 and 401 and the emitter cone 401, preferably selected from metal oxide materials to facilitate the formation of a fine and uniform film layer. In a preferred example, it is selected from aluminum oxide.

牺牲层501选自小倾角沉积,目的是为牺牲层501材料仅存在栅极301表面,包括上表面和栅极透孔边缘,但不会视线角度进入硅基底101和201-绝缘层形成的空腔内部。优选地,小倾角范围选自和栅极平面夹角15-30度。The sacrificial layer 501 is selected from deposition at a small inclination angle. The purpose is that the material of the sacrificial layer 501 only exists on the surface of the gate 301, including the upper surface and the edge of the through hole of the gate, but does not enter the void formed by the silicon substrate 101 and 201-the insulating layer at the angle of sight. cavity inside. Preferably, the range of the small inclination angle is selected from an angle of 15-30 degrees with the grid plane.

牺牲层501真空镀膜,优选自平行束流入射的真空蒸发镀膜。平行束流入射,以保证Spindt阴极阵列上各个单元的栅极收口一致性;真空蒸发,保证沉积材料颗粒细小以便在栅极透孔形成光滑边缘。在一个优选例中,真空镀膜选自电子束蒸发镀膜。The sacrificial layer 501 is vacuum-coated, preferably vacuum-evaporated from parallel beams. Parallel beams are injected to ensure the consistency of the grid closure of each unit on the Spindt cathode array; vacuum evaporation ensures that the deposited material particles are fine to form smooth edges in the grid through holes. In a preferred example, the vacuum coating is selected from electron beam evaporation coating.

牺牲层501沉积厚度,主要取决于栅极301透孔的开孔缩小程度,和沉积材料束流入射角度相关。优选地,栅极透孔的开孔直径缩小约为0.2μm,相应地牺牲层501沉积厚度范围100-200nm。The deposition thickness of the sacrificial layer 501 mainly depends on the reduction degree of the opening of the through hole of the grid 301 and is related to the incident angle of the deposition material beam. Preferably, the opening diameter of the gate through hole is reduced by about 0.2 μm, and correspondingly, the thickness of the sacrificial layer 501 is deposited in a range of 100-200 nm.

5)表面垂直真空镀膜一层发射尖锥材料,在空腔内形成发射尖锥401,如图7d所示。5) A layer of emitting cone material is vacuum-coated vertically on the surface to form an emitting cone 401 in the cavity, as shown in FIG. 7d.

表面垂直沉积目的,在于形成发射尖锥401。垂直沉积的材料,部分堆积在牺牲层501上面,形成附带沉积层403;部分透过经牺牲层501缩小的栅极透孔,堆积在硅基底101上,由于该过程中不断沉积的材料也会收缩栅极透孔,致使堆积在硅基底101上材料范围不断缩小,从而形成圆锥形状发射尖锥401。The purpose of the surface vertical deposition is to form the emitting cone 401 . The vertically deposited material is partially deposited on the sacrificial layer 501 to form the incidental deposition layer 403; part of it is deposited on the silicon substrate 101 through the gate through hole narrowed by the sacrificial layer 501, because the continuously deposited material in the process will also Shrinking the through-holes of the gate leads to the continuous reduction of the range of materials deposited on the silicon substrate 101 , thereby forming a conical emission tip 401 .

发射尖锥材料选自高熔点、低功函数的纯金属,例如优选钼或钨,以实现对电子的有效发射。在另一个优选示例中,还可以在发射尖锥401表面沉积高熔点、低功函数的导电非金属材料,如碳化锆作为电子发射材料。The emission tip material is selected from pure metals with high melting point and low work function, such as preferably molybdenum or tungsten, so as to realize efficient emission of electrons. In another preferred example, a conductive non-metallic material with a high melting point and low work function, such as zirconium carbide, can also be deposited on the surface of the emission cone 401 as the electron emission material.

发射尖锥材料沉积,选自真空蒸发,保证沉积材料颗粒细小、均匀,以便形成结构致密、表面光滑的发射尖锥;适应高熔点材料沉积要求,发射尖锥材料沉积选自电子束蒸发镀膜。Emission cone material deposition is selected from vacuum evaporation, which ensures that the particles of the deposited material are fine and uniform, so as to form an emission cone with a dense structure and smooth surface; to meet the requirements of high melting point material deposition, the emission cone material deposition is selected from electron beam evaporation coating.

发射尖锥材料沉积厚度,取决于所要求形成的发射尖锥401高度,二者基本为(1-1.2):1比例关系。对于高度范围在0.8-1μm尖锥的形成,优选沉积厚度为1-1.2μm。鉴于优选结构中,小角度沉积牺牲层501已将栅极透孔缩小至0.6-1μm,发射尖锥401材料沉积过程中,由于栅极透孔会不断缩小直至完全封闭,导致沉积材料不能再进入空腔增高发射尖锥401,一次材料沉积形成的发射尖锥401高度不会超过1μm。因而对于高度范围在1-2.2μm尖锥的形成,需要进行多次发射尖锥材料沉积工艺。The deposition thickness of the emission cone material depends on the required height of the emission cone 401 , and the ratio between the two is basically (1-1.2):1. For the formation of pointed cones with a height in the range of 0.8-1 μm, the preferred deposition thickness is 1-1.2 μm. In view of the preferred structure, the deposition of the sacrificial layer 501 at a small angle has narrowed the gate through-hole to 0.6-1 μm. During the deposition of the emitter tip 401 material, since the gate through-hole will continue to shrink until it is completely closed, the deposited material cannot enter The cavity heightens the emission cone 401, and the height of the emission cone 401 formed by one material deposition will not exceed 1 μm. Therefore, for the formation of a cone with a height in the range of 1-2.2 μm, multiple emission cone material deposition processes are required.

6)去除牺牲层501及沉积在牺牲层上的发射尖锥材料,如图7e所示。6) Removing the sacrificial layer 501 and the emission tip material deposited on the sacrificial layer, as shown in FIG. 7e.

牺牲层501的材料,选自和硅基底101,绝缘层201,栅极301,发射尖锥401以及后续包被层207具有腐蚀选择比的材料,以便在腐蚀去除牺牲层材料时,腐蚀液不会损伤其他材料。在一个优选例中,牺牲层材料选自三氧化二铝,相应地腐蚀液选自120℃热磷酸,或者浓度20%的氢氧化钾溶液。The material of the sacrificial layer 501 is selected from a material having an etching selectivity ratio with the silicon substrate 101, the insulating layer 201, the gate 301, the emission tip 401 and the subsequent cladding layer 207, so that when the sacrificial layer material is removed by etching, the etching solution does not Can damage other materials. In a preferred example, the material of the sacrificial layer is selected from aluminum oxide, and the corrosion solution is selected from hot phosphoric acid at 120° C., or potassium hydroxide solution with a concentration of 20%.

7)旋转基片,采用表面大倾角的方法仅在栅极301表面和发射尖锥601上侧面真空镀膜一层保护层601和602,如图7f所示。7) The substrate is rotated, and a protection layer 601 and 602 is vacuum-coated only on the surface of the gate 301 and the upper side of the emission cone 601 by adopting a method with a large surface inclination, as shown in FIG. 7f.

大倾角沉积保护层目的,在于在栅极301和发射尖锥401表面形成一层临时保护,使得在后续形成包被层207工艺中,栅极301表面和发射尖锥401部分表面状态不受影响。The purpose of depositing the protective layer at a large inclination angle is to form a layer of temporary protection on the surface of the gate 301 and the emitting cone 401, so that in the subsequent process of forming the cladding layer 207, the surface state of the gate 301 and the surface of the emitting cone 401 will not be affected. .

保护层材料,选自和硅基底101,绝缘层201,栅极301和发射尖锥401具有腐蚀选择比的材料,并且不受后续形成包被层207工艺影响,优选地选自金属氧化物材料以利于形成晶粒细小均匀膜层。在一个优选例中,选自三氧化二铝。The protective layer material is selected from materials having an etching selectivity ratio with the silicon substrate 101, the insulating layer 201, the gate 301 and the emission tip 401, and is not affected by the subsequent process of forming the cladding layer 207, preferably selected from metal oxide materials In order to facilitate the formation of fine and uniform film layer. In a preferred example, it is selected from aluminum oxide.

保护层选自大倾角沉积,是相对于前述牺牲层的小倾角沉积而言,目的是为保护层材料存在栅极301表面,包括上表面和栅极透孔边缘,以及发射尖锥401的上半部分表面;附带地,保护层材料还可能存在于绝缘层201侧壁的上半部分601,这部分材料并无实际用途;但保护层材料应确保不会视线角度到达硅基底101表面,避免影响后续包被层207的形成。优选地,大倾角范围选自和栅极301平面夹角30-60度。The protection layer is selected from high-inclination-angle deposition, which is relative to the small-inclination-angle deposition of the aforementioned sacrificial layer. half of the surface; incidentally, the protective layer material may also exist in the upper half 601 of the sidewall of the insulating layer 201, and this part of the material has no practical use; but the protective layer material should ensure that the angle of sight does not reach the surface of the silicon substrate 101, to avoid It affects the formation of the subsequent cladding layer 207 . Preferably, the range of the large inclination angle is selected from an angle of 30-60 degrees with the grid 301 plane.

保护层真空镀膜,优选自平行束流入射的真空蒸发镀膜。平行束流入射,保证在倾角蒸镀时没有乱向粒子进入空腔到达硅基底101表面;真空蒸发,保证沉积材料颗粒细小以形成均匀保护。在一个优选例中,真空镀膜选自电子束蒸发镀膜。The protective layer is vacuum-coated, preferably vacuum-evaporated from parallel beams. Parallel beam flow ensures that no chaotic particles enter the cavity and reach the surface of the silicon substrate 101 during evaporation at an oblique angle; vacuum evaporation ensures that the deposited material particles are fine to form a uniform protection. In a preferred example, the vacuum coating is selected from electron beam evaporation coating.

保护层沉积厚度,以在栅极301和发射尖锥401表面形成连续致密薄膜为基准,优选地,沉积厚度范围50-100nm。The thickness of the protective layer is deposited on the basis of forming a continuous dense film on the surface of the gate 301 and the emitting cone 401 , preferably, the deposition thickness is in the range of 50-100 nm.

8)热氧化硅基底101,空腔内硅基底101表面形成所述包被层207,发射尖锥401未保护部分附带受氧化,形成附带氧化层402,如图7g所示。8) The silicon substrate 101 is thermally oxidized, the coating layer 207 is formed on the surface of the silicon substrate 101 in the cavity, and the unprotected part of the emission tip 401 is additionally oxidized to form an additional oxide layer 402, as shown in FIG. 7g.

热氧化硅基底101的目的,是将硅材料直接氧化,形成的二氧化硅在空腔内硅基底101表面形成包被层207,完全覆盖硅基底,以消除由硅基底101、绝缘层201和空腔内真空形成的三结合点。包被层207要求一定的厚度以耐受电场击穿,以及有效形成电子发射阻隔,厚度优选为30-100nm。The purpose of thermally oxidizing the silicon substrate 101 is to directly oxidize the silicon material, and the formed silicon dioxide forms a coating layer 207 on the surface of the silicon substrate 101 in the cavity, completely covering the silicon substrate, so as to eliminate the problems caused by the silicon substrate 101, the insulating layer 201 and Three junctions created by the vacuum inside the cavity. The cladding layer 207 requires a certain thickness to withstand electric field breakdown and effectively form an electron emission barrier, and the thickness is preferably 30-100 nm.

常温下硅片即可自然氧化,但其氧化层厚度一般不超过20nm,不能满足所述包被层207要求,因而使用高温氧化方法。优选地,硅基底101热氧化使用较低温度700-800℃,既保证实现所需氧化层厚度,又不过度影响发射尖锥401和硅基底101结合。更优选地,热氧化可以使用干氧热氧化或水汽热氧化,前者速率慢可以得到致密氧化层,后者速率快可以缩短工艺时间。The silicon wafer can be naturally oxidized at room temperature, but the thickness of the oxide layer generally does not exceed 20nm, which cannot meet the requirements of the coating layer 207, so a high temperature oxidation method is used. Preferably, a lower temperature of 700-800° C. is used for the thermal oxidation of the silicon substrate 101 , so as to ensure the required thickness of the oxide layer and not excessively affect the combination of the emission tip 401 and the silicon substrate 101 . More preferably, dry oxygen thermal oxidation or water vapor thermal oxidation can be used for thermal oxidation, the former is slow to obtain a dense oxide layer, and the latter is fast to shorten the process time.

9)腐蚀去除所述保护层601,602和603,露出栅极301以及发射尖锥401上侧面,得到所述Spindt阴极电子源,如图7h所示。9) Etching and removing the protective layers 601, 602 and 603, exposing the gate 301 and the upper side of the emission cone 401 to obtain the Spindt cathode electron source, as shown in FIG. 7h.

发射尖锥保护层601和栅极保护602材料,选自和硅基底101,绝缘层201,栅极301,发射尖锥401以及包被层207具有腐蚀选择比的材料,腐蚀去除保护层材料时,腐蚀液不会损伤其他材料。在一个优选例中,牺牲层材料选自三氧化二铝,相应地腐蚀液选自120℃热磷酸,或者浓度20%的氢氧化钾溶液。Emitting cone protection layer 601 and gate protection 602 materials, selected from silicon substrate 101, insulating layer 201, gate 301, emitting cone 401 and cladding layer 207 have corrosion selectivity materials, when etching to remove the protection layer material , the corrosive liquid will not damage other materials. In a preferred example, the material of the sacrificial layer is selected from aluminum oxide, and the corrosion solution is selected from hot phosphoric acid at 120° C., or potassium hydroxide solution with a concentration of 20%.

以下,结合具体实施例进行说明:Below, illustrate in conjunction with specific embodiment:

实施例1Example 1

一种带基底包被层的Spindt阴极电子源,发射尖锥常规高宽比接近1:1,其结构如图6所示,包括从下到上依次设置的硅基底101、发射尖锥401及附带氧化层402、包被层207、绝缘层201和栅极301。其制作方法包括如下步骤:A Spindt cathode electron source with a base cladding layer, the conventional aspect ratio of the emission cone is close to 1:1, and its structure is shown in Figure 6, including a silicon substrate 101, an emission cone 401 and An oxide layer 402 , a cladding layer 207 , an insulating layer 201 and a gate 301 are attached. Its preparation method comprises the following steps:

1)硅基底101选用N型掺杂,<100>晶向、电阻率0.01Ω·cm硅片,在1200℃热氧化16小时,生长一层厚度0.8μm二氧化硅作为绝缘层201。1) The silicon substrate 101 is a silicon wafer with N-type doping, <100> crystal orientation, and a resistivity of 0.01 Ω·cm, thermally oxidized at 1200° C. for 16 hours, and grows a layer of silicon dioxide with a thickness of 0.8 μm as the insulating layer 201 .

2)使用射频磁控溅射真空镀膜方法,600W功率下溅射3分钟,在绝缘层201上沉积一层厚度0.2μm钼作为栅极301,如图7a所示。2) Using the radio frequency magnetron sputtering vacuum coating method, sputtering for 3 minutes at a power of 600W, depositing a layer of molybdenum with a thickness of 0.2 μm on the insulating layer 201 as the gate 301, as shown in FIG. 7a.

3)在栅极301涂敷厚度1.4μm的Shipley S1818光刻胶,用紫外光刻在光刻胶层形成直径1μm圆孔阵列作为掩蔽层;透过光刻胶掩蔽层,通过感应耦合等离子体方法,使用六氟化硫工艺气氛刻蚀栅极301,放电功率500W,刻蚀功率300W,4分钟完全刻透,得到栅极301开孔(透孔);透过栅极开孔,通过感应耦合等离子体方法,使用三氟甲烷工艺气氛刻蚀绝缘层201,放电功率500W,刻蚀功率300W,6分钟刻蚀大约0.6μm深度,而后使用BOE缓冲液(氢氟酸:氟化铵:水=3ml:6g:10ml)继续腐蚀,5分钟完全腐蚀二氧化硅绝缘层直至硅基底101,同时产生一定程度的横向钻蚀;去除残余Shipley S1818光刻胶,形成栅极控制的空腔结构,如图7b所示。3) Coat the gate 301 with Shipley S1818 photoresist with a thickness of 1.4 μm, and use ultraviolet lithography to form an array of circular holes with a diameter of 1 μm on the photoresist layer as a masking layer; through the photoresist masking layer, through inductively coupled plasma method, using sulfur hexafluoride process atmosphere to etch the gate 301, with a discharge power of 500W and an etching power of 300W, and complete etching in 4 minutes to obtain the opening (through hole) of the gate 301; through the opening of the gate, through the induction Coupled plasma method, using trifluoromethane process atmosphere to etch the insulating layer 201, discharge power 500W, etching power 300W, etch to a depth of about 0.6 μm in 6 minutes, and then use BOE buffer solution (hydrofluoric acid: ammonium fluoride: water =3ml: 6g: 10ml) to continue etching, completely etch the silicon dioxide insulating layer to the silicon substrate 101 in 5 minutes, and at the same time produce a certain degree of lateral undercutting; remove the residual Shipley S1818 photoresist to form a gate-controlled cavity structure, As shown in Figure 7b.

4)上述基片沿平面法向,以30RPM自旋转,同时在平面夹角20度方向,用电子束蒸发三氧化二铝,2kW功率沉积10分钟,在栅极301平面上形成200nm厚度三氧化二铝作为牺牲层501;该牺牲层完全包裹栅极301上表面和开孔侧面,并将栅极开孔由1μm缩减至0.8μm,如图7c所示。4) The above-mentioned substrate is rotated at 30 RPM along the normal direction of the plane, and at the same time, in the direction of the included angle of 20 degrees, the Al2O3 is evaporated with an electron beam and deposited at a power of 2kW for 10 minutes to form a 200nm thick Al2O3 on the plane of the gate 301. Dialuminum is used as the sacrificial layer 501; the sacrificial layer completely wraps the upper surface of the gate 301 and the sides of the opening, and reduces the gate opening from 1 μm to 0.8 μm, as shown in FIG. 7c.

5)上述基片沿垂直方向,用电子束蒸发钼,沉积材料透过301-栅极301开孔到达101-硅基底101,随着栅极开孔不断缩小,在硅基底101上逐渐形成发射尖锥401。4kW功率沉积40分钟,沉积钼层厚度1.1μm,得到发射尖锥401高度约0.9μm,同时在牺牲层501平面上形成厚度1.1μm的附带沉积层403,如图7d所示。5) The above substrate is evaporated molybdenum with electron beam along the vertical direction, and the deposited material reaches 101-silicon substrate 101 through the opening of 301-grid 301. As the opening of the gate continues to shrink, emission Spike 401. 4kW power deposition for 40 minutes, deposited molybdenum layer thickness of 1.1 μm, resulting in emission cone 401 with a height of about 0.9 μm, and an incidental deposition layer 403 with a thickness of 1.1 μm formed on the plane of the sacrificial layer 501, as shown in Figure 7d.

6)使用浓度85%温度120℃热磷酸,腐蚀牺牲层501,1分钟完全溶解,牺牲层501上的附带沉积层403随之从基体剥离,留下硅基底101、发射尖锥401、绝缘层201和栅极301构成的传统结构Spindt阴极电子源,如图7e所示。6) Use hot phosphoric acid with a concentration of 85% and a temperature of 120°C to etch the sacrificial layer 501 and completely dissolve it in 1 minute, and the incidental deposition layer 403 on the sacrificial layer 501 is peeled off from the substrate, leaving the silicon substrate 101, the emission cone 401, and the insulating layer 201 and grid 301 constitute the traditional Spindt cathode electron source structure, as shown in FIG. 7e.

7)上述基片沿平面法向,以30RPM自旋转,同时在平面夹角45度方向,用电子束蒸发三氧化二铝,2kW功率沉积2分钟,在栅极301平面上形成50nm厚度栅极保护层602,完全包裹栅极301上表面和开孔侧面,在发射尖锥401上半部分形成50nm厚度发射尖锥保护层601,完全包裹发射尖锥401顶端电子发射部分;同时在绝缘层201侧壁形成附带保护层,如图7f所示。7) The above-mentioned substrate is rotated at 30 RPM along the normal direction of the plane, and at the same time, in the direction of 45 degrees included in the plane, Al2O3 is evaporated with an electron beam and deposited for 2 minutes at a power of 2kW to form a 50nm thick grid on the grid 301 plane The protective layer 602 completely wraps the upper surface of the grid 301 and the sides of the opening, and forms a 50nm-thick emission cone protection layer 601 on the upper half of the emission cone 401 to completely wrap the electron emission part at the top of the emission cone 401; at the same time, the insulating layer 201 The sidewalls form an accompanying protective layer, as shown in Figure 7f.

8)进行热氧化,在800℃下干氧氧化5小时,在空腔内101-硅基底101表面形成厚度30nm的二氧化硅207-包被层207,同时401-发射尖锥下半部分未受保护部分附带形成氧化表面附带氧化层402,如图7g所示。8) Carry out thermal oxidation, dry oxygen oxidation at 800°C for 5 hours, and form a silicon dioxide 207-coating layer 207 with a thickness of 30nm on the surface of the cavity 101-silicon substrate 101, and at the same time, 401-the lower half of the emission cone is not exposed. The protected portion incidentally forms an oxidized surface incidentally with an oxide layer 402, as shown in FIG. 7g.

9)使用浓度85%温度120℃热磷酸,腐蚀发射尖锥保护层601、栅极保护层602和附带保护层603,1分钟完全溶解,露出栅极301以及发射尖锥401上半部分,得到基底包被的Spindt阴极电子源,如图7h所示。9) Use hot phosphoric acid with a concentration of 85% and a temperature of 120°C to corrode the protective layer 601 of the emission tip, the protective layer 602 of the gate and the protective layer 603, and completely dissolve it in 1 minute, exposing the upper part of the gate 301 and the upper part of the tip of the emission 401, and obtain The substrate-coated Spindt cathode electron source is shown in Fig. 7h.

由上述流程得到基底包被的Spindt阴极电子源,发射阵列单元栅极开孔直径1μm,绝缘层厚度0.8μm,栅极厚度0.2μm,发射尖锥高度0.9μm,发射尖锥的尖端曲率半径50nm,包被层厚度30nm,该Spindt阴极电子源阵列及局部放大发射单元的扫描电子照片分别如图8a和8b所示。The substrate-coated Spindt cathode electron source is obtained by the above process, the diameter of the gate opening of the emission array unit is 1 μm, the thickness of the insulating layer is 0.8 μm, the thickness of the gate is 0.2 μm, the height of the emission cone is 0.9 μm, and the radius of curvature of the tip of the emission cone is 50nm , the thickness of the cladding layer is 30nm, the scanning electron photos of the Spindt cathode electron source array and the partially enlarged emission unit are shown in Fig. 8a and 8b respectively.

实施例2Example 2

一种带基底包被层的Spindt阴极电子源,发射尖锥常规高宽比接近1.5:1,其结构如图6所示,包括从下到上依次设置的硅基底101、发射尖锥401及附带氧化层402、包被层207、绝缘层201和栅极301。其制作方法包括重复实施例1,区别在于:A Spindt cathode electron source with a base cladding layer, the conventional aspect ratio of the emission cone is close to 1.5:1, and its structure is shown in Figure 6, including a silicon substrate 101, an emission cone 401 and An oxide layer 402 , a cladding layer 207 , an insulating layer 201 and a gate 301 are attached. Its preparation method comprises repeating embodiment 1, difference is:

步骤1中,201-绝缘层201生长采用化学气相沉积方法,四乙基原硅酸盐(TEOS)640度分解120分钟,得到厚度1.2μm二氧化硅绝缘层。In step 1, 201-insulating layer 201 is grown by chemical vapor deposition, and tetraethylorthosilicate (TEOS) is decomposed at 640°C for 120 minutes to obtain a silicon dioxide insulating layer with a thickness of 1.2 μm.

步骤3中,使用三氟甲烷工艺气氛刻蚀绝缘层201,工艺参数不变,15分钟刻蚀大约1μm深度二氧化硅。In step 3, the insulating layer 201 is etched using a trifluoromethane process atmosphere with constant process parameters, and the silicon dioxide is etched to a depth of approximately 1 μm in 15 minutes.

步骤4-6需循环做两次:第一次循环,步骤5中沉积钼层厚度0.6μm,得到发射尖锥401高度约0.5μm。第二次循环,步骤4中电子束蒸发三氧化二铝,在栅极301平面上形成250nm厚度牺牲层501,将栅极开孔由1μm缩减至0.7μm;步骤5中沉积钼层厚度1μm,在发射尖锥401已有0.5μm高度上叠加0.8μm。Steps 4-6 need to be repeated twice: in the first cycle, the thickness of the molybdenum layer deposited in step 5 is 0.6 μm, and the height of the emitting cone 401 is about 0.5 μm. In the second cycle, in step 4, the electron beam evaporates aluminum oxide to form a sacrificial layer 501 with a thickness of 250 nm on the plane of the gate 301, reducing the gate opening from 1 μm to 0.7 μm; in step 5, depositing a molybdenum layer with a thickness of 1 μm, 0.8 μm is superimposed on the already 0.5 μm height of emission cone 401 .

步骤8中,在800℃下水汽热氧化2小时,在空腔内硅基底101表面形成厚度100nm的二氧化硅包被层207。In step 8, thermal oxidation was performed with water vapor at 800° C. for 2 hours to form a silicon dioxide coating layer 207 with a thickness of 100 nm on the surface of the silicon substrate 101 in the cavity.

由上述流程得到基底包被的Spindt阴极电子源,发射阵列单元栅极开孔直径1μm,绝缘层厚度1.2μm,栅极厚度0.2μm,发射尖锥高度1.3μm,发射尖锥的尖端曲率半径40nm,包被层厚度100nm,该Spindt阴极电子源一次、二次循环制作发射尖锥阵列及最终局部放大发射单元的扫描电子照片分别如图9a、9b和9c所示。The substrate-coated Spindt cathode electron source is obtained by the above process, the diameter of the gate opening of the emission array unit is 1 μm, the thickness of the insulating layer is 1.2 μm, the thickness of the gate is 0.2 μm, the height of the emission cone is 1.3 μm, and the radius of curvature of the tip of the emission cone is 40nm , the thickness of the cladding layer is 100nm, the scanning electron photos of the Spindt cathode electron source for the first and second cycles of manufacturing the emission cone array and the final partial enlarged emission unit are shown in Figures 9a, 9b and 9c, respectively.

上述各实施例验证结果表明,本发明提出的基底包被的Spindt阴极电子源,可以有效消除硅基底、绝缘层和真空三结合点产生非期望电子发射,进而避免由之导致的真空电弧电子源失效问题。The verification results of the above examples show that the substrate-coated Spindt cathode electron source proposed by the present invention can effectively eliminate the undesirable electron emission generated by the silicon substrate, the insulating layer and the vacuum triple junction, thereby avoiding the resulting vacuum arc electron source Invalidation problem.

以实施例结构参数(主要是栅极孔直径、发射尖锥高度和尖锥顶端曲率半径)和材料为例,不带有基底包被层结构的Spindt阴极电子源,产生电子发射的栅极电压阈值70-80V,发射电流随栅极电压升高而增大,但在栅极电压超过120-130V时,就可会产生明显真空电弧,导致阴极电子源损毁。而本实施例1中带有基底包被结构的Spindt阴极电子源,产生电子发射的栅极电压阈值基本不变,在栅极电压超过130V以上时仍能够稳定工作,保持大电流可靠发射。实施例2及其它实施例验证显示了相似的结果,表明了本发明能够较好解决Spindt阴极电子源三结合点非期望电子导致的真空电弧失效问题。Taking the structural parameters of the embodiment (mainly the diameter of the grid hole, the height of the emission tip and the radius of curvature of the tip of the tip) and the material as an example, the Spindt cathode electron source without the base cladding layer structure generates the grid voltage for electron emission The threshold value is 70-80V, and the emission current increases with the increase of the grid voltage, but when the grid voltage exceeds 120-130V, an obvious vacuum arc may be generated, resulting in damage to the cathode electron source. However, the Spindt cathode electron source with a substrate-coated structure in Example 1 basically does not change the gate voltage threshold for electron emission, and can still work stably when the gate voltage exceeds 130V, maintaining high current and reliable emission. Example 2 and other examples show similar results, indicating that the present invention can better solve the problem of vacuum arc failure caused by undesired electrons at triple junctions of the Spindt cathode electron source.

图10给出了两个带有基底包被结构的Spindt阴极电子源发射性能测试曲线,测试环境真空度2×10-7Pa。测试采用外加阳极的三极式测试,外加阳极施加固定高压,逐步升高栅极电压测试发射电流,发射总电流包括阳极电流和栅极截获电流。图10a对应实施例1得到的包含11000个发射单元阵列、单元中心间距5μm的Spindt阴极,其在70V栅极电压下开始产生电子发射,在148V时得到24.62mA的稳定发射电流,相应发射电流密度8.7A/cm2。图10b对应实施例2得到的包含25个发射单元阵列、单元中心间距5μm的Spindt阴极,其在80V栅极电压下开始产生电子发射,在160V时得到159μA的稳定发射电流,相应发射电流密度25.4A/cm2Figure 10 shows the emission performance test curves of two Spindt cathode electron sources with a substrate-coated structure, and the vacuum degree of the test environment is 2×10 -7 Pa. The test adopts a three-pole test with an external anode. A fixed high voltage is applied to the external anode, and the grid voltage is gradually increased to test the emission current. The total emission current includes the anode current and the grid interception current. Figure 10a corresponds to the Spindt cathode obtained in Example 1 that contains 11,000 emitting unit arrays and a unit center spacing of 5 μm. It starts to generate electron emission at a gate voltage of 70V, and obtains a stable emission current of 24.62mA at 148V. The corresponding emission current density 8.7A/cm 2 . Figure 10b corresponds to the Spindt cathode obtained in Example 2, which contains 25 emitting unit arrays and a unit center spacing of 5 μm. It starts to generate electron emission at a gate voltage of 80V, and obtains a stable emission current of 159 μA at 160V, corresponding to an emission current density of 25.4 A/cm 2 .

显然,本发明的上述实施例仅仅是为清楚地说明本发明所作的举例,而并非是对本发明的实施方式的限定,对于所属领域的普通技术人员来说,在上述说明的基础上还可以做出其它不同形式的变化或变动,这里无法对所有的实施方式予以穷举,凡是属于本发明的技术方案所引伸出的显而易见的变化或变动仍处于本发明的保护范围之列。Apparently, the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. Those of ordinary skill in the art can also make It is impossible to exhaustively list all the implementation modes here, and any obvious changes or changes derived from the technical solutions of the present invention are still within the scope of protection of the present invention.

Claims (10)

1. A Spindt cathode electron source, characterized in that the structure comprises:
the silicon substrate, the insulating layer and the grid are sequentially arranged from bottom to top, and an insulating layer cavity is formed among the silicon substrate, the insulating layer and the grid through hole;
an emission sharp cone arranged on the silicon substrate and positioned in the cavity of the insulating layer, wherein the emission sharp cone corresponds to the gate through hole; and the number of the first and second groups,
a coating layer arranged on the silicon substrate, wherein the coating layer is positioned in the insulating layer cavity and completely covers the silicon substrate exposed in the insulating layer cavity;
the attached oxide layer is positioned between the coating layer and the emission tip cone and coated on the lower side surface of the emission tip cone; the upper side surface of the emission tip cone is exposed outside the incidental oxide layer.
2. The Spindt cathode electron source of claim 1, wherein the coating layer is silicon dioxide obtained by thermal oxidation of the surface of the silicon substrate;
preferably, the coating layer has a thickness of 30-100nm.
3. A Spindt cathode electron source according to claim 1, wherein the upper side of the emission tip is exposed outside the incidental oxide layer to a height of 0.3-0.4 μm;
preferably, the material of the emission tip cone is selected from pure metals with high melting point and low work function, preferably W or Mo;
preferably, the diameter of the bottom of the emission sharp cone is 0.6-1 μm, the height is 0.8-2.2 μm, and the radius of curvature of the top is 20-50nm.
4. A Spindt cathode electron source according to claim 1, wherein the upper side of the emission tip is exposed outside the incidental oxide layer to a height of 15-50% of the overall height of the emission tip.
5. A Spindt cathode electron source according to claim 1, wherein the incidental oxide layer is thermally oxidised from the surface of the underside of the emission cusp.
6. The Spindt cathode electron source of claim 1, wherein the silicon substrate is selected from a semiconductor process standard N-type doped silicon wafer; preferably, the silicon substrate has a resistivity of 0.005 to 5 Ω · cm.
7. A Spindt cathode electron source according to claim 1, wherein the insulating layer material is selected from silicon dioxide or silicon nitride; preferably, the thickness of the insulating layer material is 0.8-2 μm.
8. A Spindt cathode electron source according to claim 1, wherein the material of the grid is selected from a high melting point pure metal, preferably W or Mo; preferably, the thickness of the grid electrode is 100-200nm, and the diameter of the grid through hole is 0.8-1.2 μm.
9. A method of producing a Spindt cathode electron source according to any of claims 1 to 8, comprising the steps of:
forming an insulating layer on the silicon substrate;
vacuum coating, forming a grid layer on the insulating layer;
etching the grid layer and the insulating layer in sequence until reaching the silicon substrate by photoetching to form a grid containing a grid through hole and an insulating layer cavity;
rotating the substrate, and performing vacuum coating on the surface of the grid only by adopting a method with a small surface inclination angle to form a sacrificial layer and reduce the through holes of the grid;
vacuum coating a layer of emission pointed cone material on the surface of the hollow cavity in a vertical manner to form an emission pointed cone in the hollow cavity;
removing the sacrificial layer and the emission pointed cone material deposited on the sacrificial layer;
rotating the substrate, and performing vacuum coating on the surface of the grid and the upper side surface of the emission pointed cone only by adopting a method of large surface inclination angle to form a protective layer;
thermally oxidizing the silicon substrate, wherein the coating layer is formed on the surface of the silicon substrate in the cavity, and the unprotected part of the emission sharp cone is subjected to oxidation to form an attached oxidation layer;
and corroding and removing the protective layer to expose the grid and the upper side surface of the emission pointed cone to obtain the Spindt cathode electron source.
10. Use of a Spindt cathode electron source according to any of the claims 1-8 in a device for vacuum electronics.
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JPH05198253A (en) * 1991-10-02 1993-08-06 Sharp Corp Field emission electron source
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