CN115527598A - Memory operating method, reading method, memory and memory system - Google Patents

Abstract

Embodiments of the present application provide a memory operating method, a reading method, a memory, and a storage system. Wherein, the operation method includes: determining the first change amount of the threshold voltage of the memory cell in the single-layer cell SLC erasing state; comparing the first change amount with a reference threshold; When the set relationship between the first variation and the reference threshold is not satisfied, the threshold voltage of the memory cell in the SLC erased state is adjusted to have a second variation, so that the second variation Satisfy the set relationship with the reference threshold.

Description

Operation method, reading method, memory and storage system of a memory

technical field

The present application relates to the technical field of memory, and in particular to a method for operating a memory, a reading method, a memory, and a storage system.

Background technique

Recently, with the development of memory, memory may be volatile or nonvolatile. Because of its ability to retain data even when power is not applied, non-volatile memory has been widely used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices, as one example, 3D Charge Trapping Flash (CTF, Charge Trapping Flash) memories are widely used. The 3D charge-trapping flash memory realizes the function of data storage by trapping and storing charges in the gate dielectric layer of the memory cells it contains. Random telegraph noise (RTN, Random telegraph noise) caused by charge trapping and loss in the gate dielectric layer of the memory cell will affect the correctness of reading data stored in the memory cell.

Contents of the invention

In view of this, the present application provides a memory operation method, a reading method, a memory and a storage system, which adjust the magnitude of the RTN corresponding to the memory unit, thereby reducing read interference caused by the RTN.

In order to achieve the above object, the technical solution of the present application is achieved in this way:

In a first aspect, an embodiment of the present application provides a method for operating a memory, including:

determining a first variation in threshold voltage of a storage cell in the memory in a single-level cell SLC erase state;

comparing the first variation with a reference threshold;

When the comparison result is that the set relationship between the first variation and the reference threshold is not satisfied, the threshold voltage of the memory cell in the SLC erased state is adjusted to have a second variation, so that the The set relationship is satisfied between the second change amount and the reference threshold.

In the second aspect, the embodiment of the present application also provides a memory reading method, including:

When performing a read operation on a memory cell of the memory, providing a read voltage to a selected word line coupled to the memory cell;

providing a pass voltage to an unselected word line coupled to other memory cells in the same memory cell string as the memory cell;

Wherein, the pass voltage is determined based on the recorded total offset and a default pass voltage.

In a third aspect, the embodiment of the present application further provides a memory, including: a storage array, where the storage array includes a storage unit;

and peripheral circuitry coupled to the memory array and configured to control the memory array;

The peripheral circuit is configured as: the operation method described in any one of the foregoing.

In a fourth aspect, the embodiment of the present application further provides a storage system, including: one or more aforementioned memories; and a memory controller coupled to the memories; the memory controller is configured to: Send various operation commands to the memory.

Embodiments of the present application provide a memory operating method, a reading method, a memory, and a storage system. Wherein, the operation method of the memory includes: determining the first change amount of the threshold voltage of the memory cell in the single-layer cell SLC erasing state; comparing the first change amount with a reference threshold; adjusting the threshold voltage of the memory cell in the SLC erasing state to have a second variation when the first variation and the reference threshold do not satisfy a set relationship, so that the second The set relationship is satisfied between the variation amount and the reference threshold. The operation method of the memory provided by the embodiment of the present application compares the RTN of the storage unit with a reference threshold, and when the comparison result does not satisfy the set relationship, adjusts the comparison result with the reference threshold to satisfy the set relationship, thereby Reduce read disturbance caused by RTN. Generally speaking, the operation method provided by the embodiment of the present application is to adjust the magnitude of the RTN of the memory cell (the variation of the threshold voltage in the SLC erased state of the memory cell represents the magnitude of the RTN) to a known minimum magnitude (reference threshold For example, the magnitude of the minimum RTN may be the magnitude of the RTN corresponding to the memory cell adjacent to the bit line), so as to reduce the read disturbance caused by the RTN, so that the data stored in the memory cell can be read correctly.

Description of drawings

Aspects of the present application are best understood from the following detailed description when read with the accompanying figures. Note that, in accordance with the standard practice in industry assembly, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

FIG. 1 shows a block diagram of an exemplary system with a memory in the related art;

Figure 2 shows a schematic diagram of an exemplary memory card with memory;

Figure 3 shows a schematic diagram of an exemplary solid-state drive (SSD) with memory;

4 shows a schematic diagram of an exemplary memory including peripheral circuits;

5 illustrates a side view of a cross-section of an exemplary memory array including strings of memory cells according to some aspects of the present application;

6 shows a block diagram of an exemplary memory including a memory array and peripheral circuits;

Fig. 7 shows the schematic diagram of the threshold voltage distribution of the memory cell of MLC type;

Fig. 8 shows the schematic diagram of the threshold voltage distribution of the memory cell of TLC type;

Fig. 9 shows the schematic diagram of the threshold voltage distribution of the memory cell of QLC type;

FIG. 10 shows three schematic diagrams of factors affecting the RWM of the storage unit;

FIG. 11 shows a schematic flowchart of a method for operating a memory provided in an embodiment of the present application;

Fig. 12 shows the first schematic flow chart of determining the first variation of random telegraph noise provided by the embodiment of the present application;

FIG. 13 shows a schematic diagram of a read voltage in a first read condition;

FIG. 14 shows the second schematic flow diagram for determining the first variation of random telegraph noise provided by the embodiment of the present application;

Fig. 15 shows the third schematic flow chart of determining the first variation of random telegraph noise provided by the embodiment of the present application;

FIG. 16 shows a schematic diagram of the variation distribution of the threshold voltage of the memory cells coupled to the word lines WL0, WL31, and WL63 in the SLC erased state provided by the embodiment of the present application;

FIG. 17 shows a schematic diagram of the 3σ distribution of the variation distribution of the threshold voltage when the memory cells coupled to each word line are in the SLC erased state provided by the embodiment of the present application;

FIG. 18 shows a schematic flow diagram of the adjustment of the amount of change of the storage unit in the SLC erasing state provided by the embodiment of the present application;

FIG. 19 shows a schematic flow diagram of determining the adjustment timing of the change amount of the storage unit in the SLC erasing state provided by the embodiment of the present application;

FIG. 20 shows a schematic flow chart of the reading method provided by the embodiment of the present application;

Fig. 21 shows that the CTF including 64 word lines provided by the embodiment of the present application uses the process of Fig. 18 to determine the total offset of the pass voltage applied by the unselected word lines coupled to the unselected memory cells relative to the default pass voltage Schematic diagram of the process;

FIG. 22 shows a schematic flow diagram of judging whether the current programming/erasing times need to be adjusted by RTN provided by the embodiment of the present application;

FIG. 23 shows a schematic flowchart of adjusting the amplitude of RTN of unselected memory cells when the current programming/erasing times reach the preset times provided by the embodiment of the present application.

detailed description

The following disclosure provides many different embodiments, or examples, for implementing different features of the presented subject matter. Specific examples of components and arrangements are described below to simplify the present application. Of course, these are examples only, not limiting. For example, in the following description, a first feature formed on or over a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include that additional features may be formed over the first feature and the second feature. An embodiment in which the first feature and the second feature may not be in direct contact between the two features. Additionally, this application may repeat reference numerals and/or letters in various instances. Such repetition is for the sake of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or configurations discussed.

In addition, spatially relative terms such as "under", "beneath", "lower", "above", "upper" may be used herein to describe an element or feature for convenience of description Relationship to another element or feature(s) as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The technical solution of the present application will be described in detail below in conjunction with the accompanying drawings.

FIG. 1 shows a block diagram of an exemplary system with memory in the related art. In FIG. 1, the system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a pointing device, a wearable electronic device, a smart sensor, a virtual reality (VR, Virtual Reality ) device, an augmented reality (AR, Argument Reality) device, or any other suitable electronic device having a memory therein. As shown in FIG. 1 , the system 100 may include a host 108 and a storage system 102, wherein the storage system 102 has one or more memories 104 and a memory controller 106; the host 108 may be a processor of an electronic device, such as a central processing unit ( CPU, Central Processing Unit) or a system on chip (SoC, System of Chip), where the system on chip may be, for example, an application processor (AP, Application Processor). Host 108 may be configured to send data to or receive data from memory 104 . Specifically, the memory 104 may be any memory disclosed in this application. For example, phase change random access memory (PCRAM, Phase Change Random Access Memory), three-dimensional NAND flash memory, and the like.

According to some implementations, memory controller 106 is coupled to memory 104 and host 108 . And configured to control the memory 104 . Memory controller 106 may manage data stored in memory 104 and communicate with host 108 . In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as in a Secure Digital (SD, Secure Digital) card, a Compact Flash (CF, Compact Flash) card, a general-purpose serial USB (Universal Serial Bus) flash drives, or other media intended for use in electronic devices in low duty cycle environments such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment, such as a solid state drive (SSD, Solid State Drive) or an embedded multimedia card (eMMC, embedded Muti Media Card), where the SSD Or eMMC is used as data storage for mobile devices in high duty cycle environments such as smartphones, tablets, laptops, and enterprise storage arrays. The memory controller 106 may be configured to control operations of the memory 104, such as read, erase and program operations. Memory controller 106 may also be configured to manage various functions related to data stored or to be stored in memory 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, and the like. In some implementations, the memory controller 106 is further configured to process an Error Correction Code (ECC, Error Correction Code) on data read from or written to the memory 104 . Memory controller 106 may also perform any other suitable functions, such as formatting memory 104 . Memory controller 106 may communicate with external devices (eg, host 108 ) according to a particular communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, peripheral component interconnection (PCI, Peripheral Component Interconnection) protocol, PCI Express (PCI-E , PCI Express) protocol, Advanced Technology Attachment (ATA, Advanced Technology Attachmnet) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI, SmallComputer Small Interface) protocol, Enhanced Small Disk Interface (ESDI, Enhanced Small DiskInterface ) protocol, Integrated Drive Electronics (IDE, Integrated Drive Electronics) protocol, Firewire protocol, etc.

Memory controller 106 and one or more memories 104 may be integrated into various types of storage devices, eg, included in the same package (eg, Universal Flash Storage (UFS) package or eMMC package). That is, the storage system 102 can be implemented and packaged into different types of terminal electronic products. In one example as shown in FIG. 2 , memory controller 106 and a single memory 104 may be integrated into memory card 202 . Memory cards can include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD , SDHC), UFS, etc. The memory card may also include a memory card connector 204 that couples the memory card with a host (eg, host 108 in FIG. 1 ). In another example as shown in FIG. 3 , memory controller 106 and multiple memories 104 may be integrated into SSD 302 . The SSD may also include an SSD connector 304 that couples the SSD to a host (eg, host 108 in FIG. 1 ). In some embodiments, the storage capacity and/or operating speed of the SSD is greater than the storage capacity and/or operating speed of the memory card. In addition, the memory controller 106 can also be configured to control the erasing, reading, and writing operations of the memory 104 .

Figure 4 shows a schematic diagram of an exemplary memory including peripheral circuitry. As shown in FIG. 4, the memory 104 may include a storage array 401 and a peripheral circuit 402 coupled to the storage array 401, wherein the storage array 401 may be a NAND flash storage array, wherein the storage unit 406 is an array of NAND memory strings 408 Provided in the form of , each NAND memory string 408 extends vertically above a substrate (not shown). In some embodiments, each NAND memory string 408 includes a plurality of memory cells 406 coupled in series and stacked vertically. Each storage cell 406 may hold a continuous analog value, such as a voltage or charge, depending on the number of electrons trapped within the storage area of the storage cell 406 . Each memory cell 406 may be a floating gate type memory cell including a floating gate transistor, or a charge trap type memory cell including a charge trap transistor.

In some embodiments, each memory cell 406 is a single-level cell (SLC, Single Level Cell) with two possible data states and thus can store one bit of data, for example, the first data state "0" may correspond to the A voltage range, and the second data state "1" may correspond to the second voltage range. In some embodiments, the first voltage range and the second voltage range may be referred to as threshold voltage distributions of memory cells. In some embodiments, each storage unit 406 is a multi-level cell (MLC, Multi Level Cell) capable of storing data for a single bit in a plurality of four data states, for example, the MLC can store two bits per unit, Store three bits per unit (also known as Trinary Level Cell (TLC, Trinary Level Cell), or store four bits per unit (also known as Quadruple Level Cell (QLC, Quadruple Level Cell). Among them, regardless of the type of storage The data state of the cell includes the erased state and the programmed state. When the programming operation is performed on the memory cell, the memory cell in the erased state is programmed to a certain programmed state. Generally speaking, the voltage range corresponding to the programmed state of the memory cell The voltage value in is relatively large.

As shown in FIG. 4, each NAND memory string 408 may include a source select gate (SSG) 410 at its source terminal and a drain select gate (DSG) 412 at its drain terminal. SSG 410 and DSG 412 may be configured to activate selected NAND memory strings 408 (columns of the array) during read and program (or write) operations. In some embodiments, the sources of the NAND memory strings 408 in the same block 404 are coupled by the same source line (SL) 414 (eg, a common SL). In other words, according to some embodiments, all NAND memory strings 408 in the same block 404 have an array common source (ACS). According to some implementations, the DSG 412 of each NAND memory string 408 is coupled to a corresponding bit line 416 from which data can be read and written via an output bus (not shown). In some embodiments, each NAND memory string 408 is configured to pass a select voltage (eg, above the threshold voltage of the transistor with DSG 412 ) or a deselect voltage (eg, 0 volts (V )) is applied to the corresponding DSG 412 and/or a select voltage (eg, higher than the threshold voltage of a transistor with SSG 410 ) or a deselect voltage (eg, 0 V) is applied to the corresponding SSG 410 via one or more SSG lines 415 Selected or deselected.

As shown in FIG. 4, NAND memory string 408 may be organized into a plurality of blocks 404, each of which may have a common source line 414 (eg, coupled to ground). In some embodiments, each block 404 is a basic unit of data with an erase operation, ie, all memory cells 406 on the same block 404 are erased simultaneously. In order to erase the memory cells 406 in the selected block 404, a bias coupled to the selected block 404 and on the same side as the selected block 404 (Plane Source lines 414 of unselected blocks 404 in ). It should be understood that, in some examples, erase operations may be performed at the half-block level, at the quarter-block level, or with any suitable number or fraction of blocks. Memory cells 406 of adjacent NAND memory strings 408 may be coupled by word lines 418 that select which row of memory cells 406 receives read and program operations. In some implementations, the memory cells 406 coupled on the same word line 418 are referred to as a page 420 . A page 420 is a basic data unit for a program operation or a read operation, and the size of a page 420 in units of bits may be related to the number of NAND memory strings 408 coupled by word lines 418 in one block 404 . Each word line 418 may include a plurality of control gates (gate electrodes) at each memory cell 406 in a corresponding page 420 and a gate line coupling the control gates.

5 illustrates a side view of a cross-section of an exemplary memory array 401 including strings 408 of NAND memory cells, in accordance with aspects of the present application. As shown in FIG. 5 , NAND memory cell string 408 may extend vertically through memory stack layer 502 above substrate 501 . The substrate 501 may comprise silicon (eg, monocrystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable Material.

The memory stack layer 502 may include alternating gate conductive layers 503 and gate-to-gate dielectric layers 504 . The number of gate conductive layer 503 and gate-to-gate dielectric layer 504 pairs in memory stack layer 502 may determine the number of memory cells 406 in memory array 401 . The gate conductive layer 503 may include conductive materials including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide or any combination thereof. In some embodiments, each gate conductive layer 503 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 503 includes a doped polysilicon layer. Each gate conductive layer 503 may include a control gate surrounding the memory cell 406 and may extend laterally at the top of the memory stack layer 502 as a DSG line 413 and at the bottom of the memory stack layer 502 as a SSG line 415 , or extend laterally between the DSG line 413 and the SSG line 415 as a word line 418 .

As shown in FIG. 5 , NAND memory cell string 408 includes a channel structure 505 extending vertically through memory stack layer 502 . In some embodiments, the channel structure 505 includes a channel hole filled with a semiconductor material(s) and a dielectric material(s). In some embodiments, the semiconductor channel includes silicon, eg, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping/storage layer"), and a blocking layer. The channel structure 505 may have a cylindrical shape (eg, a pillar shape). According to some embodiments, the semiconductor channel, the tunneling layer, the storage layer and the barrier layer are radially arranged in this order from the center of the pillar toward the outer surface of the pillar. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The memory layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, high-k (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO).

Referring back to FIG. 4 , peripheral circuitry 402 may be coupled to memory array 401 through bit lines 416 , word lines 418 , source lines 414 , SSG lines 415 , and DSG lines 413 . Peripheral circuitry 402 may include any suitable analog, digital, and mixed-signal circuitry for applying voltage and/or current signals via bit lines 416, word lines 418, source lines 414, SSG lines 415, and DSG lines 413. Sensing voltage signals and/or current signals to and from each target memory cell 406 facilitates operation of the memory array 401 . The peripheral circuit 402 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, FIG. 6 shows some exemplary peripheral circuits. Peripheral circuit 402 includes page buffer/sense amplifier 604, column decoder/bit line driver 606, row decoder/word line driver 608, voltage generator 610, control Logic unit 612 , registers 614 , interface 616 and data bus 618 . It should be understood that in some examples, additional peripheral circuitry not shown in FIG. 6 may also be included.

The page buffer/sense amplifier 604 may be configured to read data from and program (write) data to the memory array 401 according to control signals from the control logic unit 612 . In one example, page buffer/sense amplifier 604 may store a page of program data (write data) to be programmed into one page 420 of memory array 401 . In another example, page buffer/sense amplifier 604 may perform a program verify operation to ensure that data has been correctly programmed into memory cell 406 coupled to selected word line 418 . In yet another example, page buffer/sense amplifier 604 may also sense a low power signal from bit line 416 representing a data bit stored in memory cell 406 and amplify the small voltage swing during a read operation to a recognizable logic level. Column decoder/bit line driver 606 may be configured to be controlled by control logic unit 612 and to select one or more NAND memory strings 408 by applying bit line voltages generated from voltage generator 610 .

Row decoder/word line driver 608 may be configured to be controlled by control logic unit 612 and select/deselect blocks 404 of memory array 401 and select/deselect word lines 418 of blocks 404 . Row decoder/wordline driver 608 may also be configured to drive wordline 418 using a wordline voltage generated from voltage generator 610 . In some implementations, the row decoder/wordline driver 608 can also select/deselect and drive the SSG line 415 and the DSG line 413 . As described in detail below, row decoder/wordline driver 608 is configured to perform erase operations on memory cells 406 coupled to selected wordline(s) 418 . The voltage generator 610 may be configured to be controlled by the control logic unit 612, and generate word line voltages (eg, read voltages, program voltages, pass voltages, local voltages, verify voltages, etc.), bit line voltages to be supplied to the memory array 401, line voltage and source line voltage.

Control logic unit 612 may be coupled to each of the peripheral circuits described above and configured to control the operation of each of the peripheral circuits. Registers 614 may be coupled to control logic unit 612 and include status registers, command registers and address registers for storing status information, command operation codes (OP codes) and command addresses for controlling the operation of each peripheral circuit. Interface 616 may be coupled to control logic unit 612 and act as a control buffer to buffer and relay control commands received from a host (not shown) to control logic unit 612 and to buffer status received from control logic unit 612 information and relay it to the host. Interface 616 may also be coupled to column decoder/bit line driver 606 via data bus 618 and act as a data I/O interface and data buffer to buffer and relay data to or from memory array 401 or buffer data.

For the storage system and memory described above, the Read Window Margin (RWM, Read Window Margin) is an important parameter for correctly reading storage unit data. The definition of RWM can be divided into two types: first, RWM is the sum of the intervals between the threshold voltage distributions corresponding to two adjacent data states of the memory cell, for example, the MLC type memory cell shown in Figure 7 Threshold voltage distributions are described. As shown in FIG. 7 , the first RWM of the MLC memory cell may be a voltage interval between the erased state S1 and the programmed state S2 . Second, RWM can be defined as the voltage interval between the programming verification voltage of the programming state of the memory cell and the read voltage used to distinguish the programming state from its adjacent data state. For example, the RWM contained in Figure 7 is: V The voltage interval between _RD1 and V _FY1 , the voltage interval between V _RD2 and V _FY2 , and the voltage interval between V _RD3 and V _FY3 , among them, V _RD1 , V _RD2 , and V _RD3 are used to distinguish between erase state S1 and programming The reading voltage of state S2, the reading voltage of distinguishing erased state S2 and programming state S3, the reading voltage of distinguishing erased state S3 and programming state S4; V _FY1 , V _FY2 , V _FY3 are the programming The verification voltage, the programming verification voltage of the programming state S3, and the programming verification voltage of the programming state S4. As the data density of a single memory cell can be further increased, the width of the RWM decreases, for example, the threshold voltage distribution of the TLC type memory cell shown in Figure 8 and the threshold voltage of the QLC type memory cell shown in Figure 9 distribution, the RWM shown by the two is narrower than the RWM corresponding to the MLC type memory cell shown in FIG. 7 . When performing a read operation on the memory, if you want to read the data of the storage unit correctly, you need a RWM with sufficient width. However, there are many factors affecting the RWM, as shown in FIG. 10 , which shows three main factors affecting the RWM of the storage unit. Among many factors, there are many studies on the impact of programming accuracy and the coupling between word lines on RWM, but there are relatively few studies on the impact of RTN on RWM and how to reduce the read disturbance caused by RTN.

According to research, the RTN caused by the electron capture and electron loss of the memory cell is one of the main factors for the fluctuation of the threshold voltage of the memory cell during the read operation of the planar NAND flash memory. The fluctuation of the threshold voltage of the memory cell is the cause of the change of RWM, that is, the RTN of the memory cell will affect the RWM, thereby affecting the correct reading of the data stored in the memory cell. Among them, RTN is a kind of noise with non-Gaussian distribution in the inherent noise of electronic devices. It is the disturbance of charge migration caused by the capture and release of charges by defects or traps in electronic devices. Macroscopically, it causes current fluctuations. Therefore, for a memory including a channel structure 505 made of polysilicon, such as 3D NAND flash memory, or 3D charge trap flash memory (CTF, Charge Trap Flash), the channel structure 505 includes polysilicon, whether there is a defect or For the trap, combined with the introduction of the principle of storing data in the memory cell described above, the charge trapping layer of the memory cell needs to capture and release charges, so as to store and erase data. Then, there is RTN in the channel corresponding to the memory cell, It will cause the threshold voltage of the storage unit to fluctuate, thereby affecting the RWM of the memory, and further affecting the correct reading of the storage unit.

In order to solve the above technical problem, referring to FIG. 11 , an embodiment of the present application provides a method for operating a memory. Specifically, the operation method includes:

S1101: Determine a first change amount of a threshold voltage of a storage cell in the memory in a single-level cell SLC erased state.

It should be noted that the structure of the memory described here may include the structures described above in FIGS. 1 to 7 , and may also include other known structures. Basically, the memory includes a string of memory cells, the string of memory cells includes a bit line, a plurality of memory cells, and a source line electrically connected in sequence, wherein each layer of the plurality of memory cells is coupled to the same word line On, a physical storage page (Page) can be formed. For other descriptions about the structure of the memory cell string, reference may be made to the above-mentioned FIGS. 1 to 6 , which will not be repeated here.

Since there are many factors that affect the RWM of the storage unit, in order to exclude the influence of other factors, only the problem of read interference caused by the influence of RTN on the RWM is solved separately. After research, the magnitude of the RTN corresponding to the storage unit contained in the memory can use the storage unit In the SLC erasing state, the threshold voltage change is measured, and the magnitude of RTN is positively correlated with the threshold voltage change of the memory cell in the SLC erasing state, and the threshold voltage change of the memory cell in the SLC erasing state The larger the amount, the larger the magnitude of the RTN corresponding to the storage unit. In addition, the influence of the RTN corresponding to the memory cell on the RWM of the memory cell is also positively correlated with the magnitude of the RTN; The RWM effect corresponding to the cell is greater (the RWM becomes narrower), so that when the read operation is performed, the disturbance corresponding to the memory cell is also greater. That is: the change amount of the threshold voltage of the memory cell in the SLC erased state is used to measure the magnitude of the RTN corresponding to the memory cell.

In some embodiments, for an optional implementation of step S1101, refer to FIG. 12 , and the specific process may include:

S1201: Perform an erasing operation on the storage block where the storage unit is located, so that all the storage units contained in the storage block are erased to the SLC erasing state;

S1202: Perform multiple read operations on the storage unit based on the first read condition;

S1203: Obtain the voltage value of the threshold voltage of the memory cell read each time;

S1204: Determine the first variation based on each voltage value.

It should be noted that the magnitude of the RTN corresponding to the memory cell is measured according to the variation of the threshold voltage of the memory cell in the SLC erased state. Cell is in SLC erased state. Therefore, the first step to obtain the first variation of the threshold voltage of the memory cell in the SLC erased state is to perform an erase operation on the memory block where the memory cell is located, so that all the memory cells contained in the memory block are erased to the SLC erased state.

Afterwards, multiple read operations are continuously performed on the storage unit according to the first read condition. Wherein, the number of times of reading can be designed according to specific conditions, and is not limited here. In an example, the storage unit may be read continuously 10 times according to the first read condition.

Here, the first reading condition may include:

applying a set of read voltages to a selected word line coupled to the memory cell;

applying a corresponding default pass voltage to an unselected word line coupled to other memory cells belonging to the same memory cell string as the memory cell;

Wherein, the set of read voltages includes a set of voltage values between the minimum voltage value and the maximum voltage value of the threshold voltage distribution corresponding to the SLC erasing state.

Here, the set of read voltages includes a set of voltage values between the minimum voltage value and the maximum voltage value of the threshold voltage distribution corresponding to the SLC erasing state. As shown in FIG. 13 , it shows a schematic diagram of the threshold voltage distribution of the SLC type memory cell provided by the embodiment of the present invention. Wherein, the threshold voltage distribution corresponding to the L0 state is the threshold voltage distribution corresponding to the SLC erasing state. The memory cell is erased to the L0 state when multiple read operations are performed consecutively. An example of the set of read voltages is V1 to V7 mentioned in FIG. 13 .

The said performing multiple read operations on the storage unit based on the first read condition may refer to continuously perform multiple rounds of read operations on the storage unit according to the first read condition. In each round of read operation, the read voltage applied to the selected word line coupled to the memory cell is sequentially applied from the minimum value to the maximum value in the set of read voltages, and the memory cell belonging to the same memory cell as the memory cell The corresponding default pass voltage Vpass0 is applied to the unselected word lines coupled to other memory cells in the string, and then the voltage values of the threshold voltages of the plurality of memory cells in this round of read operation are applied. Multiple rounds of reading operations are performed sequentially to obtain multiple voltage values for each round of reading operations. Then the first variation is determined according to each voltage value.

For example, assuming that an example of the set of read voltages is V1 to V7 mentioned in FIG. To V7 is sequentially applied to the selected word line coupled to the memory cell. In this round, during each read operation, the default pass voltage Vpass0 is applied to the unselected word line in the same memory cell string, based on the peripheral circuit The included sense amplifier circuit measures the voltage value of the threshold voltage of each memory cell read.

It should be noted that, when performing a read operation on the memory, the memory cell to be read in a certain memory cell string is the selected memory cell, and the word line coupled with the memory cell is the selected word line; During fetch operation, other memory cells that do not need to be read in the same memory cell string are unselected memory cells, and word lines coupled to the unselected memory cells are unselected word lines.

The default pass voltage Vpass0 may refer to the voltage value provided to the unselected word lines coupled to the unselected memory cells when performing a read operation on the memory, which may be an empirical value or a factory default value

After performing multiple read operations on the storage unit, in some embodiments, for step S1203, may include:

obtaining an average voltage value of threshold voltages of the memory cells based on each of the voltage values;

The first variation is determined based on any one of the voltage values and the average voltage value.

Specifically, the calculation of the first variation can adopt the following formula:

ΔV _th0 = V _th,i - V _th,avg (1)

Wherein, ΔV _th0 is the first variation of the threshold voltage of the memory cell in the SLC erasing state; V _th,i is the measured value of the memory cell during the i-th round of read operation in multiple rounds of read operations. The voltage value of the threshold voltage, wherein, i is any one of multiple rounds of read operations; V _{th, avg} is the average value of the voltage values of the threshold voltages of the memory cells measured by the multiple read operations, That is the average voltage value.

The above calculation formula indicates that the first variation is determined based on any voltage value in each of the voltage values and the average voltage value.

In some other embodiments, for step 1102, refer to FIG. 14 , which shows another optional implementation manner. Specific procedures may include:

S1401: Perform an erasing operation on the storage block where the storage unit is located, so that all the storage units included in the storage block are erased to the SLC erasing state;

S1402: Perform multiple read operations on each memory cell coupled to the selected word line based on the first read condition, and obtain the variation distribution of the threshold voltage of each memory cell; the selected word line is the memory block A word line coupled to the memory cell;

S1403: Determine 3σ of the variation distribution as the first variation.

It should be noted that step S1401 is the same as step S1201 described above, and will not be repeated here. In the actual reading process, the first variation may also be 3σ of the variation of the threshold cell distribution of the memory cells in the SLC erased state. Among them, the way of obtaining 3σ may include but not limited to the following two ways: one way is to execute the steps in the aforementioned Figure 12 for each storage unit in all storage units of the same selected word as the storage unit, and obtain each The amount of change corresponding to the threshold voltage of a memory cell in the SLC erasing state is to form the change amount distribution in the SLC erasing state, and then determine its corresponding 3σ according to this change distribution; Each memory cell in all memory cells of the same memory block executes the aforementioned steps in Figure 12 to obtain the amount of change corresponding to the threshold voltage of each memory cell in the SLC erased state to form the amount of change in the SLC erased state distribution, and then determine its corresponding 3σ according to this change distribution.

In some embodiments, the method further includes: after performing the erasing operation on the storage block, waiting for a first preset time period.

It should be noted that the above-mentioned erasing operation and waiting are for avoiding the influence of background pattern dependence (BPD, Background Pattern Dependency) response and the influence of charge instability of the memory cells included in the memory block just after erasing. Wherein, the first preset duration can be set according to actual conditions. For example, the first preset duration may be 30 minutes.

Based on the foregoing description, a specific and achievable process for evaluating the magnitude of the RTN of the storage unit, as shown in FIG. 15 , may include:

S1501: Perform an erasing operation on the storage block where the storage unit is located, so that all the storage units included in the storage block are erased to the SLC erasing state;

S1502: Wait for 30 minutes after the erasing operation;

S1503: Continuously read the storage block or the storage unit 10 times according to the first reading condition;

S1504: Calculate the variation distribution of the threshold voltage of the storage cells included in the storage block or the variation of the threshold voltage of the storage cells;

S1505: Use the variation as a first variation; or obtain 3σ of the variation distribution, and use the 3σ as the first variation.

It should be noted that, here only an example is used to show the manner of evaluating the magnitude of the RTN corresponding to the storage unit. For the variation of the threshold voltage of the memory cell in step S1504 ; or the calculation of 3σ of the variation distribution has been described in detail above, and will not be repeated here.

S1102: Compare the first variation with a reference threshold.

Here, the reference threshold may be an estimated value of the amplitude of RTN corresponding to the storage unit in the memory that has the least read disturbance caused by RTN. After research, as shown in Figure 16 and Figure 17, for the memory cells in the same memory cell string, from the memory cells close to the source line to the memory cells close to the bit line, the amplitude of the corresponding RTN decreases sequentially, that is to say , the magnitude of the RTN corresponding to the memory cell adjacent to the bit line is the smallest, and the impact on the RWM of the memory cell is the smallest. Therefore, comparing the first change amount of the threshold voltage of the memory cell with the reference threshold, and when the comparison result is that the first change amount and the reference threshold do not satisfy the set relationship, the relationship between the two is adjusted to satisfy the set relationship. relationship, so that the magnitude of the RTN corresponding to the storage unit is reduced, thereby reducing the read disturbance caused by the RTN. It should be noted that the ordinate in FIG. 16 is a probability value, which may refer to the probability value that all memory cells coupled in a word line are at a certain threshold voltage variation, which can be obtained by obtaining The number of memory cells with a change amount is compared with the total number of all memory cells coupled in a word line to obtain. The abscissa in FIG. 16 is the variation of the threshold voltage of the memory cell in the SLC erased state under the first reading condition. Fig. 16 depicts the variation distribution of the threshold voltage of the memory cell on the word line WL0, WL31, WL63 in the SLC erasing state, wherein, the positions of the word line WL0, WL31, WL63 in the memory cell string are sequentially from bottom to top (or , are arranged sequentially from close to the source line to close to the bit line in the memory cell string). The abscissa in FIG. 17 is the word line; the ordinate is the size of 3σ.

Therefore, in some embodiments, the reference threshold is the variation amount of the threshold voltage of the memory cells adjacent to the bit line in the memory cell string in the SLC erased state.

S1103: When the comparison result is that the set relationship between the first variation and the reference threshold is not satisfied, adjust the threshold voltage of the memory cell in the SLC erased state to have a second variation, The set relationship is satisfied between the second change amount and the reference threshold.

In some embodiments, when the comparison result is that the set relationship between the first variation and the reference threshold value is not satisfied, the threshold voltage of the memory cell in the single-layer cell SLC erasing state is adjusted to have a second delta, which may include:

erasing the memory cell to the SLC erased state;

Gradually adjust the first read condition, and perform multiple read operations on the memory cell based on each adjusted first read condition until the threshold voltage of the memory cell in the SLC erased state is adjusted to has a second variation.

It should be noted that, each time the magnitude of the RTN of the memory cell is determined, the memory cell needs to be erased to the SLC erase state, so as to eliminate the influence of other factors on the RWM. Here, the manner of erasing the storage unit to the SLC erasing state is the manner described in the aforementioned step S1201 and step S1401 , which will not be repeated here.

Here, the set relationship may include that an absolute value of a difference between a change amount of the threshold voltage of the memory cell and the reference threshold is less than or equal to a preset threshold. The preset threshold can be set according to the actual situation, and it can be an empirical value. For example, the preset threshold may be a product of a reference threshold and a set percentage, wherein the smaller the set percentage, the greater the probability of correct reading. Wherein, the set percentage can be set but not limited to 10%.

Based on the foregoing description, the process described above is that when the comparison result is that the first variation and the reference threshold do not satisfy the set relationship, then it is necessary to adjust the The amount of change in the threshold voltage, so that the adjusted amount of change in the threshold voltage satisfies the set relationship between the reference thresholds, so that the amplitude of the RTN corresponding to the storage unit is adjusted to the minimum, and the impact on the RWM of the storage unit is minimized , thereby improving the accuracy rate of reading data stored in the storage unit.

It should be noted that another way of saying that the adjusted second variation of the storage unit satisfies the set relationship with the reference threshold may be that the second variation is approximately equal to the reference threshold, that is to say When the absolute value of the difference between the second variation and the reference threshold is less than or equal to the preset threshold, it may be considered that the second variation is equal to the reference threshold.

In some embodiments, the stepwise adjustment of the first reading condition may include:

A set of read voltages applied to a selected word line coupled to the memory cell remains unchanged;

The pass voltage applied to the unselected word lines coupled to other memory cells belonging to the same memory cell string as the memory cell is gradually increased on the basis of the default pass voltage according to a set offset.

It should be noted that, after research, the magnitude of the RTN corresponding to the memory cell decreases with the increase of the pass voltage on the unselected word line in the same memory cell string. Therefore, between the first variation and the When the reference threshold value does not meet the set relationship, the first read condition is gradually adjusted, and the change amount of the threshold voltage of the memory cell is obtained according to the adjusted first read condition, until the obtained second change amount and the reference threshold value meet the set The fixed relationship, wherein, the method of gradually adjusting the first read condition: the read voltage applied to the selected word line remains unchanged, and the pass voltage applied to the unselected word line in the same memory cell string is based on the default pass voltage. Set the offset to increase step by step. The set offset may be a default offset provided by the system.

For example, assume that a total of 3 adjustments are required so that the threshold voltage of the memory cell in the SLC erased state reaches the second variation; the set offset is P; and the read voltage is the aforementioned V1 to V7. Based on this, the first reading condition is gradually adjusted, that is, the first reading condition is adjusted for the first time, and the obtained reading condition is: the reading voltage is the aforementioned V1 to V7, and the pass voltage is Vpass0+P; the second time Adjust the first reading condition, and the obtained reading condition is: the reading voltage is the aforementioned V1 to V7, and the pass voltage is Vpass0+2P; adjust the first reading condition for the third time, and the obtained reading condition is: read The voltages are the aforementioned V1 to V7, and the pass voltage is Vpass0+3P.

It should be noted that the values of Vpass0 required by unselected word lines in different positions in the same memory cell string are different, that is, in the application, the unselected word lines in different positions in the same memory cell string The magnitude of the line-applied default pass voltage Vpass0 can be different. Correspondingly, the setting offsets corresponding to the word lines at different positions may also be different.

For example, assuming that the word lines of the storage cell string of the memory are sequentially from bottom to top: WL0, WL1, ..., WLn, ...; when reading the storage cell coupled to the word line WLn in the storage cell string , and the default pass voltages Vpass0 applied to the other word lines are shown in Table 1, which are: different voltage values Vpass0-1, Vpass0-2, and Vpass0-3. Based on this, the voltage value of the default pass voltage Vpass0 applied to the unselected word lines at different positions is different, and the set offsets corresponding to the unselected word lines at different positions may be the same or different, depending on the memory internal It depends on what the operating system of the voltage generator in the peripheral circuit can provide. For example, when all are different, the set offset corresponding to Vpass0-1 may be 50 millivolts (mV); the set offset corresponding to Vpass0-2 The fixed offset may be 20mV; the corresponding set offset of Vpass0-3 may be 10mV. For another example, when they are all the same, the set offsets corresponding to Vpass0-1, Vpass0-2, and Vpass0-3 may be any voltage increment step size that the system can provide, such as any one of 50mV, 20mV, and 10mV. The set offsets corresponding to the unselected word lines at different positions may also be partly the same and partly different, and may be in any possible combination, which will not be repeated here.

Table 1

word line WL Default pass voltage Vpass0 voltage value WLn&above Vpass0-2 WLn+3 Vpass0-2 WLn+2 Vpass0-2 WLn+1 Vpass0-1 wxya Vread WLn-1 Vpass0-1 WLn-2 Vpass0-3 WLn-3 Vpass0-3 WLn-4&WL16 Vpass0-3 WL2-WL15 Vpass0-3 WL0-WL1 Vpass0-3

The above adjustment process is, on the basis of the default pass voltage, gradually increase the pass voltage provided to the unselected memory cells that belong to the same memory cell string as the memory cell (that is, increase the pass voltage applied to the unselected memory cells that belong to the same memory cell string) Select the pass voltage on the unselected word line coupled to the memory cell), and determine the magnitude of the RTN corresponding to the memory cell after each increased pass voltage (that is, the threshold voltage of the memory cell in the SLC erase state amount of change), until the amount of change in the threshold voltage of the memory cell in the SLC erased state satisfies the set relationship with the reference threshold under a certain increased pass voltage, at this time the selected memory cell The variation of the threshold voltage in the SLC erasing state is the aforementioned second variation, so far the adjustment of the amplitude of the RTN corresponding to the memory cell is completed. It should be noted that after each time the pass voltage on the unselected word line is increased, the memory cell is read multiple times or the word belonging to the same word as the memory cell is still read according to the read voltage in the first read condition. All the memory cells of the line are read multiple times or all the memory cells belonging to the same memory block as the memory cells are read multiple times to obtain the second change amount of the threshold voltage of the memory cells in the SLC erased state.

In some embodiments, the method also includes:

When the threshold voltage of the memory cell in the SLC erasing state is adjusted to have a second variation, record the total offset of the pass voltage applied to the unselected word line relative to the default pass voltage.

Here, the total offset is the previously obtained variation of the threshold voltage of the memory cell in the SLC erase state and the reference threshold satisfy the set relationship, and belong to the same memory cell as the memory cell The offset of the pass voltage applied by unselected word lines coupled to other memory cells in the string relative to the default pass voltage. In other words, according to the operation method provided by the embodiment of the present application, the total offset of the pass voltage corresponding to the default pass voltage relative to the default pass voltage can be obtained when the amplitude of the RTN corresponding to the storage cell is minimized, and this value is used when performing a subsequent read operation. The total electrical offset plus the default pass voltage results in a pass voltage provided to the memory cell at which read disturb is minimized.

In some embodiments, when the comparison result is that the set relationship between the first change amount and the reference threshold is satisfied, feedback indicating information or wait for a second preset time length, so as to end the operation of the storage unit. adjustment of the threshold voltage during the SLC erase state.

It should be noted that the second preset time can be customized manually, which is not limited in this application.

In order to understand the adjustment process of the amplitude of the above RTN, please refer to FIG. 18 . The amplitude adjustment manner of the RTN of the storage unit specifically includes:

S1801: Based on the first reading condition, determine the variation of the threshold voltage of the memory cell adjacent to the bit line belonging to the same memory cell string as the memory cell in the SLC erased state, and obtain a reference threshold;

S1802: Determine, based on the first read condition, a first amount of change in threshold voltage of a storage cell in the memory when it is in an SLC erase state;

S1803: Compare the first variation with the reference threshold;

S1804: When the comparison result is that the first variation and the reference threshold satisfy the set relationship, feed back indication information or wait for a second preset time period to end the memory unit in the SLC erasing state When the threshold voltage is adjusted, the process ends;

S1805: When the comparison result is that the first change amount and the reference threshold do not satisfy the set relationship, erase the storage unit to the SLC erase state; gradually adjust the first read condition, based on Each adjusted first read condition executes multiple read operations on the memory cell until the threshold voltage of the memory cell in the SLC erase state is adjusted to have a second variation, the first The set relationship is satisfied between the second change amount and the reference threshold, and the process ends.

It should be noted that, in step S1805, the first reading condition is gradually adjusted, and steps 1802 to 1803 are re-executed until the second change amount of the storage unit and the reference threshold satisfy a set relationship, and the process ends. The end process mentioned here is the end process when the RTN adjustment of a certain storage unit on the storage unit string is completed. The adjustment of the RTN amplitude of any storage unit in the same storage unit string can be adjusted according to step 1801 to step S1805.

It should be noted that the aforementioned detailed descriptions of the reference threshold, the first change amount, and the second change amount in the process will not be repeated here.

In the actual application process, the magnitude of the RTN corresponding to the storage unit increases with the increase of the erasing/programming times of the memory, therefore, the adjustment of the magnitude of the RTN of the storage unit needs to be During the erase/program lifetime of the cell, multiple adjustments are made to reduce disturbance to subsequent reads.

Therefore, in some embodiments, the method may also include:

Determining the number of programming/erasing times that have been performed on the memory block where the memory cell is located;

judging whether the number of times of programming/erasing reaches a preset number of times;

When the number of programming/erasing times reaches the preset number of times, re-determine a third variation of the threshold voltage of the memory cell in the SLC erase state; and when the third variation is the same as the When the reference threshold does not satisfy the set relationship, adjusting the change amount of the threshold voltage of the memory cell in the SLC erasing state, so that the change amount and the reference threshold meet the set relationship.

It should be noted that what is described here is that when the number of programming/erasing times reaches the preset number of times, the amplitude of the RTN of the storage unit described above is adjusted to obtain The total offset provided by the cell is compensated by the voltage, thereby reducing the read disturbance caused by RTN.

In some embodiments, the preset number of times is determined based on the maximum programming/erasing times of the storage unit and a set evaluation cycle; wherein, the set evaluation cycle is used to reflect that two adjacent adjustments of the storage unit The time interval of the amount of change in the threshold voltage during the SLC erased state.

It should be noted that the maximum number of times of programming/erasing may refer to the maximum number of times that programming/erasing can be performed within the erasing/programming lifetime of the memory cell. The so-called set evaluation period is also artificially designed to reflect the time interval between two adjacent adjustments of the threshold voltage variation of the memory cell in the SLC erased state, in other words, that is, Within the maximum programming/erasing times, how many times programming/erasing is performed is to adjust the magnitude of the RTN of the memory cell. The determination of the preset number of times may include: first dividing the maximum programming/erasing times by the set evaluation cycle to obtain the number of times that RTN needs to be adjusted within the maximum programming/erasing times, and then, setting 0 to the number of times that needs to be adjusted All integers between the times of RTN are multiplied by the set evaluation period in turn to obtain the preset times.

For example, assuming that the maximum number of programming/erasing times is 1000, and the evaluation period is set to 100, then the number of times the RTN needs to be adjusted is 10 times. At this time, the preset times are 0, 100, 200, 300 , 400, 500, 600, 700, 800, 900, 1000.

For the above determination of when to adjust the magnitude of the RTN corresponding to the storage unit, the specific process can be as shown in Figure 19, and the process includes:

S1901: Determine that the maximum programming/erasing times of the memory cell is M;

S1902: Determine that the current programming/erasing times of the storage unit is Z;

S1903: Determine whether the programming/erasing times reach a preset number of times;

It should be noted that, for how to judge whether the number of times of programming/erasing in S1903 reaches the preset number of times, the following formula can be used to judge: whether Z is equal to n*M/N, where N is the maximum number of times of programming/erasing M The quotient with the set evaluation period, for example, N=10; n is any integer from 0 to 10.

S1904: When the number of programming/erasing times reaches a preset number of times, redetermine a third variation of the threshold voltage of the memory cell in the SLC erase state; and when the third variation is the same as the When the reference threshold does not satisfy the set relationship, adjusting the amount of change in the threshold voltage of the memory cell in the SLC erased state, so that the change amount and the reference threshold meet the set relationship;

S1905: When the programming/erasing times do not reach the preset times, do not adjust the change amount of the threshold voltage of the memory cell in the SLC erasing state, and end the process.

In some embodiments, the method further includes: when the current programming/erasing times is zero, directly determining the third threshold voltage of the memory cell in the SLC erasing state based on the first reading condition amount of change.

In some embodiments, the method may also include:

When the current number of times of programming/erasing is not zero and reaches the preset number of times, obtain the recorded total offset; the total offset is the previously obtained memory cell in the SLC erase state When the amount of variation of the threshold voltage and the reference threshold meet the set relationship, the pass voltage applied by the unselected word line coupled to other memory cells belonging to the same memory cell string as the memory cell is relative to the default pass voltage voltage offset;

obtaining a second read condition based on the total offset and the first read condition;

A third amount of change in the threshold voltage of the memory cell in the SLC erased state is determined based on the second read condition.

It should be noted that what is described here is that when the preset number of times is 0, it is the first time that the RTN corresponding to the storage unit is adjusted, and the total offset of the passing voltage has not been recorded before. Therefore, the read condition for obtaining the third variation of the threshold voltage of the memory cell in the SLC erased state is the first read condition. When the preset number of times is not 0, there is already a recorded total offset, therefore, the read condition for obtaining the third variation of the threshold voltage of the memory cell in the SLC erase state is the second read condition. The second read condition is determined for the recorded total offset and the first read condition, ie the default pass voltage in the first read condition plus the total offset.

Based on the aforementioned operation method, as shown in Figure 20, the embodiment of the present application also provides a reading method, which may include:

S2001: When performing a read operation on a memory cell of the memory, provide a read voltage to a selected word line coupled to the memory cell;

S2002: Provide a pass voltage to an unselected word line coupled to other memory cells in the same memory cell string as the memory cell; wherein the pass voltage is determined based on a recorded total offset and a default pass voltage.

It should be noted that, as described above, when performing a read operation on the memory, for the same memory cell string, the pass voltage required by the unselected memory cells can be determined by the above-described operation method. How to obtain the foregoing has been clearly described, and will not be repeated here.

The operation method of the memory provided by the embodiment of the present application compares the RTN of the storage unit with a reference threshold, and when the comparison result does not satisfy the set relationship, adjusts the comparison result with the reference threshold to satisfy the set relationship, thereby Reduce read disturbance caused by RTN. Generally speaking, the operation method provided by the embodiment of the present application is to adjust the magnitude of the RTN of the memory cell (the variation of the threshold voltage in the SLC erased state of the memory cell represents the magnitude of the RTN) to a known minimum magnitude (reference threshold , for example, the minimum amplitude may be the amplitude of the RTN corresponding to the memory cell adjacent to the bit line), so as to reduce the read disturbance caused by the RTN, so that the data stored in the memory cell can be correctly read.

In order to understand the operation method and reading method provided by the embodiment of the present application, a 3DCTF including 64 layers of word lines is taken as an example for description below. See Figures 21 to 23 for details.

FIG. 21 shows a schematic flowchart of the CTF including 64 word lines provided by the embodiment of the present application using RTN to obtain the total offset of the pass voltage of the unstored cells corresponding to each word line relative to the default pass voltage. Specifically, in step S2101, make the memory cell coupled with the word line WL63 be in the SLC erasing state, and read a certain memory block of the 3D CTF multiple times continuously based on the first reading condition; wherein, the first The read condition comprises: the pass voltage Vusel provided to the unselected word line in the same memory cell string is the default pass voltage Vpass0, and the read voltage Vsel provided to the selected word line in the same memory cell string is Vread; in step S2102, for and The memory cell coupled with the word line WL63 calculates the amount of change in the threshold voltage of the SLC erasing state to obtain a reference threshold; specifically includes: making the memory cell coupled with the word line WL63 in the SLC erasing state; The coupled memory cells are selected memory cells, and the rest are unselected memory cells; after reading multiple times according to the above-mentioned first read condition, obtain the variation distribution of the threshold voltage of the memory cells coupled with the word line WL63; based on the Variation distribution obtains 3σ corresponding to the variation distribution of the threshold voltage of the memory cell coupled to word line WL63, denoted as σ ₆₃ , and this σ ₆₃ is used as a reference threshold; The 3σ corresponding to the variation distribution of the threshold voltage of the memory cell coupled to WL62 in the SLC erased state is denoted as σ ₀ -σ ₆₂ , each of which can be referred to as a first variation. The specific calculation process is as described in step S2102, and will not be repeated here. In step S2104, respectively compare the 3σ corresponding to the word line WL0 to the word line WL62 with the reference threshold _σ63 , if the σi corresponding to the memory cell coupled to a certain word line is equal to the reference threshold _{σ63 (} σ ₆₃ is approximately equal to σ _i , that is, the two described above satisfy the setting relationship), then the amplitude of the RTN corresponding to the memory cell coupled to the word line does not need to be adjusted, and the memory cell coupled to the word line is currently selected for storage unit, the pass voltage provided by other unselected memory cells can be the default pass voltage Vpass0; if the σ _i of the memory cell coupled to a word line is greater than the reference threshold σ ₆₃ , then the word line The magnitude of the RTN corresponding to the memory cell of , needs to be adjusted by increasing the pass voltage of other unselected word lines until σ _i is equal to σ 63 (σ ₆₃ is approximately equal to σ _i , that is, the two described above satisfy the set relationship). It should be noted that the adjustment may not be completed at one time, and multiple times are required to make σ _i equal to σ63. Here, through step S2105 and step S2106, each RTN adjustment is realized, wherein, step S2105 is to judge whether the passing voltage has increased to the maximum value (the passing voltage cannot be infinitely increased, and infinite increase may introduce other reading Interference problem); in step S2106, a way to obtain a new reading condition, wherein, ΔV is the set offset increased by the voltage when RTN is adjusted each time. In step S2107, after σ _i is equal to σ63, the total offset ΔVpass (i) of the pass voltage applied by the word line relative to the default pass voltage is obtained by the formula ΔVpass(i)=Vpass(i)-Vpass; In S2108, the ΔVpass(i) is sent to the memory controller or the micro-controller of the control logic unit for storage, so as to be used in subsequent read operations.

It should be noted that Vusel represents the pass voltage applied on the unselected word lines; Vsel represents the read voltage applied on the selected word lines. The evaluation of the RTN corresponding to the storage unit in steps S2102 and S2103 is performed in the manner described above, and will not be repeated here.

FIG. 22 shows a schematic flowchart of judging whether the current programming/erasing times need to be adjusted by RTN provided by the embodiment of the present application. As shown in Figure 22, in step S2201, determine the maximum programming/erasing times of the memory, denoted as M; in step S2202, perform programming/erasing to a certain storage block of the memory; in step S2203 , determine the current programming/erasing times of the memory block in the memory, denoted as Z; in step S2204, use the judgment statement if Z=n*M/N? Judging whether the preset number of times has been reached; if the preset number of times has been reached, execute step S2205, and execute the adjustment process in FIG. 21; if the preset number of times has not been reached, end the process.

When the current program/erase count reaches the preset count, there are two situations for adjusting the RTN, as shown in FIG. 23 .

In step S2301, it is judged whether the current programming/erasing count is zero, and if it is zero, execute step S2302, and directly adjust the amplitude of RTN corresponding to the memory cells coupled to each word line according to the flow shown in FIG. 21 , To obtain the total offset of the passing voltage of other unselected word lines relative to the default passing voltage when each word line corresponds to the selected word line, for subsequent reading use; when it is not zero, perform step S2303 to obtain the previous One RTN adjusts the total offset corresponding to each word line; after obtaining the recorded total offset ΔVpass(i), execute step S2304 to obtain a new read condition; then execute step S2305 to execute according to the new read condition The process shown in Figure 21 adjusts the magnitude of RTN corresponding to the memory cells coupled to each word line to obtain the new total offset of the pass voltage relative to the default pass voltage when each word line is an unselected word line , for use in subsequent read operations.

The operation method provided by the embodiment of the present application essentially uses the amplitude of the RTN of the memory cell to adjust to obtain the pass voltage provided by the subsequent read operation for the unselected word line. In this way, the read operation on the memory cell is reduced. The read disturbance caused by its corresponding RTN. This operation method can improve the magnitude of RTN of the memory cells at different positions, thereby effectively improving the influence of the RWM consistency caused by the position difference of the word line. As a result, the RTN consistency of memory cells coupled with word lines on the same memory cell string can be effectively improved; the impact of word line positions on RTN and read window margin can be effectively reduced; it can be performed based on the usage of the memory Calibration to compensate for RTN amplitude; no additional process improvements required, etc.

An embodiment of the present application also provides a memory, including: a storage array for storing data; and a peripheral circuit coupled to the storage array and used to control the storage array; wherein the peripheral circuit is configured to: Realize the operation method described in any one of the foregoing.

In some embodiments, the peripheral circuit includes: a register for storing the recorded total offset.

It should be noted that the memory and the aforementioned method of erasing the memory belong to the same inventive concept, and the terms appearing in the memory are explained in detail in the aforementioned programming method, and they are also applicable here, and will not be repeated one by one. It should be understood that only the structure of the memory most relevant to the technology of the present application is described here, and other structures may be the structures shown in FIGS. 1 to 6 , or other memory structures.

Based on the same inventive concept, an embodiment of the present application further provides a storage system, the storage system includes: one or more aforementioned memories;

And a memory controller coupled to the memory; the memory controller is configured to: send various operation commands to the memory. The various operation commands mentioned above, for example, read, program, erase and other commands.

In some embodiments, the storage system is a solid state disk SSD or a memory card.

It should be noted that the storage system includes the aforementioned memory, therefore, the two have the same technical features, and the nouns appearing in the storage system are explained in detail in the aforementioned memory, and they are also applicable here, and will not be repeated one by one. . It should be understood that only the structure of the storage system most relevant to the technology of the present application is described here, and other structures may be the structures shown in FIGS. 1 to 6 above, or other storage system structures.

The above descriptions are only preferred embodiments of the present application, and are not intended to limit the protection scope of the present application.

Claims (22)

1. A method of operating a memory, comprising:

determining a first amount of change in threshold voltage of memory cells in the memory in a single cell SLC erased state;

comparing the first variation with a reference threshold;

and when the comparison result shows that the first variation and the reference threshold value do not satisfy a set relationship, adjusting the threshold voltage of the memory unit in the SLC erasing state to have a second variation, so that the second variation and the reference threshold value satisfy the set relationship.

2. The method of claim 1, wherein determining a first amount of change in threshold voltage of memory cells in the memory in a single-level-cell (SLC) erased state comprises:

erasing the memory block where the memory unit is located, so that the memory units contained in the memory block are all erased to the SLC erasing state;

performing a plurality of read operations on the memory cell based on a first read condition;

obtaining the voltage value of the threshold voltage of the memory cell read each time;

determining the first variation amount based on each of the voltage values.

3. The method of claim 1, wherein determining a first amount of change in threshold voltage of memory cells in the memory in a single-level-cell (SLC) erased state comprises:

erasing the memory block where the memory unit is located, so that the memory units contained in the memory block are all erased to the SLC erasing state;

performing a plurality of times of reading operations on each memory cell coupled to a selected word line based on a first reading condition, and obtaining variation distribution of threshold voltages of the memory cells; the selected word line is a word line in the memory block coupled to the memory cell;

determining 3 σ of the variation distribution as the first variation.

4. The operating method of claim 2, wherein the first read condition comprises:

applying a set of read voltages to a selected word line coupled to the memory cells;

applying respective default pass voltages to unselected word lines coupled to other memory cells of the same memory cell string as the memory cell;

wherein the set of read voltages includes a set of voltage values between a minimum voltage value and a maximum voltage value of a threshold voltage distribution corresponding to the SLC erased state.

5. The method of claim 2, wherein said determining the first amount of change based on each voltage value comprises:

obtaining an average voltage value of the threshold voltage of the memory cell based on each voltage value;

determining the first variation amount based on any one of the voltage values and the average voltage value.

6. The operating method according to claim 2 or 3, characterized in that the method further comprises: and waiting for a first preset time after the erasing operation is executed on the storage block.

7. The method of claim 1, wherein the reference threshold is a variation of a threshold voltage of a memory cell adjacent to a bit line in the memory cell string in the SLC erased state.

8. The method of claim 1, wherein the adjusting the threshold voltage of the memory cell in the SLC erased state to have a second variation when the comparison result is that the first variation and the reference threshold do not satisfy a predetermined relationship comprises:

erasing the memory cell to the SLC erased state;

gradually adjusting the first reading condition, and performing a plurality of reading operations on the memory cell based on each adjusted first reading condition until the threshold voltage of the memory cell in the SLC erasing state is adjusted to have a second variation.

9. The operating method of claim 8, wherein the step-wise adjusting the first reading condition comprises:

a set of read voltages applied to a selected word line coupled to the memory cells remain unchanged;

the pass voltage applied to unselected word lines coupled to other memory cells belonging to the same memory cell string as the memory cell is increased stepwise by a set offset amount based on the default pass voltage.

10. The method of operation of claim 9, further comprising:

recording a total offset of a pass voltage applied to the unselected word lines with respect to a default pass voltage when the threshold voltage of the memory cell in the SLC erased state is adjusted to have a second variation.

11. The operating method according to claim 1, wherein the setting relationship includes that an absolute value of a difference between a variation of the threshold voltage of the memory cell and the reference threshold is less than or equal to a preset threshold.

12. The method of operation of claim 1, further comprising:

determining the programming/erasing times of the memory block where the memory unit is located;

judging whether the programming/erasing times reach preset times or not;

re-determining a third variation of the threshold voltage of the memory cell in the SLC erased state when the program/erase count reaches the preset count; and when the third variation and the reference threshold do not satisfy the set relationship, adjusting the variation of the threshold voltage of the storage unit in the SLC erase state to make the variation and the reference threshold satisfy the set relationship.

13. The operating method of claim 12, wherein the preset number is determined based on a maximum program/erase number of the memory cell and a set evaluation period; wherein the set evaluation period is used for reflecting a time interval of two adjacent times of adjusting the variation of the threshold voltage of the memory cell in the SLC erase state.

14. The method of operation of claim 12, further comprising:

when the current program/erase count is zero, directly determining a third amount of change in threshold voltage of the memory cell in the SLC erased state based on the first read condition.

15. The method of operation of claim 12, further comprising:

when the current programming/erasing times are not zero and reach the preset times, acquiring the recorded total offset; the total offset is an offset of pass voltages applied by unselected word lines coupled to other memory cells in the same memory cell string relative to a default pass voltage when the previously obtained variation of the threshold voltage of the memory cell in the SLC erase state and the reference threshold satisfy the set relationship;

obtaining a second read condition based on the total offset and the first read condition;

determining a third amount of change in threshold voltage of the memory cell in the SLC erased state based on the second read condition.

16. The method of claim 1, wherein the threshold voltage of the memory cell in the single-level cell SLC erased state varies by an amount that is a measure of the magnitude of the Random Telegram Noise (RTN) associated with the memory cell.

17. The method of operation of claim 1, further comprising:

and when the comparison result shows that the first variation and the reference threshold satisfy the set relationship, feeding back indication information or waiting for a second preset time to finish the adjustment of the threshold voltage of the memory unit in the SLC erasing state.

18. A method for reading a memory, comprising:

when a read operation is performed on a memory cell of the memory, providing a read voltage to a selected word line to which the memory cell is coupled;

providing a pass voltage to unselected word lines coupled to other memory cells in the same memory cell string as the memory cell;

wherein the pass voltage is determined based on the recorded total offset and a default pass voltage.

19. A memory, comprising: a storage array for storing data; and peripheral circuitry coupled to and for controlling the memory array; wherein the peripheral circuitry is configured to: implementing the operating method of any one of claims 1 to 17.

20. The memory of claim 19, wherein the peripheral circuitry comprises: a register for storing the total offset of the record; the total offset amount is an offset amount of a pass voltage applied by an unselected word line coupled to another memory cell in the same memory cell string with respect to a default pass voltage when the previously obtained variation amount of the threshold voltage of the memory cell in the SLC erase state and the reference threshold satisfy the setting relationship.

21. A storage system, comprising: one or more memories as claimed in any one of claims 19 to 20;

and a memory controller coupled to the memory; the memory controller to: various operation commands are sent to the memory.

22. The storage system according to claim 21, wherein the storage system is a Solid State Disk (SSD) or a memory card.

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