CN115549610A - DCOC calibration circuit and method of XGS-PON BM-LA - Google Patents

Abstract

The invention provides a low-cost design solution for common mode recovery of XGS-PON OLT BM-LA. Among them, the calibration circuit of the DCOC module is composed of a low-pass filter, an amplifier, a comparator, a digital controller and a current differential DAC. Among them, the low-pass filter and the amplifier extract and scale the DC offset respectively; the comparator judges the polarity of the DC offset; the digital controller increases or decreases the output value of the current differential DAC according to the comparison result of the CMP until the DC offset is completed. offset calibration.

Description

DCOC calibration circuit and method of XGS-PON BM-LA

technical field

The invention relates to a DC offset (DCOC) calibration circuit and method for a burst mode limiting amplifier (BM-LA) of a 10G passive optical network receiver (XGS-PON).

Background technique

The patent application of the present invention is a continuation application of CN2022108300371. Based on CN2022108300371, a DC offset calibration circuit and method for a burst mode limiting amplifier of a 10G passive optical network receiver are further proposed.

Statement: In order to avoid duplication of content and save space, the content in CN2022108300371 is regarded as a part of the specification of this application, and part of the content will not be repeated in this application. The inventor/applicant reserves the right to quote all or part of the content in CN2022108300371 into this application document rights in.

The gigabit passive optical network 10G passive optical network (GPON/XGS-PON) OLT receiver in the prior art is mainly composed of an avalanche photodiode (APD), a burst mode transimpedance amplifier (BM-TIA), a burst mode Limiting amplifier (BM-LA) and other modules. In the traditional simple AC (AC) coupling, the common-mode recovery time of the BM-LA receiver and the low-frequency energy loss of the signal are a pair of mutually restrictive indicators; the traditional DC offset calibration (Direct current offset calibration, DCOC) feedback loop, the loop The channel bandwidth is usually at the level of MHz or even KHz, and the corresponding calibration time is usually tens to hundreds of microseconds, while the long-term goal of the XGS-PON protocol for the common mode recovery time of the signal is less than 25.6ns. Therefore, great challenges are posed to high-speed common-mode recovery and high-speed offset calibration in BM-LA design.

The DCOC loop in the prior art requires a clock source up to 6.25GHz, and both the digital circuit and the digital-to-analog converter (DAC) in the DCOC loop need to work at a rate of 6.25GHz. The design is extremely difficult and the process requirements are high. , high cost, not suitable for low-cost XGS-PON receiver design. In the paper Chen K C, Emami A.A 25-gb/s avalanche photodetector-based burst-mode optical receiver with 2.24-ns reconfigurationtime in 28-nm cmos[J].IEEE Journal of Solid-State Circuits,vol.54,pp.1– The high-speed digital DCOC loop in 12,032019 requires advanced technology and high cost.

Contents of the invention

Statement: The patent application for this invention is a continuation application based on CN2022108300371. In order to avoid duplication of content, part of the content will not be repeated in this application. The content in CN2022108300371 is regarded as a part of the specification of this application. Or part of the content is quoted and added to the right of this application document.

The purpose of the present invention is to provide a low-cost design solution for a DC offset (DCOC) calibration circuit suitable for XGS-PON OLT BM-LA. The DCOC calibration circuit proposed by the present invention adopts a single digital control calibration method, and the DC offset calibration is only performed when the chip is powered on or the system is idle. After a single calibration, the current-mode DAC is locked, and at the same time, other circuits in the calibration loop are closed to reduce power consumption of the chip.

The concrete technical scheme that realizes the object of the invention is:

A DC Offset Calibration (DCOC) Feedback Loop for a Burst Mode Limiting Amplifier (BM-LA) of a 10G Passive Optical Network (XG-PON) Receiver, the 10G Passive Optical Network Receiver Burst Mode Limit The fast common-mode recovery circuit of the amplitude amplifier includes three parts: dynamic time constant control unit (RC_CONTROL), burst mode limiting amplifier (BM-LA) and DC offset calibration circuit (DCOC).

The dynamic time constant control unit (RC_CONTROL) has signal input terminals In+, In-, and the signal input terminals In+, In- are respectively connected to the signal input terminals of the burst mode limiting amplifier (BM-LA) through two identical capacitors C, Wherein, the signal input terminal In+ of the dynamic time constant control unit (RC_CONTROL) is connected in parallel with the input common mode voltage terminal after passing through the capacitor C, and the first resistor R and the first controllable switch are connected in parallel, and the dynamic time constant control unit (RC_CONTROL) After the signal input terminal In- passes through the capacitor C, a second resistor R and a second controllable switch are connected in parallel between the input common mode voltage terminal; the control terminals of the first controllable switch and the second controllable switch are connected to the OR gate (OR) circuit, and the two input terminals of the OR gate (OR) circuit are respectively connected to the reset terminal (RST, Reset) and the DOC_ON signal terminal of the DC offset calibration (DCOC) feedback loop.

The DCOC module calibration circuit consists of a low-pass filter, amplifier, comparator, digital controller and current differential DAC. Among them, the low-pass filter and the amplifier extract and scale the DC offset respectively; the comparator judges the polarity of the DC offset; the digital controller increases or decreases the output value of the current differential DAC according to the comparison result of the comparator until the completion DC offset calibration.

The output signal of the dynamic time constant control unit (RC_CONTROL) is transmitted to the burst mode limiting amplifier, and the burst mode limiting amplifier is composed of a first operational amplifier, a second operational amplifier, a third operational amplifier, and a fourth operational amplifier connected in sequence .

The output signal of the burst mode limiting amplifier (BM-LA) is output to the input terminal of the low-pass filter of the DC offset calibration circuit (DCOC), and then output to the amplifier and comparator in turn after low-pass filtering, and the output signal of the comparator is transmitted to to the input of the digital controller.

The input signal of the current differential DAC comes from the output terminal of the first operational amplifier of the Burst Mode Limiting Amplifier (BM-LA). The output signal of the current differential DAC is also transmitted to the digital controller. The digital controller controls the working state of the dynamic time constant control unit (RC_CONTROL) through an OR gate circuit.

The digital controller has a DOC_ON port connected to one of the inputs of the OR gate of the dynamic time constant control unit (RC_CONTROL). Combined with the characteristics of the burst system, DOC_ON is set to 1 when the calibration starts, and the resistors in RC_CONTROL are shorted. This operation will greatly attenuate the input signal of the burst mode limiting amplifier (BM-LA), thereby greatly reducing the interference of the input signal to the DC offset calibration loop, and simplifying the design of the LPF. After the calibration, the digital controller Dig locks the value of the DAC and sets DOC_ON to 0, and closes the DCOC loop except the DAC.

So far, the inventor has elaborated on the working principle, technical solutions and technical effects of the present invention. The content that is not described in detail in this specification belongs to the prior art known to those skilled in the art, and shall not be regarded as not fully disclosing the content of the invention in the specification of the present invention.

In addition, abbreviations that are not specifically described in this application are general abbreviations in the fields of optical communication and electronic science.

Description of drawings

Figure 1: Block diagram of the BM-LA DCOC of the present invention.

Figure 2: The specific circuit diagram of the BM-LA DCOC of the present invention.

Figure 3: Small-signal response of an input signal passed to a DCOC comparator under different conditions.

detailed description

In order to facilitate the understanding of the present invention, the technical solution of the present invention will be specifically introduced below in conjunction with examples.

A DC Offset Calibration (DCOC) Feedback Loop for a 10G Passive Optical Network (XGS-PON) Receiver Burst Mode Limiting Amplifier (BM-LA), the 10G Passive Optical Network Receiver Burst Mode Limiting The fast common-mode recovery circuit of the amplitude amplifier includes three parts: dynamic time constant control unit (RC_CONTROL), burst mode limiting amplifier (BM-LA) and DC offset calibration circuit (DCOC).

The dynamic time constant control unit (RC_CONTROL) has signal input terminals In+, In-, and the signal input terminals In+, In- are respectively connected to the signal input terminals of the burst mode limiting amplifier (BM-LA) through two identical capacitors C, Wherein, the signal input terminal In+ of the dynamic time constant control unit (RC_CONTROL) is connected in parallel with the input common mode voltage terminal after passing through the capacitor C, and the first resistor R and the first controllable switch are connected in parallel, and the dynamic time constant control unit (RC_CONTROL) After the signal input terminal In- passes through the capacitor C, a second resistor R and a second controllable switch are connected in parallel between the input common mode voltage terminal; the control terminals of the first controllable switch and the second controllable switch are connected to the OR gate (OR) circuit, and the two signal input terminals of the OR gate (OR) circuit are respectively connected to the reset terminal (RST, Reset) and the DOC_ON terminal of the DC offset calibration (DCOC) feedback loop. The extreme shortening of the time constant of the RC circuit is realized by a high-level signal (that is, RST=1) of the reset terminal (RST, Reset).

As shown in Figure 1, the DCOC module calibration circuit consists of a low-pass filter LPF, amplifier F, comparator CMP, digital controller DIG and current differential DAC. Among them, the low-pass filter LPF and the amplifier F extract and scale the DC offset respectively; the comparator CMP judges the polarity of the DC offset; the digital controller DIG increases or decreases the current differential DAC according to the comparison result of the comparator CMP Output value until DC offset calibration is complete.

In the present invention, the digital controller DIG specifically selects the digital dichotomy state machine to realize the above functions, and the digital dichotomy state machine belongs to the contents well known to those skilled in the art.

The output signal of the dynamic time constant control unit (RC_CONTROL) is sent to the burst mode limiting amplifier.

The specific DC offset calibration circuit (DCOC) in Figure 1 is shown in Figure 2. The burst mode limiting amplifier is composed of the first operational amplifier 1st, the second operational amplifier 2st, the third operational amplifier 3st, and the fourth operational amplifier connected in sequence. 4st composition. The output signal of the first operational amplifier 1st is also transmitted to the input terminal of the current differential DAC, and the output signal of the current differential DAC is transmitted to the digital controller DIG. The structure of the current differential DAC is a well-known DAC in the art.

The low-pass filter LPF is a low-pass filter of RC structure, and the input terminals IN+ and IN- are connected in series with a resistor R, and a capacitor C is connected in parallel after the resistor R, preferably, R=40KΩ, C=10pF. The input IN+ and IN− signals of the low pass filter LPF come from the output of the fourth operational amplifier 4st of the burst mode limiting amplifier (BM-LA).

The output signal of the burst mode limiting amplifier (BM-LA) is output to the input terminal of the low-pass filter LPF of the DC offset calibration circuit (DCOC), and after low-pass filtering, it is output to the amplifier F, the comparator CMP, and the comparator CMP The output signal is transmitted to the input terminal of the digital controller DIG.

The input terminal signal of the current differential DAC comes from the output terminal of the first operational amplifier 1st of the burst mode limiting amplifier (BM-LA). The output signal of the current differential DAC is also transmitted to the digital controller DIG. The digital controller DIG controls the working state of the dynamic time constant control unit (RC_CONTROL) through an OR gate (OR) circuit.

The main design parameters of the DCOC circuit are shown in Table 1.

Table 1 Main design parameters of DCOC circuit

module parameter or indicator LPF bandwidth f_LPF=200kHz amplifier F＝2, equivalent input offset<2mV Comparators Equivalent input offset <4mV dig Digital Divide by 2 State Machine DAC 6-bit current DAC working frequency 2MHz

Combined with the characteristics of the burst system, DOC_ON is set to 1 when the calibration starts, and the resistors in RC_CONTROL are shorted. This operation will greatly attenuate the input signal of the burst mode limiting amplifier (BM-LA), thereby greatly reducing the interference of the input signal to the DC offset calibration loop, and simplifying the design of the LPF. After the calibration, the digital controller Dig locks the value of the DAC while setting DOC_ON to 0, and closes the DCOC loop circuit except the DAC to reduce the overall circuit power consumption.

In the traditional continuous mode DCOC feedback loop, the loop working speed cannot meet the 25.6ns index requirement. In order to reduce the core cost, the DCOC calibration circuit in the present invention adopts a single digital control calibration method, and the DC offset calibration is only performed when the chip is powered on or the system is idle. After a single calibration, the current-mode DAC is locked, and at the same time, other circuits in the calibration loop are closed to reduce power consumption of the chip.

Figure 3 shows the small-signal response of the input signal transmitted to the DCOC comparator under different conditions. The details are as follows:

1) When DCOC starts, DOC_ON is always 0, that is, DCOC does not participate in time constant control. If the influence of the input signal on the comparator is less than 0dB, the bandwidth of the low-pass filter LPF needs to be as low as 1KHz;

2) When DCOC starts, DOC_ON is set to 1, and this signal controls RC_CONTROL to enter the reset state. At this time, even if the LPF bandwidth is increased to 200 times (200KHz), the input signal still has an attenuation of more than 20dB when it reaches the comparator. Therefore, by adopting collaborative design, the LPF bandwidth index can be relaxed from 1KHz to 200KHz, and the chip area occupied by the low-pass filter LPF circuit is reduced by 200 times, which reduces the chip cost.

The simulation results show the effectiveness of the fast common-mode recovery and offset calibration circuit. It only takes 14ns to restore the input common-mode level to 99.99%, and the DCOC loop is simple and easy to implement.

As mentioned above, in the present invention, due to the working mechanism of the OR gate (OR) circuit, the level of the DOC_ON terminal of the DC offset calibration (DCOC) feedback loop will not affect the dynamic time constant control unit (RC_CONTROL) on the fast common The working mechanism and performance of mode recovery. Similarly, the level of the RST terminal will not affect the working mechanism and performance of the DCOC calibration circuit for DC offset calibration

Table 2 presents a comparison of published BM-LA design parameters. It can be seen from Table 2 that literature [1] uses DC coupling and high-speed digital-to-analog conversion to shorten the common-mode recovery time of burst signals to 2.24ns. The DCOC loop in this scheme requires a 6.25GHz clock source, and Both the digital circuit and the DAC in the DCOC loop need to work at a rate of 6.25 GHz, the circuit structure is complex, the process requirements are high, and the cost is high. In the design scheme proposed in this paper, the common mode recovery time of the burst signal is 14ns, and the DCOC circuit has a simple structure and low cost.

Table 2 Summary of the latest design for BM-LA related common-mode recovery time and offset calibration

The relevant literature involved in Table 2 is listed as follows:

[1]Chen K C,Emami A.A 25-gb/s avalanche photodetector-based burst-mode optical receiver with 2.24-ns reconfiguration time in 28-nm cmos[J].IEEEJournal of Solid-State Circuits,vol.54,pp. 1–12,03 2019.

[2] Coudyzer G, Ossieur P, Bauwelinck J, et al.A 25gbaud pam-4linearburst-mode receiver with analog gain-and offset control in 0.25m sige:cbicmos,IEEE Journal of Solid-State Circuits,vol.55,pp .1–1,04 2020.

[3]Lee S H, Kim J, Le Q, et al. A single chip 2.5-gb/s burst-mode optical receiver with wide dynamic range. IEEE Photonics Technology Letters, vol.23, pp.85–87, 02 2011.

To sum up, the design scheme proposed by the present invention is the simplest scheme of the DCOC circuit structure among the few that meet the 25.6 ns recovery time requirement stipulated in the XGS-PON protocol standard. The solution reduces chip cost and is suitable for XGS-PON receivers.

Explanation: In the present invention, the word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

Words such as "first", "second", "third" and the like used in the description and claims to modify the corresponding elements do not in themselves mean that the elements have any ordinal numbers, nor The use of these ordinal numbers to represent the sequence of an element with respect to another element, or the order of manufacturing methods, is only used to clearly distinguish one element with a certain designation from another element with the same designation.

Claims (10)

1. A DCOC calibration circuit suitable for XGS-PON burst mode limiting amplifier, characterized in that: the fast common mode recovery circuit of the XGS-PON burst mode limiting amplifier comprises: dynamic time constant control unit (RC_CONTROL ), burst mode limiting amplifier (BM-LA) and DC offset (DCOC) calibration circuit; The DCOC calibration circuit (DC offset calibration circuit) consists of a low-pass filter, amplifier, comparator, digital controller and current differential DAC; The output signal of the dynamic time constant control unit (RC_CONTROL) is transmitted to the burst mode limiting amplifier; The output signal of the burst mode limiting amplifier (BM-LA) is output to the input terminal of the low-pass filter of the DC offset calibration circuit (DCOC), and then output to the amplifier and comparator in turn after low-pass filtering, and the output signal of the comparator is transmitted to the input of the digital controller; The output signal of the burst mode limiting amplifier (BM-LA) is output to the input terminal of the low-pass filter of the DC offset (DCOC) calibration circuit, and then output to the amplifier and comparator in turn after low-pass filtering, and the output signal of the comparator is transmitted to the input of the digital controller; The digital controller has a DOC_ON port connected to one of the inputs of the OR gate in the dynamic time constant control unit (RC_CONTROL); Among them, the low-pass filter and the amplifier extract and scale the DC offset respectively; the comparator judges the polarity of the DC offset; the digital controller increases or decreases the output value of the current differential DAC according to the comparison result of the comparator until the completion DC offset calibration. 2. The DCOC calibration circuit as claimed in claim 1, characterized in that: the burst mode limiting amplifier (BM-LA) consists of sequentially connected first operational amplifier, second operational amplifier, third operational amplifier, fourth operational amplifier The amplifier is formed; the output signal of the first operational amplifier is also transmitted to the input terminal of the current differential DAC, and the output signal of the current differential DAC is transmitted to the digital controller DIG. 3. The DCOC calibration circuit according to claim 1, characterized in that: the output signal of the burst mode limiting amplifier (BM-LA) is output to the input terminal of the low-pass filter of the DC offset calibration circuit (DCOC), and passes through the low-pass filter After filtering, it is output to the amplifier and the comparator in turn, and the output signal of the comparator is transmitted to the input terminal of the digital controller. 4. The DCOC calibration circuit as claimed in claim 1, characterized in that: the input signal of the current differential DAC is from the output terminal of the first operational amplifier of the burst mode limiting amplifier (BM-LA); the current differential DAC The output signal is also transmitted to the digital controller; The digital controller controls the working state of the dynamic time constant control unit (RC_CONTROL) through an OR gate circuit. 5. The DCOC calibration circuit according to claim 4, characterized in that: the output signal of the current differential DAC is also transmitted to the digital controller; the digital controller controls the working state of the dynamic time constant control unit (RC_CONTROL) through the OR gate circuit . 6. The DCOC calibration circuit as claimed in claim 1, wherein the low-pass filter LPF is a low-pass filter of RC structure, and the input terminals IN+ and IN- are connected in series with a resistor R, and a capacitor is connected in parallel after the resistor R C, the input terminals IN+ and IN- of the low-pass filter LPF come from the output terminal of the fourth operational amplifier 4st in the burst mode limiting amplifier (BM-LA). 7. The DCOC calibration circuit according to claim 6, characterized in that: R=40KΩ, C=10pF. 8. The DCOC calibration circuit according to claim 1, characterized in that: DOC_ON is set to 1 when the calibration is started, and the resistor in RC_CONTROL is short-circuited, so that the input signal of the burst mode limiting amplifier (BM-LA) is greatly attenuated, Therefore, the interference of the input signal to the DC offset calibration loop is greatly reduced, and the design of the low-pass filter is simplified; after the calibration, the digital controller Dig locks the value of the DAC and sets DOC_ON to 0, and closes the DCOC loop except Circuitry outside the DAC to reduce power consumption of the XGS-PON burst mode limiting amplifier. 9. The DCOC calibration circuit according to claim 1, characterized in that: the dynamic time constant control unit (RC_CONTROL) has signal input terminals In+, In-, and the signal input terminals In+, In- are respectively connected through two identical capacitors C To the signal input terminal of the burst mode limiting amplifier (BM-LA), where the signal input terminal In+ of the dynamic time constant control unit (RC_CONTROL) is connected in parallel with the first resistor after passing through the capacitor C and the input common mode voltage terminal R and the first controllable switch, the signal input terminal In- of the dynamic time constant control unit (RC_CONTROL) passes through the capacitor C and is connected in parallel with the input common mode voltage terminal and the second resistor R and the second controllable switch; the first Both the control terminals of the controllable switch and the second controllable switch are connected to an OR gate (OR) circuit, and the two input terminals of the OR gate (OR) circuit are respectively connected to the reset terminal (RST, Reset) and DC offset calibration (DCOC) The DOC_ON signal terminal of the feedback loop. 10. A DCOC calibration method applicable to XGS-PON burst mode limiting amplifier, the method is realized based on the DCOC calibration circuit according to any one of claims 1-9, characterized in that: The digital controller has a DOC_ON port connected to one of the inputs of the OR gate in the dynamic time constant control unit (RC_CONTROL); When the calibration starts, set DOC_ON to 1, and short the resistor in RC_CONTROL, so that the input signal of the burst mode limiting amplifier (BM-LA) is greatly attenuated, thereby greatly reducing the interference of the input signal to the DC offset calibration loop, simplifying the After the calibration, the digital controller Dig locks the value of DAC and sets DOC_ON to 0, and closes the DCOC loop circuit except DAC to reduce the XGS-PON burst mode limiting amplifier. power consumption.

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