CN115543874A - An adaptation module and memory control system - Google Patents

Abstract

The present application provides an adaptation module and a memory control system, so as to improve the quality of the signal transmitted between the controller and the storage module, and meet the performance requirement of the memory control system at high speed. The memory control system includes: a main board, a memory module and an adapter module, and the main board is provided with a controller and at least two connectors electrically connected to the controller. The storage module is electrically connected to the first connector for storing data; the controller is used to perform signal transmission with the storage module through the first connector, so as to write data to the storage module or read data stored in the storage module; The module is electrically connected to the second connector for reducing reflection of signals transmitted between the controller and the storage module, and the second connector is not connected to the storage module.

Description

An adaptation module and memory control system

technical field

The present application relates to the field of storage technology, in particular to an adaptation module and a memory control system.

Background technique

With the continuous development of storage technologies, double data rate synchronous dynamic random access memory (DDR SDRAM) systems are widely used in computing products or server products, wherein DDR SDRAM is usually abbreviated as DDR.

The DDR system may include multiple independent channels, and each channel may include a circuit board, a control module, and dual inline memory modules (dual inline memory modules, DIMMs). Among them, multiple DDR memory particles are integrated in the DIMM, and the DDR memory particles can be used as a memory medium. The control module is arranged on the circuit board, and the DIMM is pluggably connected to the slot connector on the circuit board. The control module is electrically connected to the slot connector through the link in the circuit board, so as to realize writing data into the DIMM or reading data in the DIMM.

In some application scenarios of the DDR system, in order to improve the compatibility of the DDR system, at least two slot connectors can be provided on the circuit board, and the number of DIMMs on the circuit board can be set according to actual needs. However, when there is no DIMM installed on the socket connector, that is, when the socket connector is empty, the quality of the signal transmitted between the control module and the DIMM will be reduced, resulting in poor performance of the DDR system.

Contents of the invention

The application provides an adapter module and a memory control system, which are used to reduce the influence of vacant slot connectors on signals and improve the performance of the memory control system.

In a first aspect, the present application provides a memory control system. The memory control system includes: a mainboard, a storage module and an adapter module. The mainboard is provided with a controller and at least two connectors electrically connected to the controller. The storage module is electrically connected to the first connector of the at least two connectors for storing data; the controller is used to perform signal transmission with the storage module through the first connector, so as to write data to the storage module or read the stored data. The data stored in the module; the adaptation module is electrically connected to the second connector of the at least two connectors for reducing the reflection of the signal transmitted between the controller and the storage module, wherein the second connector is not connected to the storage module.

In the embodiment of the present application, by setting the adapter module in the memory control system, the adapter module can be electrically connected to the vacant connector during the working process of the memory control system (it should be noted that in the embodiment of the present application, A vacant connector is one that is not connected to a memory module). Since the adapter module can reduce the reflection of the signal, the adapter module connected to the vacant connector can reduce the loss of the signal transmitted between the storage module and the controller, improve the quality of the signal transmitted between the controller and the storage module, and meet the The performance requirements of the memory control system at high speeds make the memory control system compatible with high performance and high capacity, improving product competitiveness.

Optionally, in the above-mentioned memory control system, the above-mentioned at least one connector is provided with a slot on the side away from the main board, the storage module can be pluggably connected to the first connector through the slot, and the adapter module can be connected to the first connector through the slot. Pluggable connection with the second connector. In this way, the user can insert the storage module (or adaptation module) into the slot of the connector according to actual needs, and also can remove the storage module (or adaptation module) from the slot of the connector, so the operation is more flexible.

When designing the structure of the storage module and the adaptation module, a plurality of connection pins can be provided on the edges of the storage module and the adaptation module, and connection terminals corresponding to the positions of the connection pins can be provided in the slots of the connector. Insert one end of the memory module with connection pins into the slot, and make the connection pins in the memory module contact and electrically connect with the connection terminals at the corresponding positions in the slot, so as to realize the electrical connection between the memory module and the connector, thereby realizing The electrical connection between the storage module and the controller enables signal transmission between the storage module and the controller. Insert one end of the adapter module with connection pins into the slot, and electrically connect the connection pins in the adapter module with the connection terminals at the corresponding positions in the slot, so that the connection between the adapter module and the connector can be realized. Electrically connected, so that the adapter module can be connected to the signal transmission link between the controller and the storage module, thus, the adapter module can reduce the reflection of the signal transmitted between the controller and the storage module, and improve the signal quality.

In an implementation manner of the present application, the above-mentioned adapter module may include: a base material, at least one load unit located on the base material, and at least one first connection pin, and the connector includes at least one connection terminal; each load unit The unit is electrically connected to a first connecting pin, and each first connecting pin is electrically connected to a connecting terminal. In specific implementation, the first connection pins can be arranged at the edge of the base material, and one end of the adapter module having the first connection pins is inserted into the slot of the connector, so that the first connection pins are connected to the slot The connecting terminal at the corresponding position in the contact is electrically connected, so that the load unit can be electrically connected with the connector, and furthermore, the load unit can be connected to the signal transmission link between the controller and the storage module.

When no adapter module is connected to the vacant connector, the vacant connector is in an open state, that is, the impedance of the vacant connector is infinite. After connecting the adapter module at the vacant connector, the load unit is electrically connected to the connector, and the impedance at the connector is about the resistance of the load unit, so by setting the load unit, the impedance change at the vacant connector can be reduced To a certain extent, the impedance at the vacant connector tends to be continuous, thereby reducing the signal reflection at the vacant connector. In addition, the load unit can absorb the reflected amount of the signal, thus, the load unit can further reduce the impact of the vacant connector on the quality of the signal transmitted between the controller and the memory module.

In an implementation manner of the present application, the above-mentioned motherboard is also provided with a power terminal; the above-mentioned adapter module may also include: a power module and a second connection pin located on the base material, and the second connection pin passes through the connector It is electrically connected to the power supply terminal on the main board, the input terminal of the power supply module is electrically connected to the second connection pin, and the output terminal of the power supply module is electrically connected to at least one load unit. In specific implementation, the second connection pins can be arranged at the edge of the base material, and one end of the adapter module having the second connection pins is inserted into the slot of the connector, so that the second connection pins are connected to the slot The connecting terminal at the corresponding position in the middle is in contact with the electrical connection, so that the power module can be electrically connected with the power terminal on the main board through the connector. Moreover, the power module can convert the voltage of the power supply terminal to provide the required high level to the load unit.

In an implementation manner of the present application, each load unit may include at least one resistor. When the load unit includes multiple resistors, the resistors in the load unit can be connected in series or in parallel, or the resistors in the load unit can be connected in a combination of series and parallel, which is not limited here.

Further, in the embodiment of the present application, the load unit may further include a capacitor, the first electrode of the capacitor is electrically connected to the resistor, and the second electrode of the capacitor is electrically connected to the first connection pin. The capacitor has the function of blocking DC and passing through AC. When the signal is low frequency, because the capacitor has the function of blocking DC, the adapter module is open at this time, and the resistor in the adapter module does not work, and the signal cannot be pulled up. When the signal is high-frequency, since the capacitor has the function of passing alternating current, the adapter module is a path at this time, and the resistor can pull the signal to a high level.

In an implementation manner of the present application, the above-mentioned first connection pin may serve as a second electrode of a capacitor. Since the second electrode of the capacitor is electrically connected to the first connection pin, using the first connection pin as the second electrode of the capacitor can simplify the structure and manufacturing process of the adaptation module.

Optionally, the first electrode of the capacitor is located on the side of the resistor facing away from the substrate, and the first electrode of the capacitor can be located on the adjacent film layer with the resistor, so that the first electrode of the capacitor can be directly electrically connected to the resistor , making the connection between the two simple, and simplifying the structure of the adapter module. The second electrode of the capacitor is located on the side of the first electrode away from the substrate, and a medium layer is arranged between the first electrode and the second electrode. Such arrangement can make the first connection pin (second electrode) be on the surface layer of the adapter module, which facilitates pluggable connection between the adapter module and the connector. In practical applications, the capacitance value of the capacitor can be adjusted by adjusting the relative area of the first electrode and the second electrode, and adjusting the material and thickness of the dielectric layer between the first electrode and the second electrode. The resistance value of the resistor can be adjusted by changing the material and shape of the resistor.

In an implementation manner of the present application, the above-mentioned adaptation module may further include a connecting wire for connecting the power module and the load unit, and the connecting wire is located on a side of the resistor away from the substrate. The connecting wire and the resistor can be disposed on adjacent film layers, so that the connecting wire and the resistor can be electrically connected through direct contact. In addition, in order to simplify the structure and manufacturing process of the adaptation module, the connecting wire and the first electrode of the capacitor can be set in the same film layer. A via hole may be provided in the dielectric layer, through which the connection wire is led out, and the power module is installed at the via hole, so as to realize the electrical connection between the connection wire and the power module.

In addition, in the memory control system of the embodiment of the present application, an adapter module can be installed at an empty connector and parameters in the storage module can be adjusted to increase the voltage window of the signal and further improve the signal quality.

In a second aspect, the present application also provides an adapter module, which may include: a base material, at least one load unit and at least one first connection pin located on the base material, each load unit is connected to a The first connecting pins are electrically connected, and each first connecting pin is used for electrically connecting with a connecting terminal in a target connector on the motherboard, and the target connector is a connector not connected with a memory module.

In some embodiments of the present application, the above-mentioned adapter module may further include: a power supply module located on the base material and a second connection pin, and the second connection pin is used to communicate with the power supply on the main board through the connector on the main board. The terminals are electrically connected, the input terminal of the power module is electrically connected with the second connection pin, and the output terminal of the power module is electrically connected with at least one load unit.

For the specific implementation of the adaptation module and the technical effects that can be achieved in the embodiments of the present application, refer to the description of the implementation and technical effects of the adaptation module in the above-mentioned memory control system, and repeated descriptions will not be repeated.

Description of drawings

Figure 1 is a schematic structural diagram of a DDR system in a 1DPC/1SPC architecture;

Figure 2 is a schematic structural diagram of a DDR system in a 2DPC/2SPC architecture;

FIG. 3 is a schematic structural diagram of a DDR system in a 1DPC/2SPC architecture;

FIG. 4 is a schematic structural diagram of a memory control system provided by an embodiment of the present application;

Fig. 5 is a schematic diagram of the planar structure of the adapter module in the embodiment of the present application;

FIG. 6 is a schematic diagram of another planar structure of the adapter module in the embodiment of the present application;

FIG. 7 is a schematic diagram of another planar structure of the adapter module in the embodiment of the present application;

Fig. 8 is a schematic cross-sectional view at the dotted line L in Fig. 7;

FIG. 9 is a schematic diagram of an equivalent circuit of a memory control system without an adapter module;

FIG. 10 is a schematic diagram of an equivalent circuit of a memory control system when an adaptation module is provided.

Reference signs:

20-mainboard; 21-storage module; 22-adapter module; 221-substrate; 222-load unit; 223-power module; 224-connection line; 225-medium layer; 23-controller; 25-signal line; U-slot; P1-first connecting pin; P2-second connecting pin; R-resistor; C-capacitor; C1-first electrode; C2-second electrode; T1, T2 - Transistors; odt0, odt1 - on-chip termination.

detailed description

In the related art, each channel of a DDR system may include a circuit board, a control module, and a DIMM. One or more DIMMs can be set in each channel, and one or more slot connectors can also be set on the circuit board in each channel, which can be divided into various architectures according to the number of DIMMs and slot connectors in the channel, Several architectures are illustrated below with reference to the accompanying drawings.

Architecture one:

Fig. 1 is the structure diagram of DDR system in 1DPC/1SPC architecture, as shown in Fig. 1, each channel of DDR system comprises: circuit board 11, control module 12 and DIMM, slot connector 13 on DIMM and circuit board 11 Pluggable connection, the control module 12 is electrically connected to the slot connector 13 through the link 14 in the circuit board 11, so that the control module 12 can write data to the DIMM or read data in the DIMM. In Architecture 1, the channel has only one slot connector 13, which can be expressed as 1 Solt Pre Channel (that is, one slot per channel), or 1SPC for short. This channel has only one DIMM, which can be expressed as 1DIMM Pre Channel (that is, the meaning of single DIMM per channel), or 1DPC for short. Therefore, architecture 1 can be expressed as a 1DPC/1SPC architecture, and the link 14 in architecture 1 is approximately a point-to-point structure. Therefore, the quality of the signal transmitted between the control module 12 and the DIMM is better.

Architecture two:

Fig. 2 is the structure schematic diagram of DDR system in 2DPC/2SPC architecture, as shown in Fig. 2, in architecture two, this channel is provided with two slot connectors, namely slot connector 131 and slot connector 132, can Expressed as 2Solt Pre Channel (that is, double slots per channel), referred to as 2SPC. The channel is provided with two DIMMs, namely DIMM0 and DIMM1, which can be expressed as 2DIMM Pre Channel (that is, double DIMM per channel), or 2DPC for short. Therefore, the second architecture can be expressed as a 2DPC/2SPC architecture. There are two DIMMs in the channel of Architecture 2, so the capacity of the channel in Architecture 2 is larger. However, the link 14 in the second architecture has many load structures, which leads to poor quality of the signal transmitted between the control module 12 and the DIMM.

Architecture three:

FIG. 3 is a schematic structural diagram of a DDR system in a 1DPC/2SPC architecture. As shown in FIG. 3 , in the third architecture, the channel is provided with two slot connectors, namely, slot connector 131 and slot connector 132 . Wherein, the socket connector 131 is provided with a DIMM, and the socket connector 132 is empty, that is to say, only one DIMM is provided in this channel. Therefore, the third architecture can be expressed as a 1DPC/2SPC architecture. In the third architecture, the quality of the signal transmitted between the control module 12 and the DIMM will be reduced due to the vacancy of the slot connector, resulting in poor performance of the DDR system.

Among the above three architectures, only one DIMM can be installed on the circuit board in architecture 1. Architecture 2 and Architecture 3 can share the same circuit board, that is, the circuit boards in Architecture 2 and Architecture 3 can have two or more slot connectors, so that the circuit board can be installed with one DIMM or two Or more than two DIMMs, so that it can be compatible with 1DPC and 2DPC architectures, which makes the compatibility of the circuit board better and can improve the competitiveness of the product. However, in the third architecture, the quality of the signal transmitted between the control module 12 and the DIMM will be degraded due to the vacancy of the slot connector.

In the DDR system, the signal transmission path between the control module 12 and the DIMM can be defined as a link, and the characteristics of the link can be represented by characteristic impedance. If the impedance in the link is continuous, no signal reflection will occur in the link. If there is an impedance discontinuity point (impedance increase or impedance decrease) in the link, the signal will reflect at the impedance discontinuity point, making The signal received by the receiver (such as a control module or DIMM) is attenuated or distorted. The channel in Architecture 3 is equivalent to adding a slot connector on the basis of the channel in Architecture 1. This vacant slot connector forms a link branch and becomes an impedance discontinuity point, so that the signal in the vacant slot connector The reflection occurs at the location of the socket connector. In addition to the position of the vacant slot connector, there may also be impedance discontinuities in other positions of the link, and the signal is reflected between the impedance discontinuities, and finally superimposed on the signal transmitted by the link, so that the receiving end The received signal is attenuated or distorted. Therefore, in the third architecture, the vacant slot connectors will degrade the quality of the signal transmitted between the control module 12 and the DIMM.

For the 4th generation DDR (4th DDR, DDR4) and earlier DDR systems, due to the relatively low data transmission rate, generally up to 3200Mbps, the signal margin is relatively sufficient, and the impact of vacant slot connectors is not great. The channel design can be optimized by improving the performance of the transceiver so that the signal margin is sufficiently large. In this way, although the signal quality in the third architecture will be reduced to a certain extent compared with the first architecture, the speed of the DDR system is not reduced at this time, and the overall performance of the system is not lowered for the entire DDR system.

However, with the continuous development of storage technology, the data transmission rate of the 5th generation DDR (5th DDR, DDR5) system has been planned to be up to 8400Mbps. In this case, the signal margin is greatly reduced, and the impact of socket connector vacancy will become greater and greater. Compared with architecture 1, the signal in architecture 3 will slow down by one or even two gears, which cannot meet the performance requirements of DDR systems.

Based on this, an embodiment of the present application provides an adapter module and a memory control system, which are used to reduce the influence of vacant slot connectors on signals and improve the performance of the memory control system.

In order to make the purpose, technical solution and advantages of the application clearer, the application will be further described in detail below in conjunction with the accompanying drawings. It should be noted that in this specification, similar numerals and letters denote similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be identified in subsequent drawings. for further definition and explanation.

The memory control system provided by the embodiment of the present application can be applied to the third architecture above. Of course, the memory control system can also be applied to other architectures in which the number of DIMMs is less than the number of socket connectors, which is not limited here. The memory control system may be a double rate synchronous dynamic random access (DDR) system, for example, the memory control system may be a 5th generation DDR system. The memory control system provided in the embodiment of the present application can be applied to electronic devices such as servers and computers. Of course, the memory control system can also be applied to other electronic devices, which is not limited here.

Fig. 4 is a schematic structural diagram of the memory control system provided by the embodiment of the present application. As shown in Fig. There is a controller 23 and at least two connectors 24 respectively electrically connected to the controller 23 . Here, the connector 24 electrically connected to the storage module 21 is defined as a first connector, and the connector 24 electrically connected to the adapter module 22 is defined as a second connector. Wherein, the storage module 21 is used to store data; the controller 23 is used to perform signal transmission with the storage module 21 through the first connector 24, so as to write data to the storage module 21, or read data in the storage module 21; The matching module 22 is used to reduce the reflection of the signal transmitted between the controller 23 and the storage module 21, wherein the second connector is a connector not connected to the storage module 21, that is, the vacant connector mentioned above.

In the embodiment of the present application, by setting the adapter module 22 in the memory control system, the adapter module 22 can be electrically connected to the vacant connector 24 during the working process of the memory control system (it should be noted that in the implementation of the present application In this example, the vacant connector 24 refers to the connector 24 not connected to the storage module 21). Because the adaptation module 22 can reduce the reflection of the signal, therefore, the adaptation module 22 connected to the vacant connector 24 can reduce the loss of the signal transmitted between the storage module 21 and the controller 23, and improve the connection between the controller 23 and the storage module 21. The quality of the signals transmitted between them meets the performance requirements of the memory control system at high speeds, making the memory control system compatible with high performance and high capacity, and improving product competitiveness.

Optionally, the main board 20 may be a printed circuit board, of course, the main board 20 may also be other types of circuit boards, which is not limited here. The above storage module 21 may be a dual inline memory module (dual inline memory modules, DIMM). Specifically, a plurality of memory particles may be integrated in the storage module 21, and the memory particles may serve as a storage medium. Alternatively, the above-mentioned storage module 21 may also be another type of storage module, which is not limited here. Different from the storage module 21, there is no storage medium in the adaptation module 22.

Exemplarily, the above-mentioned controller 23 may be electrically connected to the connector 24 through the signal line 25 in the motherboard 20 . When the storage module 21 is electrically connected to the connector 24 , the controller 23 can perform signal transmission with the storage module 21 to implement writing data into the storage module 21 or reading data stored in the storage module 21 . When the adapter module 22 is electrically connected to the connector 24 , the adapter module 22 can be connected to a signal transmission link, thus, the reflection of the signal can be reduced through the adapter module 22 . In practical applications, the adapter module 22 can be electrically connected to the connector 24 closer to the controller 23 , and the storage module 21 can be electrically connected to the connector 24 farther away from the controller 23 . Optionally, the controller 23 can be implemented by a separate chip, or the controller 23 can also be integrated into other chips, for example, the controller 23 can be integrated into a central processing unit (central processing unit, CPU).

In the embodiment of the present application, the above-mentioned memory control system may include at least two connectors 24. In FIG. 4, the memory control system includes two connectors 24 as an example for illustration. More connectors 24, the number of connectors 24 is not limited here. Optionally, the sum of the above-mentioned storage modules 21 and adapter modules 22 may be greater than or equal to the number of connectors 24 . In the embodiment of the present application, each storage module 21 may be electrically connected to a corresponding connector 24 , and each adapter module 22 may be electrically connected to a corresponding connector 24 not connected to a storage module 21 . Certainly, the storage module 21 (or the adaptation module 22 ) and the connector 24 may also have other corresponding relationships, which are not limited here.

In practical applications, the user can set the number of storage modules 21 electrically connected to the connector 24 according to the requirement of the actual memory capacity. When the number of storage modules 21 in the above-mentioned memory control system is less than the number of connectors 24, that is, when the connector 24 is vacant, the adapter module 22 can be electrically connected to the vacant connector 24. The module 22 reduces the reflection of the signal transmitted between the storage module 21 and the controller 23 , thereby reducing the impact of the vacant connector 24 on the signal transmitted between the storage module 21 and the controller 23 . In specific implementation, each vacant connector 24 can be electrically connected to a corresponding adapter module 22 to better reduce signal reflection, or only a part of vacant connectors 24 can be connected to the adapter module 22 electrical connection, which is not limited here. Of course, each connector 24 may also be electrically connected to the storage module 21 if the performance requirements of the memory control system can be met.

Continuing to refer to FIG. 4 , in the above-mentioned memory control system, the above-mentioned connector 24 is provided with a slot U on the side away from the motherboard 20, and the storage module 21 can be pluggably connected to the first connector 24 through the slot U. The module 22 can be pluggably connected to the second connector 24 through the slot U. In this way, the user can insert the storage module 21 (or the adapter module 22) into the slot U of the connector 24 according to actual needs, or insert the storage module 21 (or the adapter module 22) from the slot U of the connector 24 It can be pulled out in the U, and the operation is more flexible.

When designing the structure of the storage module 21 and the adapter module 22, a plurality of connection pins can be arranged on the edges of the storage module 21 and the adapter module 22, and the positions of the connection pins can be arranged in the slot U of the connector 24. corresponding connection terminals. Insert one end of the storage module 21 with connection pins into the slot U, and make the connection pins in the storage module 21 contact and electrically connect with the connection terminals at the corresponding positions in the slot U, so that the storage module 21 and the connector 24 can be realized. The electrical connection between the storage module 21 and the controller 23 is realized, so that the signal transmission between the storage module 21 and the controller 23 is realized. Insert one end of the adapter module 22 with connection pins into the slot U, and electrically connect the connection pins in the adapter module 22 to the corresponding connection terminals in the slot U, so that the adapter module 22 and The electrical connection between the connectors 24, so that the adapter module 22 can be connected to the signal transmission link between the controller 23 and the storage module 21, thus, the adapter module 22 can reduce the distance between the controller 23 and the storage module 21. The reflection of the signal transmitted between them improves the signal quality.

FIG. 5 is a schematic plan view of the planar structure of the adapter module in the embodiment of the present application. As shown in FIGS. A first connection pin P1, the connector 24 includes at least one connection terminal. Each load unit 222 is electrically connected to a corresponding first connection pin P1 , and each first connection pin P1 is electrically connected to a corresponding connection terminal included in the connector 24 . In specific implementation, the first connection pin P1 can be arranged at the edge of the base material 221, and the end of the adapter module 22 with the first connection pin P1 is inserted into the slot of the connector, so that the first connection pin P1 The pin P1 is electrically connected to the connecting terminal at the corresponding position in the slot, so that the load unit 222 can be electrically connected to the connector 24, and then the load unit 222 can be connected to the signal transmission between the controller 24 and the storage module 21. on the link.

When the adapter module 22 is not connected to the vacant connector 24 , the vacant connector 24 is in an open circuit state, that is, the impedance of the vacant connector is infinite. After connecting the adapter module 22 at the vacant connector 24, the load unit 222 is connected to the connector 24, and the impedance at the connector 24 is about the resistance of the load unit 222, so by setting the load unit 222, the vacant load unit 222 can be reduced. The degree of impedance change at the connector 24 makes the impedance at the vacant connector 24 tend to be continuous, thereby reducing the signal reflection at the vacant connector 24 . In addition, the load unit 222 can absorb the reflection of the signal, thus, the load unit 222 can further reduce the impact of the vacant connector 24 on the quality of the signal transmitted between the storage module 21 and the controller 23 .

As shown in Figure 4 and Figure 5, in some embodiments of the present application, the above-mentioned motherboard 11 may also be provided with a power terminal (not shown in the figure); the above-mentioned adapter module 22 may also include a The power supply module 223 and the second connection pin P2, the second connection pin P2 is electrically connected to the power supply terminal on the motherboard through the connector 24, the input terminal of the power supply module 223 is electrically connected to the second connection pin P2, the power supply module 223 The output terminal of is electrically connected with at least one load unit 222 . In specific implementation, the second connection pin P2 can be arranged at the edge of the base material 221, and one end of the adapter module having the second connection pin P2 is inserted into the slot of the connector 24, so that the second connection The pin P2 is electrically connected to the connecting terminal at the corresponding position in the slot, so that the power supply module 223 can be electrically connected to the power terminal on the motherboard 11 through the connector 24 . Moreover, the power supply module 223 can convert the voltage of the power supply terminal to provide the required high level to the load unit 222. For example, the power supply module 223 can convert the level of about 12V or 1.8V at the power supply terminal to about 1.1V. V to get the high level required by the load unit 222. Optionally, the power module 223 may be a DC converter (direct current/direct current, DC/DC). Of course, the power module 223 may also be other types of converters, which is not limited here.

In the embodiment of the present application, by setting the load unit 222 and the power module 223 , the signal can be pulled up at the adaptation module 22 . Make the signal at the adaptation module 22 a high level, so that the storage module 21 on the same link can be at the same high level as the adaptation module 22, so that the voltage window of the signal will not be reduced. Wherein, the voltage window of the signal can be understood as the difference between the high level and the low level of the signal. In practical applications, eye diagrams can be used to characterize the quality of signals in memory control systems. The eye diagram mainly includes two parameters: eye height and eye width. The larger the value of eye height and eye width, the better the quality of the signal. The embodiment of the present application can keep the voltage window of the signal larger, so that the eye height of the signal is larger, that is, the signal quality is better. Moreover, the adaptation module 22 can reduce the reflection of the signal, reduce the crosstalk caused by the reflection to the signal, and optimize the intersymbol interference (inter symbol interference, ISI). In this way, the eye height and eye width can also be made larger, so that the signal quality is better .

As shown in FIG. 5 , in a possible implementation manner, each load unit 222 may include at least one resistor R. When the load unit 222 includes a plurality of resistors R, the resistors R in the load unit 222 can be connected in series or in parallel, or each resistor R in the load unit 222 can be connected in a combination of series and parallel. No limit.

Fig. 6 is another schematic diagram of the planar structure of the adapter module in the embodiment of the present application. As shown in Fig. 4 and Fig. 6, the above-mentioned load unit may further include a capacitor C, the first electrode of the capacitor C is electrically connected to the resistor R, and the capacitor The second electrode of C is electrically connected to the first connection pin P1. Capacitor C has the function of blocking direct current and passing through alternating current. When the signal is low frequency, since capacitor C has the function of blocking direct current, the adapter module 22 is an open circuit at this time, and the resistor R in the adapter module 22 does not work, and the signal cannot be pull up. When the signal is of high frequency, since the capacitor C has the function of passing alternating current, the adapter module 22 is a passway at this time, and the resistor R can pull up the signal to a high level.

In a specific implementation, the above-mentioned adaptation module 22 can be implemented by a printed circuit board, and the appearance of the adaptation module 22 can be consistent with the specifications of the printed circuit board, or the appearance of the adaptation module 22 can also be reduced. Moreover, the number of stacked film layers in the adaptation module 22 may also be less than the number of stacked film layers in the storage module 21 . Of course, the above adaptation module 22 may also adopt other implementation manners, which are not limited here.

Fig. 7 is another schematic plan view of the adapter module in the embodiment of the present application, and Fig. 8 is a schematic cross-sectional view at the dotted line L in Fig. 7. Combining Fig. 7 and Fig. 8, the above-mentioned first connection pin P1 can be used as a capacitor C The second electrode C2. Since the second electrode C2 of the capacitor C is electrically connected to the first connection pin P1, using the first connection pin P1 as the second electrode C2 of the capacitor C can simplify the structure and manufacturing process of the adaptation module.

In order to facilitate the electrical connection with the connector, the first connection pin P1 and the second connection pin P2 in the adaptation module can be arranged on the edge of the adaptation module, and each first connection pin P1 and each second connection pin The connection pins P2 are arranged in a set order. For example, in FIG. 7, each first connection pin P1 and each second connection pin P2 are arranged in a row. The pin P1 and each second connection pin P2 are not limited here. In addition, each first connection pin P1 and each second connection pin P2 can be arranged on the surface layer of the adapter module, so that when the adapter module is inserted into the slot of the connector, the first connection pins can P1 and the second connection pin P2 are easier to contact with corresponding connection terminals.

Optionally, the first electrode C1 of the capacitor C may be located on the side of the resistor R facing away from the substrate 221, and the first electrode C1 of the capacitor C may be located in an adjacent film layer with the resistor R, so that the first electrode of the capacitor C C1 can be directly contacted and electrically connected with the resistor R, so that the connection between the two is simple, and the structure of the adaptation module is simplified. The second electrode C2 of the capacitor C is located on a side of the first electrode C1 facing away from the substrate 221 , and a dielectric layer 225 is disposed between the first electrode C1 and the second electrode C2 . Such setting can make the first connection pin P1 (second electrode C2) be on the surface layer of the adapter module, which facilitates pluggable connection between the adapter module and the connector. In practical applications, the capacitance of the capacitor C can be adjusted by adjusting the relative area of the first electrode C1 and the second electrode C2, and adjusting the material and thickness of the dielectric layer 225 between the first electrode C1 and the second electrode C2. value. Moreover, the resistance value of the resistor R can be adjusted by changing the material and shape of the resistor R.

Continuing to refer to FIG. 7 and FIG. 8 , the adapter module may further include a connection wire 224 for connecting the power module 223 and the load unit 222 , and the connection wire 224 is located on the side of the resistor R away from the substrate 221 . The connecting wire 224 and the resistor R can be disposed on adjacent film layers, so that the connecting wire 224 and the resistor R can be electrically connected through direct contact. In addition, in order to simplify the structure and manufacturing process of the adaptation module, the connection line 224 and the first electrode C1 of the capacitor C can be set in the same film layer. A via hole may be provided in the dielectric layer 225 , through which the connection wire 224 is led out, and the power module 223 is installed at the via hole, so as to realize the electrical connection between the connection wire 224 and the power module 223 .

In specific implementation, the above-mentioned resistor R, the first electrode C1 of the capacitor C, the second electrode C2 of the capacitor C, and the connecting wire 224 can be made of metal copper, or other materials with better conductivity are used. Here No limit.

In the embodiments shown in FIG. 7 and FIG. 8 , integrating the capacitor C and the resistor R inside the adaptation module can reduce the parasitic parameters and improve the performance of the adaptation module. In specific implementation, the connection line 224, the signal line between the resistor R and the capacitor C, the signal line between the capacitor C and the first connection pin P, etc. can also be formed in the adaptation module, and can be formed in the adapter module. The surface is provided with a connection pad for connecting the capacitor C (or resistor R), and then the prepared discrete capacitor C and resistor R are mounted to the corresponding connection pads, so that the internal structure of the adaptation module can be simplified , reducing the process difficulty of the adaptation module. In addition, the above capacitor C, resistor R and power module 223 may also be replaced by other devices with similar functions, which is not limited here.

In the memory control system of the embodiment of the present application, an adapter module may be installed at a vacant connector and parameters in the storage module may be adjusted to increase the voltage window of the signal and further improve the signal quality. A detailed description will be given below in conjunction with the accompanying drawings.

FIG. 9 is a schematic diagram of an equivalent circuit of the memory control system without an adaptation module, and FIG. 10 is a schematic diagram of an equivalent circuit of the memory control system with an adaptation module. As shown in Figure 9, the controller 23 may include two transistors, namely a transistor T1 and a transistor T2, one end of the transistor T1 is electrically connected to the high-level terminal Vddq, the other end is electrically connected to the transistor T2, and the transistor T2 is electrically connected to the low-level terminal . In this way, the controller 23 can output a high level signal by controlling the transistor T1 to be turned on and the transistor T2 to be turned off, and can output a low level signal by controlling the transistor T1 to be turned off and the transistor T2 to be turned on. The controller 23 can perform signal transmission with the storage module 21 through the signal line 25 to realize writing data into the storage module 21 or reading data in the storage module 21 .

The storage module 21 includes multiple memory granules, and the multiple memory granules in the storage module 21 can be divided into multiple memory granule groups according to the number of bits of signals transmitted between the controller 23 and the storage module 21 . Take the storage module 21 including two memory particle groups Rank0 and Rank1 as an example, each memory particle group can be electrically connected to the high-level terminal Vddq through an on-die termination (ODT), and the memory particle group Rank0 is connected to the on-die termination odt0 Connection, the memory particle group Rank1 is connected to the on-chip termination odt1. Each on-chip termination may include n transistors, where n is a positive integer. When the memory module 21 and the controller 23 perform signal transmission, the memory particle group Rank0 and the memory particle group Rank1 can be pulled to high level by turning on the on-chip termination odt0 and the on-chip termination odt1. Optionally, the resistance value of the on-chip termination odt0 (or odt1) can be set to values such as 1, 1/2, 1/3...1/n of Ro, where Ro represents the on-chip termination odt0 (or odt1) The resistance value of a transistor, for example, Ro may be 240 ohms, and the value of n may be 7.

Take the process of the controller 23 writing data into the storage module 21 as an example. When the transistor T1 in the controller 23 is turned on and the transistor T2 is turned off, the controller 23 outputs a high-level signal, and the storage module 21 is pulled up to a high level through the on-chip terminals odt0 and odt1. At this time, the high level of the signal It is: Vhigh=Vddq. When the transistor T1 in the controller 23 is closed and the transistor T2 is opened, the controller 23 outputs a low level signal. At this time, the potential of the storage module 21 is still high level, and the low level of the signal is connected to dot0, The on-chip terminal is connected to odt1 and transistor T2 to divide the voltage, that is, the low level of the signal is:

Among them, R _on represents the equivalent resistance value of transistor T2, R _odt0 represents the equivalent resistance value of on-chip termination odt0, R _odt1 represents the equivalent resistance value of on-chip termination odt1, // represents the parallel connection value of R _odt0 and R _odt1 .

Then the voltage window (i.e. voltage swing) of the signal is:

In practical applications, the impedance of the signal transmission link in the memory control system needs to match the target value, so as to prevent the impedance of the signal transmission link in the memory control system from deviating too much from the target value, which will cause the impedance of the memory control system to fail. matching, degrading the quality of the signal. For example, the target value can be 50 ohms, 60 ohms, etc. During actual implementation, the specific value of the target value can be set according to the specific architecture of the memory control system, which is not limited here.

In the memory control system, the voltage window of the signal is larger, which can make the eye height of the eye diagram larger and improve the quality of the signal. According to the formula of the voltage window of the above signal, it can be known that the voltage window of the signal can be adjusted by adjusting the resistance values of the on-chip terminal odt0 and the on-chip terminal odt1 in the storage module 21, specifically, the on-chip terminal odt0 and the on-chip terminal odt1 The larger the resistance in parallel, the larger the voltage window of the signal. However, in the memory control system shown in FIG. 9, by increasing the resistance value of the parallel connection between the on-chip terminal odt0 and the on-chip terminal odt1, that is, increasing the equivalent resistance of the memory module 21, although the voltage window of the signal can be increased, However, it is easy for the impedance of the memory control system to deviate greatly from the target value, resulting in an impedance mismatch of the memory control system.

For example, the resistance of the on-chip termination odt0 is 120 ohms, the resistance of the on-chip termination odt1 is 60 ohms, the line resistance of the signal transmission link is 15 ohms, and the impedance of the memory control system is about 50 ohms. Increase the resistance value of the on-chip termination odt0 to 240ohms, and increase the resistance value of the on-chip termination odt1 to 80ohms, which can make the impedance of the memory control system about 75ohms. At this time, although the voltage window of the signal is increased, however, The impedance of the memory control system deviates greatly from the target value (taking the target value of 50 ohms as an example), resulting in impedance mismatch of the memory control system.

As shown in Figure 10, by setting the adapter module 22 in the memory control system, in Figure 10, the adapter module 22 includes a resistor R and a capacitor C connected in series as an example, in specific implementation, the adapter module 22 can also save Remove the capacitor C, which is not limited here.

For the low-frequency component of the signal, due to the DC blocking effect of the capacitor C, the resistance R in the adaptation module 22 has no effect, and the resistance value of the on-chip termination odt0 and the on-chip termination odt1 in the storage module 21 can be increased, that is, the The equivalent resistance of the storage module 21 is increased to increase the voltage window of the signal.

For the high-frequency component of the signal, the adaptation module 22 is pulled up to a high level through the resistor R. Since the adaptation module 22 and the storage module 21 are arranged in parallel, the impedance of the memory control system can be reduced. In this way, the adjustment range of the resistance values of the on-chip termination odt0 and the on-chip termination odt1 in the memory module 21 can be enlarged, making it easier for the impedance of the memory control system to match the target value. During specific implementation, the resistor R can be set to an appropriate resistance value, so that the memory control system will not be mismatched due to the change of the equivalent resistance of the memory module 21 . For example, the total resistance of the adapter module 22 is 240 ohms, the resistance of the on-chip terminal odt0 is 240 ohms, and when the resistance of the on-chip terminal odt1 is 80 ohms, the impedance of the memory control system is about 57 ohms. At this time, the memory control system The deviation between the impedance and the target value (still taking the target value of 50ohms as an example) is small. In addition, the adaptation module 22 can also reduce signal reflections at vacant connectors and absorb signal reflections. Therefore, in the embodiment of the present application, by setting the adaptation module 22 and adjusting the resistance value of the on-chip termination in the storage module 21, it is possible to ensure that the quality of the signal transmitted between the storage module 21 and the controller 23 is better. On the basis, the voltage window of the signal is increased to improve the performance of the memory control system.

Based on the same technical idea, the embodiment of the present application also provides an adapter module, which may include: a base material, at least one load unit located on the base material and at least one first connection pin, each load The unit is electrically connected with a first connecting pin, and each first connecting pin is used for electrically connecting with a connecting terminal in a target connector on the motherboard, and the target connector is a connector not connected with a memory module.

In some embodiments of the present application, the above-mentioned adapter module may further include: a power supply module located on the base material and a second connection pin, and the second connection pin is used to communicate with the power supply on the main board through the connector on the main board. The terminals are electrically connected, the input terminal of the power module is electrically connected with the second connection pin, and the output terminal of the power module is electrically connected with at least one load unit.

The specific implementation and achievable technical effects of the adapter module in the embodiment of the present application, as well as the connection relationship with the main board, can be implemented by referring to the above-mentioned methods shown in Figures 4 to 10, and the repetitions will not be repeated.

The above is only a specific implementation of the application, but the scope of protection of the application is not limited thereto. Anyone familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the application. Should be covered within the protection scope of this application. Therefore, the protection scope of the present application should be determined by the protection scope of the claims.

Claims (10)

1. A memory control system, comprising: the system comprises a mainboard, a storage module and an adaptation module;

the mainboard is provided with a controller and at least two connectors electrically connected with the controller;

the storage module is electrically connected with a first connector of the at least two connectors and is used for storing data; the controller is used for carrying out signal transmission with the storage module through the first connector so as to write data into the storage module or read data stored in the storage module;

the adapter module is electrically connected to a second connector of the at least two connectors for reducing reflections of signals transmitted between the controller and the memory module, the second connector not being connected to the memory module.

2. The memory control system of claim 1, wherein the adaptation module comprises: the device comprises a substrate, at least one load unit and at least one first connecting pin, wherein the load unit and the first connecting pin are positioned on the substrate;

the connector includes at least one connection terminal;

each of the load units is electrically connected to one of the first connection pins, and each of the first connection pins is electrically connected to one of the connection terminals.

3. The memory control system of claim 2, wherein a power supply terminal is further provided on the motherboard; the adaptation module further comprises: a power module and a second connection pin located on the substrate;

the second connecting pin is electrically connected with the power supply end on the mainboard through the connector;

the input end of the power supply module is electrically connected with the second connecting pin, and the output end of the power supply module is electrically connected with the at least one load unit.

4. The memory control system of claim 2, wherein each of said load cells comprises at least one resistor;

the at least one resistor is connected in parallel, or the at least one resistor is connected in series.

5. The memory control system of claim 4, wherein the load cell further comprises a capacitor, a first electrode of the capacitor being electrically connected to the resistor, a second electrode of the capacitor being electrically connected to the first connection pin.

6. The memory control system of claim 5, wherein the first electrode of the capacitor is located on a side of the resistor facing away from the substrate, the second electrode of the capacitor is located on a side of the first electrode facing away from the substrate, and a dielectric layer is disposed between the first electrode and the second electrode.

7. The memory control system of claim 5 or 6, wherein the adaptation module further comprises a connection line connecting the power module and the load unit; the connecting line is positioned on one side of the resistor, which faces away from the substrate.

8. The memory control system according to any one of claims 1 to 7, wherein the connector is provided with a slot on a side facing away from the motherboard;

the storage module is connected with the first connector in a pluggable mode through the slot, and the adaptation module is connected with the second connector in a pluggable mode through the slot.

9. An adaptation module, comprising:

a substrate;

at least one load cell and at least one first connection pin located on the substrate; each load unit is electrically connected with one first connecting pin, each first connecting pin is used for being electrically connected with one connecting terminal in a target connector on the mainboard, and the target connector is a connector which is not connected with a storage module.

10. The adaptation module of claim 9, further comprising:

a power module and a second connection pin located over the substrate;

the second connecting pin is used for being electrically connected with a power supply end on the mainboard through a connector on the mainboard;

the input end of the power supply module is electrically connected with the second connecting pin, and the output end of the power supply module is electrically connected with the at least one load unit.

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