CN115543907A - A control method and device based on a PCIe chip in a storage device - Google Patents

Abstract

The embodiment of the present application provides a control method and device based on a PCIe chip in a storage device. The method includes: when any PCIe interface is inserted into the motherboard, an enable signal is sent to the interface card through the motherboard to control the power supply of the motherboard through The first power supply circuit communicates with the interface card, and communicates with the PCIe chip through the second power supply circuit, so that the interface card and the PCIe chip are powered on; when the power-off requirement of the interface card is detected, a shutdown signal is sent to the interface card through any main board , to control the disconnection of the second power supply circuit between the interface card and the PCIe chip, so that the PCIe chip is powered off separately while the interface card remains powered on, realizing the independent power-off repair of the PCIe chip and ensuring the normal operation of other services and reduce operating costs, so as to achieve quality reinforcement on the business path and improve product reliability and self-healing capabilities.

Description

A control method and device based on a PCIe chip in a storage device

technical field

The present application relates to the field of storage devices, in particular to a control method and device based on a PCIe chip in a storage device.

Background technique

Currently, Quad Hosts (Quad baseboard) and Single Card (Single Controller) of the storage controller box have gradually become the trend of high-end storage due to their strong reliability of four bad and three bad. One frame with four controllers means that four controllers (main boards) are installed in one chassis. Four failures and three failures mean that after three of the four controllers fail, the remaining one controller can still provide customers with normal services.

When there is at least one main board in the chassis, the interface card needs to be powered on to provide a service data flow path. And when the interface card fails to be upgraded or due to service requirements, it is necessary to control the power-off of the chip of the interface card to perform repair operations. At this time, all main boards can only be controlled to power off the interface cards, and powering off the entire interface cards will affect other services, and the operation cost is also high.

Contents of the invention

In view of the above problems, embodiments of the present application are proposed to provide a PCIe chip-based control method and device in a storage device that overcome the above problems or at least partially solve the above problems.

In order to solve the above problems, the embodiment of the present application discloses a control method based on a PCIe chip in a storage device. The storage device is provided with an interface card, and the interface card is provided with a PCIe chip and a plurality of PCIe interfaces connected to the PCIe chip. In the case of any PCIe interface, the power supply of the motherboard is connected to the interface card through the first power circuit, and the interface card is connected to the PCIe chip through the second power circuit. The method includes:

When any PCIe interface is inserted into the mainboard, an enable signal is sent to the interface card through the mainboard to control the power supply of the mainboard to communicate with the interface card through the first power supply circuit, and to communicate with the PCIe chip through the second power supply circuit, so that the interface card and Power on the PCIe chip;

When the power-off requirement of the interface card is detected, a shutdown signal is sent to the interface card through any main board to control the disconnection of the second power supply circuit between the interface card and the PCIe chip, so that the PCIe chip remains powered on when the interface card is powered on Power off separately.

Optionally, the main board is provided with a first signal circuit, and sending an enable signal to the interface card through the main board to control the power supply of the main board to communicate with the interface card through the first power circuit includes:

The main board calls the first signal circuit to send an enable signal to the interface card to control the power supply of the main board to communicate with the interface card through the first power circuit; wherein, the first signal circuit is used to control the connection or disconnection of the first power circuit.

Optionally, the first power supply circuit is provided with a first switch, the first signal circuit is connected to the first switch to control the opening or closing of the first switch, and calling the first signal circuit through the main board to send the enabling signal to the interface card includes :

The main board invokes the first signal circuit to send an enabling signal to the first switch, so that the first switch is turned on.

Optionally, a first control member is also provided between the first signal circuit and the first switch, and the first signal circuit controls the opening or closing of the first switch through the first control member.

Optionally, the first control component includes an OR gate logic circuit.

Optionally, the main board is provided with a second signal circuit, and sending a shutdown signal to the interface card through any main board to control the disconnection of the second power circuit between the interface card and the PCIe chip includes:

Call the second signal circuit to send a shutdown signal to the interface card through any one of the main boards to control the disconnection of the second power circuit between the interface card and the PCIe chip; wherein the second signal circuit is used to control the connection or disconnection of the second power circuit open.

Optionally, a second switch is provided on the second power supply circuit, and the second signal circuit is connected to the second switch to control the opening or closing of the second switch, and the second signal circuit is called by any main board to send a closing signal to the interface card include:

The second signal circuit is invoked by any one of the main boards to send an off signal to the second switch, so that the second switch is turned off.

Optionally, a second control member is further provided between the second signal circuit and the second switch, and the second signal circuit controls the opening or closing of the second switch through the second control member.

Optionally, the second control component includes an AND gate logic circuit.

Optionally, a programmable logic device is provided on the main board.

Optionally, sending the enable signal to the interface card through the main board includes:

Sending the first control signal to the programmable logic device, so that the programmable logic device sends an enabling signal to the interface card.

Optionally, sending a shutdown signal to the interface card through any main board includes:

Sending the second control signal to any programmable logic device, so that any programmable logic device sends a shutdown signal to the interface card.

Optionally, the power-off requirements include upgrade failure and/or service requirements.

Optionally, after the PCIe chip is powered off separately while the interface card is kept powered on, the method further includes:

Repair the PCIe chip.

Optionally, there are four main boards.

Optionally, the interface card further includes a data distribution algorithm module and/or an EBOF module.

Optionally, an overload fuse is provided between the power supply of the mainboard and the first switch.

The embodiment of the present application also discloses a control device based on a PCIe chip in a storage device, the storage device is provided with an interface card, the interface card is provided with a PCIe chip and a plurality of PCIe interfaces connected to the PCIe chip, and any PCIe interface is inserted into the motherboard In this case, the power supply of the motherboard is connected to the interface card through the first power circuit, and the interface card is connected to the PCIe chip through the second power circuit. The device includes:

The power-on module is used to send an enable signal to the interface card through the motherboard when any PCIe interface is inserted into the motherboard, so as to control the power supply of the motherboard to communicate with the interface card through the first power circuit, and to communicate with the PCIe chip through the second power circuit Connect to power on the interface card and PCIe chip;

The separate power-off module is used to send a shutdown signal to the interface card through any main board to control the disconnection of the second power supply circuit between the interface card and the PCIe chip when the power-off requirement of the interface card is detected, so that the PCIe chip is in the The interface card is powered off separately while the interface card remains powered on.

The embodiment of the present application also discloses an electronic device, including a processor, a memory, and a computer program stored on the memory and capable of running on the processor. When the computer program is executed by the processor, the above-mentioned PCIe chip based on the storage device is implemented. steps of the control method.

The embodiment of the present application also discloses a computer non-volatile readable storage medium. Computer programs are stored on the computer non-volatile readable storage medium. When the computer programs are executed by the processor, the above-mentioned PCIe chip based on the storage device is implemented. steps of the control method.

The embodiment of the present application includes the following advantages:

In the embodiment of the present application, the storage device is provided with an interface card, and the interface card is provided with a PCIe chip and a plurality of PCIe interfaces connected to the PCIe chip. When the motherboard is inserted into any PCIe interface, the power supply of the motherboard and the interface card pass through The first power supply circuit is connected, and the interface card is connected to the PCIe chip through the second power supply circuit. When any PCIe interface is inserted into the mainboard, an enable signal is sent to the interface card through the mainboard to control the power supply of the mainboard through the first power supply circuit and The interface card is connected, and is connected with the PCIe chip through the second power supply circuit, so that the interface card and the PCIe chip are powered on; when the power-off demand of the interface card is detected, a shutdown signal is sent to the interface card through any main board to control the interface card The second power supply circuit between the PCIe chip and the PCIe chip is disconnected, so that the PCIe chip is powered off separately while the interface card remains powered on, realizing the independent power-off repair of the PCIe chip, ensuring the normal operation of other services, and reducing the Operating costs, so as to achieve quality reinforcement on the business path, and improve product reliability and self-healing capabilities.

Description of drawings

FIG. 1 is a structural block diagram of a one-frame four-control storage device;

Fig. 2 is a schematic diagram of an embodiment of a control method based on a PCIe chip in a storage device of the present application;

Fig. 3 is a schematic diagram of an embodiment of a control method based on a PCIe chip in a storage device of the present application;

Fig. 4 is a flow chart of steps of an embodiment of a control method based on a PCIe chip in a storage device of the present application;

FIG. 5 is a flow chart of the steps of another embodiment of a control method based on a PCIe chip in a storage device of the present application;

FIG. 6 is a flow chart of the steps of another embodiment of a control method based on a PCIe chip in a storage device of the present application;

FIG. 7 is a flow chart of the steps of another embodiment of a control method based on a PCIe chip in a storage device of the present application;

FIG. 8 is a structural block diagram of an embodiment of a control device based on a PCIe chip in a storage device according to the present application.

detailed description

In order to make the above objects, features and advantages of the present application more obvious and comprehensible, the present application will be further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

As shown in Figure 1, a one-frame four-control storage device includes four motherboards. The client server is interconnected with multiple hosts through a 400G network. The EBOF (a type of network card) network disk cabinet is interconnected with the EBOF interface card through a 400G network. The data distribution algorithm interface cards and EBOF interface cards of multiple hosts are respectively connected to the four main boards in the chassis through PCIe (peripheral component interconnect express, a high-speed serial computer expansion bus standard) chip. The data distribution algorithm interface card undertakes the business data of the front-end server, and the EBOF interface card forwards the business data to the EBOF network disk cabinet. The data distribution algorithm interface card and the EBOF interface card are the physical links used by the business data flow.

However, when the data distribution algorithm interface card and the EBOF interface card fail to be upgraded or due to business requirements, it is necessary to control the power-off of the PCIe chip for repair operations. At this time, the power-off control of the PCIe chip by the four mainboards has an "AND" logic. It is necessary for the four mainboards to send a shutdown signal at the same time to control the power-off of the PCIe chip, and the data distribution algorithm interface card and the EBOF interface card will also be activated. Power off will affect other services.

However, in the OCP (Open compute project, development computing engineering) NIC (network interface controller, network interface controller) 3.0 standard protocol that can be referred to at present, the definition of PCIe Bifurcation (fork) is as follows:

Single Host (1x16) and 1x16 OCP NIC 3.0 Card (Single Controller) (single main board single host and single board single PCIe port);

Single Host (2x8) and 2x8 OCP NIC 3.0 Card (Dual Controllers) (single main board single host and single board dual PCIe ports);

Quad Hosts (4x4) and 4x4 OCP NIC 3.0 Card (Single Controller) (four hosts on a single motherboard and a single PCIe port on a single board);

Quad Hosts (4x4) and 4x4 OCP NIC 3.0 Card (Quad Controllers) (four hosts on a single motherboard and four PCIe ports on a single board).

It can be seen that the above protocol does not define the interconnection topology scenario of four mainboards and four hosts and a single PCIe end of a single board.

Based on this, this application proposes an embodiment of a control method based on the PCIe chip in the storage device, as shown in Figure 2 and Figure 3, when the host (host) x86 loads the bios (basic input and output system) and runs, the host x86 passes The smbus (System Management Bus, system management bus) can directly access the CPLD (Complex Programmable Logic Device, complex programmable logic chip) of the motherboard, and the CPLD provides an enable command interface and a shutdown command interface.

Each motherboard provides MAIN-PWR-EN (main power supply signal circuit), and the MAIN-PWR-EN of the four motherboards are combined by OR gate logic circuits to finally control the switch A from P12V-edge to P12V on the multi-homing interface card , when at least one motherboard is inserted into the chassis, the CPLD of the host x86 control motherboard sends an enable signal through MAIN-PWR-EN, and the multi-homing interface card can be powered on.

Each main board provides PWR-EN (independent power signal circuit), and the PWR-EN of the four main boards are combined by AND gate logic circuits to finally control the DCDC switch from P12V to P3V3_PCIE on the multi-homing interface card (P3V3_PCIE is the PCIe end chip The working power supply used, DCDC is a device that converts a DC power supply of a certain voltage level into a DC power supply of another voltage level, which is equivalent to a switch). When the multi-homing interface card fails to be upgraded or due to business needs, host x86 controls the CPLD of any motherboard to send a shutdown signal through PWR-EN, and P12V and P3V3_PCIE are disconnected, while P12V and P12V-edge are still connected, realizing the PCIe terminal The need to power off the chip separately ensures the normal operation of other services and reduces operating costs, thereby achieving quality reinforcement on the service path and improving product reliability and self-healing capabilities.

Below the application embodiment is described further:

With reference to Fig. 4, show a kind of step flowchart of the embodiment of the control method based on the PCIe chip in the storage device of the present application, the storage device is provided with an interface card, the interface card is provided with a PCIe chip and a plurality of PCIe interfaces connected with the PCIe chip , when the motherboard is inserted into any PCIe interface, the power supply of the motherboard is connected to the interface card through the first power supply circuit, and the interface card is connected to the PCIe chip through the second power supply circuit. The method may include the following steps:

Step 401, when any PCIe interface is inserted into the motherboard, send an enable signal to the interface card through the motherboard, to control the power supply of the motherboard to communicate with the interface card through the first power circuit, and communicate with the PCIe chip through the second power circuit, so that Power on the interface card and PCIe chip.

When any PCIe interface is inserted into the motherboard, the interface card needs to be powered on to provide a service data flow path for the motherboard, so the enable signal is sent to the interface card through the motherboard to control the power supply of the motherboard to pass through the first power supply circuit and the interface card connected, and communicated with the PCIe chip through the second power supply circuit, so that the interface card and the PCIe chip are powered on.

In a specific implementation, there may be four main boards.

By setting up four mainboards, a storage control box with four controllers in one frame is formed, thereby improving the reliability of storage devices. Even if three of the four mainboards fail, the remaining one can still provide customers with normal services.

In practical applications, the interface card may also include a data distribution algorithm module and/or an EBOF module.

By being equipped with an algorithm module and/or an EBOF module, the interface card can receive the business data of the front-end server and forward it to the EBOF network disk cabinet, thereby providing a business data flow path.

Step 402, when detecting the power-off requirement of the interface card, send a shutdown signal to the interface card through any main board to control the disconnection of the second power circuit between the interface card and the PCIe chip, so that the PCIe chip remains on the interface card In the case of power off, power off separately.

When the power-off demand of the interface card is detected, in order to avoid the impact of other services, a shutdown signal is sent to the interface card through any main board to control the disconnection of the second power supply circuit between the interface card and the PCIe chip, so that the PCIe The chip is powered off independently while the interface card remains powered on.

In an embodiment of the present application, the power-off requirements include upgrade failure and/or service requirements.

When the interface card fails to be upgraded or due to service requirements, it is necessary to power off the PCIe chip to troubleshoot and meet service requirements.

In an embodiment of the present application, after the PCIe chip is powered off separately under the condition that the interface card remains powered on in step 402, the method may further include the following steps:

Repair the PCIe chip.

After completing the repair operation to the PCIe chip, the main board that sends the closing signal to the interface card in step 402 can send an enable signal to the interface card to reconnect with the second power supply circuit between the control interface card and the PCIe chip, so that the PCIe The chip is powered on again.

In the embodiment of the present application, the storage device is provided with an interface card, and the interface card is provided with a PCIe chip and a plurality of PCIe interfaces connected to the PCIe chip. When the motherboard is inserted into any PCIe interface, the power supply of the motherboard and the interface card pass through The first power supply circuit is connected, and the interface card is connected to the PCIe chip through the second power supply circuit. When any PCIe interface is inserted into the mainboard, an enable signal is sent to the interface card through the mainboard to control the power supply of the mainboard through the first power supply circuit and The interface card is connected, and is connected with the PCIe chip through the second power supply circuit, so that the interface card and the PCIe chip are powered on; when the power-off demand of the interface card is detected, a shutdown signal is sent to the interface card through any main board to control the interface card The second power supply circuit between the PCIe chip and the PCIe chip is disconnected, so that the PCIe chip is powered off separately while the interface card remains powered on, realizing the independent power-off repair of the PCIe chip, ensuring the normal operation of other services, and reducing the Operating costs, so as to achieve quality reinforcement on the business path, and improve product reliability and self-healing capabilities.

Referring to Fig. 5, it shows a flow chart of steps of another embodiment of a control method based on a PCIe chip in a storage device of the present application, the storage device is provided with an interface card, the interface card is provided with a PCIe chip and a plurality of PCIe chips connected to the PCIe chip interface, when the motherboard is inserted into any PCIe interface, the power supply of the motherboard is connected to the interface card through the first power supply circuit, the interface card is connected to the PCIe chip through the second power supply circuit, and the motherboard is provided with the first signal circuit. This method can Including the following steps:

Step 501, when any PCIe interface is inserted into the motherboard, call the first signal circuit through the motherboard to send an enable signal to the interface card, so as to control the power supply of the motherboard to communicate with the interface card through the first power circuit, and communicate with the interface card through the second power circuit The PCIe chip is connected, so that the interface card and the PCIe chip are powered on.

Wherein, the first signal circuit is used to control the connection or disconnection of the first power supply circuit, so that the control of the first power supply circuit can be completed through the first signal circuit, and the influence on the control of the second power supply circuit can be avoided.

When any PCIe interface is inserted into the motherboard, the interface card needs to be powered on to provide a service data flow path for the motherboard, so the motherboard calls the first signal circuit to send an enable signal to the interface card to control the power supply of the motherboard through the first The power supply circuit communicates with the interface card, and communicates with the PCIe chip through the second power supply circuit, so that the interface card and the PCIe chip are powered on.

In an embodiment of the present application, the first power supply circuit is provided with a first switch, and the first signal circuit is connected to the first switch to control the opening or closing of the first switch. In step 601, calling the first signal circuit through the main board Sending the enable signal to the interface card may include the following substeps:

Sub-step 11, calling the first signal circuit through the main board to send an enable signal to the first switch, so that the first switch is turned on.

By setting the first switch, it is more convenient to control the connection or disconnection of the first power supply circuit, and accurately realize the power-on control of the interface card and the PCIe chip.

In yet another embodiment of the present application, an overload fuse may be provided between the power supply of the mainboard and the first switch.

When the current in the first power supply circuit is too large, the overload fuse will disconnect the power supply from the first switch, so as to prevent the interface card and the PCIe chip from being damaged due to overload and ensure the safe operation of the circuit.

In specific applications, the overload fuse can be set as an efause switch.

In a specific implementation, a first control member is further provided between the first signal circuit and the first switch, and the first signal circuit controls the opening or closing of the first switch through the first control member.

Control logic is built in the first control part, and the first signal circuit can be controlled by the control logic of the first control part, so that the first switch is opened or closed according to the control logic of the first control part.

In practical applications, the first control unit may include an OR gate logic circuit, and its control logic is as follows:

As long as one of the input signals is high level (logic "1", that is, the enable signal), the output signal is high level, which can make the first switch open; only when all the input signals are all low level (logic "0", that is, when the signal is turned off), the output signal is at a low level, that is, the first switch is turned off.

In a specific implementation, there may be four main boards.

By setting up four mainboards, a storage control box with four controllers in one frame is formed, thereby improving the reliability of storage devices. Even if three of the four mainboards fail, the remaining one can still provide customers with normal services.

In practical applications, the interface card may also include a data distribution algorithm module and/or an EBOF module.

By being equipped with an algorithm module and/or an EBOF module, the interface card can receive the business data of the front-end server and forward it to the EBOF network disk cabinet, thereby providing a business data flow path.

Step 502, when detecting the power-off requirement of the interface card, send a shutdown signal to the interface card through any main board to control the disconnection of the second power circuit between the interface card and the PCIe chip, so that the PCIe chip remains on the interface card In the case of power off, power off separately.

When the power-off demand of the interface card is detected, in order to avoid the impact of other services, a shutdown signal is sent to the interface card through any main board to control the disconnection of the second power supply circuit between the interface card and the PCIe chip, so that the PCIe The chip is powered off independently while the interface card remains powered on.

In an embodiment of the present application, the power-off requirements include upgrade failure and/or service requirements.

When the interface card fails to be upgraded or due to service requirements, it is necessary to power off the PCIe chip to troubleshoot and meet service requirements.

In an embodiment of the present application, after the PCIe chip is powered off separately while the interface card remains powered on in step 502, the method may further include the following steps:

Repair the PCIe chip.

After completing the repair operation to the PCIe chip, the main board that sends the closing signal to the interface card in step 502 can send an enabling signal to the interface card to reconnect with the second power supply circuit between the control interface card and the PCIe chip, so that the PCIe The chip is powered on again.

In the embodiment of the present application, the storage device is provided with an interface card, and the interface card is provided with a PCIe chip and a plurality of PCIe interfaces connected to the PCIe chip. When the motherboard is inserted into any PCIe interface, the power supply of the motherboard and the interface card pass through The first power supply circuit is connected, the interface card is connected to the PCIe chip through the second power supply circuit, the motherboard is provided with a first signal circuit, and when any PCIe interface is inserted into the motherboard, the first signal circuit is called by the motherboard to send an enabling signal to the interface card , so as to control the power supply of the motherboard to communicate with the interface card through the first power circuit, and communicate with the PCIe chip through the second power circuit, so that the interface card and the PCIe chip are powered on; when the power-off demand of the interface card is detected, through any A main board sends a shutdown signal to the interface card to control the disconnection of the second power supply circuit between the interface card and the PCIe chip, so that the PCIe chip is powered off separately while the interface card is kept powered on, realizing the separate power-off of the PCIe chip The repair ensures the normal operation of other businesses and reduces operating costs, thereby achieving quality reinforcement on the business path and improving product reliability and self-healing capabilities.

Referring to FIG. 6 , it shows a flow chart of steps of another embodiment of a control method based on a PCIe chip in a storage device of the present application. The storage device is provided with an interface card, and the interface card is provided with a PCIe chip and a plurality of PCIe chips connected to the PCIe chip. Interface, when the motherboard is inserted into any PCIe interface, the power supply of the motherboard is connected to the interface card through the first power supply circuit, the interface card is connected to the PCIe chip through the second power supply circuit, and the motherboard is provided with a second signal circuit. This method can Including the following steps:

Step 601, when any PCIe interface is inserted into the motherboard, send an enabling signal to the interface card through the motherboard, to control the power supply of the motherboard to communicate with the interface card through the first power circuit, and communicate with the PCIe chip through the second power circuit, so that Power on the interface card and PCIe chip.

When any PCIe interface is inserted into the motherboard, the interface card needs to be powered on to provide a service data flow path for the motherboard, so the enable signal is sent to the interface card through the motherboard to control the power supply of the motherboard to pass through the first power supply circuit and the interface card connected, and communicated with the PCIe chip through the second power supply circuit, so that the interface card and the PCIe chip are powered on.

In a specific implementation, there may be four main boards.

By setting up four mainboards, a storage control box with four controllers in one frame is formed, thereby improving the reliability of storage devices. Even if three of the four mainboards fail, the remaining one can still provide customers with normal services.

In practical applications, the interface card may also include a data distribution algorithm module and/or an EBOF module.

By being equipped with an algorithm module and/or an EBOF module, the interface card can receive the business data of the front-end server and forward it to the EBOF network disk cabinet, thereby providing a business data flow path.

Step 602, when detecting the power-off demand of the interface card, call the second signal circuit to send a shutdown signal to the interface card through any one of the motherboards, so as to control the disconnection of the second power circuit between the interface card and the PCIe chip, so that the PCIe chip Power off the interface card separately while the interface card remains powered on.

Wherein, the second signal circuit is used to control the connection or disconnection of the second power supply circuit, so that the control of the second power supply circuit can be completed through the second signal circuit, avoiding the influence on the control of the first power supply circuit.

When the power-off requirement of the interface card is detected, in order to avoid the impact of other services, the second signal circuit is called to send a shutdown signal to the interface card through any main board to control the second power supply circuit between the interface card and the PCIe chip. Enable to enable the PCIe chip to be powered off independently while the interface card remains powered on.

In an embodiment of the present application, the second power supply circuit is provided with a second switch, and the second signal circuit is connected to the second switch to control the opening or closing of the second switch. In step 602, calling the second The signal circuit sending the closing signal to the interface card may include the following sub-steps:

Sub-step 21, calling the second signal circuit through any one of the main boards to send a shutdown signal to the second switch, so that the second switch is turned off.

By setting the second switch, it is more convenient to control the connection or disconnection of the second power supply circuit, and accurately realize the independent power-off control of the PCIe chip when the interface card remains powered on.

In a specific implementation, a second control member is further provided between the second signal circuit and the second switch, and the second signal circuit controls the opening or closing of the second switch through the second control member.

Control logic is built in the second control part, and the second signal circuit can be controlled by the control logic of the second control part, so that the second switch is opened or closed according to the control logic of the second control part.

In practical applications, the second control part may include an AND gate logic circuit, and its control logic is as follows:

When all the input signals are high level at the same time (logic "1", that is, the enable signal), the output signal is high level, which can make the second switch open; as long as one of the input signals is low level (logic "0", that is, turn off the signal), the output signal is low level, that is, the second switch is turned off.

In an embodiment of the present application, the power-off requirements include upgrade failure and/or service requirements.

When the interface card fails to be upgraded or due to service requirements, it is necessary to power off the PCIe chip to troubleshoot and meet service requirements.

In an embodiment of the present application, after the PCIe chip is powered off separately while the interface card remains powered on in step 602, the method may further include the following steps:

Repair the PCIe chip.

After completing the repair operation to the PCIe chip, the main board that sends the shutdown signal to the interface card in step 602 can send an enable signal to the interface card to reconnect with the second power supply circuit between the control interface card and the PCIe chip, so that the PCIe The chip is powered on again.

In the embodiment of the present application, the storage device is provided with an interface card, and the interface card is provided with a PCIe chip and a plurality of PCIe interfaces connected to the PCIe chip. When the motherboard is inserted into any PCIe interface, the power supply of the motherboard and the interface card pass through The first power supply circuit is connected, the interface card is connected to the PCIe chip through the second power supply circuit, and the main board is provided with a second signal circuit. When any PCIe interface is inserted into the main board, the main board sends an enable signal to the interface card to control the operation of the main board. The power supply is connected to the interface card through the first power supply circuit, and is connected to the PCIe chip through the second power supply circuit, so that the interface card and the PCIe chip are powered on; when the power-off demand of the interface card is detected, the second The signal circuit sends a shutdown signal to the interface card to control the disconnection of the second power supply circuit between the interface card and the PCIe chip, so that the PCIe chip is powered off separately while the interface card is kept powered on, realizing the separate power-off of the PCIe chip The repair ensures the normal operation of other businesses and reduces operating costs, thereby achieving quality reinforcement on the business path and improving product reliability and self-healing capabilities.

Referring to FIG. 7 , it shows a flow chart of steps of another embodiment of a control method based on a PCIe chip in a storage device of the present application. The storage device is provided with an interface card, and the interface card is provided with a PCIe chip and a plurality of PCIe chips connected to the PCIe chip. interface, when the motherboard is inserted into any PCIe interface, the power supply of the motherboard is connected to the interface card through the first power circuit, the interface card is connected to the PCIe chip through the second power circuit, and the motherboard is provided with a programmable logic device. May include the following steps:

Step 701, when any PCIe interface is inserted into the motherboard, send the first control signal to the programmable logic device, so that the programmable logic device sends an enable signal to the interface card, so as to control the power supply of the motherboard to pass through the first power supply circuit and the interface card connected, and communicated with the PCIe chip through the second power supply circuit, so that the interface card and the PCIe chip are powered on.

When any PCIe interface is inserted into the motherboard, the interface card needs to be powered on to provide a service data flow path for the motherboard, so the first control signal is sent to the programmable logic device, so that the programmable logic device sends an enable signal to the interface card, The power supply of the control board is communicated with the interface card through the first power circuit, and communicated with the PCIe chip through the second power circuit, so that the interface card and the PCIe chip are powered on.

In a specific implementation, there may be four main boards.

By setting up four mainboards, a storage control box with four controllers in one frame is formed, thereby improving the reliability of storage devices. Even if three of the four mainboards fail, the remaining one can still provide customers with normal services.

In practical applications, the interface card may also include a data distribution algorithm module and/or an EBOF module.

By being equipped with an algorithm module and/or an EBOF module, the interface card can receive the business data of the front-end server and forward it to the EBOF network disk cabinet, thereby providing a business data flow path.

Step 702, when the power-off requirement of the interface card is detected, send a second control signal to any programmable logic device, so that any programmable logic device sends a shutdown signal to the interface card to control the connection between the interface card and the PCIe chip. The second power supply circuit is disconnected, so that the PCIe chip is powered off independently while the interface card remains powered on.

When the power-off demand of the interface card is detected, in order to avoid the impact of other services, send the second control signal to any programmable logic device, so that any programmable logic device sends a shutdown signal to the interface card to control the interface card The second power supply circuit between the PCIe chip and the PCIe chip is disconnected, so that the PCIe chip is powered off independently while the interface card is kept powered on.

In an embodiment of the present application, the power-off requirements include upgrade failure and/or service requirements.

When the interface card fails to be upgraded or due to service requirements, it is necessary to power off the PCIe chip to troubleshoot and meet service requirements.

In an embodiment of the present application, after the PCIe chip is powered off separately while the interface card remains powered on in step 702, the method may further include the following steps:

Repair the PCIe chip.

After completing the repair operation to the PCIe chip, the main board that sends the closing signal to the interface card in step 702 can send an enabling signal to the interface card to reconnect with the second power supply circuit between the control interface card and the PCIe chip, so that the PCIe The chip is powered on again.

By setting the programmable logic device, different signal paths can be selected according to different control signals, and the corresponding control can be accurately completed, so as to avoid false control affecting the normal operation of the business.

In a specific implementation, the programmable logic device can be set as a CPLD, so as to deal with various control logics and meet various control requirements.

In the embodiment of the present application, the storage device is provided with an interface card, and the interface card is provided with a PCIe chip and a plurality of PCIe interfaces connected to the PCIe chip. When the motherboard is inserted into any PCIe interface, the power supply of the motherboard and the interface card pass through The first power supply circuit is connected, the interface card is connected to the PCIe chip through the second power supply circuit, the main board is provided with a programmable logic device, and when any PCIe interface is inserted into the main board, the first control signal is sent to the programmable logic device, so that the The programming logic sends an enabling signal to the interface card to control the power supply of the motherboard to communicate with the interface card through the first power circuit, and to communicate with the PCIe chip through the second power circuit, so that the interface card and the PCIe chip are powered on; When the interface card needs to be powered off, send a second control signal to any programmable logic device, so that any programmable logic device sends a shutdown signal to the interface card to control the second power supply circuit between the interface card and the PCIe chip. On, so that the PCIe chip is powered off separately while the interface card is powered on, realizing the individual power-off repair of the PCIe chip, ensuring the normal operation of other services, and reducing operating costs, so as to achieve quality in the service path Reinforcement improves the reliability and self-healing ability of the product.

It should be noted that, for the method embodiment, for the sake of simple description, it is expressed as a series of action combinations, but those skilled in the art should know that the embodiment of the present application is not limited by the described action sequence, because According to the embodiment of the present application, certain steps may be performed in other orders or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification belong to preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present application.

Referring to FIG. 8 , it shows that the embodiment of the present application also discloses a structural block diagram of a control device embodiment based on a PCIe chip in a storage device. The storage device is provided with an interface card, and the interface card is provided with a PCIe chip and multiple devices connected to the PCIe chip. A PCIe interface, when the motherboard is inserted into any PCIe interface, the power supply of the motherboard is connected to the interface card through the first power supply circuit, and the interface card is connected to the PCIe chip through the second power supply circuit. The device can include the following modules:

The power-on module 801 is used to send an enable signal to the interface card through the motherboard when any PCIe interface is inserted into the motherboard, so as to control the power supply of the motherboard to communicate with the interface card through the first power supply circuit, and to communicate with the PCIe interface through the second power supply circuit. The chip is connected to power on the interface card and the PCIe chip.

In an embodiment of the present application, the main board may be provided with a first signal circuit, and the power-on module 801 may include the following sub-modules:

The first signal circuit sub-module is used to call the first signal circuit through the main board to send an enabling signal to the interface card, so as to control the power supply of the main board to communicate with the interface card through the first power circuit; wherein, the first signal circuit is used to control the first signal circuit The connection or disconnection of a power circuit.

In an embodiment of the present application, the first power supply circuit may be provided with a first switch, and the first signal circuit is connected to the first switch to control the opening or closing of the first switch. The first signal circuit sub-module may include the following sub-modules: unit:

The first switch subunit is configured to invoke the first signal circuit through the main board to send an enabling signal to the first switch, so as to turn on the first switch.

In an embodiment of the present application, the main board may be provided with a programmable logic device, and the power-on module 801 may also include the following sub-modules:

The first control logic sub-module is configured to send a first control signal to the programmable logic device, so that the programmable logic device sends an enabling signal to the interface card.

A separate power-off module 802, used to send a shutdown signal to the interface card through any one of the motherboards to control the disconnection of the second power supply circuit between the interface card and the PCIe chip when the power-off requirement of the interface card is detected, so that the PCIe chip Power off the interface card separately while the interface card remains powered on.

In an embodiment of the present application, the main board is provided with a second signal circuit, and the separate power-off module 802 may include the following sub-modules:

The second signal circuit submodule is used to call the second signal circuit through any one of the main boards to send a shutdown signal to the interface card to control the disconnection of the second power circuit between the interface card and the PCIe chip; wherein the second signal circuit is used for Controlling the connection or disconnection of the second power supply circuit.

In an embodiment of the present application, the second power supply circuit is provided with a second switch, and the second signal circuit is connected to the second switch to control the opening or closing of the second switch. The second signal circuit submodule may include the following subunits :

The second switch sub-unit is configured to call the second signal circuit through any one of the main boards to send a closing signal to the second switch, so that the second switch is turned off.

In an embodiment of the present application, a programmable logic device may be provided on the motherboard, and the separate power-off module 802 may also include the following submodules:

The second control logic sub-module is configured to send a second control signal to any programmable logic device, so that any programmable logic device sends a shutdown signal to the interface card.

In yet another embodiment of the present application, the device may also include the following modules:

The chip repair module is used for repairing the PCIe chip.

As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and for related parts, please refer to the part of the description of the method embodiment.

The embodiment of the present application also provides an electronic device, which may include a processor, a memory, and a computer program stored on the memory and capable of running on the processor. When the computer program is executed by the processor, the above-mentioned PCIe-based storage device is implemented The steps of the control method of the chip.

The embodiment of the present application also provides a computer non-volatile readable storage medium. Computer programs are stored on the computer non-volatile readable storage medium. When the computer programs are executed by the processor, the above-mentioned PCIe chip based on the storage device is implemented. steps of the control method.

Each embodiment in this specification is described in a progressive manner, each embodiment focuses on the difference from other embodiments, and the same and similar parts of each embodiment can be referred to each other.

Those skilled in the art should understand that the embodiments of the embodiments of the present application may be provided as methods, devices, or computer program products. Therefore, the embodiment of the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present application may adopt the method of computer program products implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage devices, CD-ROMs, optical storage devices, etc.) containing computer-usable program codes therein. form.

Embodiments of the present application are described with reference to flowcharts and/or block diagrams of methods, terminal devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each procedure and/or block in the flowchart and/or block diagram, and a combination of procedures and/or blocks in the flowchart and/or block diagram can be realized by computer program instructions. These computer program instructions may be provided to a general purpose computer, special purpose computer, embedded processor or processor of other programmable data processing terminal equipment to produce a machine such that instructions executed by the computer or processor of other programmable data processing terminal equipment Produce means for realizing the functions specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

These computer program instructions may also be stored in a computer-readable storage device capable of directing a computer or other programmable data processing terminal to operate in a specific manner, such that the instructions stored in the computer-readable storage device produce an article of manufacture comprising instruction means , the instruction device implements the functions specified in one or more procedures of the flow chart and/or one or more blocks of the block diagram.

These computer program instructions can also be loaded into a computer or other programmable data processing terminal equipment, so that a series of operational steps are performed on the computer or other programmable terminal equipment to produce computer-implemented processing, thereby The instructions executed above provide steps for implementing the functions specified in the procedure or procedures of the flowchart and/or the block or blocks of the block diagram.

While the preferred embodiments of the embodiments of the present application have been described, additional changes and modifications can be made to these embodiments by those skilled in the art once the basic inventive concept is understood. Therefore, the appended claims are intended to be interpreted to cover the preferred embodiment and all changes and modifications that fall within the scope of the embodiments of the application.

Finally, it should also be noted that in this text, relational terms such as first and second etc. are only used to distinguish one entity or operation from another, and do not necessarily require or imply that these entities or operations, any such actual relationship or order exists. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or terminal equipment comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements identified, or also include elements inherent in such a process, method, article, or end-equipment. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article or terminal device comprising said element.

The above is a detailed introduction to the control method and device based on the PCIe chip in the storage device provided by the present application. In this paper, specific examples are used to illustrate the principle and implementation of the present application. The description of the above embodiments is only used To help understand the method and its core idea of this application; at the same time, for those of ordinary skill in the art, according to the idea of this application, there will be changes in the specific implementation and application scope. In summary, this specification The content should not be construed as a limitation of the application.

Claims (20)

1. A control method based on PCIe chips in storage equipment is characterized in that the storage equipment is provided with an interface card, the interface card is provided with the PCIe chips and a plurality of PCIe interfaces connected with the PCIe chips, under the condition that any one PCIe interface is inserted into a mainboard, a power supply of the mainboard is connected with a first power circuit of the interface card, the interface card is connected with the PCIe chips through a second power circuit, and the method comprises the following steps:

when any PCIe interface is inserted into the mainboard, an enabling signal is sent to the interface card through the mainboard so as to control a power supply of the mainboard to be communicated with the interface card through the first power circuit and communicated with the PCIe chip through the second power circuit, and the interface card and the PCIe chip are powered on;

when the power-off requirement of the interface card is detected, a shutdown signal is sent to the interface card through any one mainboard to control the disconnection of the second power circuit between the interface card and the PCIe chip, so that the PCIe chip is powered off independently under the condition that the interface card is kept powered on.

2. The method of claim 1, wherein a motherboard is provided with a first signal circuit, and the sending an enable signal to the interface card via the motherboard to control power of the motherboard to communicate with the interface card via the first power circuit comprises:

calling the first signal circuit through the mainboard to send an enabling signal to the interface card so as to control a power supply of the mainboard to be communicated with the interface card through the first power circuit; the first signal circuit is used for controlling connection or disconnection of the first power supply circuit.

3. The method of claim 2, wherein a first switch is disposed on the first power circuit, the first signal circuit is connected to the first switch to control the first switch to be turned on or off, and the invoking of the first signal circuit by the motherboard to send the enable signal to the interface card comprises:

and calling the first signal circuit through a mainboard to send an enabling signal to the first switch so as to open the first switch.

4. The method of claim 3, wherein a first control element is further disposed between the first signal circuit and the first switch, and the first signal circuit controls the first switch to be turned on or off through the first control element.

5. The method of claim 4, wherein the first control comprises OR gate logic.

6. The method of claim 1, wherein a second signal circuit is provided on a motherboard, and wherein sending a shutdown signal to the interface card via any of the motherboards to control disconnection of the second power circuit between the interface card and the PCIe chip comprises:

calling the second signal circuit through any one mainboard to send a shutdown signal to the interface card so as to control the disconnection of the second power supply circuit between the interface card and the PCIe chip; the second signal circuit is used for controlling connection or disconnection of the second power supply circuit.

7. The method according to claim 6, wherein a second switch is disposed on the second power circuit, the second signal circuit is connected to the second switch to control the second switch to be turned on or off, and the invoking of the second signal circuit by any one of the motherboards to send the off signal to the interface card comprises:

and calling the second signal circuit through any one mainboard to send a closing signal to the second switch so as to close the second switch.

8. The method of claim 7, wherein a second control element is further disposed between the second signal circuit and the second switch, and the second signal circuit controls the second switch to be turned on or off through the second control element.

9. The method of claim 8, wherein the second control comprises and gate logic.

10. The method of claim 1, wherein the motherboard has programmable logic disposed thereon.

11. The method of claim 10, wherein sending an enable signal to the interface card via the motherboard comprises:

and sending a first control signal to the programmable logic device to enable the programmable logic device to send an enabling signal to the interface card.

12. The method of claim 10, wherein said sending a shutdown signal to said interface card via any of the motherboards comprises:

and sending a second control signal to any one of the programmable logic devices to enable any one of the programmable logic devices to send a closing signal to the interface card.

13. The method of any one of claims 1 to 12, wherein the power down requirements include upgrade failures and/or business requirements.

14. The method of any of claims 1-12, wherein after said powering down the PCIe chip alone with the interface card remaining powered up, the method further comprises:

and repairing the PCIe chip.

15. Method according to any of claims 1 to 12, characterized in that four main boards are provided.

16. The method of any of claims 1 to 12, wherein the interface card further comprises a data distribution algorithm module and/or an EBOF module.

17. The method according to any one of claims 3 to 5, wherein an overload fuse is provided between a power supply of the main board and the first switch.

18. The utility model provides a controlling means based on PCIe chip in storage device, its characterized in that, storage device is provided with the interface card, the interface card be provided with the PCIe chip and with a plurality of PCIe interfaces that the PCIe chip is connected, under the condition that the mainboard inserts arbitrary one PCIe interface, the power supply of mainboard with the first power supply circuit of interface card links to each other, the interface card with the PCIe chip passes through the second power supply circuit and links to each other, the device includes:

the power-on module is used for sending an enabling signal to the interface card through the mainboard when any PCIe interface is inserted into the mainboard, so as to control a power supply of the mainboard to be communicated with the interface card through the first power supply circuit and communicated with the PCIe chip through the second power supply circuit, and power-on of the interface card and the PCIe chip is realized;

and the independent power-off module is used for sending a closing signal to the interface card through any mainboard when the power-off requirement of the interface card is detected so as to control the disconnection of the second power circuit between the interface card and the PCIe chip and enable the PCIe chip to be powered off independently under the condition that the interface card is kept powered on.

19. An electronic device, comprising a processor, a storage device, and a computer program stored on the storage device and capable of running on the processor, the computer program, when executed by the processor, implementing the steps of the method according to any one of claims 1 to 17.

20. A computer non-transitory readable storage medium, on which a computer program is stored, which, when executed by a processor, implements the steps of the method according to any one of claims 1 to 17.

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