CN115592488A - Chip polishing method - Google Patents
Chip polishing method Download PDFInfo
- Publication number
- CN115592488A CN115592488A CN202210980506.8A CN202210980506A CN115592488A CN 115592488 A CN115592488 A CN 115592488A CN 202210980506 A CN202210980506 A CN 202210980506A CN 115592488 A CN115592488 A CN 115592488A
- Authority
- CN
- China
- Prior art keywords
- chip
- carrier sheet
- sample
- isolation layer
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 57
- 238000005498 polishing Methods 0.000 title claims abstract description 47
- 238000002955 isolation Methods 0.000 claims abstract description 98
- 239000011248 coating agent Substances 0.000 claims abstract description 19
- 238000000576 coating method Methods 0.000 claims abstract description 19
- 230000002787 reinforcement Effects 0.000 claims description 52
- 239000000463 material Substances 0.000 claims description 34
- 238000010438 heat treatment Methods 0.000 claims description 16
- 230000003014 reinforcing effect Effects 0.000 claims description 14
- 239000007788 liquid Substances 0.000 claims description 10
- 238000000465 moulding Methods 0.000 claims description 9
- 239000012188 paraffin wax Substances 0.000 claims description 8
- 230000004888 barrier function Effects 0.000 claims description 4
- 239000007787 solid Substances 0.000 claims description 4
- 229920005989 resin Polymers 0.000 claims description 3
- 239000011347 resin Substances 0.000 claims description 3
- 239000012779 reinforcing material Substances 0.000 claims description 2
- 239000000853 adhesive Substances 0.000 abstract description 15
- 230000001070 adhesive effect Effects 0.000 abstract description 15
- 238000010030 laminating Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 17
- 230000008859 change Effects 0.000 description 11
- 238000001514 detection method Methods 0.000 description 9
- 230000008569 process Effects 0.000 description 8
- 239000013072 incoming material Substances 0.000 description 4
- 238000001816 cooling Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 230000004308 accommodation Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 244000137852 Petrea volubilis Species 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000009969 flowable effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012943 hotmelt Substances 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003032 molecular docking Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
- 239000001993 wax Substances 0.000 description 1
Images
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B7/00—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor
- B24B7/20—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground
- B24B7/22—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain
- B24B7/228—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain for grinding thin, brittle parts, e.g. semiconductors, wafers
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B41/00—Component parts such as frames, beds, carriages, headstocks
- B24B41/06—Work supports, e.g. adjustable steadies
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N1/00—Sampling; Preparing specimens for investigation
- G01N1/28—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q
- G01N1/286—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q involving mechanical work, e.g. chopping, disintegrating, compacting, homogenising
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N1/00—Sampling; Preparing specimens for investigation
- G01N1/28—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q
- G01N1/286—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q involving mechanical work, e.g. chopping, disintegrating, compacting, homogenising
- G01N2001/2866—Grinding or homogeneising
Landscapes
- Engineering & Computer Science (AREA)
- Mechanical Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Health & Medical Sciences (AREA)
- Inorganic Chemistry (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Life Sciences & Earth Sciences (AREA)
- Analytical Chemistry (AREA)
- Biochemistry (AREA)
- General Health & Medical Sciences (AREA)
- General Physics & Mathematics (AREA)
- Immunology (AREA)
- Pathology (AREA)
- Sampling And Sample Adjustment (AREA)
Abstract
Description
技术领域technical field
本发明涉及半导体器件的失效检测领域,尤其是涉及一种芯片打磨方法。The invention relates to the field of failure detection of semiconductor devices, in particular to a chip polishing method.
背景技术Background technique
在对芯片进行失效检测时,为了查清产生在芯片内部的缺陷,需要对芯片的背面进行打磨,便于通过红外线显微镜对芯片的内部缺陷进行观察,或利用EMMI(微光显微镜)进行失效点定位。相关技术中,通常是将芯片的正面通过粘接剂粘接在治具上,然后将治具固定在打磨设备上,并对芯片的背面进行打磨,由于粘接剂的流动难以控制,因此粘接剂很容易出现厚度不均匀的问题,芯片不能水平固定,在后续打磨过程中不同区域的打磨量不一致,导致最后获得的芯片的厚度不均匀,影响检测结果。In the failure detection of the chip, in order to find out the defects inside the chip, it is necessary to polish the back of the chip, so that the internal defects of the chip can be observed through an infrared microscope, or the failure point can be located by using an EMMI (micro-light microscope) . In the related art, the front side of the chip is usually bonded to the jig with an adhesive, and then the jig is fixed on the grinding equipment, and the back side of the chip is polished. Since the flow of the adhesive is difficult to control, the sticking Adhesives are prone to the problem of uneven thickness, the chip cannot be fixed horizontally, and the amount of polishing in different areas is inconsistent in the subsequent polishing process, resulting in uneven thickness of the finally obtained chip, which affects the test results.
发明内容Contents of the invention
本发明旨在至少解决现有技术中存在的技术问题之一。为此,本发明提出一种芯片打磨方法,能够改善芯片打磨后厚度不均匀的问题。The present invention aims to solve at least one of the technical problems existing in the prior art. Therefore, the present invention proposes a chip polishing method, which can improve the problem of uneven thickness of the chip after polishing.
根据本发明第一实施例的芯片打磨方法,包括以下步骤:The chip polishing method according to the first embodiment of the present invention includes the following steps:
准备待处理的样本与硬质的承载片,所述样本包括芯片与框架,所述芯片连接于所述框架的正面,所述承载片具有相对设置的第一表面与第二表面;Prepare a sample to be processed and a hard carrier sheet, the sample includes a chip and a frame, the chip is connected to the front of the frame, and the carrier sheet has a first surface and a second surface oppositely arranged;
将所述框架的背面与所述承载片的所述第一表面贴合;bonding the back of the frame to the first surface of the carrier sheet;
至少在所述芯片的外侧面包覆隔离层,并在所述隔离层的外侧面包覆增强层,且至少使所述承载片的所述第二表面露出;Coating an isolation layer at least on the outer side of the chip, and coating a reinforcing layer on the outer side of the isolation layer, and exposing at least the second surface of the carrier sheet;
从所述第二表面开始向所述芯片打磨,直至所述芯片剩余设定厚度;Grinding the chip from the second surface until the chip has a predetermined remaining thickness;
去除所述隔离层,以使所述样本与所述增强层分离。The isolation layer is removed to separate the sample from the reinforcement layer.
根据本发明第一实施例的芯片打磨方法,至少具有如下有益效果:The chip polishing method according to the first embodiment of the present invention has at least the following beneficial effects:
样本的背面与承载片的第一表面贴合,二者之间不存在粘接剂,因此样本不会因粘接剂厚度不均而相对承载片歪斜,有助于改善芯片打磨后厚度不均匀的问题。The back of the sample is attached to the first surface of the carrier sheet, and there is no adhesive between the two, so the sample will not be skewed relative to the carrier sheet due to uneven thickness of the adhesive, which helps to improve the uneven thickness of the chip after polishing The problem.
在本发明的其他实施例中,使所述隔离层包覆所述框架除背面之外的其他外表面,且使得所述隔离层与所述承载片的所述第一表面连接。In other embodiments of the present invention, the isolation layer is made to cover the outer surface of the frame except the back surface, and the isolation layer is connected to the first surface of the carrier sheet.
在本发明的其他实施例中,设置所述隔离层的方法包括:In other embodiments of the present invention, the method for setting the isolation layer includes:
当所述样本放置于所述承载片后,在所述芯片的顶部施加固态的隔离材料;applying a solid isolation material on top of the chip after the sample is placed on the carrier;
加热所述隔离材料,使所述隔离材料熔化并向下流动至所述承载片,以覆盖所述芯片与所述框架;heating the isolation material to melt the isolation material and flow down to the carrier sheet to cover the chip and the frame;
使熔融的所述隔离材料固化以形成所述隔离层。The molten barrier material is solidified to form the barrier layer.
在本发明的其他实施例中,所述隔离层的材料为石蜡,加热温度为100℃至105℃。In other embodiments of the present invention, the material of the isolation layer is paraffin, and the heating temperature is 100°C to 105°C.
在本发明的其他实施例中,使所述增强层包覆所述承载片除所述第二表面之外的其他外表面。In other embodiments of the present invention, the reinforcing layer is made to cover other outer surfaces of the carrier sheet except the second surface.
在本发明的其他实施例中,设置所述增强层的方法包括:In other embodiments of the present invention, the method for setting the enhancement layer includes:
设置具有容置腔的模具,将承载有所述样本的所述承载片放置于模具内,使所述第二表面与所述容置腔的底壁贴合;setting a mold with an accommodating cavity, placing the carrying sheet carrying the sample in the mold, and making the second surface fit the bottom wall of the accommodating cavity;
向所述容置腔内添加液态的增强材料,直至液面高于所述隔离层;Adding a liquid reinforcement material into the accommodating cavity until the liquid level is higher than the isolation layer;
使液态的所述增强材料固化以形成所述增强层。The reinforcing material in a liquid state is cured to form the reinforcing layer.
在本发明的其他实施例中,所述增强层的材料为树脂。In other embodiments of the present invention, the material of the reinforcing layer is resin.
在本发明的其他实施例中,通过目数逐渐增加的砂纸分别打磨所述承载片、所述框架与所述芯片。In other embodiments of the present invention, the carrier sheet, the frame and the chip are respectively polished with sandpaper of increasing mesh.
根据本发明第五实施例的芯片打磨方法,包括以下步骤:The chip polishing method according to the fifth embodiment of the present invention includes the following steps:
准备承载片与待处理的芯片,所述承载片具有相对设置的第一表面与第二表面;preparing a carrier sheet and chips to be processed, the carrier sheet has a first surface and a second surface oppositely arranged;
将所述芯片的背面与所述承载片的所述第一表面贴合;bonding the back of the chip to the first surface of the carrier sheet;
在所述芯片的外侧包覆隔离层,并在所述隔离层的外侧包覆增强层,且至少使所述承载片的所述第二表面露出;Coating an isolation layer on the outer side of the chip, and coating a reinforcement layer on the outer side of the isolation layer, and exposing at least the second surface of the carrier sheet;
从所述第二表面开始打磨,直至所述芯片达到设定厚度;Grinding starts from the second surface until the chip reaches a set thickness;
去除所述隔离层,以使所述芯片与所述增强层分离。The isolation layer is removed to separate the chip from the enhancement layer.
根据本发明第六实施例的芯片打磨方法,包括以下步骤:The chip polishing method according to the sixth embodiment of the present invention includes the following steps:
准备承载片与待处理的样本,所述样本包括模封体,以及位于所述模封体内的芯片与框架,所述芯片连接于所述框架的正面,所述承载片具有相对设置的第一表面与第二表面;Prepare a carrier sheet and a sample to be processed, the sample includes a molded body, and a chip and a frame located in the molded body, the chip is connected to the front of the frame, and the carrier sheet has a first surface and second surface;
将所述模封体的背面与所述承载片的所述第一表面贴合;bonding the back side of the molding body to the first surface of the carrier sheet;
在所述模封体的外侧包覆隔离层,并在所述隔离层的外侧包覆增强层,且至少使所述承载片的所述第二表面露出;Coating an isolation layer on the outer side of the molded body, and coating a reinforcement layer on the outer side of the isolation layer, and exposing at least the second surface of the carrier sheet;
从所述第二表面开始向所述芯片打磨,直至所述芯片剩余设定厚度;Grinding the chip from the second surface until the chip has a predetermined remaining thickness;
去除所述隔离层,以使所述样本与所述增强层分离。The isolation layer is removed to separate the sample from the reinforcement layer.
本发明的附加方面和优点将在下面的描述中部分给出,部分将从下面的描述中变得明显,或通过本发明的实践了解到。Additional aspects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
附图说明Description of drawings
下面结合附图和实施例对本发明做进一步的说明,其中:The present invention will be further described below in conjunction with accompanying drawing and embodiment, wherein:
图1为相关技术中芯片与治具连接的简要示意图;Fig. 1 is a brief schematic diagram of the connection between a chip and a jig in the related art;
图2为相关技术中芯片打磨后的简要示意图;Fig. 2 is a brief schematic diagram of a chip polished in the related art;
图3为本发明适用的典型样本的内部结构的示意图;Fig. 3 is a schematic diagram of the internal structure of a typical sample applicable to the present invention;
图4为依靠第一实施例打磨方法打磨时样本的状态变化图;Fig. 4 is a state change diagram of the sample when the polishing method of the first embodiment is used;
图5为采用相关技术打磨后芯片侧边具有倒角的示意图;Fig. 5 is a schematic diagram of chamfering on the side of the chip after being polished by the related technology;
图6为依靠第二实施例打磨方法打磨时样本的状态变化图;Fig. 6 is a state change diagram of the sample when the polishing method of the second embodiment is used;
图7为第二实施例中形成隔离层的示意图;7 is a schematic diagram of forming an isolation layer in the second embodiment;
图8为依靠第三实施例打磨方法打磨时样本的状态变化图;Fig. 8 is a state change diagram of the sample when the polishing method of the third embodiment is used;
图9为第三实施例中形成增强层的示意图;Fig. 9 is a schematic diagram of forming a reinforcement layer in the third embodiment;
图10为依靠第四实施例打磨方法打磨时样本的状态变化图;Fig. 10 is a state change diagram of the sample when it is polished by the polishing method of the fourth embodiment;
图11为依靠第五实施例打磨方法打磨时样本的状态变化图;Fig. 11 is a state change diagram of the sample when it is polished by the polishing method of the fifth embodiment;
图12为依靠第六实施例打磨方法打磨时样本的状态变化图。Fig. 12 is a state change diagram of the sample when polished by the polishing method of the sixth embodiment.
附图标记:Reference signs:
承载片100、第一表面110、第二表面120;The
样本200、模封体210、芯片220、框架230;
隔离层300;
增强层400;
加热装置500;
模具600、容置腔610;
样本10、倒角11、粘接剂20、治具30。
具体实施方式detailed description
下面详细描述本发明的实施例,所述实施例的示例在附图中示出,其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的,仅用于解释本发明,而不能理解为对本发明的限制。Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention.
在本发明的描述中,需要理解的是,涉及到方位描述,例如上、下、前、后、左、右等指示的方位或位置关系为基于附图所示的方位或位置关系,仅是为了便于描述本发明和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本发明的限制。In the description of the present invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc. indicated orientations or positional relationships are based on the orientations or positional relationships shown in the drawings, and are only In order to facilitate the description of the present invention and simplify the description, it does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention.
在本发明的描述中,若干的含义是一个以上,多个的含义是两个以上,大于、小于、超过等理解为不包括本数,以上、以下、以内等理解为包括本数。如果有描述到第一、第二只是用于区分技术特征为目的,而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量或者隐含指明所指示的技术特征的先后关系。In the description of the present invention, several means more than one, and multiple means more than two. Greater than, less than, exceeding, etc. are understood as not including the original number, and above, below, within, etc. are understood as including the original number. If the description of the first and second is only for the purpose of distinguishing the technical features, it cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features relation.
本发明的描述中,除非另有明确的限定,设置、安装、连接等词语应做广义理解,所属技术领域技术人员可以结合技术方案的具体内容合理确定上述词语在本发明中的具体含义。In the description of the present invention, unless otherwise clearly defined, words such as setting, installation, and connection should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above words in the present invention in combination with the specific content of the technical solution.
本发明的描述中,参考术语“一个实施例”、“一些实施例”、“示意性实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中,对上述术语的示意性表述不一定指的是相同的实施例或示例。而且,描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。In the description of the present invention, reference to the terms "one embodiment," "some embodiments," "exemplary embodiments," "examples," "specific examples," or "some examples" is intended to mean that the embodiments are A specific feature, structure, material, or characteristic described by or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
相关技术中如果需要对芯片打磨以分析内部的缺陷,通常是将待处理样本10的背面通过粘接剂20粘接于治具30,在粘接之前,需要将能够流动的粘接剂20涂覆于样本10和/或治具30上,然而,粘接剂20的流动难以精确控制,导致粘接剂容易产生厚度不均匀的问题,即使粘接剂20的厚度在结合之前能够保持均匀,样本10与治具30对接的过程中也容易发生歪斜,最终形成图1所示的歪斜状态。In the related art, if it is necessary to polish the chip to analyze internal defects, usually the back of the
当样本10以图1所示的歪斜状态与水平的打磨面接触而被打磨时,不同区域的打磨量存在差异,导致最后获得的样本10存在厚度不均匀的问题,例如,图1左侧的打磨量相比于右侧的打磨量更多,最终获得的样本10的左侧薄于右侧,如此,当样本10左侧的厚度满足要求时,右侧可能因为过厚而导致不能清晰显现内部的结构,从而影响检测结果。基于此,本发明提出了一种芯片打磨方法,能够保证芯片220打磨后厚度均匀一致,以下结合附图进行具体描述。When the
本发明第一实施例中打磨方法所适用的样本200可以是功率模块,如图3所示,一种典型的样本200包括芯片220与框架230,芯片220通常为长方体结构,其中,将芯片220连接有引线的一侧表面定位为芯片220的正面,与正面相对设置的一侧表面为背面,具体至图3中,则芯片220的上表面为正面,下表面为背面。需要说明的是,为了便于描述,对于本发明所提及的其他构件,均以水平放置时的上表面作为正面,下表面作为背面,基于此,芯片220的背面与框架230的正面连接,The
本实施例适用的样本200还可以包括模封体210,模封体210的材料通常为环氧树脂,模封体210将芯片220与框架230包覆在内,以起到绝缘与保护的作用。为了减少打磨量,通常会先去除样本200上的模封体210,以使芯片220与框架230露出,其中,可以利用酸液去除样本200外侧的模封体210。需要说明的是,样本200来料时可以带有模封体210,打磨之前需要先去除模封体210,样本200也可以在来料之前去除模封体210。The
参照图4,示出了依靠第一实施例打磨方法打磨时样本200的状态变化图,按照从上向下的顺序,打磨方法包括以下步骤:Referring to FIG. 4 , it shows a state change diagram of the
第一步:准备去除了模封体210的样本200,样本200包括框架230与放置于框架230的正面的芯片220。Step 1: Prepare the
第二步:将样本200放置在承载片100上,承载片100具有第一表面110与第二表面120,其中第一表面110位于图示的上侧,第二表面120位于图示的下侧,样本200具体是通过框架230的背面与承载片100的第一表面110贴合。承载片100为硬质且厚度均一的片材,可以避免承载片100发生变形,同时能够作为基准实现样本200的水平放置,在一些具体实施例中,承载片100可以是金属片,例如铜片,铜片具有一定的强度以支撑样本200,同时硬度又不会过高而增加打磨难度,承载片100还可以是玻璃片或者陶瓷片,从而进一步避免变形,以及具有更高的平整度。需要说明的是,在保证能够水平支撑芯片220的基础上,承载片100应该尽可能地减薄,以减少后续打磨的工作量。Step 2: Place the
第三步:在芯片220的外侧面包覆隔离层300,此处所称芯片220的外侧面,是指除了芯片220背面的其他表面。隔离层300能够在设定条件下去除,便于取出打磨完成的样本200。Step 3: Cover the outer surface of the
第四步:在隔离层300的外侧面包覆增强层400,此处所称隔离层300的外侧面,是指除了隔离层300与框架230贴合的背面之外的其他表面。增强层400除了包覆隔离层300之外,还与承载片100连接,例如与承载片100的第一表面110连接,从而将承载片100、样本200、隔离层300与增强层400连接为整体的待打磨组件,增强层400的强度相对较高,能够承受一定的振动和冲击,因此可以作为打磨过程中实现上述待打磨组件与打磨设备连接的安装结构。Step 4: Coating the
需要说明的是,无论增强层400如何与承载片100连接,均需要保证承载片100的第二表面120露出,使得第二表面120能够作为基准面与打磨设备接触。It should be noted that no matter how the
第五步:以第二表面120作为打磨的起始位置,向芯片220的方向开始打磨,直至芯片220剩余的厚度满足设定厚度后停止打磨。具体是,将上述待打磨组件通过增强层400连接于打磨设备的驱动组件,使得第二表面120朝向打磨设备的打磨组件,然后调节待打磨组件的位置与姿态,使得第二表面120与打磨组件的打磨面保持平行并相互贴合,最后启动打磨设备,使得打磨组件相对待打磨组件之间发生相互转动,从而从第二表面120开始打磨,随着打磨的进行,待打磨组件的厚度降低,因此打磨设备的驱动组件还能够驱动待打磨组件朝打磨组件进给,使得打磨面与待打磨面时刻保持接触。Step 5: Using the
在一些具体实施例中,承载片100、样本200、隔离层300与增强层400共同形成的待打磨组件为圆柱体结构,打磨设备上的打磨组件相应包括适配该圆柱体的夹持机构。In some specific embodiments, the assembly to be polished jointly formed by the
打磨完成后的样本200如图所示,其中承载片100、框架230、芯片220的背侧部分、隔离层300的背侧部分与增强层400的背侧部分均已经通过打磨去除,芯片220的剩余部分通过隔离层300与增强层400连接。The
第六步:根据隔离层300的材料,选择相应的方式去除隔离层300,从而使芯片220与增强层400分离,至此,芯片220已经打磨完成,且能够与增强层400分离而进行后续的检测工作。Step 6: According to the material of the
本实施例的打磨方案具有以下优点:The grinding scheme of the present embodiment has the following advantages:
一、样本200的背面与承载片100的第一表面110贴合,二者之间不存在粘接剂,因此样本200不会因粘接剂厚度不均而相对承载片100歪斜。同时,以承载片100的第二表面120作为基准面与打磨设备的打磨面贴合,能够使样本200与承载片100不会相对打磨面歪斜,如此,能够使芯片220打磨后厚度均匀一致。1. The back of the
二、当采用图1、图2所示方式打磨时,芯片220的侧面暴露在外,芯片220相对于打磨装置移动的过程中,除了背面被打磨之外,芯片220的侧面也会被打磨,使得芯片220的底部侧边处形成如图5所示的倒角11,倒角11会导致红外线的反射与折射,从而导致成像不清晰。本实施例在芯片220的外表面(包括前述侧面)包覆隔离层300,使得隔离层300除了隔离芯片220与增强层400的作用之外,还能够起到保护芯片220底部侧边的作用,避免因倒角11影响检测结果。Two, when adopting Fig. 1, when the mode shown in Fig. 2 is polished, the side of
三、本实施例还设置有隔离层300,隔离层300位于芯片220与增强层400之间,其能够在设定条件下自芯片220上去除,从而实现芯片220与增强层400的分离,与增强层400直接连接芯片220的方式相比,能够显著降低增强层400与芯片220的分离难度,同时也能够避免在芯片220上发生残留。Three, the present embodiment is also provided with an
四、本实施例还设置有增强层400,增强层400相比于隔离层300具有更高的强度,能够承受更强的振动与冲击,因此以增强层400包覆隔离层300而形成待打磨组件,并以增强层400作为安装部件安装至打磨设备,与依靠隔离层300作为安装部件安装至打磨设备的方案相比,可以减少待打磨组件在打磨过程中发生碎裂、断裂的概率。4. The present embodiment is also provided with a reinforced
本发明第二实施例还提出了另一种打磨方法,其同样适用于具有框架230的样本200,其与第一实施例的区别在于:本实施例中的隔离层300除了包覆在芯片220之外,还包覆在框架230之外。The second embodiment of the present invention also proposes another grinding method, which is also applicable to the
参照图6,示出了依靠本发明第二实施例打磨方法打磨时样本200的状态变化图,包括以下步骤:Referring to FIG. 6 , it shows a state change diagram of the
第一步:准备去除了模封体210的样本200,样本200包括框架230与放置于框架230的正面的芯片220。Step 1: Prepare the
第二步:将样本200放置在承载片100上,使得框架230的背面与承载片100的第一表面110贴合。Step 2: Place the
第三步:在芯片220的外侧面与框架230的外侧面包覆隔离层300,且使得隔离层300与承载片100的第一表面110连接,从而将芯片220、框架230与承载片100连接在一起。此处所称框架230的外侧面,是指除了框架230的背面,以及框架230正面与芯片220贴合区域之外的其他表面。Step 3: Cover the outer surface of the
第四步:在隔离层300的外侧面包覆增强层400,且使得第二表面120露出以作为基准面与打磨设备接触。Step 4: Coating the
第五步:以第二表面120作为打磨的起始位置,向芯片220的方向开始打磨,直至芯片220剩余的厚度满足设定厚度后停止打磨。Step 5: Using the
第六步:根据隔离层300的材料,选择相应的方式去除隔离层300,从而使芯片220与增强层400分离,至此,芯片220已经打磨完成,且与增强层400分离而能够进行后续的检测工作。Step 6: According to the material of the
本实施例的打磨方案除了具有第一实施例中的优点之外,还具有以下优点:In addition to the advantages of the first embodiment, the grinding scheme of this embodiment also has the following advantages:
一、通常框架230超出芯片220部分的面积不会太大,如果以样品本身的框架作为后续打磨的基准面,则需将隔离层300限制在框架230范围内以防止隔离层溢到框架背面而影响样品打磨基准面的水平度,但此操作难度较大,而承载片100的面积不受限制,可以设置得较大,因此隔离层300同时覆盖芯片220与框架230更容易操作。1. Generally, the area of the
二、样本200与承载片100预先通过隔离层300固定,能够避免样本200与承载片100在包覆增强层400的过程发生移动。2. The
作为上述第二实施例的改进,隔离层300采用具有热熔性质的材料制成,从而能够通过先加热后固化的方式形成隔离层300,参照图7,本实施例设置隔离层300的方法包括:As an improvement of the second embodiment above, the
第一步:当样本200放置在承载片100上后,在芯片220的顶部施加固态的隔离材料。Step 1: After the
第二步:加热隔离材料,使隔离材料熔化并向下流动至承载片100的第一表面110,以覆盖芯片220与框架230。在一些具体实施例中,可以通过加热装置500加热隔离材料,加热装置500可以是图中具有水平加热面的加热台,承载片100的第二表面120与加热面贴合,加热台启动时,热量通过承载片100与样本200传递至隔离材料。Step 2: heating the isolation material to melt the isolation material and flow down to the
第三步:使熔融的隔离材料固化以形成隔离层300。例如,可以关闭加热装置500使得隔离材料自行固化,也可以通过外部的冷却装置加速其固化。Step 3: solidify the molten isolation material to form the
上述实施例利用隔离材料熔化后的流动自动包覆芯片220与框架230,实验人员无需进行其他操作,有助于简化工艺。In the above embodiment, the melted flow of the isolation material is used to automatically cover the
在一些具体实施例中,隔离层300的材料为石蜡,石蜡在常温下为固体,加热后能够融化,冷却后能够重新固化,因此可以满足前述加热时自动流动、冷却后固化的要求。另一方面,石蜡可以溶解于丙酮,从而实现隔离层300的去除,且去除过程中不会损伤芯片220,当石蜡溶解之后,芯片220将自动与增强层400分离。In some specific embodiments, the material of the
本实施例中,石蜡的加热温度为100℃至105℃,经过发明人验证,石蜡在该温度范围内具有一定的流动性,但是流动性不会过强,因此能够聚拢形成类似于图7所示的半球状结构,使得隔离层300保持一定的厚度以起到相应的隔离作用。In this example, the heating temperature of the paraffin wax is 100°C to 105°C. After verification by the inventors, the paraffin wax has a certain fluidity within this temperature range, but the fluidity is not too strong, so it can be gathered to form a wax similar to that shown in Figure 7. The shown hemispherical structure makes the
本发明第三实施例还提出了另一种打磨方法,其同样适用于具有框架230的样本200,其与第一实施例的区别在于:本实施例中的增强层400除了包覆在隔离层300之外,还包覆在承载片100除第二表面120之外的其他表面。The third embodiment of the present invention also proposes another grinding method, which is also applicable to the
参照图8,示出了依靠本发明第三实施例打磨方法打磨时样本200的状态变化图,包括以下步骤:Referring to FIG. 8 , it shows a state change diagram of the
第一步:准备去除了模封体210的样本200,样本200包括框架230与放置于框架230的正面的芯片220。Step 1: Prepare the
第二步:将样本200放置在承载片100上,使得框架230的背面与承载片100的第一表面110贴合。Step 2: Place the
第三步:在芯片220的外侧面包覆隔离层300。Step 3: coating the outer surface of the
第四步:在隔离层300的外侧面,以及承载片100除第二表面120之外的外侧面包覆增强层400,且使得第二表面120露出以作为基准面与打磨设备接触。Step 4: Cover the outer surface of the
第五步:以第二表面120作为打磨的起始位置,向芯片220的方向开始打磨,直至芯片220剩余的厚度满足设定厚度后停止打磨。Step 5: Using the
第六步:根据隔离层300的材料,选择相应的方式去除隔离层300,从而使芯片220与增强层400分离,至此,芯片220已经打磨完成,且与增强层400分离而能够进行后续的检测工作。Step 6: According to the material of the
本实施例的打磨方案除了具有第一实施例中的优点之外,还具有以下优点:承载片100嵌设于增强层400内,能够增加承载片100与增强层400之间的连接强度,避免打磨过程中承载片100与增强层400发生脱离。In addition to the advantages of the first embodiment, the grinding scheme of this embodiment also has the following advantages: the
作为上述第三实施例的改进,参照图9,本实施例设置增强层400的方法包括以下步骤:As an improvement of the third embodiment above, referring to FIG. 9 , the method for setting the
第一步:设置具有容置腔610的模具600,模具600的底部封闭,顶部具有开口。将承载有样本200的承载片100放置于模具600内,使第二表面120与容置腔610的底壁贴合。Step 1: Set up a
第二步:向容置腔610内添加液态的增强材料,液态的增强材料能够自动填充容置腔610,直至液面高于隔离层300。Step 2: Add liquid reinforcement material into the
第三步:使液态的增强材料固化以形成增强层400后,使增强层400与模具600脱离。Step 3: After the liquid reinforcement material is solidified to form the
上述实施例通过容置腔610的底壁遮挡第二表面120,能够避免第二表面120黏附增强材料,此外,增强层400与第二表面120齐平设置,便于以第二表面120作为基准面进行打磨。In the above embodiment, the
在一些具体实施例中,增强层400的材料为树脂,相对于石蜡,树脂具有更高的强度,能够抵御打磨过程中的冲击与震动。In some specific embodiments, the material of the reinforcing
需要说明的是,上述第二实施例至第三实施例可以组合,参照图10,本发明第四实施例中的隔离层300包覆在芯片220与框架230的外侧,增强层400包覆在隔离层300的外侧,以及承载片100除第二表面120之外的其他表面,从而具有上述第一实施例至第三实施例的优点。It should be noted that the above-mentioned second embodiment to the third embodiment can be combined. Referring to FIG. The outer side of the
本发明第四实施例还提出了另一种打磨方法,其与第一实施例至第三实施例区别在于:本实施例适用于芯片220的直接打磨,也即,样本200来料即为裸芯片,因此不需要进行前面的去除模封体210的步骤。The fourth embodiment of the present invention also proposes another polishing method, which differs from the first to third embodiments in that this embodiment is suitable for direct polishing of the
参照图11,示出了依靠本发明第五实施例打磨方法打磨时样本200的状态变化图,包括以下步骤:Referring to FIG. 11 , it shows a state change diagram of the
第一步:准备待打磨的芯片220。Step 1: Prepare the
第二步:将芯片220直接放置在承载片100上,使得芯片220的背面与承载片100的第一表面110贴合。Step 2: Place the
第三步:在芯片220的外侧面包覆隔离层300,隔离层300与承载片100的第一表面110连接,从而将芯片220与承载片100连接在一起。Step 3: Cover the outer surface of the
第四步:在隔离层300的外侧面包覆增强层400,增强层400与承载片100的第一表面110连接,承载片100的第二表面120露出以作为基准面与打磨设备接触。Step 4: Coating the
第五步:以第二表面120作为打磨的起始位置,向芯片220的方向开始打磨,直至芯片220剩余的厚度满足设定厚度后停止打磨。Step 5: Using the
第六步:根据隔离层300的材料,选择相应的方式去除隔离层300,从而使芯片220与增强层400分离,至此,芯片220已经打磨完成,且与增强层400分离而能够进行后续的检测工作。Step 6: According to the material of the
本实施例的打磨方案除了具有第一实施例中的优点之外,无需通过打磨的方式去除框架230,因此能够减少打磨的工作量。In addition to the advantages of the first embodiment, the grinding scheme of this embodiment does not need to remove the
本发明第六实施例还提出了另一种打磨方法,其与第一实施例至第三实施例区别在于:本实施例适用于带有模封体210的样本200的直接打磨,例如,样本200来料为完整的功率模块,不需要进行前面的去除模封体210的步骤。The sixth embodiment of the present invention also proposes another grinding method, which differs from the first to third embodiments in that this embodiment is suitable for direct grinding of a
参照图12,示出了依靠本发明第五实施例打磨方法打磨时样本200的状态变化图,包括以下步骤:Referring to FIG. 12 , it shows a state change diagram of the
第一步:准备待打磨的样本200,样本200包括模封体210,以及位于模封体210内的芯片220与框架230,芯片220放置于框架230的正面。Step 1: Prepare the
第二步:将样本200放置在承载片100上,使得样本200的背面与承载片100的第一表面110贴合。Step 2: Place the
第三步:在样本200的外侧面包覆隔离层300,隔离层300与承载片100的第一表面110连接,从而将样本200与承载片100连接在一起。Step 3: Cover the outer surface of the
第四步:在隔离层300的外侧面包覆增强层400,增强层400与承载片100的第一表面110连接,承载片100的第二表面120露出以作为基准面与打磨设备接触。Step 4: Coating the
第五步:以第二表面120作为打磨的起始位置,向芯片220的方向开始打磨,直至芯片220剩余的厚度满足设定厚度后停止打磨。Step 5: Using the
第六步:根据隔离层300的材料,选择相应的方式去除隔离层300,从而使芯片220与增强层400分离,至此,芯片220已经打磨完成,且与增强层400分离而能够进行后续的检测工作。Step 6: According to the material of the
需要说明的是,在上述各实施例中,样本200或者芯片220的打磨通过砂纸完成,具体是通过目数逐渐增加的砂纸分别打磨承载片100、框架230与芯片220,其中,砂纸的目数越低,单次摩擦的去除量越大,打磨速度越快,打磨面越粗糙,砂纸的目数越高,单次摩擦的去除量越小,打磨速度越慢,打磨面越光滑。基于上述,当打磨承载片100时,由于其距离芯片220较远,因此可以采用目数较低的砂纸进行快速打磨;当打磨框架230时,由于框架230与芯片220相邻设置,因此采用目数相对较高的砂纸打磨,保证一定打磨速度的前提下,能够在打磨至接近芯片220时避免对芯片220的损伤;当打磨芯片220时,采用目数最高的砂纸打磨,从而保证打磨面的打磨质量。通过在不同阶段采用不同的砂纸打磨,能够兼顾打磨速度与打磨质量。It should be noted that, in the above-mentioned embodiments, the polishing of the
例如,打磨承载片100时,可以采用180目的砂纸,打磨框架230时,可以采用400目的砂纸,当打磨芯片220时,可以采用800目的砂纸。For example, when polishing the
需要说明的是,可以根据已打磨的厚度或者目视观察的方式判断打磨阶段。It should be noted that the grinding stage can be judged according to the polished thickness or visual observation.
上面结合附图对本发明实施例作了详细说明,但是本发明不限于上述实施例,在所属技术领域普通技术人员所具备的知识范围内,还可以在不脱离本发明宗旨的前提下作出各种变化。此外,在不冲突的情况下,本发明的实施例及实施例中的特征可以相互组合。The embodiments of the present invention have been described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned embodiments. Within the scope of knowledge of those skilled in the art, various modifications can be made without departing from the spirit of the present invention. Variety. In addition, the embodiments of the present invention and the features in the embodiments can be combined with each other if there is no conflict.
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210980506.8A CN115592488A (en) | 2022-08-16 | 2022-08-16 | Chip polishing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210980506.8A CN115592488A (en) | 2022-08-16 | 2022-08-16 | Chip polishing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115592488A true CN115592488A (en) | 2023-01-13 |
Family
ID=84842691
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210980506.8A Pending CN115592488A (en) | 2022-08-16 | 2022-08-16 | Chip polishing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115592488A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6395580B1 (en) * | 1999-11-29 | 2002-05-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Backside failure analysis for BGA package |
| CN102253325A (en) * | 2010-05-21 | 2011-11-23 | 中芯国际集成电路制造(上海)有限公司 | Method for analyzing chip failure |
| CN202870249U (en) * | 2012-09-17 | 2013-04-10 | 上海华力微电子有限公司 | Chip back thinning device used for failure analysis |
| CN106338684A (en) * | 2016-11-09 | 2017-01-18 | 上海华力微电子有限公司 | Failure analysis method |
| CN110031277A (en) * | 2019-04-29 | 2019-07-19 | 武汉光迅科技股份有限公司 | A kind of chip sample production method for failure analysis |
-
2022
- 2022-08-16 CN CN202210980506.8A patent/CN115592488A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6395580B1 (en) * | 1999-11-29 | 2002-05-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Backside failure analysis for BGA package |
| CN102253325A (en) * | 2010-05-21 | 2011-11-23 | 中芯国际集成电路制造(上海)有限公司 | Method for analyzing chip failure |
| CN202870249U (en) * | 2012-09-17 | 2013-04-10 | 上海华力微电子有限公司 | Chip back thinning device used for failure analysis |
| CN106338684A (en) * | 2016-11-09 | 2017-01-18 | 上海华力微电子有限公司 | Failure analysis method |
| CN110031277A (en) * | 2019-04-29 | 2019-07-19 | 武汉光迅科技股份有限公司 | A kind of chip sample production method for failure analysis |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101017786B (en) | Manufacturing method of semiconductor package | |
| US8106495B2 (en) | Semiconductor apparatus and manufacturing method thereof | |
| US8101527B2 (en) | Dicing film having shrinkage release film and method for manufacturing semiconductor package using the same | |
| US7969026B2 (en) | Flexible carrier for high volume electronic package fabrication | |
| KR20100065185A (en) | Method for producing semiconductor chip with adhesive film, adhesive film for semiconductor used in the method, and method for producing semiconductor device | |
| TW201108308A (en) | Manufacturing method of semiconductor device and semiconductor device | |
| CN111207973A (en) | Unsealing method of chip | |
| CN102496596B (en) | Wafer bearing structure and preparation method thereof, and wafer thinning method | |
| KR20060059825A (en) | Attaching device of support plate | |
| CN115592488A (en) | Chip polishing method | |
| KR101099248B1 (en) | Supporting plate attaching method | |
| KR101977203B1 (en) | Underfill method of semiconductor package | |
| TWI357104B (en) | Wafer grinding method | |
| JP2000164535A (en) | Laser processing equipment | |
| CN117524891A (en) | High-power chip packaging bonding method and chip packaging piece | |
| JP2002110736A (en) | Semiconductor device and manufacturing method thereof | |
| KR102734775B1 (en) | Method for machining wafer | |
| CN209045534U (en) | Chip plastic package structure and wafer chip level plastic package structure | |
| CN101295655A (en) | Flat plate/wafer structure packaging equipment and method thereof | |
| CN101211791A (en) | Wafer level chip packaging process and chip packaging structure | |
| CN221302804U (en) | Sampling mechanism | |
| CN111668117B (en) | Packaging method of semiconductor module and two structures in packaging process of semiconductor module | |
| CN117613107A (en) | A packaging structure and packaging method for a high-reliability sensor | |
| CN115139216B (en) | Grinding and polishing method for sharp corner of chip | |
| CN114006160B (en) | Liquid crystal antenna and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |