CN115629926B - Control system, method and device based on joint test working group interface - Google Patents

Abstract

The embodiment of the application provides a control system, a method and a device based on a joint test work group (JTAG) interface, wherein the control system based on the JTAG interface comprises: the JTAG connector comprises a first JTAG interface and a second JTAG interface; the first processing device comprises a first JTAG input interface and a first JTAG output interface; the first control device comprises a second JTAG input interface and a second JTAG output interface, and the second JTAG output interface is connected with the second JTAG interface; and the first gating module is respectively connected with the first JTAG interface, the first JTAG output interface and the second JTAG input interface.

Description

Control system, method and device based on joint test working group interface

technical field

The embodiments of the present application relate to the computer field, and in particular, relate to a control system, method and device based on the Joint Test Working Group JTAG interface.

Background technique

FPGA (Field Programmable Gate Array, Field Programmable Gate Array) chip has customizability, low latency and high performance per power ratio, and is widely used in machine learning reasoning, image speech recognition, big data analysis, storage virtualization, etc. . FPGA chips often require different power supplies to meet certain power-on sequence requirements.

In the prior art, a CPLD (Complex Programmable Logic Device) chip is often used to control the power-on sequence of the FPGA, and the JTAG (Joint Test Action Group) interface between the FPGA and the CPLD is often used in a chrysanthemum The connection mode of the chain realizes the control and debugging of multiple JTAG logic devices by a single JTAG connector interface. This method may cause the FPGA to fail to power on normally when there is no program in the CPLD or the program is wrong, which will cause the JTAG link between the CPLD and FPGA to fail, and the JTAG connector will not be able to connect to the CPLD, and thus cannot be updated. CPLD program.

In the related art, when the power-on sequence of the FPGA chip is controlled by the CPLD chip and the power-on of the FPGA chip is not completed, the technical problem that the CPLD cannot be connected to the JTAG connector has not yet been proposed.

Contents of the invention

The embodiment of the present application provides a control system, method and device based on the JTAG interface of the joint test working group, to at least solve the problem of CPLD chip controlling the power-on sequence of the FPGA chip and the power-on sequence of the FPGA chip in the related art. Problem with not being able to connect with the JTAG connector.

According to one embodiment of the present application, a control system based on the Joint Test Working Group JTAG interface is provided, including: a JTAG connector, the JTAG connector includes a first JTAG interface and a second JTAG interface, wherein the first A JTAG interface is used to send data, and the second JTAG interface is used to receive data; the first processing device, the first processing device includes a first JTAG input interface and a first JTAG output interface; the first control device, the The first control device includes a second JTAG input interface and a second JTAG output interface, the second JTAG output interface is connected to the second JTAG interface, wherein the first control device is used to control the first processing device the power-on; the first gating module is respectively connected with the first JTAG interface, the first JTAG output interface and the second JTAG input interface, wherein the first gating module is used for the When the first processing device is not powered on, connect the first JTAG interface to the second JTAG input interface, and when the first processing device is powered on, disconnect the first JTAG The interface is connected to the second JTAG input interface, and the first JTAG output interface is connected to the second JTAG input interface.

In an exemplary embodiment, it further includes: a first power supply connected to the first control device, the first gating module and the first processing device, wherein the first power supply is used for When the first processing device is not powered on, output the first control signal to the first gating module, and when the first processing device is powered on, output the first control signal to the first gating module Outputting a second control signal, wherein the first control signal is used to control the first gating module to connect the first JTAG interface to the second JTAG input interface, and the second control signal is used to control The first gating module disconnects the connection between the first JTAG interface and the second JTAG input interface, and connects the first JTAG output interface to the second JTAG input interface; wherein, the first A control device is used to control the power-on of the first processing device through the first power supply.

In an exemplary embodiment, the first control device is configured to output a third control signal to the first power supply when the first processing device is powered on, wherein the third control signal It is used to control the first power supply to supply power to the first processing device.

In an exemplary embodiment, the first power supply includes: a first power-on detection module, wherein the first power-on detection module is used to detect whether the first processing device is powered on; the first control signal An output module, connected to the first power-on detection module, wherein the first control signal output module is used to detect that the first processing device has not been powered on when the first power-on detection module detects , outputting the first control signal to the first gating module, and sending the first control signal to the first gating module when the first power-on detection module detects that the first processing device is powered on outputting the second control signal.

In an exemplary embodiment, the first JTAG input interface is connected to the first JTAG interface.

In an exemplary embodiment, it also includes: a second processing device, wherein the first JTAG interface is connected to the JTAG input interface of the second processing device, and the first JTAG input interface is connected to the second processing device The JTAG output interface of the device is connected; or the second processing device and the third processing device, wherein, the first JTAG interface is connected with the JTAG input interface of the second processing device, and the JTAG output interface of the second processing device is connected with The JTAG input interface of the third processing device is connected, and the first JTAG input interface is connected to the JTAG output interface of the third processing device; or N processing devices, wherein N is a positive integer greater than 2, and the The first JTAG interface is connected to the JTAG input interface of the first processing device in the N processing devices, and the JTAG input interface of the i-th processing device in the N processing devices is connected to the JTAG input interface of the N processing devices. The JTAG output interface of the i-1th processing device is connected, the JTAG output interface of the i-th processing device in the N processing devices is connected to the JTAG input interface of the i+1-th processing device in the N processing devices connected, the first JTAG input interface is connected to the JTAG output interface of the Nth processing device among the N processing devices, and i is a positive integer greater than or equal to 2 and less than N.

In an exemplary embodiment, it also includes: a second processing device, the second processing device includes a third JTAG input interface and a third JTAG output interface, and the third JTAG input interface is connected to the first JTAG interface ; The second gating module is respectively connected with the first JTAG interface, the third JTAG output interface and the first JTAG input interface, wherein the second gating module is used to process the When the device is not powered on, connect the first JTAG interface to the first JTAG input interface, and when the second processing device is powered on, disconnect the first JTAG interface from the first JTAG input interface. The first JTAG input interface is connected, and the third JTAG output interface is connected to the first JTAG input interface.

In an exemplary embodiment, it further includes: a second power supply connected to the first control device, the second gating module and the second processing device, wherein the second power supply is used for When the second processing device is not powered on, output a fourth control signal to the second gating module, and when the second processing device is powered on, output the fourth control signal to the second gating module Outputting a fifth control signal, wherein the fourth control signal is used to control the second gating module to connect the first JTAG interface to the first JTAG input interface, and the fifth control signal is used to control The second gating module disconnects the connection between the first JTAG interface and the first JTAG input interface, and connects the third JTAG output interface to the first JTAG input interface; wherein, the first A control device is used to control the power-on of the second processing device through the second power supply.

In an exemplary embodiment, the first control device is configured to output a sixth control signal to the second power supply when the second processing device is powered on, wherein the sixth control signal It is used to control the second power supply to supply power to the second processing device.

In an exemplary embodiment, the second power supply includes: a second power-on detection module, wherein the second power-on detection module is used to detect whether the second processing device is powered on; the second control signal An output module connected to the second power-on detection module, wherein the second control signal output module is used to detect that the second processing device has not been powered on when the second power-on detection module detects , outputting the fourth control signal to the second gating module, and sending the fourth control signal to the second gating module when the second power-on detection module detects that the second processing device is powered on outputting the fifth control signal.

In an exemplary embodiment, the interface level required by the first JTAG input interface and the first JTAG output interface is the same as that required by the second JTAG input interface and the second JTAG output interface.

In an exemplary embodiment, the first processing device is a field programmable gate array FPGA device, and the first control device is a complex programmable logic device CPLD.

In an exemplary embodiment, the first gating module includes one of the following: a switch control device, and a triode switch control circuit.

In an exemplary embodiment, the JTAG connector further includes a third JTAG interface and a fourth JTAG interface, wherein the third JTAG interface is used to transmit a clock signal, and the fourth JTAG interface is used for transmission mode selection signal, the first processing device is connected to the third JTAG interface and the fourth JTAG interface, and the first control device is connected to the third JTAG interface and the fourth JTAG interface.

According to another embodiment of the present application, a control method based on the JTAG interface of the joint test working group is provided, including: when the first processing device in the control system based on the JTAG chain is not powered on, through the The first gating module in the control system connects the first JTAG interface with the second JTAG input interface; when the first processing device is powered on, disconnect the first JTAG interface through the first gating module. JTAG interface and the connection of described second JTAG input interface, and the first JTAG output interface is connected with described second JTAG input interface; Wherein, described control system comprises: JTAG connector, and described JTAG connector comprises described The first JTAG interface and the second JTAG interface; the first processing device, the first processing device includes a first JTAG input interface and the first JTAG output interface; a first control device, the first control device includes The second JTAG input interface and the second JTAG output interface, the second JTAG output interface is connected to the second JTAG interface, wherein the first control device is used to control the power-on of the first processing device ; The first gating module is respectively connected to the first JTAG interface, the first JTAG output interface and the second JTAG input interface.

In an exemplary embodiment, when the first processing device in the control system based on the JTAG chain has not been powered on, the first JTAG interface and the second Two JTAG input interface connections, including: when the first processing device is not powered on, output a first control signal to the first gating module through the first power supply, wherein the first control signal is used Controlling the first gating module to connect the first JTAG interface to the second JTAG input interface; in response to the first control signal, connecting the first JTAG interface to the first JTAG input interface through the first gating module Connected to the second JTAG input interface; when the first processing device is powered on, disconnect the first JTAG interface and the second JTAG input interface through the first gating module connection, and connecting the first JTAG output interface with the second JTAG input interface, including: when the first processing device is powered on, sending the first gating module through the first power supply Outputting a second control signal, wherein the second control signal is used to control the first gating module to disconnect the first JTAG interface from the second JTAG input interface, and connect the first JTAG The output interface is connected to the second JTAG input interface; in response to the second control signal, the connection between the first JTAG interface and the second JTAG input interface is disconnected through the first gating module, and the The first JTAG output interface is connected to the second JTAG input interface; wherein, the control system further includes: the first power supply, the first control device, the first gating module and the The first processing device is connected; wherein, the first control device is configured to control power-on of the first processing device through the first power supply.

In an exemplary embodiment, the method further includes: when the first processing device is powered on, outputting a third control signal to the first power supply through the first control device, wherein the third The control signal is used to control the first power supply to supply power to the first processing device; in response to the third control signal, the first power supply supplies power to the first processing device.

In an exemplary embodiment, the method further includes: using a first power-on detection module in the first power supply to detect whether the first processing device is powered on; When the first processing device is not powered on, output the first control signal to the first gating module through the first control signal output module in the first power supply; When the power-on detection module detects that the first processing device is powered on, the second control signal is output to the first gating module through the first control signal output module.

According to yet another embodiment of the present application, a control device based on the joint test working group JTAG interface is provided, including: a first connection module, which is used to complete the first processing device in the control system based on the JTAG chain without being powered on In the case of the first gating module in the control system, the first JTAG interface is connected to the second JTAG input interface; the second connection module is used to complete the power-on of the first processing device, Disconnect the connection between the first JTAG interface and the second JTAG input interface through the first gating module, and connect the first JTAG output interface to the second JTAG input interface; wherein, the control system Including: a JTAG connector, the JTAG connector includes the first JTAG interface and a second JTAG interface; the first processing device, the first processing device includes a first JTAG input interface and the first JTAG output Interface; a first control device, the first control device includes the second JTAG input interface and the second JTAG output interface, the second JTAG output interface is connected to the second JTAG interface, wherein the first The control device is used to control the power-on of the first processing device; the first gating module is respectively connected to the first JTAG interface, the first JTAG output interface and the second JTAG input interface.

According to yet another embodiment of the present application, a computer-readable storage medium is also provided, and a computer program is stored in the computer-readable storage medium, wherein the computer program is configured to perform any one of the above-mentioned methods when running Steps in the examples.

According to yet another embodiment of the present application, there is also provided an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to perform any of the above Steps in the method examples.

Through the embodiment of this application, since the CPLD device (ie, the first control device) controls the power-on sequence of the FPGA device (ie, the first processing device), during the power-on process of the FPGA device, the first gating module can be used to realize the connection with JTAG The switching of the device connected with the connector; and regardless of whether the FPGA device is powered on or not, the connection between the CPLD device and the JTAG connector can be realized through the first gating module. Therefore, it can solve the problem that the CPLD cannot be connected to the JTAG connector when the CPLD chip controls the power-on sequence of the FPGA chip and the power-on of the FPGA chip is not completed, and then achieves the control of the power-on sequence of the FPGA chip by the CPLD chip and the power-on sequence of the FPGA chip. In the case that the electricity is not completed, the effect of the connection between the CPLD and the JTAG connector is guaranteed.

Description of drawings

Fig. 1 is a kind of block diagram one based on the control system of joint test working group JTAG interface according to the embodiment of the application;

Fig. 2 is the structural block diagram two of a kind of control system based on joint test working group JTAG interface according to the embodiment of the application;

Fig. 3 is the structural block diagram three of a kind of control system based on joint test working group JTAG interface according to the embodiment of the application;

Fig. 4 is a structural block diagram four of a control system based on a JTAG interface of a joint test working group according to an embodiment of the present application;

Fig. 5 is a structural block diagram five of a control system based on the joint test working group JTAG interface according to an embodiment of the present application;

Fig. 6 is a structural block diagram six of a control system based on a joint test working group JTAG interface according to an embodiment of the present application;

Fig. 7 is a structural block diagram seven of a control system based on a joint test working group JTAG interface according to an embodiment of the present application;

Fig. 8 is a structural block diagram eight of a control system based on a joint test working group JTAG interface according to an embodiment of the present application;

FIG. 9 is a structural block diagram nine of a control system based on a joint test working group JTAG interface according to an embodiment of the present application;

Fig. 10 is a structural block diagram of an FPGA accelerator card according to an embodiment of the present application;

Fig. 11 is a structural block diagram ten of a control system based on a joint test working group JTAG interface according to an embodiment of the present application;

12 is a schematic diagram of a connection between a CPLD and an FPGA and a JTAG connector according to an embodiment of the present application;

13 is a schematic diagram of a connection between a JTAG connector and a CPLD according to an embodiment of the present application;

14 is a second schematic diagram of a connection between a CPLD, an FPGA, and a JTAG connector according to an embodiment of the present application;

FIG. 15 is a schematic diagram of a connection between a CPLD, an FPGA, and a JTAG connector according to an embodiment of the present application;

FIG. 16 is a block diagram of the hardware structure of a mobile terminal based on the control method of the joint test working group JTAG interface according to the embodiment of the present application;

Fig. 17 is the flow chart of the control method based on joint test working group JTAG interface according to the embodiment of the present application;

Fig. 18 is a structural block diagram of a control device based on a joint test working group JTAG interface according to an embodiment of the present application.

Detailed ways

Embodiments of the present application will be described in detail below with reference to the drawings and in combination with the embodiments.

It should be noted that the terms "first" and "second" in the description and claims of the embodiments of the present application and the above drawings are used to distinguish similar objects, and not necessarily used to describe a specific order or sequence order.

In the embodiment of the present application, a control system based on the joint test working group JTAG interface is provided. FIG. 1 is a structural block diagram one of a control system based on the joint test working group JTAG interface according to the embodiment of the present application, as shown in FIG. 1 As shown, the control system includes: JTAG connector 102, the JTAG connector 102 includes TDI (Test Data Input, test data input) interface 102-1 (ie the first JTAG interface), TDO (Test Data Output, test data Output) interface 102-2 (that is, the second JTAG interface) TCK (Test Clock, test clock) interface and TMS (Test Mode Select, test mode selection) interface, wherein, TDI interface 102-1 is used to send data, TDO interface 102 -2 is used to receive data; the first processing device 108, the first processing device 108 includes a TDI interface 108-1 (ie the first JTAG input interface) and a TDO interface 108-2 (ie the first JTAG output interface); the first A control device 104, the first control device 104 includes a TDI interface 104-1 (ie the second JTAG input interface) and a TDO interface 104-2 (ie the second JTAG output interface), the TDO interface 104-2 and the TDO interface 102 -2 connections, wherein the first control device 104 is used to control the power-on of the first processing device 108; the first gating module 106 includes pin 1, pin 2 and pin 3, pin 1, pin 2 and pin 3 are respectively connected to the TDI interface 104-1, the TDI interface 102-1 and the TDO interface 108-2, wherein the first gating module 106 is used to, when the first processing device 108 is not powered on, Connect the TDI interface 102-1 to the TDI interface 104-1 (that is, connect pin 1 to pin 2), and disconnect the TDI interface 102-1 from the TDI interface 104 when the first processing device is powered on -1, and connect the TDO interface 108-2 with the TDI interface 104-1 (that is, connect pin 1 and pin 3).

It should be noted that, in Fig. 1, the structure of the control system based on the joint test working group JTAG interface in the embodiment of the present application is explained only with the gating module including the switching device, and the embodiment of the present application only uses the gating module structure and the devices included are not limited. The gating module in the embodiment of the present application can be understood with reference to the gating module in FIG. 1 .

In an exemplary embodiment, the above control system further includes: a first power supply connected to the first control device, the first gating module, and the first processing device, wherein the first power supply uses Outputting a first control signal to the first gating module when the power-on of the first processing device is not completed, and outputting a first control signal to the first gate module when the power-on of the first processing device is completed The gating module outputs a second control signal, wherein the first control signal is used to control the first gating module to connect the first JTAG interface to the second JTAG input interface, and the second control signal Used to control the first gating module to disconnect the first JTAG interface from the second JTAG input interface, and connect the first JTAG output interface to the second JTAG input interface; wherein, The first control device is configured to control power-on of the first processing device through the first power supply.

Optionally, in this embodiment, Fig. 2 is a structural block diagram two of a control system based on a joint test working group JTAG interface according to an embodiment of the present application. As shown in Fig. 2, the above-mentioned control system includes: a JTAG connector 102. The JTAG connector 102 includes a TDI interface 102-1 (ie, the first JTAG interface) and a TDO interface 102-2 (ie, the second JTAG interface), wherein the TDI interface 102-1 is used to send data, and the TDO interface 102-2 For receiving data; the first processing device 108, the first processing device 108 includes a TDI interface 108-1 (ie, the first JTAG input interface) and a TDO interface 108-2 (ie, the first JTAG output interface); the first control device 104 , the first control device 104 includes a TDI interface 104-1 (ie, the second JTAG input interface) and a TDO interface 104-2 (ie, the second JTAG output interface), and the TDO interface 104-2 is connected to the TDO interface 102-2, wherein, The first control device 104 is used to control the power on of the first processing device 108; the first gating module 106 is connected to the TDI interface 104-1, the TDI interface 102-1 and the TDO interface 108-2, wherein the first gating The module 106 is used to connect the TDI interface 102-1 to the TDI interface 104-1 when the first processing device 108 is not powered on, and disconnect the TDI interface 102-1 when the first processing device is powered on. 1. Connect with the TDI interface 104-1, and connect the TDO interface 108-2 with the TDI interface 104-1; the first power supply 110 is connected with the first control device 104, the first gating module 106 and the first processing device 108 .

In an exemplary embodiment, the first control device is configured to output a third control signal to the first power supply when the first processing device is powered on, wherein the third control signal It is used to control the first power supply to supply power to the first processing device.

Optionally, in this embodiment, but not limited to, when the first control device is powered on, outputting a third control signal to the first power supply can further control the time for the first power supply to supply power to the first processing device and the sequence realize the control of the power-on sequence of the first processing device by the first control device.

In an exemplary embodiment, the first power supply includes: a first power-on detection module, wherein the first power-on detection module is used to detect whether the first processing device is powered on; the first control signal An output module, connected to the first power-on detection module, wherein the first control signal output module is used to detect that the first processing device has not been powered on when the first power-on detection module detects , outputting the first control signal to the first gating module, and sending the first control signal to the first gating module when the first power-on detection module detects that the first processing device is powered on outputting the second control signal.

In an exemplary embodiment, the first JTAG input interface is connected to the first JTAG interface.

Optionally, in this embodiment, FIG. 3 is a structural block diagram three of a control system based on a joint test working group JTAG interface according to an embodiment of the present application. As shown in FIG. 3, the above-mentioned control system includes: a JTAG connector 102. The JTAG connector 102 includes a TDI interface 102-1 (ie, the first JTAG interface) and a TDO interface 102-2 (ie, the second JTAG interface), wherein the TDI interface 102-1 is used to send data, and the TDO interface 102-2 For receiving data; the first processing device 108, the first processing device 108 includes a TDI interface 108-1 (ie the first JTAG input interface) and a TDO interface 108-2 (ie the first JTAG output interface), the first JTAG input interface 108-1 is connected to the first JTAG interface 102-1; the first control device 104, the first control device 104 includes a TDI interface 104-1 (ie the second JTAG input interface) and a TDO interface 104-2 (ie the second JTAG output interface), the TDO interface 104-2 is connected to the TDO interface 102-2, wherein the first control device 104 is used to control the power on of the first processing device 108; the first gating module 106 is connected to the TDI interface 104-1, TDI The interface 102-1 is connected to the TDO interface 108-2, wherein the first gating module 106 is configured to connect the TDI interface 102-1 to the TDI interface 104-1 when the first processing device 108 is not powered on, When the first processing device is powered on, disconnect the connection between the TDI interface 102-1 and the TDI interface 104-1, and connect the TDO interface 108-2 to the TDI interface 104-1; the first power supply 110, and the second A control device 104, a first gating module 106 and a first processing device 108 are connected, and the first power supply 110 includes a first power-on detection module 110-1 and a first control signal output module 110-2, wherein the first power-on The detection module 110-1 is connected to the first control signal output module 110-2, the first control signal output module 110-2 is connected to the first gating module 106, the first power-on detection module 110-1 is connected to the first processing device 108 connect.

In an exemplary embodiment, the above-mentioned control device may also include one of the following situations:

Case 1: the second processing device, wherein the first JTAG interface is connected to the JTAG input interface of the second processing device, and the first JTAG input interface is connected to the JTAG output interface of the second processing device.

Optionally, in this embodiment, FIG. 4 is a structural block diagram four of a control system based on a joint test working group JTAG interface according to an embodiment of the present application. As shown in FIG. 4, the control system includes: a JTAG connector 102, the JTAG connector 102 includes a TDI interface 102-1 (i.e. the first JTAG interface) and a TDO interface 102-2 (i.e. the second JTAG interface), wherein the TDI interface 102-1 is used to send data, and the TDO interface 102 -2 is used to receive data; the first processing device 108, the first processing device 108 includes a TDI interface 108-1 (ie the first JTAG input interface) and a TDO interface 108-2 (ie the first JTAG output interface); the first Two processing devices 112, the second processing device 112 includes a JTAG input interface 112-1 and a JTAG output interface 112-2; the JTAG input interface 112-1 is connected to the TDI interface 102-1, and the JTAG output interface 112-2 is connected to the TDI interface 108-1 connection; the first control device 104, the first control device 104 includes a TDI interface 104-1 (ie the second JTAG input interface) and a TDO interface 104-2 (ie the second JTAG output interface), the TDO interface 104 -2 is connected to the TDO interface 102-2, wherein the first control device 104 is used to control the power-on of the first processing device 108; the first gating module 106 is connected to the TDI interface 104-1 and the TDI interface 102-1 respectively And the TDO interface 108-2 connection, wherein the first gating module 106 is used to connect the TDI interface 102-1 to the TDI interface 104-1 when the first processing device 108 has not been powered on. When the processing device is powered on, the connection between the TDI interface 102-1 and the TDI interface 104-1 is disconnected, and the TDO interface 108-2 is connected to the TDI interface 104-1.

Situation 2: a second processing device and a third processing device, wherein the first JTAG interface is connected to the JTAG input interface of the second processing device, and the JTAG output interface of the second processing device is connected to the third processing device connected to the JTAG input interface of the device, and the first JTAG input interface is connected to the JTAG output interface of the third processing device.

Optionally, in this embodiment, FIG. 5 is a structural block diagram five of a control system based on a joint test working group JTAG interface according to an embodiment of the present application. As shown in FIG. 5, the control system includes: a JTAG connector 102, the JTAG connector 102 includes a TDI interface 102-1 (i.e. the first JTAG interface) and a TDO interface 102-2 (i.e. the second JTAG interface), wherein the TDI interface 102-1 is used to send data, and the TDO interface 102 -2 for receiving data; the first processing device 108, the second processing device 112 and the third processing device 114, the first processing device 108 includes a TDI interface 108-1 (ie the first JTAG input interface) and a TDO interface 108 -2 (ie the first JTAG output interface); the second processing device 112 includes a JTAG input interface 112-1 and a JTAG output interface 112-2; the third processing device 114 includes a JTAG input interface 114-1 and a JTAG output interface 114-2 The first JTAG interface 102-1 is connected to the JTAG input interface 112-1 of the second processing device 112, and the JTAG output interface 112-2 of the second processing device 112 is connected to the JTAG output interface 112 of the third processing device 114; The JTAG input interface 114 - 1 is connected, and the first JTAG input interface 108 - 1 is connected to the JTAG output interface 114 - 2 of the third processing device 114 .

The first control device 104, the first control device 104 includes a TDI interface 104-1 (ie the second JTAG input interface) and a TDO interface 104-2 (ie the second JTAG output interface), the TDO interface 104-2 and the TDO interface 102-2, wherein the first control device 104 is used to control the power on of the first processing device 108; the first gating module 106 is connected with the TDI interface 104-1, the TDI interface 102-1 and the TDO interface 108- 2 connections, wherein the first gating module 106 is used to connect the TDI interface 102-1 to the TDI interface 104-1 when the first processing device 108 is not powered on, and the first processing device is powered on When finished, disconnect the TDI interface 102-1 from the TDI interface 104-1, and connect the TDO interface 108-2 to the TDI interface 104-1.

Situation 3: N processing devices, wherein N is a positive integer greater than 2, the first JTAG interface is connected to the JTAG input interface of the first processing device in the N processing devices, and the N processing devices The JTAG input interface of the i-th processing device in the N processing device is connected to the JTAG output interface of the i-1 processing device in the N processing devices, and the JTAG output interface of the i-th processing device in the N processing devices Connected to the JTAG input interface of the i+1th processing device among the N processing devices, the first JTAG input interface is connected to the JTAG output interface of the Nth processing device among the N processing devices, i It is a positive integer greater than or equal to 2 and less than N.

Optionally, in this embodiment, it may be explained but not limited to that N is equal to 5. FIG. 6 is a structural block diagram 6 of a control system based on the joint test working group JTAG interface according to an embodiment of the present application, as shown in FIG. 6, the control system includes: a JTAG connector 102, the JTAG connector 102 includes a TDI interface 102-1 (i.e. the first JTAG interface) and a TDO interface 102-2 (i.e. the second JTAG interface), wherein the TDI interface 102 -1 is used to send data, and TDO interface 102-2 is used to receive data.

The first processing device 118, the second processing device 120, the third processing device 122, the fourth processing device 124 and the fifth processing device 126, the JTAG input interface 118-1 of the first processing device 118 and the first processing device 118-1 A JTAG interface 102-1 is connected, the JTAG output interface 118-2 of the first processing device 118 is connected with the JTAG input interface 120-1 of the second processing device 120, and the JTAG output interface 120-2 of the second processing device 120 Connect with the JTAG input interface 122-1 of the 3rd processing device 122, the JTAG output interface 122-2 of the 3rd processing device 122 is connected with the JTAG input interface 124-1 of the 4th processing device 124, the 4th processing device The JTAG output interface 124-2 of 124 is connected with the JTAG input interface 126-1 of the fifth processing device 126, and the JTAG output interface 126-2 of the fifth processing device 126 is connected with the first JTAG input interface 108 of the first processing device 108 -1 connection.

The first control device 104, the first control device 104 includes a TDI interface 104-1 (ie the second JTAG input interface) and a TDO interface 104-2 (ie the second JTAG output interface), the TDO interface 104-2 and the TDO interface 102- 2 connections, wherein the first control device 104 is used to control the power on of the first processing device 108 .

The first gating module 106 is respectively connected with the first JTAG output interface 108-2 of the TDI interface 104-1, the TDI interface 102-1 and the first processing device 108, wherein the first gating module 106 is used for processing When the device 108 is not powered on, connect the TDI interface 102-1 to the TDI interface 104-1, and when the first processing device is powered on, disconnect the TDI interface 102-1 from the TDI interface 104-1. Connect, and connect the TDO interface 108-2 with the second JTAG input interface 104-1.

In an exemplary embodiment, the above-mentioned control system further includes: a second processing device, the second processing device includes a third JTAG input interface and a third JTAG output interface, and the third JTAG input interface is connected to the first JTAG input interface. A JTAG interface is connected; the second gating module is respectively connected with the first JTAG interface, the third JTAG output interface and the first JTAG input interface, wherein the second gating module is used to When the second processing device is not powered on, connect the first JTAG interface to the first JTAG input interface, and when the second processing device is powered on, disconnect the first JTAG interface. The JTAG interface is connected to the first JTAG input interface, and the third JTAG output interface is connected to the first JTAG input interface.

Optionally, in this embodiment, FIG. 7 is a structural block diagram seven of a control system based on a joint test working group JTAG interface according to an embodiment of the present application. As shown in FIG. 7, the control system includes: a JTAG connector 102. The JTAG connector 102 includes a TDI interface 102-1 (ie, the first JTAG interface) and a TDO interface 102-2 (ie, the second JTAG interface), wherein the TDI interface 102-1 is used to send data, and the TDO interface 102-2 Used to receive data.

The first processing device 108, the first processing device 108 includes a TDI interface 108-1 (ie, the first JTAG input interface) and a TDO interface 108-2 (ie, the first JTAG output interface); the second processing device 112, the second processing device 112 includes a JTAG input interface 112-1 (ie the third JTAG input interface) and a JTAG output interface 112-2 (ie the third JTAG output interface); the JTAG input interface 112-1 is connected to the TDI interface 102-1, and the JTAG output interface 112 -2 is connected to the TDI interface 108-1; the first control device 104, the first control device 104 includes a TDI interface 104-1 (ie, the second JTAG input interface) and a TDO interface 104-2 (ie, the second JTAG output interface), The TDO interface 104-2 is connected to the TDO interface 102-2, wherein the first control device 104 is used to control the power-on of the first processing device 108; the first gating module 106 is respectively connected to the TDI interface 104-1 and the TDI interface 102- 1 and the TDO interface 108-2, wherein the first gating module 106 is used to connect the TDI interface 102-1 to the TDI interface 104-1 when the first processing device 108 has not been powered on. When the processing device is powered on, disconnect the TDI interface 102-1 from the TDI interface 104-1, and connect the TDO interface 108-2 to the TDI interface 104-1. The second gating module 202 is respectively connected to the first JTAG interface 102-1, the third JTAG output interface JTAG output interface 112-2 and the first JTAG input interface 108-1.

In an exemplary embodiment, the above control system further includes: a second power supply connected to the first control device, the second gating module, and the second processing device, wherein the second power supply uses Outputting a fourth control signal to the second gating module when the second processing device is not powered on, and outputting a fourth control signal to the second gate module when the second processing device is powered on The gating module outputs a fifth control signal, wherein the fourth control signal is used to control the second gating module to connect the first JTAG interface to the first JTAG input interface, and the fifth control signal Used to control the second gating module to disconnect the first JTAG interface from the first JTAG input interface, and connect the third JTAG output interface to the first JTAG input interface; wherein, The first control device is used to control the power-on of the second processing device through the second power supply.

Optionally, in this embodiment, FIG. 8 is a structural block diagram eight of a control system based on a joint test working group JTAG interface according to an embodiment of the present application. As shown in FIG. 8, the control system includes: a JTAG connector 102. The JTAG connector 102 includes a TDI interface 102-1 (ie, the first JTAG interface) and a TDO interface 102-2 (ie, the second JTAG interface), wherein the TDI interface 102-1 is used to send data, and the TDO interface 102-2 Used to receive data.

The first processing device 108, the first processing device 108 includes a TDI interface 108-1 (ie, the first JTAG input interface) and a TDO interface 108-2 (ie, the first JTAG output interface); the second processing device 112, the second processing device 112 includes a JTAG input interface 112-1 (ie the third JTAG input interface) and a JTAG output interface 112-2 (ie the third JTAG output interface); the JTAG input interface 112-1 is connected to the TDI interface 102-1, and the JTAG output interface 112 -2 is connected to the TDI interface 108-1.

The first control device 104, the first control device 104 includes a TDI interface 104-1 (ie the second JTAG input interface) and a TDO interface 104-2 (ie the second JTAG output interface), the TDO interface 104-2 and the TDO interface 102- 2 connections, wherein the first control device 104 is used to control the power on of the first processing device 108 .

The first gating module 106 is respectively connected to the TDI interface 104-1, the TDI interface 102-1 and the TDO interface 108-2, wherein the first gating module 106 is used for when the first processing device 108 is not powered on , connect the TDI interface 102-1 to the TDI interface 104-1, and disconnect the TDI interface 102-1 from the TDI interface 104-1 when the first processing device is powered on, and connect the TDO interface 108-2 Connect with TDI interface 104-1. The second gating module 202 is respectively connected to the first JTAG interface 102-1, the third JTAG output interface JTAG output interface 112-2 and the first JTAG input interface 108-1.

The first power supply 110 is connected to the first control device 104 , the first gating module 106 and the first processing device 108 . The second power supply 204 is connected with the first control device 104 , the second gating module 202 and the second processing device 112 .

In an exemplary embodiment, the first control device is configured to output a sixth control signal to the second power supply when the second processing device is powered on, wherein the sixth control signal It is used to control the second power supply to supply power to the second processing device.

Optionally, in this embodiment, the same control device may be used to control the power-on sequence of multiple processing devices, but is not limited to.

In an exemplary embodiment, the second power supply includes: a second power-on detection module, wherein the second power-on detection module is used to detect whether the second processing device is powered on; the second control signal An output module connected to the second power-on detection module, wherein the second control signal output module is used to detect that the second processing device has not been powered on when the second power-on detection module detects , outputting the fourth control signal to the second gating module, and sending the fourth control signal to the second gating module when the second power-on detection module detects that the second processing device is powered on outputting the fifth control signal.

Optionally, in this embodiment, FIG. 9 is a structural block diagram nine of a control system based on a joint test working group JTAG interface according to an embodiment of the present application. As shown in FIG. 9, the control system includes: a JTAG connector 102. The JTAG connector 102 includes a TDI interface 102-1 (ie, the first JTAG interface) and a TDO interface 102-2 (ie, the second JTAG interface), wherein the TDI interface 102-1 is used to send data, and the TDO interface 102-2 Used to receive data.

The first processing device 108, the first processing device 108 includes a TDI interface 108-1 (ie, the first JTAG input interface) and a TDO interface 108-2 (ie, the first JTAG output interface). The second processing device 112, the second processing device 112 includes a JTAG input interface 112-1 (ie the third JTAG input interface) and a JTAG output interface 112-2 (ie the third JTAG output interface); the JTAG input interface 112-1 and the TDI The interface 102-1 is connected, and the JTAG output interface 112-2 is connected to the TDI interface 108-1.

The first control device 104, the first control device 104 includes a TDI interface 104-1 (ie the second JTAG input interface) and a TDO interface 104-2 (ie the second JTAG output interface), the TDO interface 104-2 and the TDO interface 102- 2 connections, wherein the first control device 104 is used to control the power on of the first processing device 108 .

The first gating module 106 is connected to the TDI interface 104-1, the TDI interface 102-1, and the TDO interface 108-2 respectively, wherein the first gating module 106 is used when the first processing device 108 is not powered on Next, connect the TDI interface 102-1 to the TDI interface 104-1, and disconnect the TDI interface 102-1 from the TDI interface 104-1 when the first processing device is powered on, and connect the TDO interface 108- 2 is connected to the TDI interface 104-1. The second gating module 202 is respectively connected to the first JTAG interface 102-1, the third JTAG output interface JTAG output interface 112-2 and the first JTAG input interface 108-1.

The first power supply 110 is connected to the first control device 104, the first gating module 106 and the first processing device 108, wherein the first power supply 110 includes a first control signal output module 110-2 and a first power-on detection module 110 -1, the first control signal output module 110 - 2 is connected to the first gating module 106 , and the first power-on detection module 110 - 1 is connected to the first processing device 108 . The second power supply 204 is connected to the first control device 104, the second gating module 202 and the second processing device 112, and the second power supply 204 includes a second control signal output module 204-2 and a second power-on detection module 204-1 , the second control signal output module 204 - 2 is connected to the second gating module 202 , and the second power-on detection module 204 - 1 is connected to the second processing device 112 .

In an exemplary embodiment, the interface level required by the first JTAG input interface and the first JTAG output interface is the same as that required by the second JTAG input interface and the second JTAG output interface.

Optionally, in this embodiment, when the JTAG interface level is the same, the processing device and the control device can be put into the same JTAG chain, and then can be mounted in the JTAG chain through the same JTAG connector pair The device is controlled and debugged.

In an exemplary embodiment, the first processing device is a field programmable gate array FPGA device, and the first control device is a complex programmable logic device CPLD.

Optionally, in this embodiment, the first processing device and the first control device may include, but are not limited to, chips that are allowed to support a JTAG interface. It is possible but not limited to deploying CPLD and FPGA on the same accelerator card. Figure 10 is a structural block diagram of an FPGA accelerator card according to an embodiment of the present application. As shown in Figure 10, the JTAG connector can be but not limited to be connected with FPGA and CPLD connection (it should be noted that FPGA can also be connected with other connectors (Other CON)), and CPLD is connected with Universal Asynchronous Receiver/Transmitter (UART). The FPGA accelerator card can be, but is not limited to, an X16 PCIe (peripheral component interconnect express, high-speed serial computer expansion bus standard) card, and supports 4 channels of DDR (Double Data Rate, double-rate synchronous dynamic random access memory) 4 (can be, but is not limited to Including DDR4 Channel-A/B and DDR4 Channel-C/D), 2-way QSFP (Quad Small Form-factor Pluggable, four-channel pluggable optical module connector) (can but not limited to include QSFP_1, QSFP_2). The FPGA power-on sequence is controlled by the CPLD, and at the same time acts as the BMC (base-board management controller) function of the FPGA accelerator card to manage and monitor the power consumption, temperature, alarm and other information of the entire board, and at the same time communicate with the host (server) BMC communicates through SMBUS (System Management Bus, system management bus). The JTAG signal voltage of the FPGA and CPLD of the board is the same, mount the FPGA and CPLD to the same JTAG chain, and use a JTAG connector to control the logic device FPGA and CPLD, which can save board space. The communication between FPGA and CPLD can be, but not limited to, the clock generator (clock generator) and the temperature sensor (temperature sensor) through I2C (Inter-Integrated Circuit, two-wire serial bus), and can be, but not limited to, through the power management bus (PowerManagement Bus, PMBus) completes the communication and connection between VRM (Voltage Regulator Module, voltage regulation module) and eFuse (one-time programmable memory).

In an exemplary embodiment, the first gating module includes one of the following: a switch control device, and a triode switch control circuit.

Optionally, in this embodiment, the triode switch control circuit may include, but is not limited to, a PMOS (positivechannel Metal Oxide Semiconductor) tube, an N MOS (N-Metal-Oxide-Semiconductor, N-type metal-oxide-semiconductor) tube switch control circuit and so on.

In an exemplary embodiment, the JTAG connector further includes a third JTAG interface and a fourth JTAG interface, wherein the third JTAG interface is used for transmitting clock signals, and the fourth JTAG interface is used for transmission mode selection signal, the first processing device is connected to the third JTAG interface and the fourth JTAG interface, and the first control device is connected to the third JTAG interface and the fourth JTAG interface.

Fig. 11 is a structural block diagram ten of a control system based on the JTAG interface of the joint test working group according to the embodiment of the present application. -1 (i.e. the first JTAG interface), TDO interface 102-2 (i.e. the second JTAG interface), TCK interface 102-3 (i.e. the third JTAG interface) and TMS interface 102-4 (i.e. the fourth JTAG interface) wherein, The TDI interface 102-1 is used for sending data, and the TDO interface 102-2 is used for receiving data.

The first processing device 108, the first processing device 108 includes a TDI interface 108-1 (ie the first JTAG input interface) and a TDO interface 108-2 (ie the first JTAG output interface); the first processing device 108 is connected to the TCK interface 102-3 is connected to the TMS interface 102-4, and the first control device 104 is connected to the third JTAG interface TCK interface 102-3 and the TMS interface 102-4.

The first control device 104, the first control device 104 includes a TDI interface 104-1 (ie the second JTAG input interface) and a TDO interface 104-2 (ie the second JTAG output interface), the TDO interface 104-2 and the TDO interface 102- 2 connections, wherein the first control device 104 is used to control the power on of the first processing device 108 .

The first gating module 106 is connected to the TDI interface 104-1, the TDI interface 102-1, and the TDO interface 108-2, wherein the first gating module 106 is used for when the first processing device 108 is not powered on , connect the TDI interface 102-1 to the TDI interface 104-1, and disconnect the TDI interface 102-1 from the TDI interface 104-1 when the first processing device is powered on, and connect the TDO interface 108-2 Connect with TDI interface 104-1.

The first power supply 110 is connected to the first control device 104, the first gating module 106 and the first processing device 108, and the first power supply 110 includes a first power-on detection module 110-1 and a first control signal output module 110-2 , wherein the first power-on detection module 110-1 is connected to the first control signal output module 110-2, the first control signal output module 110-2 is connected to the first gating module 106, and the first power-on detection module 110- 1 is connected to the first processing device 108 .

In order to better understand the above-mentioned control system based on the JTAG interface of the joint test working group, the control system based on the JTAG interface of the joint test working group in the embodiment of the application is explained below in conjunction with optional embodiments, which can be but not limited to applicable In the embodiment of this application.

Optionally, in this embodiment, FIG. 12 is a schematic diagram of a connection between a CPLD, an FPGA, and a JTAG connector according to an embodiment of the present application. As shown in FIG. 12, JTAG CONN (connector, connector) (that is, the above-mentioned JTAG connector) includes TCK interface, TMS interface, TDI interface (that is, the first JTAG interface mentioned above) and TDO interface (that is, the second JTAG interface mentioned above), CPLD (that is, the first control device) includes TCK interface, TMS interface , TDI interface (ie the above-mentioned second JTAG input interface) and TDO interface (ie the above-mentioned second JTAG output interface), FPGA (ie the first processing device) includes a TCK interface, TMS interface, TDI interface (ie the above-mentioned first JTAG input interface) and TDO interface (that is, the first JTAG output interface mentioned above). The first gating module may but is not limited to include pin 1 , pin 2 and pin 3 and pin 4 . The power supply (power) A can, but is not limited to, supply power to the JTAG connector and CPLD, and the CPLD controls the power supply sequence (PowerSequence) of the FPGA by controlling the power supply.

The TCK interface and TMS interface of JTAG CONN are connected with the TCK interface and TMS interface of CPLD, the TCK interface and TMS interface of JTAG CONN are connected with the TCK interface and TMS interface of FPGA, and the TDI interface of JTAG CONN is connected with pin 2 and the TDI interface of FPGA Connection, the TDO interface of the FPGA is connected to pin 3, the pin 4 is connected to the power supply of the FPGA, and the pin 1 is connected to the TDI interface of the CPLD.

The level of pin 4 is controlled by the Power Good signal output by the FPGA power VR (Voltage Regulator, voltage regulation). When the FPGA is not powered on, the Power Good (power normal) signal output of VR is low. When the FPGA is powered on, the Power Good signal output of the VR is at a high level.

When pin 4 is a low-level signal, pin 1 and pin 2 are connected. At this time, the CPLD is completely mounted in the JTAG chain, and the TDO of the FPGA is disconnected, so the JTAG control of the FPGA cannot be performed. Under such circumstances, Figure 13 is a schematic diagram of the connection between a JTAG connector and a CPLD according to an embodiment of the present application. As shown in Figure 13, when pins 1 and 2 are connected, only the CPLD Completely mounted into the JTAG chain.

When the pin 4 is at a high level, the pin 1 is connected to the pin 3, and the CPLD and the FPGA are completely mounted on the JTAG chain at this time. The second schematic diagram of the connection between CPLD, FPGA and JTAG connector, as shown in Figure 14, in the case of connecting pin 1 and pin 3, CPLD and FPGA are completely mounted in the JTAG chain.

In this way, when the power-on sequence of the FPGA is controlled by the CPLD, when there is no program or a program error in the CPLD, the FPGA cannot be powered on normally. In such a case, the JTAG chain between the CPLD and the FPGA is blocked, and the JTAG connector cannot be connected to the CPLD, and the program of the CPLD cannot be updated. By adding the first gating module between the FPGA and the CPLD, during the power-on process of the FPGA, according to whether the FPGA is powered on, the device connected to the JTAG connector is automatically switched, regardless of whether the FPGA is powered on or not. Affects communication between CPLD and JTAG connector. Avoid manually disconnecting the connection between the TDI pin of the CPLD and the TDO interface of the FPGA by adding a Rework (rework) board, and then connect the TDI pin of the CPLD to the TDI interface on the JTAG CONN, ensuring that the CPLD and Communication between JTAG connectors is smooth.

In addition, in the embodiment of the present application, one CPLD can be used to control the power-on of multiple FPGAs. FIG. 15 is a schematic diagram of the connection between a CPLD, FPGA and JTAG connector according to the embodiment of the present application. As shown in FIG. 15, JTAG CONN (that is, the above-mentioned JTAG connector) includes TCK interface, TMS interface, TDI interface (that is, the above-mentioned first JTAG interface) and TDO interface (that is, the above-mentioned second JTAG interface), and CPLD (that is, the first control device) includes TCK interface, TMS interface, TDI interface (ie the second JTAG input interface mentioned above) and TDO interface (ie the second JTAG output interface mentioned above), FPGA1 (ie the first processing device) includes TCK interface, TMS interface, TDI interface ( That is, the above-mentioned first JTAG input interface) and TDO interface (that is, the above-mentioned first JTAG output interface), FPGA2 (that is, the second processing device) includes a TCK interface, a TMS interface, and a TDI interface (that is, the JTAG interface of the above-mentioned second processing device) input interface) and TDO interface (that is, the JTAG output interface of the above-mentioned second processing device).

The first gating module may but is not limited to include pin 1 , pin 2 and pin 3 and pin 4 . The second gating module may but is not limited to include pin 1 , pin 2 and pin 3 and pin 4 . The CPLD controls the power-on sequence (Power Sequence) of FPGA1 by controlling the power supply 1 of FPGA1, and the CPLD controls the power-on sequence (Power Sequence) of FPGA2 by controlling the power supply 2 of FPGA1.

The TCK interface and TMS interface of JTAG CONN are connected with the TCK interface and TMS interface of CPLD, the TCK interface and TMS interface of JTAG CONN are connected with the TCK interface and TMS interface of FPGA1, and the TCK interface and TMS interface of JTAG CONN are connected with the TCK interface and TMS interface connection.

The TDI interface of JTAG CONN is connected with the pin 2 of the first gating module, the pin 2 of the second gating module, and the TDI interface of FPGA2, and the TDO interface of FPGA2 is connected with the pin 3 of the second gating module, and the second The pin 4 of the gating module is connected to the power supply 2 of FPGA2, the pin 1 of the second gating module is connected to the TDI interface of FPGA1, the TDO interface of FPGA1 is connected to the pin 3 of the first gating module, and the first gating module The pin 4 of the module is connected to the power supply 1 of FPGA1, the pin 1 of the first gating module is connected to the TDI interface of the CPLD, and the TDO interface of the CPLD is connected to the TDI interface of the JTAG CONN.

Through such a connection method, during the power-on process of FPGA1 and FPGA2, the device connected to the JTAG connector can be automatically switched according to the power-on situation of FPGA1 and FPGA2, and the communication between the JTAG connector and CPLD can always be guaranteed. In detail, when pin 4 of the first gating module is a low-level signal, pin 1 and pin 2 of the first gating module are connected, and at this time the CPLD is completely mounted in the JTAG chain, The TDO of the FPGA is disconnected, and the JTAG control of the FPGA cannot be performed. When pin 4 of the first gating module is at a high level, pin 1 and pin 3 of the first gating module are connected, and at this time, the CPLD and FPGA are completely mounted to the JTAG chain. Or, in the case that the pin 4 of the second gating module is a low-level signal, the pin 1 and pin 2 of the second gating module are connected, and at this time the CPLD is completely mounted in the JTAG chain, and the FPGA2 The TDO interface is disconnected, and FPGA2 cannot be controlled by JTAG. When pin 4 of the second gating module is at a high level, pin 1 and pin 3 of the second gating module are connected, and at this time CPLD and FPGA2 are completely mounted to the JTAG chain.

It should be noted that, in Figure 15, two gating modules are used to explain the above-mentioned control system based on the JTAG interface of the joint test working group, and the number of gating modules can be adjusted according to actual needs, for example: in Figure 15, it can be Whether FPGA1 and FPGA2 are connected to the JTAG connector is controlled by the same gating block. This application does not limit this.

The method embodiments provided in the embodiments of the present application may be executed in mobile terminals, computer terminals or similar computing devices. Taking running on a mobile terminal as an example, FIG. 16 is a block diagram of the hardware structure of a mobile terminal based on a control method of a joint test working group JTAG interface according to an embodiment of the present application. As shown in FIG. 16 , the mobile terminal may include one or more (only one is shown in FIG. 1 ) processor 1602 (the processor 1602 may include but not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 1604 for storing data, wherein the above mobile The terminal may also include a transmission device 1606 and an input and output device 1608 for communication functions. Those skilled in the art can understand that the structure shown in FIG. 16 is only for illustration, and it does not limit the structure of the above mobile terminal. For example, the mobile terminal may also include more or fewer components than those shown in FIG. 16 , or have a different configuration from that shown in FIG. 16 .

The memory 1604 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the control method based on the Joint Test Working Group JTAG interface in the embodiment of the present application, and the processor 1602 is stored in the memory 1604 by running A computer program to perform various functional applications and data processing, that is, to realize the above-mentioned method. The memory 1604 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 1604 may further include memory that is remotely located relative to the processor 1602, and these remote memories may be connected to the mobile terminal through a network. Examples of the aforementioned networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

Transmission device 1606 is used to receive or transmit data via a network. The specific example of the above network may include a wireless network provided by the communication provider of the mobile terminal. In one example, the transmission device 1606 includes a network adapter (Network Interface Controller, NIC for short), which can be connected to other network devices through a base station so as to communicate with the Internet. In an example, the transmission device 1606 may be a radio frequency (Radio Frequency, RF for short) module, which is used to communicate with the Internet in a wireless manner.

In the embodiment of the present application, a control method based on the joint test working group JTAG interface running on the above-mentioned mobile terminal is provided. FIG. 17 is a flow chart of the control method based on the joint test working group JTAG interface according to the embodiment of the present application. As shown in Figure 17, the process includes the following steps:

Step S1702, when the first processing device in the control system based on the JTAG chain has not been powered on, connect the first JTAG interface to the second JTAG input interface through the first gating module in the control system;

Step S1704, when the power-on of the first processing device is completed, disconnect the connection between the first JTAG interface and the second JTAG input interface through the first gating module, and output the first JTAG The interface is connected to the second JTAG input interface;

Wherein, the control system includes: a JTAG connector, the JTAG connector includes the first JTAG interface and the second JTAG interface; the first processing device, the first processing device includes the first JTAG input interface and The first JTAG output interface; the first control device, the first control device includes the second JTAG input interface and the second JTAG output interface, the second JTAG output interface is connected to the second JTAG interface, Wherein, the first control device is used to control the power-on of the first processing device; the first gating module is respectively connected to the first JTAG interface, the first JTAG output interface and the second JTAG input interface connection.

Through the above steps, since the CPLD device (that is, the first control device) controls the power-on sequence of the FPGA device (that is, the first processing device), during the power-on process of the FPGA device, the connection with the JTAG connector can be realized through the first gating module. Switching of connected devices; and regardless of whether the FPGA device is powered on or not, the connection between the CPLD device and the JTAG connector can be realized through the first gating module. Therefore, it can solve the problem that the CPLD cannot be connected to the JTAG connector when the CPLD chip controls the power-on sequence of the FPGA chip and the power-on of the FPGA chip is not completed, and then achieves the control of the power-on sequence of the FPGA chip by the CPLD chip and the power-on sequence of the FPGA chip. In the case that the electricity is not completed, the effect of the connection between the CPLD and the JTAG connector is guaranteed.

Wherein, the execution subject of the above steps may be a terminal, etc., but is not limited thereto.

The execution order of step S1702 and step S1704 can be interchanged, that is, step S1704 can be executed first, and then S1702 can be executed.

In the technical solution provided by the above step S1702, the first control device may be used to control the power-on sequence of the first processing device (it may be but not limited to the power-on time and power-on sequence). Before the power-on is completed, or when the FPGA fails to be powered on normally, the first JTAG interface is connected to the second JTAG input interface, that is, only the first control device is connected to the JTAG connector at this time. In this way, communication interruption between the first control device and the JTAG connector caused by the first processing device not being powered on is avoided.

In an exemplary embodiment, the first JTAG interface may be connected to the second JTAG input interface in the following manner: when the first processing device is not powered on, the The first gating module outputs a first control signal, wherein the first control signal is used to control the first gating module to connect the first JTAG interface to the second JTAG input interface; in response to the The first control signal connects the first JTAG interface with the second JTAG input interface through the first gating module.

Optionally, in this embodiment, when the first processing device starts to be powered on until the power-on is completed, the first control signal may be output to the first gating module through the first power supply, and the first gating module The first JTAG interface may be connected to the second JTAG input interface in response to the first control signal, but not limited to.

In an exemplary embodiment, the first JTAG output interface may be connected to the second JTAG input interface in the following manner: when the first processing device is powered on, through the first The power supply outputs a second control signal to the first gating module, wherein the second control signal is used to control the first gating module to disconnect the first JTAG interface and the second JTAG input interface Connect, and connect the first JTAG output interface with the second JTAG input interface; in response to the second control signal, disconnect the first JTAG interface and the second JTAG interface through the first gating module Two JTAG input interfaces are connected, and the first JTAG output interface is connected to the second JTAG input interface; wherein, the control system also includes: the first power supply, the first control device, the first control device, and the second JTAG input interface; The first gating module is connected to the first processing device; wherein, the first control device is configured to control power-on of the first processing device through the first power supply.

Optionally, in this embodiment, when the first processing device starts to be powered on until the power-on is completed, the first gating module can output the second control signal to the first gating module through the first power supply, and the first gating module can But not limited to responding to the second control signal, disconnecting the first JTAG interface from the second JTAG input interface, and connecting the first JTAG output interface to the second JTAG input interface.

In the technical solution provided by the above step S1704, when the first processing device is powered on, the first JTAG output interface is connected to the second JTAG input interface, that is, at this time, the first control device and the second JTAG input interface A processing device is connected to the JTAG connector. According to the power-on status of the first processing device, the device connected to the JTAG connector is automatically switched, which avoids manual switching by adding a Rework board, and greatly improves the efficiency of switching devices connected to the JTAG connector.

In an exemplary embodiment, power may be supplied to the first processing device in the following manner, but not limited to: when the power-on of the first processing device is completed, output to the first power supply through the first control device A third control signal, wherein the third control signal is used to control the first power supply to supply power to the first processing device; in response to the third control signal, supply power to the first processing device through the first power supply Processing device power supply.

Optionally, in this embodiment, before the first control device controls the power-on sequence of the first processing device, the first control device may, but is not limited to, be powered on first, that is, the first control device needs to run normally before it can It is guaranteed that the control of the power-on sequence of the first processing device can be completed.

In an exemplary embodiment, it may be but not limited to detect whether the first processing device is powered on in the following manner: through the first power-on detection module in the first power supply to detect whether the first processing device is powered on ; when the first power-on detection module detects that the first processing device has not been powered on, outputting the first control signal output module to the first gating module through the first control signal output module in the first power supply The first control signal; when the first power-on detection module detects that the first processing device is powered on, output the first control signal output module to the first gating module. Second control signal.

Optionally, in this embodiment, the first power-on detection module in the first power supply may detect whether the first power supply is powered on and output a corresponding control signal. It may be but not limited to output a low-level signal to the first gating module through the first control signal output module in the first power supply when the first power-on detection module detects that the first processing device has not been powered on. The above-mentioned first control signal) may, but not limited to, be sent to the first gating module through the first control signal output module in the first power supply when the first power-on detection module detects that the first processing device is powered on Outputting a high-level signal (that is, the above-mentioned second control signal).

Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general-purpose hardware platform, and of course also by hardware, but in many cases the former is better implementation. Based on this understanding, the essence of the technical solutions of the embodiments of the present application or the part that contributes to the prior art can be embodied in the form of software products, and the computer software products are stored in a storage medium (such as ROM/RAM, magnetic CD, CD), including several instructions to enable a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present application.

In this embodiment, a control device based on the joint test working group JTAG interface is also provided, and the device is used to implement the above embodiments and preferred implementation modes, and those that have already been described will not be repeated. As used below, the term "module" may be a combination of software and/or hardware that realizes a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementations in hardware, or a combination of software and hardware are also possible and contemplated.

Fig. 18 is a structural block diagram of a control device based on a joint test working group JTAG interface according to an embodiment of the present application. As shown in Fig. 18, the device includes:

The first connection module 1802 is used to connect the first JTAG interface with the second JTAG through the first gating module in the control system when the first processing device in the control system based on the JTAG chain has not been powered on. Input interface connection;

The second connection module 1804 is configured to disconnect the connection between the first JTAG interface and the second JTAG input interface through the first gating module when the first processing device is powered on, and Connecting the first JTAG output interface with the second JTAG input interface;

Wherein, the control system includes: a JTAG connector, the JTAG connector includes the first JTAG interface and the second JTAG interface; the first processing device, the first processing device includes the first JTAG input interface and The first JTAG output interface; the first control device, the first control device includes the second JTAG input interface and the second JTAG output interface, the second JTAG output interface is connected to the second JTAG interface, Wherein, the first control device is used to control the power-on of the first processing device; the first gating module is respectively connected to the first JTAG interface, the first JTAG output interface and the second JTAG input interface connection.

Through the above device, since the CPLD device (that is, the first control device) controls the power-on sequence of the FPGA device (that is, the first processing device), during the power-on process of the FPGA device, the connection with the JTAG connector can be realized through the first gating module. Switching of connected devices; and regardless of whether the FPGA device is powered on or not, the connection between the CPLD device and the JTAG connector can be realized through the first gating module. Therefore, it can solve the problem that the CPLD cannot be connected to the JTAG connector when the CPLD chip controls the power-on sequence of the FPGA chip and the power-on of the FPGA chip is not completed, and then achieves the control of the power-on sequence of the FPGA chip by the CPLD chip and the power-on sequence of the FPGA chip. In the case that the electricity is not completed, the effect of the connection between the CPLD and the JTAG connector is guaranteed.

Optionally, the first connection module is configured to: output a first control signal to the first gating module through a first power supply when the first processing device is not powered on, wherein the The first control signal is used to control the first gating module to connect the first JTAG interface to the second JTAG input interface; in response to the first control signal, the first gating module will The first JTAG interface is connected to the second JTAG input interface; the second connection module is configured to: when the first processing device is powered on, send the first power supply to the second JTAG input interface. A gating module outputs a second control signal, wherein the second control signal is used to control the first gating module to disconnect the first JTAG interface from the second JTAG input interface, and connect the The first JTAG output interface is connected to the second JTAG input interface; in response to the second control signal, disconnect the first JTAG interface and the second JTAG input interface through the first gating module Connect, and connect the first JTAG output interface with the second JTAG input interface; wherein, the control system also includes: the first power supply, the first control device, the first gating The module is connected to the first processing device; wherein the first control device is used to control the power-on of the first processing device through the first power supply.

Optionally, the apparatus further includes: a first output module, configured to output a third control signal to the first power supply through the first control device when the first processing device is powered on, Wherein, the third control signal is used to control the first power supply to supply power to the first processing device; the power supply module is used to supply power to the first processing device through the first power supply in response to the third control signal. Processing device power supply.

Optionally, the device further includes: a detection module, configured to detect whether the first processing device is powered on through the first power-on detection module in the first power supply; a second output module, configured to When the first power-on detection module detects that the first processing device has not been powered on, output the first control signal output module to the first gating module through the first control signal output module in the first power supply. Control signal; when the first power-on detection module detects that the first processing device is powered on, output the second control signal to the first gating module through the first control signal output module Signal.

It should be noted that the above-mentioned modules can be realized by software or hardware. For the latter, it can be realized by the following methods, but not limited to this: the above-mentioned modules are all located in the same processor; or, the above-mentioned modules can be combined in any combination The forms of are located in different processors.

Embodiments of the present application also provide a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to perform the steps in any one of the above method embodiments when running.

In an exemplary embodiment, the above-mentioned computer-readable storage medium may include but not limited to: U disk, read-only memory (Read-Only Memory, ROM for short), random access memory (Random Access Memory, RAM for short) , mobile hard disk, magnetic disk or optical disk and other media that can store computer programs.

An embodiment of the present application also provides an electronic device, including a memory and a processor, where a computer program is stored in the memory, and the processor is configured to run the computer program to perform the steps in any one of the above method embodiments.

In an exemplary embodiment, the electronic device may further include a transmission device and an input and output device, wherein the transmission device is connected to the processor, and the input and output device is connected to the processor.

For specific examples in this embodiment, reference may be made to the examples described in the foregoing embodiments and exemplary implementation manners, and details will not be repeated here in this embodiment.

Obviously, those skilled in the art should understand that the modules or steps of the above-mentioned embodiments of the present application can be implemented by general-purpose computing devices, and they can be concentrated on a single computing device, or distributed among multiple computing devices. They may be implemented in program code executable by a computing device, stored in a storage device, executed by a computing device, and in some cases executed in an order different from that described herein. The steps shown or described are realized by making them into respective integrated circuit modules, or making multiple modules or steps among them into a single integrated circuit module. Thus, embodiments of the present application are not limited to any specific combination of hardware and software.

The above descriptions are only preferred embodiments of the present application, and are not intended to limit the embodiments of the present application. For those skilled in the art, various modifications and changes may be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the principles of the embodiments of the present application shall be included in the protection scope of the embodiments of the present application.

Claims (20)

1. A control system based on joint test group JTAG interface is characterized by comprising:

the JTAG connector comprises a first JTAG interface and a second JTAG interface, wherein the first JTAG interface is used for sending data, and the second JTAG interface is used for receiving data;

a first processing device including a first JTAG input interface and a first JTAG output interface;

the first control device comprises a second JTAG input interface and a second JTAG output interface, the second JTAG output interface is connected with the second JTAG interface, and the first control device is used for controlling the power-on of the first processing device;

the first gating module is respectively connected with the first JTAG interface, the first JTAG output interface and the second JTAG input interface, wherein the first gating module is used for connecting the first JTAG interface with the second JTAG input interface under the condition that the first processing device is not electrified, and disconnecting the first JTAG interface from the second JTAG input interface and connecting the first JTAG output interface with the second JTAG input interface under the condition that the first processing device is electrified;

the first processing device is a Field Programmable Gate Array (FPGA) device, and the first control device is a Complex Programmable Logic Device (CPLD).

2. The system of claim 1, further comprising:

a first power source connected to the first control device, the first gating module, and the first processing device, wherein the first power source is configured to output a first control signal to the first gating module when the first processing device is not powered on and is completed, and output a second control signal to the first gating module when the first processing device is powered on and is completed, wherein the first control signal is configured to control the first gating module to connect the first JTAG interface to the second JTAG input interface, and the second control signal is configured to control the first gating module to disconnect the first JTAG interface from the second JTAG input interface and connect the first JTAG output interface to the second JTAG input interface;

wherein the first control device is configured to control power-up of the first processing device via the first power supply.

3. The system of claim 2, wherein the first control device is configured to output a third control signal to the first power source if power-up of the first processing device is completed, wherein the third control signal is configured to control the first power source to supply power to the first processing device.

4. The system of claim 2, wherein the first power source comprises:

the first power-on detection module is used for detecting whether the first processing device is powered on completely;

the first control signal output module is configured to output the first control signal to the first gating module when the first power-on detection module detects that the first processing device is not powered on and is completed, and output the second control signal to the first gating module when the first power-on detection module detects that the first processing device is powered on and is completed.

5. The system of claim 1, wherein the first JTAG input interface is coupled to the first JTAG interface.

6. The system of claim 1, further comprising:

the first JTAG input interface is connected with the JTAG output interface of the second processing device; or

The first JTAG interface is connected with the JTAG input interface of the second processing device, the JTAG output interface of the second processing device is connected with the JTAG input interface of the third processing device, and the first JTAG input interface is connected with the JTAG output interface of the third processing device; or alternatively

The system comprises N processing devices, wherein N is a positive integer larger than 2, a first JTAG interface is connected with a JTAG input interface of a1 st processing device in the N processing devices, a JTAG input interface of an ith processing device in the N processing devices is connected with a JTAG output interface of an i-1 th processing device in the N processing devices, a JTAG output interface of an ith processing device in the N processing devices is connected with a JTAG input interface of an i +1 th processing device in the N processing devices, the first JTAG input interface is connected with a JTAG output interface of an Nth processing device in the N processing devices, and i is a positive integer larger than or equal to 2 and smaller than N.

7. The system of claim 1, further comprising:

the second processing device comprises a third JTAG input interface and a third JTAG output interface, and the third JTAG input interface is connected with the first JTAG interface;

and the second gating module is respectively connected with the first JTAG interface, the third JTAG output interface and the first JTAG input interface, wherein the second gating module is used for connecting the first JTAG interface with the first JTAG input interface under the condition that the second processing device is not electrified, and disconnecting the first JTAG interface from the first JTAG input interface and connecting the third JTAG output interface with the first JTAG input interface under the condition that the second processing device is electrified.

8. The system of claim 7, further comprising:

a second power supply connected to the first control device, the second gating module, and the second processing device, wherein the second power supply is configured to output a fourth control signal to the second gating module when the second processing device is not powered on, and output a fifth control signal to the second gating module when the second processing device is powered on, wherein the fourth control signal is configured to control the second gating module to connect the first JTAG interface with the first JTAG input interface, and the fifth control signal is configured to control the second gating module to disconnect the first JTAG interface from the first JTAG input interface and connect the third JTAG output interface with the first JTAG input interface;

wherein the first control device is configured to control power-up of the second processing device via the second power supply.

9. The system of claim 8, wherein the first control device is configured to output a sixth control signal to the second power source if power-up of the second processing device is completed, wherein the sixth control signal is configured to control the second power source to supply power to the second processing device.

10. The system of claim 8, wherein the second power source comprises:

a second power-on detection module, wherein the second power-on detection module is configured to detect whether power-on of the second processing device is completed;

and the second control signal output module is connected with the second power-on detection module, and is configured to output the fourth control signal to the second gating module when the second power-on detection module detects that the second processing device is not powered on and is completed, and output the fifth control signal to the second gating module when the second power-on detection module detects that the second processing device is powered on and is completed.

11. The system of any one of claims 1 to 10,

the first JTAG input interface and the first JTAG output interface have the same interface level required by the second JTAG input interface and the second JTAG output interface.

12. The system according to any one of claims 1 to 10, wherein the first gating module comprises one of: switch control device, triode switch control circuit.

13. The system of any one of claims 1-10, wherein the JTAG connector further includes a third JTAG interface and a fourth JTAG interface, wherein the third JTAG interface is configured to transmit clock signals, the fourth JTAG interface is configured to transmit mode selection signals, the first processing device is coupled to the third JTAG interface and the fourth JTAG interface, and the first control device is coupled to the third JTAG interface and the fourth JTAG interface.

14. A control method based on joint test group JTAG interface is characterized by comprising the following steps:

under the condition that a first processing device in a control system based on a JTAG chain is not powered on and completed, connecting a first JTAG interface with a second JTAG input interface through a first gating module in the control system;

under the condition that the first processing device is powered on, disconnecting the first JTAG interface from the second JTAG input interface through the first gating module, and connecting the first JTAG output interface with the second JTAG input interface;

wherein the control system comprises: a JTAG connector including the first JTAG interface and a second JTAG interface; the first processing device comprises a first JTAG input interface and a first JTAG output interface; the first control device comprises a second JTAG input interface and a second JTAG output interface, the second JTAG output interface is connected with the second JTAG interface, and the first control device is used for controlling the power-on of the first processing device; the first gating module is respectively connected with the first JTAG interface, the first JTAG output interface and the second JTAG input interface;

the first processing device is a Field Programmable Gate Array (FPGA) device, and the first control device is a Complex Programmable Logic Device (CPLD).

15. The method of claim 14,

under the condition that the first processing device in the control system based on the JTAG chain is not powered on and is completed, the first JTAG interface is connected with the second JTAG input interface through the first gating module in the control system, and the method comprises the following steps: under the condition that the first processing device is not powered on and is finished, outputting a first control signal to the first gating module through a first power supply, wherein the first control signal is used for controlling the first gating module to connect the first JTAG interface with the second JTAG input interface; connecting the first JTAG interface with the second JTAG input interface through the first gating module in response to the first control signal;

under the condition that the first processing device is powered on and completed, the first gating module is used for disconnecting the first JTAG interface from the second JTAG input interface and connecting the first JTAG output interface with the second JTAG input interface, and the method comprises the following steps: under the condition that the first processing device is powered on, outputting a second control signal to the first gating module through the first power supply, wherein the second control signal is used for controlling the first gating module to disconnect the first JTAG interface from the second JTAG input interface and connect the first JTAG output interface with the second JTAG input interface; responding to the second control signal, disconnecting the first JTAG interface from the second JTAG input interface through the first gating module, and connecting the first JTAG output interface with the second JTAG input interface;

wherein the control system further comprises: the first power supply is connected with the first control device, the first gating module and the first processing device;

wherein the first control device is configured to control power-up of the first processing device via the first power supply.

16. The method of claim 15, further comprising:

under the condition that the first processing device is powered on, outputting a third control signal to the first power supply through the first control device, wherein the third control signal is used for controlling the first power supply to supply power to the first processing device;

supplying power to the first processing device through the first power supply in response to the third control signal.

17. The method of claim 15, further comprising:

detecting whether the first processing device is powered on completely through a first power-on detection module in the first power supply;

under the condition that the first power-on detection module detects that the first processing device is not powered on completely, outputting the first control signal to the first gating module through a first control signal output module in the first power supply; and under the condition that the first power-on detection module detects that the power-on of the first processing device is completed, outputting the second control signal to the first gating module through the first control signal output module.

18. A kind of controlling device based on joint test work group JTAG interface, characterized by that, comprising:

the first connection module is used for connecting the first JTAG interface with the second JTAG input interface through the first gating module in the control system under the condition that the first processing device in the control system based on the JTAG chain is not electrified;

the second connection module is used for disconnecting the first JTAG interface from the second JTAG input interface through the first gating module and connecting the first JTAG output interface with the second JTAG input interface under the condition that the first processing device is electrified and finished;

wherein the control system comprises: a JTAG connector including the first JTAG interface and a second JTAG interface; the first processing device comprises a first JTAG input interface and a first JTAG output interface; the first control device comprises a second JTAG input interface and a second JTAG output interface, the second JTAG output interface is connected with the second JTAG interface, and the first control device is used for controlling the power-on of the first processing device; the first gating module is respectively connected with the first JTAG interface, the first JTAG output interface and the second JTAG input interface;

the first processing device is a Field Programmable Gate Array (FPGA) device, and the first control device is a Complex Programmable Logic Device (CPLD).

19. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the method of any one of claims 14 to 17.

20. An electronic device comprising a memory having a computer program stored thereon, a processor implementing the method of any of claims 14 to 17 when the processor executes the computer program.

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