CN115621352B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN115621352B CN115621352B CN202211348912.9A CN202211348912A CN115621352B CN 115621352 B CN115621352 B CN 115621352B CN 202211348912 A CN202211348912 A CN 202211348912A CN 115621352 B CN115621352 B CN 115621352B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 67
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 title abstract description 19
- 238000005468 ion implantation Methods 0.000 claims abstract description 142
- 239000000758 substrate Substances 0.000 claims abstract description 84
- 230000005684 electric field Effects 0.000 claims description 36
- 238000001514 detection method Methods 0.000 abstract description 16
- 150000002500 ions Chemical class 0.000 description 246
- 239000000969 carrier Substances 0.000 description 23
- 238000002955 isolation Methods 0.000 description 20
- 238000009792 diffusion process Methods 0.000 description 10
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 4
- 230000009471 action Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000007935 neutral effect Effects 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000005596 ionic collisions Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F30/00—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors
- H10F30/20—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors
- H10F30/21—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation
- H10F30/22—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes
- H10F30/225—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes the potential barrier working in avalanche mode, e.g. avalanche photodiodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F71/00—Manufacture or treatment of devices covered by this subclass
- H10F71/121—The active layers comprising only Group IV materials
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- Light Receiving Elements (AREA)
- Photovoltaic Devices (AREA)
Abstract
本发明提供了一种半导体器件及其制造方法，所述半导体器件包括：衬底，所述衬底具有相背的第一表面和第二表面；掺杂类型相反的第一离子掺杂区和第二离子掺杂区，所述第一离子掺杂区从所述第一表面延伸至所述衬底中，所述第二离子掺杂区从所述第一离子掺杂区远离所述第一表面的一侧朝向所述第二表面延伸，所述第二离子掺杂区包含至少两层离子注入区，在从所述第一表面朝向所述第二表面的方向上各层所述离子注入区的离子掺杂浓度逐层增大、各层所述离子注入区在平行于所述第一表面的方向上的宽度逐层增大，以使得所述第一离子掺杂区与所述第二离子掺杂区构成缓变结。本发明的技术方案能够提高半导体器件的探测效率。
The present invention provides a semiconductor device and a method for manufacturing the same, the semiconductor device comprising: a substrate having a first surface and a second surface facing each other; a first ion doping region and a second ion doping region of opposite doping types, the first ion doping region extending from the first surface into the substrate, the second ion doping region extending from the side of the first ion doping region away from the first surface toward the second surface, the second ion doping region comprising at least two layers of ion implantation regions, the ion doping concentration of each layer of the ion implantation region increasing layer by layer in the direction from the first surface toward the second surface, the width of each layer of the ion implantation region in the direction parallel to the first surface increasing layer by layer, so that the first ion doping region and the second ion doping region form a graded junction. The technical solution of the present invention can improve the detection efficiency of semiconductor devices.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly, to a semiconductor device and a method of fabricating the same.
Background
Avalanche photodiodes are P-N junction type photodiodes in which the avalanche multiplication effect of carriers is utilized to amplify the photoelectric signal to increase the sensitivity of detection. The existing avalanche photodiode structure forms are a protection ring type and a pull-through type (also called a through type), wherein a layer of annular isolation structure is deposited on the basis of the protection ring type to prevent avalanche breakdown at the edge of a P-N junction under high back pressure. A pull-through avalanche photodiode (also called RAPD) is commonly used at present, and the basic structure of the pull-through avalanche photodiode is usually a Read diode structure (i.e. an n+pip+ type structure) which easily generates an avalanche multiplication effect, wherein p+ one side receives light, I is a near intrinsic low doped region where most incident photons are absorbed and generate photon-generated carriers, a multiplied high electric field region is concentrated in a narrow region near a P-n+ junction, and n+ and p+ are high doped low resistance voltages for reducing contact resistance so as to facilitate connection with an electrode.
A semiconductor device, as shown in fig. 1a and 1b, is in the form of a P-N junction structure, wherein the P-type material is formed of three parts, and photons are injected from the p+ layer 11 into the intrinsic doped I (P) layer 12, where the material absorbs light energy and generates primary electron-hole pairs. At this time, the photoelectrons are accelerated by the weak electric field of the depletion layer in the I layer 12, move to the P-N junction formed by the P layer 13 and the n+ layer 14, undergo an avalanche collision effect by the acceleration of the strong electric field, and finally reach the n+ layer 14 after avalanche multiplication, and holes are absorbed by the p+ layer 11. The depletion region is pulled all the way from the P-N junction region to the region where the I layer 12 meets the P+ layer 11, and the multiplication region 15 is located between the P-N junction formed by the P layer 13 and the N+ layer 14. The electric field increase in the depletion region is small in the whole range, when the field intensity in the depletion region reaches enough (3 x 10 x 5V/cm), the photo-generated carriers are accelerated to a high speed, and are ionized when colliding with atoms in the crystal lattice in the movement process, so that extra electron-hole pairs are generated. These new electrons and holes are also accelerated, undergo new collisions and ionization, and produce more electron-hole pairs, a physical process known as the avalanche effect, which multiplies the primary photocurrent, causing it to be amplified.
However, the semiconductor device has the problems that 1) when a reverse bias voltage is applied to the avalanche photodiode, the potential difference between the p+ layer 11 and the n+ layer 14 is only in the vertical direction, carriers outside the width range of the multiplication region 15 in the horizontal direction cannot reach the multiplication region 15, so that the detection efficiency is low, 2) in order to improve the detection efficiency, the width of the multiplication region 15 is usually selected to be increased by increasing the width of the n+ layer 14 in the horizontal direction, but defects, damages and the like generated by shallow grooves and/or deep groove etching at the periphery of the avalanche photodiode are caused to be directly contacted with the multiplication region 15, so that the dark count rate is caused to be increased, the device performance is reduced, 3) in order to improve the absorption efficiency of the semiconductor device to near infrared light (905 nm-940 nm), the thickness of the semiconductor device is required to be large (usually more than 7.5 μm), the thickness of the multiplication region 15 in the vertical direction is small, the carriers are required to pass through an intrinsic doped layer 12 with a long distance in the depletion region between the p+ layer 11 and the multiplication region 15 in a diffusion mode, the avalanche device can be generated, the diffusion efficiency is also reduced, the sensitivity of the semiconductor device is also caused, the device can be influenced only in a long time, and the diffusion of the semiconductor device can be generated.
Therefore, how to improve the detection efficiency is a problem to be solved.
Disclosure of Invention
The invention aims to provide a semiconductor device and a manufacturing method thereof, which can improve the detection efficiency of the semiconductor device.
In order to achieve the above object, the present invention provides a semiconductor device comprising:
A substrate having first and second opposed surfaces;
A first ion doped region and a second ion doped region of opposite doping types, the first ion doped region extending from the first surface into the substrate, the second ion doped region extending from a side of the first ion doped region away from the first surface towards the second surface, the second ion doped region comprising at least two layers of ion implanted regions, the ion doping concentration of each layer of ion implanted regions increasing layer by layer in a direction from the first surface towards the second surface, the width of each layer of ion implanted regions increasing layer by layer in a direction parallel to the first surface such that the first ion doped region and the second ion doped region form a graded junction.
Optionally, the substrate includes a base and an intrinsic doped layer formed on the base, and the first ion doped region and the second ion doped region are formed in the intrinsic doped layer.
Optionally, the doping type of the substrate is P-type, the doping type of the first ion doping region is N-type, and the doping type of the second ion doping region is P-type.
Optionally, each layer of the ion implantation region is stacked layer by layer.
Optionally, in the two adjacent layers of the ion implantation regions, the ion implantation region far from the first ion doping region wraps the ion implantation region near to the first ion doping region.
Optionally, a width of a contact region of the second ion doped region with the first ion doped region in a direction parallel to the first surface is smaller than a width of the first ion doped region in a direction parallel to the first surface.
Optionally, the semiconductor device further includes:
and the protection ring is formed on the periphery of the first ion doped region.
The invention also provides a manufacturing method of the semiconductor device, which comprises the following steps:
Providing a substrate, wherein the substrate is provided with a first surface and a second surface which are opposite;
Forming a first ion doped region and a second ion doped region with opposite doping types, wherein the first ion doped region extends into the substrate from the first surface, the second ion doped region extends towards the second surface from one side of the first ion doped region away from the first surface, the second ion doped region comprises at least two layers of ion implantation regions, the ion doping concentration of each layer of ion implantation regions increases layer by layer in the direction from the first surface towards the second surface, and the width of each layer of ion implantation regions in the direction parallel to the first surface increases layer by layer, so that the first ion doped region and the second ion doped region form a graded junction.
Optionally, each layer of the ion implantation region is stacked layer by layer.
Optionally, in the two adjacent layers of the ion implantation regions, the ion implantation region far from the first ion doping region wraps the ion implantation region near to the first ion doping region.
Optionally, the method for manufacturing a semiconductor device further includes:
and forming a protection ring on the periphery of the first ion doped region.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. The semiconductor device comprises a first ion doping region and a second ion doping region with opposite doping types, wherein the first ion doping region extends into the substrate from the first surface, the second ion doping region extends towards the second surface from one side of the first ion doping region away from the first surface, the second ion doping region comprises at least two layers of ion implantation regions, the ion doping concentration of each layer of ion implantation region increases layer by layer in the direction from the first surface towards the second surface, and the width of each layer of ion implantation region increases layer by layer in the direction parallel to the first surface, so that the first ion doping region and the second ion doping region form a slow-changing junction, and the detection efficiency of the semiconductor device can be improved.
2. According to the manufacturing method of the semiconductor device, the first ion doping region and the second ion doping region with opposite doping types are formed, the first ion doping region extends into the substrate from the first surface, the second ion doping region extends towards the second surface from one side, away from the first surface, of the first ion doping region, the second ion doping region comprises at least two layers of ion implantation regions, the ion doping concentration of each layer of ion implantation region is increased layer by layer in the direction from the first surface towards the second surface, and the width of each layer of ion implantation region is increased layer by layer in the direction parallel to the first surface, so that the first ion doping region and the second ion doping region form a graded junction, and the detection efficiency of the semiconductor device can be improved.
Drawings
FIG. 1a is a schematic diagram of a semiconductor device;
fig. 1b is a carrier diffusion schematic of the semiconductor device shown in fig. 1 a;
fig. 2a is a schematic diagram of a semiconductor device according to an embodiment of the present invention;
fig. 2b is a carrier diffusion schematic of the semiconductor device shown in fig. 2 a;
fig. 3 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
The reference numerals of fig. 1a to 3 are as follows:
11-P type substrate, 12-intrinsic doped layer, 13-P type well region, 14-N type well region, 15-multiplication region, 21-substrate, 211-intrinsic doped layer, 22-first ion doped region, 221-ion heavily doped region, 23-second ion doped region, 231-first ion implanted region, 232-second ion implanted region, 233-third ion implanted region, 234-fourth ion implanted region, 24-guard ring, 25-first electrode, 26-second electrode, 27-multiplication region.
Detailed Description
In order to make the objects, advantages and features of the present invention more apparent, the following more particular description of the semiconductor device and method of fabricating the same is provided. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
An embodiment of the invention provides a semiconductor device, which comprises a substrate, a first ion doping region and a second ion doping region, wherein the first surface and the second surface are opposite, the first ion doping region and the second ion doping region are opposite in doping type, the first ion doping region extends into the substrate from the first surface, the second ion doping region extends towards the second surface from one side of the first ion doping region away from the first surface, the second ion doping region comprises at least two layers of ion implantation regions, the ion doping concentration of each layer of ion implantation regions increases layer by layer in the direction from the first surface towards the second surface, and the width of each layer of ion implantation regions increases layer by layer in the direction parallel to the first surface, so that the first ion doping region and the second ion doping region form a graded junction.
The semiconductor device provided in this embodiment is described in detail below with reference to fig. 2a to 2 b.
The substrate comprises a base 21 and an intrinsic doping layer 211 formed on the base 21, wherein the intrinsic doping layer 211 is an epitaxial layer formed on the base 21 through an epitaxial process, the substrate is provided with a first surface and a second surface which are opposite, the first surface is the side, away from the base 21, of the intrinsic doping layer 211, and the second surface is the side, away from the intrinsic doping layer 211, of the base 21.
The intrinsic doped layer 211 has a very low doping level (e.g. below 5 x 10 14 atoms/cm 3), as an example the intrinsic doped layer 211 may be an unintentionally doped semiconductor substrate, i.e. a substrate with a P-or N-type doping caused only by accidental contamination of the impurities during its manufacture, as a variant the intrinsic doped layer 211 may also be a semiconductor substrate with a higher doping level.
The doping types of the substrate 21 and the intrinsic doping layer 211 may be the same or different, for example, the doping type of the substrate 21 may be P-type, the doping type of the intrinsic doping layer 211 may be N-type or P-type, the doping type of the substrate 21 may be N-type, and the doping type of the intrinsic doping layer 211 may be N-type or P-type. Preferably, the substrate 21 is p+ type, the intrinsic doped layer 211 is P-type, and the doping concentration of the substrate 21 is greater than the doping concentration of the intrinsic doped layer 211.
The substrate may be any suitable substrate known to those skilled in the art, and may be at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), or indium phosphide (InP), for example.
The first ion doped region 22 and the second ion doped region 23 are formed in the substrate, i.e., the first ion doped region 22 extends from a first surface of the substrate into the substrate, and the second ion doped region 23 extends from a side of the first ion doped region 22 remote from the first surface toward the second surface.
The first ion doped region 22 and the second ion doped region 23 may be formed in the intrinsic doped layer 211, and the intrinsic doped layer 211 may be a neutral region because the ion doping concentration of the intrinsic doped layer 211 is very low and is far less than the ion doping concentrations of the first ion doped region 22 and the second ion doped region 23.
The doping types of the first ion doped region 22 and the second ion doped region 23 are opposite, the doping types of the second ion doped region 23, the substrate 21 and the intrinsic doped layer 211 are the same, preferably, the doping type of the first ion doped region 22 is N-type, and the doping type of the second ion doped region 23, the substrate 21 and the intrinsic doped layer 211 is P-type, so that a P-N junction is formed between the first ion doped region 22 and the second ion doped region 23.
The second ion-doped region 23 includes at least two layers of ion-doped regions, the ion-doped concentration of each layer of the ion-doped region increases layer by layer in a direction from the first surface toward the second surface, and the width of each layer of the ion-doped region increases layer by layer in a direction parallel to the first surface, so that the first ion-doped region 22 and the second ion-doped region 23 constitute a graded junction. The cross-sectional shape of the ion implantation area of each layer may be circular, square, diamond, or other suitable shape in a cross-section parallel to the first surface. The ion doping concentration of the ion implantation region of each layer may be greater than, equal to, or less than the ion doping concentration of the substrate 21. A multiplication region 27 is formed between the ion implantation region closest to the first ion doped region 22 and the first ion doped region 22.
The ion doping concentration of each layer of the ion implantation region is increased layer by layer in the direction from the first surface toward the second surface, so that a vertical built-in electric field perpendicular to the first surface is formed between two adjacent ion implantation regions, and the direction of the vertical built-in electric field is the same as the direction of an electric field generated by applying a reverse bias voltage to the photodiode in a working state, so that the diffusion speed of carriers to the multiplication region 27 is improved, the loss of carriers in the diffusion process is reduced, the occurrence probability of avalanche is improved, and the detection efficiency of the semiconductor device is improved.
Particularly, when the thickness of the substrate is designed to be large (typically above 7.5 μm) in order to improve the absorption efficiency of the semiconductor device to near infrared light (255 nm-940 nm), the thickness of the intrinsic doped layer 211 is large, and the thickness of the multiplication region 27 is small, so that carriers need to pass through a depletion region (a range from the P-N junction region to the contact of the intrinsic doped layer 211 with the substrate 21) for a long distance to generate avalanche, in this embodiment, the diffusion speed of the carriers is improved by forming a vertical built-in electric field, so that the energy consumption of the carriers in the depletion region is reduced, and more carriers can diffuse into the multiplication region 27, thereby improving the probability of avalanche occurrence.
The width of each layer of the ion implantation area in the direction parallel to the first surface is increased layer by layer in the direction from the first surface to the second surface, so that the built-in electric field formed between two adjacent ion implantation areas not only comprises a vertical built-in electric field vertical to the first surface but also comprises a bending built-in electric field non-parallel to the vertical built-in electric field. The curved built-in electric field can diffuse the carriers located in the edge region outside the width range of the ion implantation region in the intrinsic doped layer 211 into the multiplication region 27 (as curved arrow in fig. 2 b) under the action of the curved built-in electric field, so as to improve the utilization rate of the carriers and further improve the detection efficiency of the semiconductor device.
The orthographic projection of the vertical built-in electric field on the first surface overlaps with the orthographic projection of the ion implantation region closest to the first ion doping region 22 on the first surface, and the orthographic projection of the curved built-in electric field on the first surface, which is located at the periphery of the vertical built-in electric field, overlaps with or intersects with the orthographic projection of the ion implantation region farthest from the first ion doping region 22 on the first surface.
The ion implantation regions of each layer may include, but are not limited to, layer-by-layer wrapping or layer-by-layer stacking, as desired. When the ion implantation regions of the layers are wrapped layer by layer, the doping depth of the ion implantation regions of the layers in the direction perpendicular to the first surface extends from the interface between the first ion implantation region 22 and the second ion implantation region 23 towards the second surface, namely, in the two adjacent layers of ion implantation regions, the ion implantation region away from the first ion implantation region 22 is located not only on the bottom surface of the ion implantation region close to the first ion implantation region 22, but also on the side surface of the ion implantation region close to the first ion implantation region 22, namely, the ion implantation region away from the first ion implantation region 22 is wrapped in a groove shape in the ion implantation region close to the first ion implantation region 22. When the ion implantation regions of the layers are stacked layer by layer, the doping depth of the ion implantation regions of the layers in the direction perpendicular to the first surface extends from the interface of the adjacent ion implantation regions towards the second surface, and is distributed like a hemispherical shape in a step shape, namely, in the two adjacent ion implantation regions, the ion implantation region away from the first ion implantation region 22 is only located at the bottom surface of the ion implantation region close to the first ion implantation region 22, and the ion implantation region away from the first ion implantation region 22 does not include the side surface of the ion implantation region close to the first ion implantation region 22. The ion implantation regions of each layer can share the same axis, and the doping depth of the ion implantation regions of each layer in the direction vertical to the first surface can be the same or different in the adjacent two layers of the ion implantation regions.
The width of the first ion doped region 22 in the direction parallel to the first surface may be between the maximum width and the minimum width of the ion doped regions of the respective layers in the direction parallel to the first surface, or the width of the first ion doped region 22 in the direction parallel to the first surface may be greater than the maximum width of the ion doped regions of the respective layers in the direction parallel to the first surface, or the width of the first ion doped region 22 in the direction parallel to the first surface may be smaller than the minimum width of the ion doped regions of the respective layers in the direction parallel to the first surface. In an embodiment, the width of the contact area between the second ion doped region 23 and the first ion doped region 22 in the direction parallel to the first surface is smaller than the width of the first ion doped region 22 in the direction parallel to the first surface so as to avoid the lateral edge breakdown of the photodiode, wherein when the ion doped regions are stacked layer by layer, the width of the contact area between the second ion doped region 23 and the first ion doped region 22 in the direction parallel to the first surface is the width of the ion doped region closest to the first ion doped region 22 in the direction parallel to the first surface, then the width of the ion doped region closest to the first ion doped region 22 in the direction parallel to the first surface is smaller than the width of the first ion doped region 22 in the direction parallel to the first surface, and when the ion doped regions are wrapped layer by layer, the width of the second ion doped region 23 and the first ion doped region 22 in the direction parallel to the first surface is the width of the ion doped region 22 in the direction parallel to the first surface, and then the width of the ion doped region 22 in the direction parallel to the first surface is smaller than the width of the ion doped region 22 in the direction parallel to the first surface.
And, the greater the width of the ion implantation region closest to the first ion doping region 22 in the direction parallel to the first surface, the greater the width of the multiplication region 27 in the direction parallel to the first surface, and the greater the width of the ion implantation region farthest from the first ion doping region 22 in the direction parallel to the first surface, the greater the number of carriers in the edge region of the ion implantation region in the intrinsic doping layer 211 diffusing into the multiplication region 27, thereby realizing that the carriers in the edge region of the multiplication region 27 can diffuse into the multiplication region 27 under the action of the curved built-in electric field, thereby improving the utilization rate of the carriers and the detection efficiency of the semiconductor device.
In the embodiment shown in fig. 2a to 2b, the second ion doped region 23 includes four ion implanted regions stacked layer by layer in a direction from the first surface toward the second surface, namely, a first ion implanted region 231, a second ion implanted region 232, a third ion implanted region 233 and a fourth ion implanted region 234 stacked layer by layer, the ion doping concentrations of the first ion implanted region 231 to the fourth ion implanted region 234 are gradually increased, and the widths of the first ion implanted region 231 to the fourth ion implanted region 234 in a direction parallel to the first surface are gradually increased. The number of ion implantation layers in the second ion doped region 23 is not particularly limited, and may be set as needed.
The semiconductor device further includes an ion heavily doped region 221 formed on a surface of the first ion doped region 22, wherein the ion heavily doped region 221 has the same doping type as the first ion doped region 22.
The semiconductor device further includes a guard ring 24 formed at the periphery of the first ion doped region 22. The guard ring 24 surrounds the first ion doped region 22, and the substrate is spaced between the guard ring 24 and the first ion doped region 22.
Preferably, the depth of the guard ring 24 is not less than the depth of the first ion doped region 22.
The guard ring 24 may be a shallow trench isolation structure or an ion doped ring. If the guard ring 24 is an ion-doped ring, the doping type of the ion-doped ring may be N-type or P-type.
The semiconductor device further includes a ring-shaped deep trench isolation structure (not shown) formed in the substrate around the guard ring 24, the deep trench isolation structure being spaced apart from the guard ring 24 by the substrate, the deep trench isolation structure being for achieving isolation between adjacent photodiodes to avoid crosstalk.
The depth of the deep trench isolation structure is not less than the depth of the first ion doped region 22.
The deep trench isolation structure is formed in an annular trench (not shown) in the substrate, the deep trench isolation structure comprising a layer of insulating material (not shown) overlying an inner surface of the annular trench and a conductive layer (not shown) filling the annular trench.
In this embodiment of the present invention, since the width of the multiplication region 27 does not need to be increased by increasing the width of the first ion doped region 22 in the direction parallel to the first surface, defects, damages, and the like generated by etching the trench when forming the shallow trench isolation structure and the deep trench isolation structure due to the excessive width of the multiplication region 27 are avoided from directly contacting the multiplication region 27, thereby avoiding the decrease in device performance caused by the increase in the dark count rate.
The semiconductor device further comprises a first electrode 25 and a second electrode 26, wherein the first electrode 25 is formed on the ion heavily doped region 221, the second electrode 26 is formed on the first surface or the second surface of the substrate, the second electrode 26 is formed on the second surface of the substrate in the embodiment shown in fig. 2 a-2 b, the ion heavily doped region 221 is used for connecting the first ion doped region 22, so that contact resistance is reduced when voltage is applied to the first ion doped region 22 through the first electrode 25, and reverse bias voltage is applied to the photodiode through the first electrode 25 and the second electrode 26.
In summary, the semiconductor device provided by the invention comprises a substrate, a first ion doping region and a second ion doping region, wherein the substrate is provided with a first surface and a second surface which are opposite, the first ion doping region extends into the substrate from the first surface, the second ion doping region extends towards the second surface from one side of the first ion doping region away from the first surface, the second ion doping region comprises at least two layers of ion implantation regions, the ion doping concentration of each layer of ion implantation region is increased layer by layer in the direction from the first surface towards the second surface, and the width of each layer of ion implantation region is increased layer by layer in the direction parallel to the first surface, so that the first ion doping region and the second ion doping region form a variable junction. The semiconductor device can improve the detection efficiency of the semiconductor device.
An embodiment of the present invention provides a method for manufacturing a semiconductor device, referring to fig. 3, fig. 3 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, the method for manufacturing a semiconductor device includes:
step S1, providing a substrate, wherein the substrate is provided with a first surface and a second surface which are opposite;
Step S2, forming a first ion doping region and a second ion doping region with opposite doping types, wherein the first ion doping region extends into the substrate from the first surface, the second ion doping region extends towards the second surface from one side of the first ion doping region away from the first surface, the second ion doping region comprises at least two layers of ion implantation regions, the ion doping concentration of each layer of ion implantation region increases layer by layer in the direction from the first surface towards the second surface, and the width of each layer of ion implantation region increases layer by layer in the direction parallel to the first surface, so that the first ion doping region and the second ion doping region form a graded junction.
The method for manufacturing the semiconductor device according to the present embodiment is described in more detail with reference to fig. 2a to 2 b.
According to step S1, a substrate is provided, the substrate having first and second surfaces facing away from each other.
The substrate comprises a base 21 and an intrinsic doping layer 211 formed on the base 21, wherein the intrinsic doping layer 211 is an epitaxial layer formed on the base 21 through an epitaxial process, the side, away from the base 21, of the intrinsic doping layer 211 is the first surface, and the side, away from the intrinsic doping layer 211, of the base 21 is the second surface.
The doping types of the substrate 21 and the intrinsic doping layer 211 may be the same or different, for example, the doping type of the substrate 21 may be P-type, the doping type of the intrinsic doping layer 211 may be N-type or P-type, the doping type of the substrate 21 may be N-type, and the doping type of the intrinsic doping layer 211 may be N-type or P-type. Preferably, the substrate 21 is p+ type, the intrinsic doped layer 211 is P-type, and the doping concentration of the substrate 21 is greater than the doping concentration of the intrinsic doped layer 211.
The substrate may be any suitable substrate known to those skilled in the art, and may be at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), or indium phosphide (InP), for example.
According to step S2, a first ion-doped region 22 and a second ion-doped region 23 of opposite doping types are formed, the first ion-doped region 22 and the second ion-doped region 23 being formed in the substrate, i.e. the first ion-doped region 22 extends from a first surface of the substrate into the substrate, the second ion-doped region 23 extending from a side of the first ion-doped region 22 remote from the first surface towards the second surface.
The first ion doped region 22 and the second ion doped region 23 may be formed in the intrinsic doped layer 211, and the intrinsic doped layer 211 may be a neutral region because the ion doping concentration of the intrinsic doped layer 211 is very low and is far less than the ion doping concentrations of the first ion doped region 22 and the second ion doped region 23.
The doping types of the first ion doped region 22 and the second ion doped region 23 are opposite, the doping types of the second ion doped region 23, the substrate 21 and the intrinsic doped layer 211 are the same, preferably, the doping type of the first ion doped region 22 is N-type, and the doping type of the second ion doped region 23, the substrate 21 and the intrinsic doped layer 211 is P-type, so that a P-N junction is formed between the first ion doped region 22 and the second ion doped region 23.
The second ion-doped region 23 includes at least two layers of ion-doped regions, the ion-doped concentration of each layer of the ion-doped region increases layer by layer in a direction from the first surface toward the second surface, and the width of each layer of the ion-doped region increases layer by layer in a direction parallel to the first surface, so that the first ion-doped region 22 and the second ion-doped region 23 constitute a graded junction. A multiplication region 27 is formed between the ion implantation region closest to the first ion doped region 22 and the first ion doped region 22.
The ion doping concentration of each layer of the ion implantation region is increased layer by layer in the direction from the first surface toward the second surface, so that a vertical built-in electric field perpendicular to the first surface is formed between two adjacent ion implantation regions, and the direction of the vertical built-in electric field is the same as the direction of an electric field generated by applying a reverse bias voltage to the photodiode in a working state, so that the diffusion speed of carriers to the multiplication region 27 is improved, the loss of carriers in the diffusion process is reduced, the occurrence probability of avalanche is improved, and the detection efficiency of the semiconductor device is improved.
The width of each layer of the ion implantation area in the direction parallel to the first surface is increased layer by layer in the direction from the first surface to the second surface, so that the built-in electric field formed between two adjacent ion implantation areas not only comprises a vertical built-in electric field vertical to the first surface but also comprises a bending built-in electric field non-parallel to the vertical built-in electric field. The curved built-in electric field can diffuse the carriers located in the edge region outside the width range of the ion implantation region in the intrinsic doped layer 211 into the multiplication region 27 (as curved arrow in fig. 2 b) under the action of the curved built-in electric field, so as to improve the utilization rate of the carriers and further improve the detection efficiency of the semiconductor device.
The ion implantation regions of each layer may include, but are not limited to, layer-by-layer wrapping or layer-by-layer stacking, as desired. When the ion implantation regions of the layers are wrapped layer by layer, the doping depth of the ion implantation regions of the layers in the direction perpendicular to the first surface extends from the interface between the first ion implantation region 22 and the second ion implantation region 23 towards the second surface, namely, in the two adjacent layers of ion implantation regions, the ion implantation region away from the first ion implantation region 22 is located not only on the bottom surface of the ion implantation region close to the first ion implantation region 22, but also on the side surface of the ion implantation region close to the first ion implantation region 22, namely, the ion implantation region away from the first ion implantation region 22 is wrapped in a groove shape in the ion implantation region close to the first ion implantation region 22. When the ion implantation regions of the layers are stacked layer by layer, the doping depth of the ion implantation regions of the layers in the direction perpendicular to the first surface extends from the interface of the adjacent ion implantation regions towards the second surface, and is distributed like a hemispherical shape in a step shape, namely, in the two adjacent ion implantation regions, the ion implantation region away from the first ion implantation region 22 is only located at the bottom surface of the ion implantation region close to the first ion implantation region 22, and the ion implantation region away from the first ion implantation region 22 does not include the side surface of the ion implantation region close to the first ion implantation region 22. The ion implantation regions of each layer can share the same axis, and the doping depth of the ion implantation regions of each layer in the direction vertical to the first surface can be the same or different in the adjacent two layers of the ion implantation regions.
The width of the first ion doped region 22 in the direction parallel to the first surface may be between the maximum width and the minimum width of the ion doped regions of the respective layers in the direction parallel to the first surface, or the width of the first ion doped region 22 in the direction parallel to the first surface may be greater than the maximum width of the ion doped regions of the respective layers in the direction parallel to the first surface, or the width of the first ion doped region 22 in the direction parallel to the first surface may be smaller than the minimum width of the ion doped regions of the respective layers in the direction parallel to the first surface. In an embodiment, the width of the contact area between the second ion doped region 23 and the first ion doped region 22 in the direction parallel to the first surface is smaller than the width of the first ion doped region 22 in the direction parallel to the first surface so as to avoid the lateral edge breakdown of the photodiode, wherein when the ion doped regions are stacked layer by layer, the width of the contact area between the second ion doped region 23 and the first ion doped region 22 in the direction parallel to the first surface is the width of the ion doped region closest to the first ion doped region 22 in the direction parallel to the first surface, then the width of the ion doped region closest to the first ion doped region 22 in the direction parallel to the first surface is smaller than the width of the first ion doped region 22 in the direction parallel to the first surface, and when the ion doped regions are wrapped layer by layer, the width of the second ion doped region 23 and the first ion doped region 22 in the direction parallel to the first surface is the width of the ion doped region 22 in the direction parallel to the first surface, and then the width of the ion doped region 22 in the direction parallel to the first surface is smaller than the width of the ion doped region 22 in the direction parallel to the first surface.
And, the greater the width of the ion implantation region closest to the first ion doping region 22 in the direction parallel to the first surface, the greater the width of the multiplication region 27 in the direction parallel to the first surface, and the greater the width of the ion implantation region farthest from the first ion doping region 22 in the direction parallel to the first surface, the greater the number of carriers in the edge region of the ion implantation region in the intrinsic doping layer 211 diffusing into the multiplication region 27, thereby realizing that the carriers in the edge region of the multiplication region 27 can diffuse into the multiplication region 27 under the action of the curved built-in electric field, thereby improving the utilization rate of the carriers and the detection efficiency of the semiconductor device.
In the embodiment shown in fig. 2a to 2b, the second ion doped region 23 includes four ion implanted regions stacked layer by layer in a direction from the first surface toward the second surface, namely, a first ion implanted region 231, a second ion implanted region 232, a third ion implanted region 233 and a fourth ion implanted region 234 stacked layer by layer, the ion doping concentrations of the first ion implanted region 231 to the fourth ion implanted region 234 are gradually increased, and the widths of the first ion implanted region 231 to the fourth ion implanted region 234 in a direction parallel to the first surface are gradually increased. The number of ion implantation layers in the second ion doped region 23 is not particularly limited, and may be set as needed.
The first ion doped region 22 may be formed first and then the second ion doped region 23 may be formed, or the second ion doped region 23 may be formed first and then the first ion doped region 22 may be formed by using an ion implantation process.
Taking stacking of the ion implantation regions layer by layer as an example, the step of forming the second ion doped region 23 may include forming a patterned mask layer (not shown) having an opening for ion implantation into the substrate on a first surface of the substrate, then, when forming the ion implantation regions of each layer in sequence along a direction of the first surface toward the second surface, adjusting the width of the opening a plurality of times by changing a photomask, and after each adjustment of the width of the opening, performing ion implantation into the substrate with the patterned mask layer having the opening with the width each time as a mask, the energy and the dose of the ion implantation gradually increase with each adjustment of the width of the opening, so that a layer of ion implantation region having a predetermined depth and width is formed after each ion implantation, and when forming the ion implantation regions of each layer in sequence along the direction of the second surface toward the first surface, adjusting the width of the opening a plurality of times by changing the photomask, and after each adjustment of the width of the opening, performing ion implantation into the substrate with the opening with the ion implantation with the predetermined depth and the ion implantation dose gradually decreasing with each adjustment of the opening with each adjustment of the width of the ion implantation mask layer.
And, after each ion implantation, the substrate needs to be annealed to remove breakage or damage of the semiconductor lattice caused by ion collision.
The method further includes forming an ion heavily doped region 221 on the surface of the first ion doped region 22 by using an ion implantation process, wherein the ion heavily doped region 221 has the same doping type as the first ion doped region 22.
The method further includes forming a guard ring 24 around the periphery of the first ion doped region 22, the guard ring 24 surrounding the first ion doped region 22, the substrate being spaced between the guard ring 24 and the first ion doped region 22.
Preferably, the depth of the guard ring 24 is not less than the depth of the first ion doped region 22.
The guard ring 24 may be a shallow trench isolation structure or an ion doped ring. If the guard ring 24 is an ion-doped ring, the doping type of the ion-doped ring may be N-type or P-type.
The method further includes forming a ring-shaped deep trench isolation structure (not shown) in the substrate around the guard ring 24, the deep trench isolation structure and the guard ring 24 being spaced apart from each other by the substrate, the deep trench isolation structure being used to isolate adjacent photodiodes from each other, so as to avoid crosstalk.
The depth of the deep trench isolation structure is not less than the depth of the first ion doped region 22.
The deep trench isolation structure is formed in an annular trench (not shown) in the substrate, the deep trench isolation structure comprising a layer of insulating material (not shown) overlying an inner surface of the annular trench and a conductive layer (not shown) filling the annular trench.
In this embodiment of the present invention, since the width of the multiplication region 27 does not need to be increased by increasing the width of the first ion doped region 22 in the direction parallel to the first surface, defects, damages, and the like generated by etching the trench when forming the shallow trench isolation structure and the deep trench isolation structure due to the excessive width of the multiplication region 27 are avoided from directly contacting the multiplication region 27, thereby avoiding the decrease in device performance caused by the increase in the dark count rate.
The method further includes forming a first electrode 25 on the ion heavily doped region 221 and forming a second electrode 26 on the first surface or the second surface of the substrate, wherein in the embodiment shown in fig. 2 a-2 b, the second electrode 26 is formed on the second surface of the substrate, the ion heavily doped region 221 is used for connecting out the first ion doped region 22, so that when a voltage is applied to the first ion doped region 22 through the first electrode 25, a contact resistance is reduced, and a reverse bias voltage is applied to the photodiode through the first electrode 25 and the second electrode 26.
In summary, the method for manufacturing a semiconductor device includes providing a substrate having a first surface and a second surface opposite to each other, forming a first ion doped region and a second ion doped region opposite to each other in doping type, wherein the first ion doped region extends from the first surface into the substrate, the second ion doped region extends from a side of the first ion doped region away from the first surface toward the second surface, the second ion doped region includes at least two ion implantation regions, ion doping concentrations of the ion implantation regions of each layer increase layer by layer in a direction from the first surface toward the second surface, and widths of the ion implantation regions of each layer increase layer by layer in a direction parallel to the first surface, so that the first ion doped region and the second ion doped region form a graded junction. The manufacturing method of the semiconductor device can improve the detection efficiency of the semiconductor device.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (11)
1. A semiconductor device, comprising:
A substrate having first and second opposed surfaces;
A first ion doped region and a second ion doped region with opposite doping types are formed in the substrate, the first ion doped region extends from the first surface into the substrate, the second ion doped region extends from one side of the first ion doped region away from the first surface towards the second surface, the second ion doped region comprises at least two layers of ion implanted regions, the ion doping concentration of each layer of ion implanted region increases layer by layer in the direction from the first surface towards the second surface, the width of each layer of ion implanted region increases layer by layer in the direction parallel to the first surface, so that the first ion doped region and the second ion doped region form a slow-changing junction, a multiplication region is formed between the ion implanted region closest to the first ion doped region and the first ion doped region, a built-in electric field is further formed between two adjacent ion implanted regions, and the built-in electric field comprises a built-in electric field perpendicular to the first surface and a built-in electric field perpendicular to the first surface.
2. The semiconductor device of claim 1, wherein the substrate comprises a base and an intrinsic doped layer formed on the base, the first ion doped region and the second ion doped region being formed in the intrinsic doped layer.
3. The semiconductor device of claim 2, wherein the substrate is P-type in doping type, the first ion doped region is N-type in doping type, and the second ion doped region is P-type in doping type.
4. The semiconductor device of claim 1, wherein each layer of the ion implanted regions is stacked layer-by-layer.
5. The semiconductor device of claim 1, wherein in adjacent two layers of the ion implantation regions, the ion implantation region distant from the first ion doping region wraps around the ion implantation region close to the first ion doping region.
6. The semiconductor device of claim 1, wherein a width of a contact region of the second ion doped region with the first ion doped region in a direction parallel to the first surface is smaller than a width of the first ion doped region in a direction parallel to the first surface.
7. The semiconductor device according to claim 1, wherein the semiconductor device further comprises:
and the protection ring is formed on the periphery of the first ion doped region.
8. A method of manufacturing a semiconductor device, comprising:
Providing a substrate, wherein the substrate is provided with a first surface and a second surface which are opposite;
Forming a first ion doped region and a second ion doped region with opposite doping types in the substrate, wherein the first ion doped region extends from the first surface into the substrate, the second ion doped region extends from one side of the first ion doped region away from the first surface towards the second surface, the second ion doped region comprises at least two layers of ion implanted regions, the ion doping concentration of each layer of ion implanted region increases layer by layer in the direction from the first surface towards the second surface, the width of each layer of ion implanted region increases layer by layer in the direction parallel to the first surface, so that the first ion doped region and the second ion doped region form a graded junction, a multiplication region is formed between the ion implanted region closest to the first ion doped region and the first ion doped region, a built-in electric field is formed between two adjacent ion implanted regions, and the built-in electric field comprises a built-in electric field perpendicular to the first surface and a built-in electric field perpendicular to the first surface.
9. The method of manufacturing a semiconductor device according to claim 8, wherein each layer of the ion implantation regions is stacked layer by layer.
10. The method of manufacturing a semiconductor device according to claim 8, wherein the ion implantation regions distant from the first ion implantation region are wrapped around the ion implantation region close to the first ion implantation region in adjacent two layers of the ion implantation regions.
11. The manufacturing method of the semiconductor device according to claim 8, further comprising:
and forming a protection ring on the periphery of the first ion doped region.
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| US10103285B1 (en) * | 2017-04-13 | 2018-10-16 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and method of manufacturing the same |
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| CA1301895C (en) * | 1989-01-12 | 1992-05-26 | Robert J. Mcintyre | Silicon avalanche photodiode with low multiplication noise |
| KR970054544A (en) * | 1995-12-29 | 1997-07-31 | 김주용 | Avalanche Photodiode and Manufacturing Method Thereof |
| US8716792B2 (en) * | 2008-09-30 | 2014-05-06 | Infineon Technologies Austria Ag | Semiconductor device with a charge carrier compensation structure and method for the production of a semiconductor device |
| GB201014843D0 (en) * | 2010-09-08 | 2010-10-20 | Univ Edinburgh | Single photon avalanche diode for CMOS circuits |
| CN103107231A (en) * | 2013-02-05 | 2013-05-15 | 武汉电信器件有限公司 | Avalanche photodiode based on non-N-type indium phosphid (InP) substrate and preparation method thereof |
| CN109638092A (en) * | 2018-11-15 | 2019-04-16 | 天津大学 | The SPAD of the low dark counting of high detection efficient based on standard CMOS process |
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| CN112825339B (en) * | 2019-11-20 | 2025-08-26 | 深圳市灵明光子科技有限公司 | Photoelectric detection unit, photoelectric detection structure, photoelectric detector and preparation method thereof |
| CN113299787B (en) * | 2021-05-21 | 2022-04-29 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
| CN114141886B (en) * | 2021-11-22 | 2024-10-22 | 江苏尚飞光电科技股份有限公司 | Avalanche photodiode array detector |
| CN114242826B (en) * | 2021-12-02 | 2023-12-22 | 武汉新芯集成电路制造有限公司 | Single photon avalanche diode and forming method thereof |
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| CN103178120A (en) * | 2011-12-26 | 2013-06-26 | 江苏宏微科技有限公司 | Fast recovery epitaxial diode (FRED) and preparation method thereof |
| US10103285B1 (en) * | 2017-04-13 | 2018-10-16 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and method of manufacturing the same |
| CN109449083A (en) * | 2018-10-24 | 2019-03-08 | 武汉新芯集成电路制造有限公司 | Graded transition junction, high tension apparatus and semiconductor devices and its manufacturing method |
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