CN115632628B - Filter structure and manufacturing method thereof, filter chip and electronic equipment - Google Patents

Abstract

The application provides a filter structure, which comprises a piezoelectric wafer, wherein the piezoelectric wafer comprises a first surface and a second surface which are oppositely arranged, and a peripheral side surface connected between the first surface and the second surface. The filter structure further comprises a first conductive layer, a second conductive layer and a conductive pattern, wherein the first conductive layer is arranged on the first surface, and the second conductive layer is arranged on the peripheral side surface and connected with the first conductive layer. The conductive pattern is disposed on the second surface and electrically connected to the second conductive layer. The first conductive layer and the second conductive layer are used for leading out charges converged on the conductive pattern through the wafer bearing table contacted with the first conductive layer, so that electrostatic damage to the conductive pattern in the process of manufacturing the filter is avoided. The application also provides a manufacturing method of the filter structure, a filter chip and electronic equipment.

Description

Filter structure and manufacturing method thereof, filter chip and electronic equipment

Technical Field

The present application relates to the field of communication technology, and in particular to a filter structure, a method for manufacturing the filter structure, a filter chip, and an electronic device having the filter chip.

Background technique

Surface acoustic wave filter is an electronic device made of piezoelectric material. It can process the acoustic signal propagating on the surface of piezoelectric material. Surface acoustic wave filter has the advantages of low cost, small size and multiple functions, so it has been widely used in radar, communication, navigation, identification and other fields.

As surface acoustic wave filters develop towards high frequency and miniaturization, the size of surface acoustic wave filters is getting smaller and smaller, and the risk of electrostatic damage is getting higher and higher. Therefore, higher requirements are placed on static elimination during the production process of surface acoustic wave filters.

Therefore, how to eliminate static electricity during the manufacturing process of the surface acoustic wave filter is an urgent problem to be solved by those skilled in the art.

Summary of the invention

In view of the above-mentioned deficiencies in the prior art, the purpose of the present application is to provide a filter structure, a method for manufacturing a filter structure, a filter chip and an electronic device having the filter chip, which are intended to eliminate static electricity during the manufacturing process of a surface acoustic wave filter.

In order to solve the above technical problems, the present application provides a filter structure, the filter structure includes a piezoelectric chip, the piezoelectric chip includes a first surface and a second surface arranged opposite to each other and a peripheral side surface connected between the first surface and the second surface. The filter structure also includes a first conductive layer, a second conductive layer and a conductive pattern, the first conductive layer is arranged on the first surface, the second conductive layer is arranged on the peripheral side surface and connected to the first conductive layer, and the conductive pattern is arranged on the second surface and electrically connected to the second conductive layer. The first conductive layer and the second conductive layer are used to conduct the charge gathered on the conductive pattern through a wafer stage in contact with the first conductive layer.

In summary, the piezoelectric chip, the first conductive layer, the second conductive layer and the conductive pattern provided in the embodiment of the present application, the first conductive layer and the second conductive layer are used to conduct the charges gathered on the conductive pattern through the wafer support table in contact with the first conductive layer, thereby avoiding electrostatic damage to the conductive pattern during the process of manufacturing the filter.

In an exemplary embodiment, the first conductive layer is covered on the first surface; or, the first conductive layer is disposed on a portion of the first surface.

In an exemplary embodiment, the first conductive layer includes a plurality of first conductive segments, and the plurality of first conductive segments are spaced apart and disposed on a portion of the first surface.

In an exemplary embodiment, the second conductive layer is disposed on the peripheral side surface; or, the second conductive layer is disposed on a portion of the peripheral side surface.

In an exemplary embodiment, the second conductive layer includes a plurality of second conductive segments, and the plurality of second conductive segments are disposed at intervals on a portion of the peripheral side surface.

In an exemplary embodiment, the first conductive layer has a thickness of 50 nm to 1000 nm; and/or the second conductive layer has a thickness of 50 nm to 1000 nm.

In an exemplary embodiment, the first conductive layer is integrally formed with the second conductive layer.

In an exemplary embodiment, the conductive pattern includes an IDT, a pad, and a trace, and the second conductive layer is electrically connected to at least one of the IDT, the pad, and the trace.

In an exemplary embodiment, the filter chip also includes a third conductive layer, which is disposed on the second surface, one side of the third conductive layer is connected to the second conductive layer, and the other side of the third conductive layer is connected to the interdigital transducer, the pad, and at least one of the traces.

In an exemplary embodiment, the third conductive layer is disposed around the circumference of the conductive pattern; or the third conductive layer is disposed on a portion of the circumference of the conductive pattern.

In an exemplary embodiment, the third conductive layer includes a plurality of third conductive segments, and the plurality of third conductive segments are arranged at intervals on a peripheral side of the conductive pattern.

Based on the same inventive concept, the present application also provides a method for manufacturing a filter structure, the method for manufacturing the filter is applied to a piezoelectric wafer, the piezoelectric wafer includes a first surface and a second surface arranged opposite to each other and a peripheral side surface connected to the first surface and the second surface, the method includes:

forming a first conductive layer on the first surface, wherein the first conductive layer is in contact with the wafer stage;

forming a second conductive layer on the peripheral side surface, wherein the second conductive layer is connected to the first conductive layer;

A conductive pattern is formed on the second surface, wherein the conductive pattern is electrically connected to the second conductive layer.

In summary, the filter manufacturing method provided in the embodiment of the present application is applied to a piezoelectric chip, the piezoelectric chip includes a first surface and a second surface arranged opposite to each other and a peripheral side surface connected to the first surface and the second surface, the method includes: forming a first conductive layer on the first surface, the first conductive layer is used to contact with a wafer stage; forming a second conductive layer on the peripheral side surface, wherein the second conductive layer is connected to the first conductive layer; forming a conductive pattern on the second surface, wherein the conductive pattern is electrically connected to the second conductive layer. Therefore, the first conductive layer and the second conductive layer are used to conduct the charge gathered on the conductive pattern through the wafer stage in contact with the first conductive layer, thereby avoiding electrostatic damage to the conductive pattern during the process of manufacturing the filter.

In an exemplary embodiment, the first conductive layer is formed on the first surface by a sputtering process; and/or the second conductive layer is formed on the peripheral side surface by a sputtering process.

In an exemplary embodiment, the first conductive layer and the second conductive layer are integrally formed by a sputtering process.

In an exemplary embodiment, an angle between a sputtering direction of the sputtering process for forming the first conductive layer and the second conductive layer and a normal line of the piezoelectric wafer is 30 degrees to 60 degrees.

Based on the same inventive concept, an embodiment of the present application further provides a filter chip, wherein the filter chip comprises at least one filter formed by cutting the filter structure prepared by the above method.

In summary, the filter chip provided by the embodiment of the present application includes at least one filter formed by cutting the filter structure prepared by the filter manufacturing method. Therefore, the filter structure of the present application can lead out the charge gathered on the conductive pattern through the first conductive layer and the second conductive layer through the wafer stage in contact with the first conductive layer, thereby avoiding electrostatic damage to the conductive pattern during the process of making the filter. Moreover, the conductive pattern of the filter structure formed by the filter manufacturing method is not damaged, which ensures the quality and product integrity of the filter chip and increases the service life of the filter chip.

Based on the same inventive concept, an embodiment of the present application further provides an electronic device, which includes at least one of the above-mentioned filter chips.

In summary, the electronic device provided in the embodiment of the present application includes at least one filter chip as described above, and the filter chip includes at least one filter formed by cutting the filter structure prepared by the filter manufacturing method. Therefore, the filter structure of the present application can lead the charge gathered on the conductive pattern through the first conductive layer and the second conductive layer through the wafer stage in contact with the first conductive layer, thereby avoiding electrostatic damage to the conductive pattern during the process of manufacturing the filter. Moreover, the conductive pattern of the filter structure formed by the filter manufacturing method is not damaged, which ensures the quality and product integrity of the filter chip and increases the service life of the filter chip.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

FIG1 is a schematic diagram of a three-dimensional structure of a filter structure disclosed in an embodiment of the present application;

FIG2 is a bottom view of the filter structure shown in FIG1 ;

FIG3 is a schematic diagram of the cross-sectional structure of the filter structure shown in FIG1 along line III-III;

FIG4 is a schematic flow chart of a method for manufacturing a filter structure disclosed in an embodiment of the present application;

FIG. 5 is a schematic diagram of the sputtering direction of the method for manufacturing the filter structure disclosed in an embodiment of the present application.

Description of reference numerals:

1-filter structure; 10-piezoelectric chip; 11-first surface; 13-second surface; 15-side surface; 30-first conductive layer; 31-first conductive segment; 50-second conductive layer; 51-second conductive segment; 70-conductive pattern; 71-interdigital transducer; 73-pad; 75-routing; 90-third conductive layer; 91-third conductive segment; S10-S30-method for manufacturing filter structure.

Detailed ways

In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thoroughly and comprehensively understood.

The following descriptions of the embodiments are with reference to the attached diagrams to illustrate specific embodiments that the present application can be used to implement. The serial numbers for the components herein, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in the present application, unless otherwise specified, include direct and indirect connections (couplings). The directional terms mentioned in the present application, such as "upper", "lower", "front", "back", "left", "right", "inside", "outside", "side", etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the present application, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application.

In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be fixedly connected, detachably connected, or integrally connected; it can be mechanically connected; it can be directly connected, or indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances. It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including", "may include", "include", or "may include" used in this application indicate the existence of the corresponding functions, operations, elements, etc. disclosed, and do not limit one or more other functions, operations, elements, etc. In addition, the terms "including" or "include" indicate the existence of the corresponding features, numbers, steps, operations, elements, components, or combinations thereof disclosed in the specification, and do not exclude the existence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, and are intended to cover non-exclusive inclusions. It should also be understood that "at least one" described herein means one or more, such as one, two or three, etc., and "plurality" means at least two, such as two or three, etc., unless otherwise clearly defined.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

As the surface acoustic wave filters in electronic devices are becoming increasingly miniaturized, the risk of electrostatic damage to the surface acoustic wave filters during the process of manufacturing the surface acoustic wave filters is also increasing. Therefore, during the process of manufacturing the surface acoustic wave filters, the static charge on the surface acoustic wave filters will be released. In order to solve the above problems, an electrostatic release clamp is usually used for conduction, and the contact points on the electrostatic release clamp are in contact with the conductive pattern of the surface acoustic wave filter to conduct away the charge. However, the above-mentioned electrostatic release clamp is complicated to manufacture and has high processing costs. Moreover, the electrostatic release clamp may cause damage to the conductive pattern in the process of clamping the conductive pattern of the surface acoustic wave filter.

Please refer to Figures 1 to 3. Figure 1 is a schematic diagram of the three-dimensional structure of the filter structure disclosed in the embodiment of the present application, Figure 2 is a schematic diagram of the bottom-up structure of the filter structure shown in Figure 1, and Figure 3 is a schematic diagram of the cross-sectional structure of the filter structure shown in Figure 1 along III-III. The filter structure 1 provided in the embodiment of the present application may at least include a piezoelectric chip 10, a first conductive layer 30, and a second conductive layer 50. The piezoelectric chip 10 includes a first surface 11 and a second surface 13 arranged opposite to each other and a peripheral side surface 15 connected between the first surface 11 and the second surface 13, the first conductive layer 30 is arranged on the first surface 11, and the second conductive layer 50 is arranged on the peripheral side surface 15 and connected to the first conductive layer 30. The filter structure 1 also includes a conductive pattern 70, which is arranged on the second surface 13 and electrically connected to the second conductive layer 50. Among them, the first conductive layer 30 and the second conductive layer 50 are used to lead out the charges gathered on the conductive pattern 70 through a wafer stage in contact with the first conductive layer 30. Specifically, a grounding wire is provided on the wafer stage, and the grounding wire is connected to a ground terminal, and the charges on the conductive pattern 70 are conducted out through the second conductive layer 50, the first conductive layer 30 and the grounding wire of the wafer stage.

In an exemplary embodiment, the wafer stage does not belong to the filter structure 1 , and the piezoelectric wafer 10 is placed on the wafer stage when the filter structure 1 is formed.

In summary, the filter structure 1 provided in the embodiment of the present application includes a piezoelectric chip 10, a first conductive layer 30 and a second conductive layer 50. The piezoelectric chip 10 includes a first surface 11 and a second surface 13 arranged opposite to each other and a peripheral side surface 15 connected between the first surface 11 and the second surface 13, the first conductive layer 30 is arranged on the first surface 11, and the second conductive layer 50 is arranged on the peripheral side surface 15 and connected to the first conductive layer 30. The filter structure 1 also includes a conductive pattern 70, which is arranged on the second surface 13 and electrically connected to the second conductive layer 50. Therefore, the filter structure 1 can lead the charge gathered on the conductive pattern 70 through the first conductive layer 30 and the second conductive layer 50 through the wafer stage in contact with the first conductive layer 30, thereby avoiding electrostatic damage to the conductive pattern 70 during the process of making the filter.

In the embodiment of the present application, the first conductive layer 30 is covered on the first surface 11, that is, the peripheral side of the surface of the first conductive layer 30 facing the first surface 11 is flush with the peripheral side of the first surface 11, or the peripheral side of the surface of the first conductive layer 30 facing the first surface 11 extends out of the peripheral side of the first surface 11.

In an exemplary embodiment, the first conductive layer 30 is disposed on a portion of the first surface 11 , that is, the first conductive layer 30 does not completely cover the first surface 11 .

In the embodiment of the present application, the first conductive layer 30 includes a plurality of first conductive segments 31, and the plurality of first conductive segments 31 are arranged at intervals on a portion of the first surface 11. The plurality of first conductive segments 31 may be distributed in a scattered manner, that is, the plurality of first conductive segments 31 extend and diverge from the middle of the first surface 11 to the peripheral side. The plurality of first conductive segments 31 may also be arranged in a cross pattern of multiple rows and columns, so that the plurality of first conductive segments 31 are in a grid shape.

In an exemplary embodiment, the number of the first conductive segments 31 may be 2 to 50, for example, 2, 10, 25, 30, 45, 50, or other numbers, which is not specifically limited in the present application.

In the embodiment of the present application, the second conductive layer 50 is disposed around the peripheral side surface 15 , that is, the peripheral side surface 15 is completely covered by the second conductive layer 50 .

In an exemplary embodiment, the second conductive layer 50 may also be disposed on a portion of the peripheral side surface 15 , that is, a portion of the peripheral side surface 15 is covered by the second conductive layer 50 , and another portion of the peripheral side surface 15 is exposed from the second conductive layer 50 .

In the embodiment of the present application, the second conductive layer 50 includes a plurality of second conductive segments 51 , and the plurality of second conductive segments 51 are disposed at intervals on a portion of the peripheral side surface 15 .

In an exemplary embodiment, a plurality of second conductive segments 51 are evenly spaced apart on a portion of the peripheral side surface 15 , that is, the intervals between adjacent second conductive segments 51 may be equal, or the intervals between adjacent second conductive segments 51 may be unequal.

In an exemplary embodiment, one second conductive segment 51 is connected to one first conductive segment 31 , or multiple second conductive segments 51 are connected to one first conductive segment 31 , or one second conductive segment 51 is connected to multiple first conductive segments 31 , and the present application does not impose any specific limitation on this.

In the embodiment of the present application, the thickness of the first conductive layer 30 is 50nm to 1000nm; and/or the thickness of the second conductive layer 50 is 50nm to 1000nm. For example, 50nm, 200nm, 500nm, 750nm, 900nm, 1000nm, or other values, which are not specifically limited in the present application.

In an exemplary embodiment, the first conductive layer 30 and the second conductive layer 50 may be manufactured in an integrally formed manner.

In an exemplary embodiment, the conductive pattern 70 may include at least an IDT 71, a pad 73, and a trace 75 disposed on the second surface 13. The second conductive layer 50 is electrically connected to at least one of the IDT 71, the pad 73, and the trace 75.

In an exemplary embodiment, the number of the IDT 71 , the pad 73 , and the trace 75 may be multiple, and the present application does not impose any specific limitation on this.

In the embodiment of the present application, the IDT 71 includes a first bus bar and a second bus bar that are arranged opposite to each other, a plurality of first electrode fingers, and a plurality of second electrode fingers. The plurality of first electrode fingers are connected to the first bus bar and extend toward the second bus bar, the plurality of second electrode fingers are connected to the second bus bar and extend toward the first bus bar, and the plurality of first electrode fingers and the plurality of second electrode fingers are alternately arranged in sequence. The IDT 71 is used to convert an electrical signal into an acoustic wave signal or to convert an acoustic wave signal into an electrical signal.

In the embodiment of the present application, the second conductive layer 50 further includes a plurality of reflectors, which are arranged on two opposite sides of the interdigital transducer 71, that is, the first bus bar and the second bus bar are provided with the reflectors at both ends in the length direction. The reflectors are used to reflect the acoustic wave signal, thereby confining the acoustic wave signal between the two reflective structures.

In an exemplary embodiment, the IDT 71 may be electrically connected to the pad 73 via the trace 75 , the IDTs 71 may be electrically connected to each other via the trace 75 , and the pads 73 may be electrically connected to each other via the trace 75 .

In an exemplary embodiment, the number of the IDT 71 , the pad 73 , and the trace 75 may be multiple, and the present application does not impose any specific limitation on this.

In an exemplary embodiment, the component indicated by label 71 in Figure 1 is used to adaptively represent the plurality of the interdigital transducers, the component indicated by label 73 in Figure 1 is used to schematically represent the plurality of the pads, the component indicated by label 75 in Figure 1 is used to schematically represent a portion of the routing, and the remaining routing is arranged between the plurality of the interdigital transducers or between the plurality of the pads.

In an embodiment of the present application, the filter chip also includes a third conductive layer 90, which is arranged on the second surface 13, one side of the third conductive layer 90 is connected to the second conductive layer 50, and the other side of the third conductive layer 90 is connected to the interdigital transducer 71, the pad 73 and at least one of the traces 75.

In an exemplary embodiment, the third conductive layer 90 is disposed around the conductive pattern 70 .

In an exemplary embodiment, the third conductive layer 90 is disposed on a portion of the circumference of the conductive pattern 70 .

In an exemplary embodiment, the third conductive layer 90 includes a plurality of third conductive segments 91 , and the plurality of third conductive segments 91 are disposed at intervals around the conductive pattern 70 , that is, the second surface 13 exposes the plurality of third conductive segments 91 .

In an exemplary embodiment, one third conductive segment 91 is connected to one second conductive segment 51, or multiple third conductive segments 91 are connected to one second conductive segment 51, or one third conductive segment 91 is connected to multiple second conductive segments 51, and the present application does not impose any specific limitation on this.

In an exemplary embodiment, the plurality of third conductive segments 91 are directed toward the conductive pattern 70 from a peripheral side of the second surface 13 .

In an exemplary embodiment, the first conductive layer 30 , the second conductive layer 50 , and the third conductive layer 90 may be made of any one of aluminum, titanium, nickel, and chromium, or may be an alloy formed of at least any two of aluminum, titanium, nickel, and chromium.

In an exemplary embodiment, the first conductive layer 30 , the second conductive layer 50 , and the third conductive layer 90 may be made of the same material or different materials, which is not specifically limited in the present application.

In summary, the filter structure 1 provided in the embodiment of the present application includes a piezoelectric chip 10, a first conductive layer 30 and a second conductive layer 50. The piezoelectric chip 10 includes a first surface 11 and a second surface 13 arranged opposite to each other and a peripheral side surface 15 connected between the first surface 11 and the second surface 13, the first conductive layer 30 is arranged on the first surface 11, and the second conductive layer 50 is arranged on the peripheral side surface 15 and connected to the first conductive layer 30. The filter structure 1 also includes a conductive pattern 70, which is arranged on the second surface 13 and electrically connected to the second conductive layer 50. Therefore, the filter structure 1 of the present application can be used to guide the charges gathered on the conductive pattern 70 through the first conductive layer 30 and the second conductive layer 50 through the wafer stage in contact with the first conductive layer 30, thereby avoiding electrostatic damage to the conductive pattern 70 during the process of making the filter.

Based on the same inventive concept, the embodiment of the present application also provides a method for manufacturing a filter structure, the manufacturing method is applied to a piezoelectric wafer, the piezoelectric wafer includes a first surface 11 and a second surface 13 arranged opposite to each other and a peripheral side surface 15 connected to the first surface 11 and the second surface 13. For the description of the manufacturing method of the filter structure of this embodiment and the filter structure shown in Figures 1 to 3 above, please refer to the relevant description of the filter structure above, which will not be repeated here.

Please refer to FIG4 , which is a flow chart of a method for manufacturing a filter structure disclosed in an embodiment of the present application. The method for manufacturing the filter structure at least includes the following steps:

S10, forming a first conductive layer 30 on the first surface 11, wherein the first conductive layer 30 is used to contact with the wafer stage;

Specifically, the first conductive layer 30 may be formed on the first surface 11 by a sputtering process.

S20, forming a second conductive layer 50 on the peripheral side surface 15, wherein the second conductive layer 50 is connected to the first conductive layer 30;

Specifically, the second conductive layer 50 may be formed on the peripheral side surface 15 by a sputtering process.

S30 , forming a conductive pattern 70 on the second surface 13 , wherein the conductive pattern 70 is electrically connected to the second conductive layer 50 .

Specifically, the conductive pattern 70 may be formed by photolithography, electron beam evaporation, lift-off and other processes.

In an exemplary embodiment, the conductive pattern 70 includes an IDT 71 , a pad 73 , and a trace 75 disposed on the second surface 13 .

In an exemplary embodiment, the first conductive layer 30 and the second conductive layer 50 may be integrally formed by a sputtering process.

Please refer to Figure 5, which is a schematic diagram of the sputtering direction of the method for manufacturing the filter structure disclosed in the embodiment of the present application. In the embodiment of the present application, the angle α between the sputtering direction of the sputtering process for forming the first conductive layer 30 and the second conductive layer 50 and the normal of the piezoelectric wafer is 30 to 60 degrees, for example, 30 degrees, 40 degrees, 45 degrees, 50 degrees, 60 degrees, or other angle values, and the present application does not impose specific restrictions on this. It can be understood that by facilitating the simultaneous formation of the first conductive layer 30 on the first surface 11 and the formation of the second conductive layer 50 on the second surface 13.

In summary, the manufacturing method of the filter structure provided by the embodiment of the present application includes: forming a first conductive layer 30 on the first surface 11, the first conductive layer 30 is used to contact the wafer stage; forming a second conductive layer 50 on the peripheral side surface 15, wherein the second conductive layer 50 is connected to the first conductive layer 30; forming a conductive pattern 70 on the second surface 13, wherein the conductive pattern 70 is electrically connected to the second conductive layer 50. Therefore, the first conductive layer 30 and the second conductive layer 50 can lead the charges gathered on the conductive pattern 70 through the wafer stage in contact with the first conductive layer 30, thereby avoiding electrostatic damage to the conductive pattern 70 during the process of manufacturing the filter.

Based on the same inventive concept, the embodiment of the present application also provides a filter chip, the filter chip comprising at least one filter formed by cutting the filter structure 1 prepared by the above method. Each of the filters comprises a piezoelectric chip element and a conductive sub-pattern arranged on the piezoelectric chip element, the conductive sub-pattern being a part of the conductive pattern 70.

It can be understood that the filter structure 1 is divided into a plurality of filters through a cutting process, and each filter includes a piezoelectric chip element and a conductive sub-pattern arranged on the piezoelectric chip element. The piezoelectric chip is cut to form a plurality of piezoelectric chip elements, and the conductive pattern is cut to form a plurality of conductive sub-patterns. The filter formed after cutting may have part of the first conductive layer or not have part of the first conductive layer, may have part of the second conductive layer or not have part of the second conductive layer, may have part of the third conductive layer or not have part of the third conductive layer. The present application does not specifically limit the number of filters formed by the cutting process.

In an exemplary embodiment, at least one of the filters may be used to form the filter chip, which may further include a circuit board and the like.

In summary, the filter chip provided in the embodiment of the present application includes at least one filter formed by cutting the filter structure 1 prepared by the filter manufacturing method. The conductive pattern 70 of the filter structure 1 formed by the filter manufacturing method is not damaged, which ensures the quality and product integrity of the filter chip and increases the service life of the filter chip.

Based on the same inventive concept, an embodiment of the present application further provides an electronic device, which includes at least one of the above-mentioned filter chips.

In summary, the electronic device provided in the embodiment of the present application includes at least one filter chip, and the filter chip includes at least one filter formed by cutting the filter structure 1 prepared by the filter manufacturing method. The conductive pattern 70 of the filter structure 1 formed by the filter manufacturing method is not damaged, which ensures the quality and product integrity of the filter chip and increases the service life of the filter chip.

In an exemplary embodiment, the electronic device includes but is not limited to: LED panels, tablet computers, laptop computers, navigators, mobile phones, electronic watches, and any other electronic devices or components having PCBA board components, and this application does not impose specific restrictions on this.

It is understandable that the electronic device may also include electronic devices such as personal digital assistants (PDA) and/or music player functions, such as mobile phones, tablet computers, wearable electronic devices with wireless communication functions (such as smart watches), etc. The above-mentioned electronic devices may also be other electronic devices, such as laptop computers (Laptop) with touch-sensitive surfaces (such as touch panels), etc. In some embodiments, the electronic device may have a communication function, that is, it may establish communication with the network through 2G (second-generation mobile phone communication technology specifications), 3G (third-generation mobile phone communication technology specifications), 4G (fourth-generation mobile phone communication technology specifications), 5G (fifth-generation mobile phone communication technology specifications), 6G (sixth-generation mobile phone communication technology specifications) or W-LAN (wireless local area network) or communication methods that may appear in the future. For the sake of simplicity, this embodiment of the present application is not further limited.

In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples" or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

It should be understood that the application of this application is not limited to the above examples. For ordinary technicians in this field, they can make improvements or changes based on the above description, and all these improvements and changes should fall within the scope of protection of the claims attached to this application. Ordinary technicians in this field can understand that all or part of the methods for implementing the above embodiments and equivalent changes made according to the claims of this application still fall within the scope covered by this application.

Claims (15)

1. A filter structure, characterized in that it comprises: A piezoelectric wafer, comprising a first surface and a second surface arranged opposite to each other and a peripheral side surface connected between the first surface and the second surface; A first conductive layer is disposed on the first surface; A second conductive layer, disposed on the peripheral side surface and connected to the first conductive layer; a third conductive layer, disposed on the second surface, and one side of the third conductive layer is electrically connected to the second conductive layer; A conductive pattern is arranged on the second surface and electrically connected to the other side of the third conductive layer, and the third conductive layer is arranged around the conductive pattern; wherein the conductive pattern includes an interdigital transducer, a pad and a wiring, and the third conductive layer is electrically connected to the interdigital transducer, the pad and the wiring, and the first conductive layer and the second conductive layer are used to conduct the charge gathered on the conductive pattern through a wafer stage in contact with the first conductive layer. 2 . The filter structure as claimed in claim 1 , wherein the first conductive layer is covered on the first surface; or the first conductive layer is disposed on a portion of the first surface. 3 . The filter structure according to claim 1 , wherein the first conductive layer comprises a plurality of first conductive segments, and the plurality of first conductive segments are arranged at intervals on a portion of the first surface. 4 . The filter structure according to claim 1 , wherein the second conductive layer is disposed on the peripheral side surface; or the second conductive layer is disposed on a portion of the peripheral side surface. 5 . The filter structure according to claim 1 , wherein the second conductive layer comprises a plurality of second conductive segments, and the plurality of second conductive segments are arranged at intervals on a portion of the peripheral side surface. 6 . The filter structure according to claim 1 , wherein the thickness of the first conductive layer is 50 nm to 1000 nm; and/or the thickness of the second conductive layer is 50 nm to 1000 nm. 7 . The filter structure according to claim 1 , wherein the first conductive layer and the second conductive layer are integrally formed. 8. The filter structure according to claim 1, wherein the conductive pattern comprises an IDT, a pad and a trace, and the second conductive layer is electrically connected to at least one of the IDT, the pad and the trace. 9 . The filter structure according to claim 1 , wherein the third conductive layer comprises a plurality of third conductive segments, and the plurality of third conductive segments are arranged at intervals on a peripheral side of the conductive pattern. 10. A method for manufacturing a filter structure, characterized in that it is applied to a piezoelectric chip, the piezoelectric chip includes a first surface and a second surface arranged opposite to each other and a peripheral side surface connected to the first surface and the second surface, the method comprising: forming a first conductive layer on the first surface, wherein the first conductive layer is in contact with the wafer stage; forming a second conductive layer on the peripheral side surface, wherein the second conductive layer is connected to the first conductive layer; A conductive pattern is formed on the second surface, wherein the filter structure also includes a third conductive layer arranged on the second surface, the third conductive layer is arranged around the conductive pattern, and one side of the third conductive layer is electrically connected to the second conductive layer, and the conductive pattern is electrically connected to the other side of the third conductive layer, the conductive pattern includes an interdigital transducer, a pad and a trace, and the third conductive layer is electrically connected to the interdigital transducer, the pad and the trace. 11. The method for manufacturing a filter structure according to claim 10, characterized in that the first conductive layer is formed on the first surface by a sputtering process; and/or the second conductive layer is formed on the peripheral side surface by a sputtering process. 12 . The method for manufacturing a filter structure according to claim 10 , wherein the first conductive layer and the second conductive layer are integrally formed by a sputtering process. 13 . The method for manufacturing a filter structure according to claim 12 , wherein an angle between a sputtering direction of the sputtering process for forming the first conductive layer and the second conductive layer and a normal line of the piezoelectric chip is 30 to 60 degrees. 14. A filter chip, characterized by comprising at least one filter formed by cutting a filter structure prepared by the method according to any one of claims 10 to 13. 15. An electronic device, comprising at least one filter chip according to claim 14.