CN115642901A - Clock signal processing device - Google Patents

Abstract

The embodiment of the disclosure provides a clock signal processing device, belongs to the technical field of integrated circuits, and solves the problem of competition risk of an internal clock and an SCL signal in an I2C module circuit. The clock signal processing device comprises: when receiving the turning edge of the serial clock line SCL signal, the pulse generation module generates a pulse signal delaying for a set time, provides the pulse signal to the oscillator module through the first node, and provides the SCL signal to the I2C for software control; the oscillator module generates a clock signal to be processed delaying for a set time and provides the clock signal to be processed to the output module when the received pulse signal is a high level signal; the output module is configured to process a glitch signal of a specified time in the clock signal to be processed, output the clock signal and provide the clock signal to the I2C for hardware control. The embodiment of the disclosure is suitable for the clock processing process of I2C.

Description

Clock signal processing device

Technical Field

The embodiment of the disclosure relates to the technical field of integrated circuits, in particular to a clock signal processing device.

Background

In a power management IC (Integrated Circuit Chip), the turning-off and turning-on of some functional modules or the setting of register values may be controlled by a host computer through a communication software mode of an I2C bus (also referred to as "I2C"), and may also be controlled by a hardware mode triggered by the Chip itself. When the I2C in the chip performs various operations by using the internal Clock signal and simultaneously performs control by using the communication Clock SCL (Serial Clock Line) signal of the host, since the two Clock signals are asynchronous signals, there is a possibility that the two control modes are triggered simultaneously, once triggered simultaneously, the I2C module circuit may be in danger of competition, and the chip may be damaged.

Disclosure of Invention

An object of the embodiments of the present disclosure is to provide a clock signal processing apparatus, which solves the problem of race hazard of an internal clock and an SCL signal in an I2C module circuit.

In order to achieve the above object, an embodiment of the present disclosure provides a clock signal processing apparatus, including: the device comprises a pulse generation module, an oscillator module and an output module. Wherein the pulse generation module is configured to generate a pulse signal delayed by a set time and provide the pulse signal to the oscillator module via a first node when receiving a flip edge of a serial clock line SCL signal, and provide the SCL signal to an I2C for software control; the oscillator module is configured to generate a clock signal to be processed delayed by the set time and provide the clock signal to be processed to the output module when the received pulse signal is a high level signal; the output module is configured to process a glitch signal within a specified time in the clock signal to be processed, output a clock signal and provide the clock signal to the I2C for hardware control.

In some embodiments of the present disclosure, the pulse generation module comprises: the first inverter, the first negative pulse generator, the second negative pulse generator and the first NAND gate. Wherein an input terminal of the first inverter is coupled to an SCL signal terminal, and an output terminal of the first inverter is coupled to an input terminal of the first negative pulse generator; the output end of the first negative pulse generator is coupled to the first input end of the first NAND gate, and the first negative pulse generator is configured to generate a negative pulse signal delaying the falling edge of the set time; the input end of the second negative pulse generator is coupled to the SCL signal end, the output end of the second negative pulse generator is coupled to the second input end of the first NAND gate, and the second negative pulse generator is configured to generate a negative pulse signal delaying the rising edge of the set time; the output end of the first NAND gate is coupled with the first node.

In some embodiments of the present disclosure, the first negative pulse generator comprises: the second inverter, the first transistor, the second transistor, the third transistor, the fourth transistor, the first capacitor, the first Schmitt trigger, the third inverter and the second NAND gate. The input end of the second inverter is coupled to the input end of the first negative pulse generator, and the output end of the second inverter is coupled to the control electrode of the first transistor; a first pole of the first transistor is coupled to a first voltage terminal, and a second pole of the first transistor is coupled to a first pole of the second transistor; a control electrode of the second transistor is coupled to the output end of the second inverter, and a second electrode of the second transistor is coupled to a first electrode of the third transistor; a control electrode of the third transistor is coupled to the output end of the second inverter, and a second electrode of the third transistor is coupled to a first electrode of the fourth transistor; a control electrode of the fourth transistor is coupled to the output end of the second inverter, and a second electrode of the fourth transistor is coupled to a second voltage end; a first end of the first capacitor is coupled to the first electrode of the fourth transistor, and a second end of the first capacitor is coupled to the second voltage end; an input end of the first schmitt trigger is coupled to a first end of the first capacitor, and an output end of the first schmitt trigger is coupled to an input end of the third inverter; the output end of the third inverter is coupled to the first input end of the second nand gate; the second input end of the second nand gate is coupled to the input end of the first negative pulse generator, and the output end of the second nand gate is coupled to the output end of the first negative pulse generator.

In some embodiments of the present disclosure, the second negative pulse generator comprises: the fourth inverter, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the second capacitor, the second schmitt trigger, the fifth inverter and the third nand gate. An input end of the fourth inverter is coupled to an input end of the second negative pulse generator, and an output end of the fourth inverter is coupled to a control electrode of the fifth transistor; a first pole of the fifth transistor is coupled to a first voltage terminal, and a second pole of the fifth transistor is coupled to a first pole of the sixth transistor; a control electrode of the sixth transistor is coupled to the output end of the fourth inverter, and a second electrode of the sixth transistor is coupled to the first electrode of the seventh transistor; a control electrode of the seventh transistor is coupled to the output end of the fourth inverter, and a second electrode of the seventh transistor is coupled to the first electrode of the eighth transistor; a control electrode of the eighth transistor is coupled to the output end of the fourth inverter, and a second electrode of the eighth transistor is coupled to the second voltage end; a first end of the second capacitor is coupled to the first electrode of the eighth transistor, and a second end of the second capacitor is coupled to the second voltage end; an input end of the second schmitt trigger is coupled to the first end of the second capacitor, and an output end of the second schmitt trigger is coupled to an input end of the fifth inverter; the output end of the fifth inverter is coupled to the first input end of the third nand gate; the second input end of the third nand gate is coupled to the input end of the second negative pulse generator, and the output end of the third nand gate is coupled to the output end of the second negative pulse generator.

In some embodiments of the present disclosure, when the glitch signal is a high-level glitch signal, the output module includes: and a rising edge delay module. The input end of the rising edge delay module is coupled to the input end of the output module, the output end of the rising edge delay module is coupled to the output end of the output module, and the rising edge delay module is configured to filter the high-level glitch signal at the specified time in the clock signal to be processed.

In some embodiments of the present disclosure, when the glitch signal is a low-level glitch signal, the output module includes: and a falling edge delay module. The input end of the falling edge delay module is coupled to the input end of the output module, the output end of the falling edge delay module is coupled to the output end of the output module, and the falling edge delay module is configured to filter the low-level glitch signal of the specified time in the clock signal to be processed.

In some embodiments of the present disclosure, the set time is greater than or equal to 20ns.

In some embodiments of the present disclosure, the specified time is 5ns.

In some embodiments of the present disclosure, the first transistor, the second transistor, and the third transistor are all PMOS transistors, and the fourth transistor is an NMOS transistor.

In some embodiments of the present disclosure, the fifth transistor, the sixth transistor and the seventh transistor are all PMOS transistors, and the eighth transistor is an NMOS transistor.

Through the technical scheme, when the overturning edge of the SCL signal is received, the clock signal is overturned after being delayed for the set time, software control can be realized by the SCL signal firstly when software and hardware control arrives at the same time, hardware control can be realized by the clock signal CLK after the clock signal is delayed for the set time, and the risk of competition between the SCL signal and the clock signal CLK is avoided.

Additional features and advantages of embodiments of the present disclosure will be described in detail in the detailed description which follows.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the detailed description serve to explain the embodiments of the disclosure, but are not intended to limit the embodiments of the disclosure. In the drawings:

FIG. 1 is a schematic diagram of an I2C module controlled by an SCL signal and an internal clock signal CLK independently;

FIG. 2 is a schematic block diagram of a clock signal processing apparatus 200 according to an embodiment of the present disclosure;

fig. 3 is an exemplary circuit diagram of a clock signal processing apparatus 200 according to an embodiment of the present disclosure;

FIG. 4 is an exemplary circuit diagram of a rising edge delay module according to an embodiment of the disclosure;

fig. 5 is a schematic diagram of the comparison waveforms of the SCL signal and the clock signal CLK according to an embodiment of the present disclosure.

The elements in the drawings are schematic and not drawn to scale.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described below in detail and completely with reference to the accompanying drawings. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are also within the scope of protection of the disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the presently disclosed subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, the statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or joined through one or more intermediate components.

In all embodiments of the present disclosure, since the source and the drain of a Metal Oxide Semiconductor (MOS) transistor are symmetrical and the directions of on-currents between the source and the drain of an N-type transistor and a P-type transistor are opposite, in embodiments of the present disclosure, the controlled middle terminal of the MOS transistor is referred to as a control electrode, and the remaining two terminals of the MOS transistor are referred to as a first electrode and a second electrode, respectively. The transistors employed in the embodiments of the present disclosure are primarily switching transistors. For convenience of general description, a base of a Bipolar Junction Transistor (BJT) is referred to as a control electrode, an emitter of the BJT is referred to as a first electrode, and a collector of the BJT is referred to as a second electrode. In addition, terms such as "first" and "second" are only used to distinguish one element (or part of an element) from another element (or another part of an element).

Fig. 1 shows a schematic diagram of the SCL signal and the internal clock signal CLK being independently input to the I2C module for control. The oscillator OSC outputs an internal clock signal CLK to the I2C module, and the SCL signal is directly provided to the I2C module, which may cause an error state inside the I2C module and cause a contention hazard when the SCL signal and the internal clock signal CLK simultaneously generate a rising edge.

The embodiment of the disclosure provides a clock signal processing device. The clock signal that the device was handled and is obtained in case meet the upset border of SCL signal, will delay a period and overturn again to can guarantee when software and hardware control comes simultaneously, utilize the SCL signal to realize software control earlier, delay a period I2C can handle the time after, utilize clock signal to realize I2C's hardware control, thereby avoid the competition adventure of clock signal and SCL signal. Fig. 2 shows a schematic block diagram of a clock signal processing apparatus 200 according to an embodiment of the present disclosure. As shown in fig. 2, the clock signal processing apparatus 200 may include: a pulse generation module 210, an oscillator module 220, and an output module 230.

The pulse generation module 210 may be coupled to the oscillator module 220. The pulse generating module 210 may be configured to generate a pulse signal delayed by a set time and provide the pulse signal to the oscillator module 220 via the first node N1 when receiving a flip edge of an SCL signal, and provide the SCL signal to I2C for software control.

The oscillator module 220 may be coupled to the pulse generation module 210 and the output module 230. The oscillator module 220 may be configured to generate a clock signal to be processed CLK0 delayed by the set time and provide the clock signal to be processed CLK0 to the output module when the received pulse signal is a high level signal. That is, when the pulse signal is a high level signal, the clock signal to be processed CLK0 does not change, and it maintains the signal state of the previous set time.

The output module 230 may be coupled to the oscillator module 220. The output module 230 may be configured to process a glitch signal of a specified time in the clock signal to be processed CLK0, output the clock signal CLK, and provide the clock signal CLK to the I2C for hardware control.

According to the clock signal processing device disclosed by the embodiment of the disclosure, when the turning edge of the SCL signal is received, the clock signal is turned after being delayed for the set time, so that software control can be realized by using the SCL signal when software and hardware control arrives at the same time, and hardware control can be realized by using the clock signal CLK after being delayed for the set time, so that the competition risk of the SCL signal and the clock signal CLK is avoided.

Fig. 3 shows an exemplary circuit diagram of a clock signal processing apparatus 200 according to an embodiment of the present disclosure. As shown in fig. 3, the pulse generation module 210 may include: a first inverter D1, a first negative pulse generator 211, a second negative pulse generator 212, and a first nand gate G1. An input terminal of the first inverter D1 is coupled to the SCL signal terminal, and an output terminal of the first inverter D1 is coupled to the input terminal of the first negative pulse generator 211. The output terminal of the first negative pulse generator 211 is coupled to the first input terminal of the first nand gate G1, and the first negative pulse generator is configured to generate a negative pulse signal delaying the falling edge of the set time. An input terminal of the second negative pulse generator 212 is coupled to the SCL signal terminal, an output terminal of the second negative pulse generator 212 is coupled to a second input terminal of the first nand gate G1, and the second negative pulse generator 212 is configured to generate a negative pulse signal delaying a rising edge of the set time. The output end of the first nand gate G1 is coupled to the first node N1.

Specifically, the first negative pulse generator 211 may include: a second inverter D2, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first capacitor C1, a first schmitt trigger I1, a third inverter D3, and a second nand gate G2. An input terminal of the second inverter D2 is coupled to the input terminal of the first negative pulse generator 211, and an output terminal of the second inverter D2 is coupled to the control electrode of the first transistor M1. A first pole of the first transistor M1 is coupled to the first voltage terminal V1, and a second pole of the first transistor M1 is coupled to a first pole of the second transistor M2. A control electrode of the second transistor M2 is coupled to the output terminal of the second inverter D2, and a second electrode of the second transistor M2 is coupled to a first electrode of the third transistor M3. A control electrode of the third transistor M3 is coupled to the output terminal of the second inverter D2, and a second electrode of the third transistor M3 is coupled to a first electrode of the fourth transistor M4. A control electrode of the fourth transistor M4 is coupled to the output end of the second inverter D2, and a second electrode of the fourth transistor M4 is coupled to the second voltage terminal V2. A first end of the first capacitor C1 is coupled to the first electrode of the fourth transistor M4, and a second end of the first capacitor C1 is coupled to the second voltage terminal V2. An input terminal of the first schmitt trigger I1 is coupled to the first terminal of the first capacitor C1, and an output terminal of the first schmitt trigger I1 is coupled to an input terminal of the third inverter D3. The first schmitt trigger I1 prevents the input terminal of the first negative pulse generator 211 from outputting glitches during the middle level fluctuation. The output end of the third inverter D3 is coupled to the first input end of the second nand gate G2. A second input end of the second nand gate G2 is coupled to the input end of the first negative pulse generator 211, and an output end of the second nand gate G2 is coupled to the output end of the first negative pulse generator 211.

The second negative pulse generator 212 may include: a fourth inverter D4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a second capacitor C2, a second schmitt trigger I2, a fifth inverter D5, and a third nand gate G3. An input terminal of the fourth inverter D4 is coupled to the input terminal of the second negative pulse generator 212, and an output terminal of the fourth inverter D4 is coupled to the control electrode of the fifth transistor M5. A first pole of the fifth transistor M5 is coupled to the first voltage terminal V1, and a second pole of the fifth transistor M5 is coupled to a first pole of the sixth transistor M6. A control electrode of the sixth transistor M6 is coupled to the output end of the fourth inverter D4, and a second electrode of the sixth transistor M6 is coupled to a first electrode of the seventh transistor M7. A control electrode of the seventh transistor M7 is coupled to the output end of the fourth inverter D4, and a second electrode of the seventh transistor M7 is coupled to a first electrode of the eighth transistor M8. A control electrode of the eighth transistor M8 is coupled to the output end of the fourth inverter D4, and a second electrode of the eighth transistor M8 is coupled to the second voltage terminal V2. A first end of the second capacitor C2 is coupled to the first electrode of the eighth transistor M8, and a second end of the second capacitor C2 is coupled to the second voltage terminal V2. An input terminal of the second schmitt trigger I2 is coupled to the first terminal of the second capacitor C2, and an output terminal of the second schmitt trigger I2 is coupled to an input terminal of the fifth inverter D5. Also, the second schmitt trigger I2 prevents the input terminal of the second negative pulse generator 212 from outputting glitches during the middle level fluctuation. The output end of the fifth inverter D5 is coupled to the first input end of the third nand gate G3. A second input terminal of the third nand gate G3 is coupled to the input terminal of the second negative pulse generator 212, and an output terminal of the third nand gate G3 is coupled to the output terminal of the second negative pulse generator 212.

In an implementation manner of the embodiment of the present disclosure, when the glitch signal is a high-level glitch signal, i.e. I2C operates on a rising edge of the clock signal CLK, the output module 230 includes: rising edge delay module (not shown). An input terminal of the rising edge delay module is coupled to the input terminal of the output module 230, an output terminal of the rising edge delay module is coupled to the output terminal of the output module 230, and the rising edge delay module is configured to filter the high-level glitch signal at the specified time in the clock signal to be processed.

In addition, in another implementation manner of the embodiment of the present disclosure, when the glitch signal is a low-level glitch signal, that is, when I2C operates on a falling edge of the clock signal CLK, the output module 230 includes: a falling edge delay module (not shown). An input terminal of the falling edge delay module is coupled to the input terminal of the output module 230, an output terminal of the falling edge delay module is coupled to the output terminal of the output module 230, and the falling edge delay module is configured to filter the low-level glitch signal of the specified time in the clock signal to be processed.

For the rising edge delay module and the falling edge delay module, the design can be performed by using a delay circuit that is conventional in the prior art, as shown in fig. 4, which is an exemplary circuit diagram of the rising edge delay module, an input terminal in is coupled to the input terminal of the output module 230, and an output terminal out is coupled to the output terminal of the output module 230. The rising edge delay module can also be realized by using other circuits, and the falling edge delay module can also be designed by using other common delay function circuits according to the needs of users.

In the example of fig. 3, a high voltage signal is input from the first voltage terminal V1, which may be an internal power supply, and the second voltage terminal V2 is grounded. The shortest time that I2C in the disclosed embodiments is acceptable without creating a race hazard is 20ns, and thus the set time is greater than or equal to 20ns. In the disclosed embodiment, the setting of the set time depends on specific circuit requirements, such as the communication frequency of the I2C and the hardware clock period. The setting time is too short to cause the I2C to start hardware control without having time to execute the software command, and cannot be too long to cause the next edge not to be recognized, or the internal clock delay is too long to cause other functional errors, in the embodiment of the present disclosure, the setting time is made to be greater than or equal to 20ns by designing the sizes of the first capacitor C1 and the second capacitor C2 in fig. 3, and the sizes of the first transistor M1 to the eighth transistor M8. In addition, the specified time may take into account the longest time that a glitch may occur in the oscillator module 220 plus a margin, for example, the specified time may be set to 5ns, and a level signal generally shorter than 5ns may be only noise, and thus in an embodiment of the present disclosure, the specified time may be set to 5ns. The first transistor M1, the second transistor M2, the third transistor M3, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are PMOS transistors, and the fourth transistor M4 and the eighth transistor M8 are NMOS transistors. It will be appreciated by those skilled in the art that variations to the circuit shown in fig. 3 based on the inventive concepts described above are intended to fall within the scope of the present disclosure. In this modification, the above-described transistor and voltage terminal may also have different arrangements from the example shown in fig. 3.

The working process of the clock signal processing apparatus 200 according to the embodiment of the present disclosure is described below with reference to the example of fig. 3.

When the signal input from the SCL signal terminal is a high level signal and is a low level signal after passing through the first inverter D1, the second input terminal of the second nand gate G2 is a low level signal, and the output of the second nand gate G2 is a high level signal no matter whether the first input terminal of the second nand gate G2 is a high level signal or a low level signal. When the SCL signal is a high level signal for a period of time, a low level signal is continued for a period of time after passing through the first inverter D1, a high level signal is continued for a period of time after passing through the second inverter D2, the first transistor M1 to the third transistor M3 are all turned off, the fourth transistor M4 is turned on, the first capacitor C1 discharges, the input of the third inverter D3 is a low level signal, the input of the first input end of the second nand gate G2 is a high level signal, and the output of the second nand gate G2 is a high level signal.

When the signal input by the SCL signal terminal changes from a high level signal to a low level signal, the output of the first inverter D1 changes from a low level signal to a high level signal, and the second input terminal of the second nand gate G2 is a high level signal, and the output of the second nand gate G2 depends on the first input terminal thereof. Since the first input end of the second nand gate G2 is a high level signal before, the second inverter D2 outputs a low level signal changed from a high level signal, the first transistor M1 to the third transistor M3 are all turned on, the fourth transistor M4 is turned off, the first capacitor C1 is charged so that the input end of the third inverter D3 is not turned high, the first input end of the second nand gate G2 is still a high level signal, and the output of the second nand gate G2 is still a low level signal at this time. At this time, the potential of the first node N1 is determined to be a high level signal no matter whether the second input terminal of the first nand gate G1 is a high level signal or a low level signal. The high level signal of the first node N1 is input into the oscillator module 220, and the clock signal CLK0 to be processed output by the oscillator module 220 maintains a state not inverted while the first node N1 is a high level signal. Therefore, at the falling edge of the SCL signal, a high level pulse appears at the first node N1 due to the first negative pulse generator 211. The output end of the second nand gate G2 maintains the low level signal of the set time by setting the sizes of the first capacitor C1 and the first to fourth transistors M1 to M4, that is, the first input end of the first nand gate G1 maintains the low level signal of the set time.

In the path from the SCL signal terminal to the first node N1, the first negative pulse generator 211 and the second negative pulse generator 212 only have the difference of whether to pass through the first inverter D1, so similarly, on the rising edge of the SCL signal, a high level signal appears on the first node N1 due to the second negative pulse generator 212. Similarly, the output end of the third nand gate G3 maintains the low level signal for the set time by setting the sizes of the second capacitor C2 and the fifth to eighth transistors M5 to M8, that is, the second input end of the first nand gate G1 maintains the low level signal for the set time.

In summary, as shown in fig. 5, before the application of the embodiment of the present disclosure, the waveform of the clock signal CLK is shown by a dotted line in fig. 5, which has a rising edge race hazard with the SCL signal, and after the application of the embodiment of the present disclosure, the waveform of the clock signal CLK is shown by a solid line in fig. 5, and at a set time (i.e., an interval time between the solid line and the dotted line in the waveform of the clock signal CLK), the clock signal CLK does not flip and maintains the previous state, so that the I2C can perform software control by using the SCL signal first and then perform hardware control by using the clock signal CLK, thereby solving the race hazard problem of the clock signal CLK and the SCL signal in the I2C module.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus and methods according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

As used herein and in the appended claims, the singular forms of words include the plural and vice versa, unless the context clearly dictates otherwise. Thus, when referring to the singular, the plural of the corresponding terms is generally included. Similarly, the terms "comprising" and "including" are to be construed as being inclusive rather than exclusive. Likewise, the terms "include" and "or" should be construed as inclusive unless such interpretation is explicitly prohibited herein. Where the term "example" is used herein, particularly when it comes after a set of terms, it is merely exemplary and illustrative and should not be considered exclusive or extensive.

Further aspects and ranges of adaptability will become apparent from the description provided herein. It should be understood that various aspects of the present application may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.

Several embodiments of the present disclosure have been described in detail above, but it is apparent that various modifications and variations can be made to the embodiments of the present disclosure by those skilled in the art without departing from the spirit and scope of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims (10)

1. An apparatus for processing a clock signal, comprising: a pulse generating module, an oscillator module and an output module,

wherein the pulse generation module is configured to generate a pulse signal delayed by a set time and provide the pulse signal to the oscillator module via a first node when receiving a flip edge of a serial clock line SCL signal, and provide the SCL signal to an I2C for software control;

the oscillator module is configured to generate a clock signal to be processed delayed by the set time and provide the clock signal to be processed to the output module when the received pulse signal is a high level signal;

the output module is configured to process a glitch signal of a specified time in the clock signal to be processed, output a clock signal and provide the clock signal to the I2C for hardware control.

2. The apparatus for processing a clock signal according to claim 1, wherein the pulse generating module comprises: a first inverter, a first negative pulse generator, a second negative pulse generator and a first NAND gate,

wherein, the input terminal of the first inverter is coupled to the SCL signal terminal, and the output terminal of the first inverter is coupled to the input terminal of the first negative pulse generator;

the output end of the first negative pulse generator is coupled to the first input end of the first NAND gate, and the first negative pulse generator is configured to generate a negative pulse signal delaying the falling edge of the set time;

the input end of the second negative pulse generator is coupled to the SCL signal end, the output end of the second negative pulse generator is coupled to the second input end of the first NAND gate, and the second negative pulse generator is configured to generate a negative pulse signal delaying the rising edge of the set time;

the output end of the first NAND gate is coupled with the first node.

3. The apparatus for processing a clock signal according to claim 2, wherein the first negative pulse generator comprises: a second inverter, a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, a first Schmitt trigger, a third inverter, and a second NAND gate,

the input end of the second inverter is coupled with the input end of the first negative pulse generator, and the output end of the second inverter is coupled with the control electrode of the first transistor;

a first pole of the first transistor is coupled to a first voltage end, and a second pole of the first transistor is coupled to a first pole of the second transistor;

a control electrode of the second transistor is coupled to the output end of the second inverter, and a second electrode of the second transistor is coupled to a first electrode of the third transistor;

a control electrode of the third transistor is coupled to the output end of the second inverter, and a second electrode of the third transistor is coupled to a first electrode of the fourth transistor;

a control electrode of the fourth transistor is coupled to the output end of the second inverter, and a second electrode of the fourth transistor is coupled to a second voltage end;

a first end of the first capacitor is coupled to the first electrode of the fourth transistor, and a second end of the first capacitor is coupled to the second voltage end;

an input end of the first schmitt trigger is coupled to a first end of the first capacitor, and an output end of the first schmitt trigger is coupled to an input end of the third inverter;

the output end of the third inverter is coupled to the first input end of the second nand gate;

the second input end of the second nand gate is coupled to the input end of the first negative pulse generator, and the output end of the second nand gate is coupled to the output end of the first negative pulse generator.

4. The apparatus for processing a clock signal according to claim 2, wherein the second negative pulse generator comprises: a fourth inverter, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a second capacitor, a second Schmitt trigger, a fifth inverter, and a third NAND gate,

an input end of the fourth inverter is coupled to the input end of the second negative pulse generator, and an output end of the fourth inverter is coupled to the control electrode of the fifth transistor;

a first pole of the fifth transistor is coupled to a first voltage terminal, and a second pole of the fifth transistor is coupled to a first pole of the sixth transistor;

a control electrode of the sixth transistor is coupled to the output end of the fourth inverter, and a second electrode of the sixth transistor is coupled to the first electrode of the seventh transistor;

a control electrode of the seventh transistor is coupled to the output end of the fourth inverter, and a second electrode of the seventh transistor is coupled to the first electrode of the eighth transistor;

a control electrode of the eighth transistor is coupled to the output end of the fourth inverter, and a second electrode of the eighth transistor is coupled to the second voltage end;

a first end of the second capacitor is coupled to the first electrode of the eighth transistor, and a second end of the second capacitor is coupled to the second voltage end;

an input end of the second schmitt trigger is coupled to the first end of the second capacitor, and an output end of the second schmitt trigger is coupled to an input end of the fifth inverter;

the output end of the fifth inverter is coupled to the first input end of the third nand gate;

the second input end of the third nand gate is coupled to the input end of the second negative pulse generator, and the output end of the third nand gate is coupled to the output end of the second negative pulse generator.

5. The apparatus for processing a clock signal according to claim 1, wherein when the glitch signal is a high-level glitch signal, the output module comprises: a rising edge time delay module for delaying the rising edge,

the input end of the rising edge delay module is coupled to the input end of the output module, the output end of the rising edge delay module is coupled to the output end of the output module, and the rising edge delay module is configured to filter the high-level glitch signal at the specified time in the clock signal to be processed.

6. The apparatus for processing a clock signal according to claim 1, wherein when the glitch signal is a low-level glitch signal, the output module comprises: a falling edge time delay module for delaying the falling edge,

the input end of the falling edge delay module is coupled to the input end of the output module, the output end of the falling edge delay module is coupled to the output end of the output module, and the falling edge delay module is configured to filter the low-level glitch signal of the specified time in the clock signal to be processed.

7. The apparatus for processing a clock signal according to claim 1, wherein the set time is greater than or equal to 20ns.

8. The apparatus for processing a clock signal according to claim 1, wherein the specified time is 5ns.

9. The apparatus of claim 3, wherein the first transistor, the second transistor, and the third transistor are all PMOS transistors, and the fourth transistor is an NMOS transistor.

10. The apparatus of claim 4, wherein the fifth transistor, the sixth transistor, and the seventh transistor are all PMOS transistors, and the eighth transistor is an NMOS transistor.

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