CN115663021A - Germanium-silicon heterojunction bipolar transistor structure, forming method thereof and crystal growth method - Google Patents
Germanium-silicon heterojunction bipolar transistor structure, forming method thereof and crystal growth method Download PDFInfo
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- CN115663021A CN115663021A CN202211336769.1A CN202211336769A CN115663021A CN 115663021 A CN115663021 A CN 115663021A CN 202211336769 A CN202211336769 A CN 202211336769A CN 115663021 A CN115663021 A CN 115663021A
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- 238000000034 method Methods 0.000 title claims abstract description 171
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 title claims abstract description 20
- 238000002109 crystal growth method Methods 0.000 title claims abstract description 11
- 239000000463 material Substances 0.000 claims abstract description 111
- 239000000126 substance Substances 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 210000000746 body region Anatomy 0.000 claims abstract description 33
- 238000000407 epitaxy Methods 0.000 claims abstract description 13
- 150000002500 ions Chemical class 0.000 claims description 67
- 238000004381 surface treatment Methods 0.000 claims description 23
- 239000003989 dielectric material Substances 0.000 claims description 20
- 238000000137 annealing Methods 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 15
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 12
- 239000002019 doping agent Substances 0.000 claims description 11
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- 239000011737 fluorine Substances 0.000 claims description 7
- -1 fluorine ions Chemical class 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 6
- 238000004140 cleaning Methods 0.000 claims description 3
- 125000006850 spacer group Chemical group 0.000 claims 3
- 239000010410 layer Substances 0.000 description 189
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 5
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
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- 238000005516 engineering process Methods 0.000 description 4
- 229910000041 hydrogen chloride Inorganic materials 0.000 description 4
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- 238000002955 isolation Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
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Abstract
A germanium-silicon heterojunction bipolar transistor structure, a forming method thereof and a crystal growth method are disclosed, wherein the method comprises the following steps: providing a substrate, wherein the substrate comprises a base and a collector region positioned on the base; forming a mask layer structure on the substrate, wherein the mask layer structure comprises a mask layer, a first opening is formed in the mask layer, the mask layer comprises a main body region and a surface region located on the main body region, a chemical bond of a material of the main body region has a first bond energy, a doped ion is arranged in the surface region, a chemical bond formed by the doped ion and an ion of the material of the surface region has a second bond energy, and the second bond energy is greater than the first bond energy; and forming a main base region on the surface of the collector region under the first opening by using the mask layer as a mask and adopting a selective epitaxy process, so that the growth selectivity of the main base region material is improved, and further, a process window is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a germanium-silicon heterojunction bipolar transistor structure, a forming method thereof and a crystal growth method.
Background
With the development of society and the demand for high performance and low cost RF components in high frequency bands for modern communications, conventional silicon material devices are unable to meet these new performance requirements. Because the high-frequency performance of a germanium-silicon heterojunction Bipolar Transistor (HBT for short) is greatly superior to that of a silicon Bipolar Transistor, and the compatibility with a silicon process enables the HBT to have the low price of silicon, the germanium-silicon technology has been greatly developed, and the germanium-silicon HBT technology has become one of the mainstream technologies in the RF integrated circuit market and has a profound influence on the development of the modern communication technology.
The base region of the SiGe heterojunction bipolar transistor structure is made of SiGe and is obtained by adopting a selective epitaxy process. However, during the formation of the base region, the process window of the selective epitaxial process is small, and the development of the process of the germanium-silicon heterojunction bipolar transistor structure is limited.
Therefore, the formation process of the existing sige heterojunction bipolar transistor structure is to be further improved.
Disclosure of Invention
The invention aims to provide a germanium-silicon heterojunction bipolar transistor structure, a forming method thereof and a crystal growth method, so as to improve the forming process window of the germanium-silicon heterojunction bipolar transistor structure.
In order to solve the above technical problems, a sige heterojunction bipolar transistor structure according to the present invention includes: the device comprises a substrate, a first electrode and a second electrode, wherein the substrate comprises a base and a collector region positioned on the base; the mask layer structure comprises a mask layer, a second opening is formed in the mask layer structure, the top surface of the collector region is exposed out of the second opening, the mask layer comprises a main body region and a surface region, the surface region is located on the main body region, a chemical bond of a material of the main body region has first bond energy, a doped ion is arranged in the surface region, a chemical bond formed by the doped ion and an ion of the material of the surface region has second bond energy, and the second bond energy is larger than the first bond energy; and the main base region is positioned on the surface of the collector region exposed by the second opening.
Optionally, the dopant ions include fluorine ions; the chemical bonds of the bulk region material comprise silicon-nitrogen bonds and the chemical bonds of the surface region material comprise silicon-fluorine bonds.
Optionally, the mask layer structure further includes a dielectric layer, and two mutually-separated outer base regions located on the surface of the dielectric layer, the second opening is located in the dielectric layer and exposes the collector region and a part of the surface of the outer base region, the mask layer is located on the top surface and the side wall of the outer base region, a first opening is formed in the mask layer and is mutually communicated with the first opening, and the collector region and a part of the outer base region are exposed from the second opening; the mask layer comprises a covering layer located on the top surface of the outer base region and a side wall located on the side wall of the outer base region.
Correspondingly, the technical scheme of the invention also provides a method for forming the germanium-silicon heterojunction bipolar transistor structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a base and a collector region positioned on the base; forming a mask layer structure on the substrate, wherein the mask layer structure comprises a mask layer, a first opening is formed in the mask layer, the mask layer comprises a main body region and a surface region located on the main body region, a chemical bond of a material of the main body region has first bond energy, a doped ion is arranged in the surface region, a chemical bond formed by the doped ion and an ion of the material of the surface region has second bond energy, and the second bond energy is larger than the first bond energy; and forming a main base region on the surface of the collector region under the first opening by using the mask layer as a mask and adopting a selective epitaxy process.
Optionally, the mask layer structure further includes a dielectric layer, and two mutually-separated outer base regions located on the surface of the dielectric layer, a second opening is formed in the dielectric layer, the mask layer is located on the top surface and the side wall of the outer base region, the first opening and the second opening are mutually communicated, and the second opening exposes the collector region and a part of the outer base region; the mask layer comprises a covering layer positioned on the surface of the top of the outer base region and a side wall positioned on the side wall of the outer base region; the main base region is located on the collector region exposed by the second opening and part of the surface of the outer base region.
Optionally, the forming method of the mask layer structure includes: forming a dielectric material layer, two mutually-separated outer base regions positioned on the surface of the dielectric material layer and an initial covering layer positioned on the top surface of the outer base regions on the substrate, wherein the outer base regions and the initial covering layer are internally provided with initial first openings; forming a side wall material layer on the side wall of the initial first opening; performing surface treatment on the initial covering layer and the side wall material layer, forming the covering layer by using the initial covering layer, forming the side wall by using the side wall material layer on the side wall of the initial first opening, and taking the initial first opening between the side walls as the first opening; and after the mask layer is formed, etching the dielectric material layer by taking the mask layer as a mask to form the dielectric layer and the second opening.
Optionally, after forming the second opening and before the selective epitaxy process, the method further includes: and cleaning the surface of the collector region exposed by the second opening.
Optionally, the surface treatment process includes a first treatment process, and the first treatment process includes an ion doping process and an annealing process after the ion doping process.
Optionally, the process parameters of the ion doping process include: the dopant ions include fluorine ions, and the dosage of the dopant ions is in the range of 1E14 atom/cm 2 To 1E16 atom/cm 2 。
Optionally, the process parameters of the annealing process include an annealing temperature range of 900 ℃ to 1100 ℃ and an annealing time range of 10s to 60s.
Optionally, the surface treatment process further includes a second treatment process, and the second treatment process includes: and a thinning process after the ion doping process.
Optionally, the thinning process includes a wet etching process.
Optionally, the side wall material layer is also located on the surface of the initial covering layer; the method further comprises the following steps: and after the first treatment and before the thinning process, etching the side wall material layer back until the surface of the medium material layer is exposed.
Optionally, the side wall material layer is also located on the surface of the initial covering layer; the method further comprises the following steps: and after the surface treatment, etching the side wall material layer again until the surface of the medium material layer is exposed.
Optionally, the side wall material layer is also located on the surface of the initial covering layer; the method further comprises the following steps: and etching the side wall material layer back before the surface treatment until the surface of the medium material layer is exposed.
Optionally, the method further includes: and forming an emitter region on the surface of part of the main base region, wherein the emitter region and the outer base region are mutually separated.
Optionally, the chemical bond of the material of the body region comprises a silicon-nitrogen bond, and the chemical bond of the material of the surface region comprises a silicon-fluorine bond.
Optionally, the material of the main base region includes silicon germanium.
The technical scheme of the invention also provides a crystal growth method of the selective epitaxy process, which comprises the following steps: providing a substrate; forming a mask material layer on the substrate, wherein chemical bonds of the mask material layer have first bond energy; performing surface treatment on the mask material layer, and forming an exposed surface region in the mask material layer, wherein the surface region is provided with doped ions, and chemical bonds formed by the doped ions and the ions of the surface region material have a second bond energy which is greater than the first bond energy; after the surface treatment, etching the mask material layer to form a mask layer and an opening in the mask layer, wherein the opening exposes the surface of the substrate; and forming an epitaxial layer on the substrate exposed by the opening by using the mask layer as a mask and adopting a selective epitaxial growth process.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
according to the forming method of the germanium-silicon heterojunction bipolar transistor structure, a mask layer structure is formed on a substrate and comprises a mask layer, a first opening is formed in the mask layer, the mask layer comprises a main body region and a surface region located on the main body region, a chemical bond of a material of the main body region has first bond energy, a doped ion is arranged in the surface region, a chemical bond formed by the doped ion and an ion of a material of the surface region has second bond energy, the second bond energy is larger than the first bond energy, the mask layer is used as the mask, a selective epitaxial process is adopted, and in the process of forming a main base region on the surface of a collector region under the first opening, the second bond energy is larger than the first bond energy, the chemical bond in the surface region is difficult to break compared with the chemical bond in the mask layer, so that the growth of the material of the main base region on the surface of the mask layer is reduced, the growth selectivity of the material of the main base region is improved, and a process window is further improved.
Drawings
Fig. 1 to fig. 3 are schematic structural diagrams of steps of a method for forming a sige heterojunction bipolar transistor structure;
fig. 4 to 9 are schematic structural diagrams of steps of a method for forming a sige heterojunction bipolar transistor structure according to an embodiment of the present invention;
fig. 10 to 12 are schematic structural views of steps of a crystal growth method of a selective epitaxial process according to another embodiment of the present invention.
Detailed Description
It should be noted that "surface" and "upper" in the present specification are used to describe a relative positional relationship in space, and are not limited to direct contact or not.
As described in the background, the existing process for forming the heterojunction bipolar transistor structure is to be further improved. An explanation analysis will now be made in conjunction with a method of forming a sige heterojunction bipolar transistor structure.
Fig. 1 to fig. 3 are schematic structural diagrams of steps of a method for forming a sige heterojunction bipolar transistor structure.
Referring to fig. 1, a substrate is provided, where the substrate includes a base 100, and a collector region 101, an extraction region 102, and an isolation region 103 located on the base 100, and the isolation region 103 is located on sidewalls of the collector region 101 and the extraction region 102; forming an oxide layer 104, two outer base region structures located on the surface of the oxide layer 104, and a first opening 107 between the two outer base region structures on the substrate, where the outer base region structures include an outer base region 105 and a mask layer 106 located on the surface of the outer base region 105, and the first opening 107 exposes a part of the surface of the oxide layer 104 on the collector region 101; a sidewall 108 is formed on the sidewall of the first opening 107.
Referring to fig. 2, the first opening 107 is etched to expose the oxide layer 104 by using the sidewall 108 as a mask until the collector region 101 and a portion of the outer base region 105 are exposed, and a second opening 109 is formed in the oxide layer 104.
Referring to fig. 3, a main base region 110 is formed in the second opening 109.
The method is used for forming a germanium-silicon HBT device, the main base region 110 is made of germanium-silicon, the mask layer 106 is made of silicon nitride, and the side wall 108 is made of silicon nitride. The main base region 110 is formed using a selective epitaxial process. In the selective epitaxy process, hydrogen chloride and dichlorosilane are used as reaction gases, in order to improve the growth selectivity of a crystal on the surface of the collector region 101 and reduce the formation of unnecessary polysilicon materials on the surface of the mask layer 106, a possible method is to improve the proportion of hydrogen chloride in the reaction gases, however, improving the proportion of hydrogen chloride will increase the probability that the outer base region 105 exposed by the second opening 109 is etched, and an etch pit defect (pit) is generated in the region a (as shown in fig. 3) to affect the device performance.
In order to solve the above problems, in a germanium-silicon heterojunction bipolar transistor structure, a forming method thereof and a crystal growth method thereof provided by the present invention, a mask layer structure is formed on a substrate, the mask layer structure includes a mask layer, a first opening is formed in the mask layer, the mask layer includes a body region and a surface region located on the body region, a chemical bond of a material of the body region has a first bond energy, a doped ion is provided in the surface region, a chemical bond formed by the doped ion and an ion of a material of the surface region has a second bond energy, which is greater than the first bond energy, in a process of forming a main base region on a surface of a collector region under the first opening by using the mask layer as a mask and adopting a selective epitaxy process, because the second bond energy is greater than the first bond energy, the chemical bond in the surface region is difficult to break compared with the chemical bond in the mask layer, growth of a material of the main base region on the surface of the mask layer is reduced, growth selectivity of the material of the main base region is improved, and a process window is further improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 9 are schematic structural diagrams of steps of a method for forming a sige heterojunction bipolar transistor structure according to an embodiment of the present invention.
Referring to fig. 4, a substrate is provided, and the substrate includes a base 200 and a collector region 201 on the base 200.
In this embodiment, the substrate further includes an isolation layer 202 and a lead-out region 203 on the base 200, where the isolation layer 202 is located on sidewalls of the collector region 201 and the lead-out region 203.
In this embodiment, the substrate 200 is made of silicon. In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-element semiconductor material of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multielement semiconductor material made of III-V group elements comprises InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP.
In this embodiment, the substrate 200 has a heavily doped buried layer 204 therein. The extraction region 203 is connected with the heavily doped buried layer 204 and is used for extracting an electrical signal of the collector region 201.
In this embodiment, the conductive type of the substrate 200 is N-type; the conductivity type of the highly doped buried layer 204 is N-type.
Subsequently, a mask layer structure is formed on the substrate, the mask layer structure comprises a mask layer, a first opening is formed in the mask layer, the mask layer comprises a main body region and a surface region located on the main body region, a chemical bond of a material of the main body region has first bond energy, a doped ion is arranged in the surface region, a chemical bond formed by the doped ion and an ion of the material of the surface region has second bond energy, and the second bond energy is larger than the first bond energy.
In this embodiment, the mask layer structure further includes a dielectric layer, and two mutually-separated outer base regions located on the surface of the dielectric layer, a second opening is formed in the dielectric layer, the mask layer is located on the top surface and the side wall of the outer base region, the first opening is mutually communicated with the second opening, and the second opening exposes the collector region and a part of the outer base region; the mask layer comprises a covering layer positioned on the top surface of the outer base region and a side wall positioned on the side wall of the outer base region; the main base region is located on the collector region exposed by the second opening and part of the surface of the outer base region.
In this embodiment, please refer to fig. 5 to 7 for a method for forming a mask layer structure.
Referring to fig. 5, a dielectric material layer 205, two mutually discrete outer base regions 206 located on a surface of the dielectric material layer 205, and an initial capping layer 207 located on a top surface of the outer base regions 206 are formed on the substrate, and the outer base regions 206 and the initial capping layer 207 have initial first openings 208 therein.
The outer base region 206 is used for connecting the main base region to reduce the contact resistance when the main base region circuit is led out.
In this embodiment, the cover layer 207 includes a first dielectric layer 207a and a second dielectric layer 207b on the first dielectric layer 207 a.
In this embodiment, the cover layer 207 has a double-layer structure. In other embodiments, the cover layer 207 may be a single layer or a multi-layer structure.
In this embodiment, the first dielectric layer 207a is made of silicon oxide; the second dielectric layer 207b is made of silicon nitride.
In this embodiment, the dielectric material layer 205 is made of silicon oxide. The dielectric material layer 205 occupies space for the subsequent formation of the main base region.
In this embodiment, the forming method of the cover layer 207 and the outer base region 206 includes: forming an outer base region material layer (not shown in the figure) on the surface of the dielectric material layer 205; forming a covering material layer (not shown in the figure) on the surface of the outer base region material layer; patterning the covering material layer to form the covering layer 207; and etching the outer base region material layer by taking the covering layer 207 as a mask to form the outer base region 206.
Referring to fig. 6, a sidewall material layer 209 is formed on the sidewall of the initial first opening 208.
In this embodiment, the sidewall material layer 209 is also located on the surface of the initial covering layer.
The material of the side wall material layer 209 is a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.
In this embodiment, the material of the sidewall material layer 209 is silicon nitride.
The sidewall material layer 209 and the initial covering layer 207 are used for forming a mask layer. In this embodiment, the chemical bonds of the materials of the sidewall material layer 209 and the initial capping layer 207 both have silicon-nitrogen bonds.
Referring to fig. 7, the initial covering layer 207 and the sidewall material layers 209 are subjected to surface treatment, the covering layer 210 is formed by the initial covering layer 207, the sidewall 211 is formed by the sidewall material layers 209 on the sidewalls of the initial first openings 208, and the initial first openings 208 between the sidewalls 211 are used as the first openings 212.
The mask layer structure comprises a mask layer, wherein a first opening 212 is formed in the mask layer, the mask layer comprises a main body region (not shown in the figure) and a surface region (not shown in the figure) located on the main body region, a chemical bond of a material of the main body region has a first bond energy, a doped ion is arranged in the surface region, a chemical bond formed by the doped ion and an ion of a material of the surface region has a second bond energy, and the second bond energy is larger than the first bond energy.
Subsequently, in the process of forming the main base region on the surface of the collector region 201 under the first opening 212, since the second bond energy is greater than the first bond energy, the chemical bonds in the surface region are difficult to break compared with the chemical bonds in the mask layer, so that the growth of the main base region material on the surface of the mask layer is reduced, the growth selectivity of the main base region material is improved, and the process window is further improved.
Specifically, the chemical bond of the material of the body region comprises a silicon-nitrogen bond, and the chemical bond of the material of the surface region comprises a silicon-fluorine bond. The bond energy of the silicon-fluorine bond is larger than that of the silicon-nitrogen bond, so that the silicon-fluorine bond cannot be broken in the subsequent selective epitaxial process for forming the main base region, the growth of the main base region material on the surface of the mask layer is reduced, and the crystal growth selectivity is improved.
In this embodiment, the mask layer includes a covering layer 210 located on the top surface of the outer base region 206 and a sidewall 211 located on the sidewall of the outer base region 206.
In this embodiment, the material of the mask layer includes silicon nitride.
In this embodiment, the surface treatment process includes a first treatment process, and the first treatment process includes an ion doping process and an annealing process after the ion doping process.
In this embodiment, the process parameters of the ion doping process include: the dopant ions include fluorine ions, and the dosage of the dopant ions is in the range of 1E14 atom/cm 2 To 1E16 atom/cm 2 。
In this embodiment, the process parameters of the annealing process include an annealing temperature range of 900 ℃ to 1100 ℃ and an annealing time range of 10s to 60s.
In this embodiment, the surface treatment process further includes a second treatment process, and the second treatment process includes: and a thinning process after the ion doping process. Because the area with the highest concentration of the doped ions has a certain distance from the surface in the ion doping process, the thinning process is used for exposing the area with the highest concentration of the doped ions and simultaneously reducing the damage to the surface of the mask layer in the ion doping process. In another embodiment, the second treatment process may not be included.
In this embodiment, the thinning process includes a wet etching process.
In this embodiment, after the first treatment and before the thinning process, the sidewall material layer is etched back until the surface of the dielectric material layer is exposed. The back etching process is arranged before the thinning process, so that the thinning process can reduce the surface damage caused by the back etching process.
In another embodiment, after the surface treatment, the side wall material layer is etched back until the surface of the dielectric material layer is exposed.
In yet another embodiment, before the surface treatment, the side wall material layer is etched back until the surface of the dielectric material layer is exposed.
Referring to fig. 8, after the mask layer is formed, the dielectric material layer 205 is etched by using the mask layer as a mask to form the dielectric layer 213 and the second opening 214.
The process of etching the dielectric material layer 205 includes one or both of a dry etching process and a wet etching process.
In this embodiment, the process of etching the dielectric material layer 205 is a wet etching process.
Referring to fig. 9, a main base region 215 is formed on the surface of the collector region 201 under the first opening 212 by using the mask layer as a mask and using a selective epitaxy process.
The crystal growth selectivity in the selective epitaxial process of the main base region 215 improves the process window.
The process parameters of the selective epitaxy process comprise: the reaction gas comprises one or more of dichlorosilane, germane and methylsilane in combination, and the reaction gas further comprises hydrogen chloride.
Specifically, the main base region 215 is formed on the surface of the collector region 201 exposed by the second opening 214 and a part of the outer base region 206.
In this embodiment, the material of the main base region 215 includes silicon germanium.
In this embodiment, after the second opening 214 is formed and before the selective epitaxy process, the surface of the collector region 201 exposed by the second opening 214 is also cleaned. The cleaning process is used to remove impurity contamination from the surface of the collector region 201 to improve the quality of the formed main base region 215.
In this embodiment, subsequently, an emitter region (not shown in the figure) is further formed on a portion of the surface of the main base region, and the emitter region and the outer base region 206 are separated from each other.
Accordingly, an embodiment of the present invention further provides a sige heterojunction bipolar transistor structure formed by the above method, with reference to fig. 9, including: the device comprises a substrate, a first electrode and a second electrode, wherein the substrate comprises a base 200 and a collector region 201 positioned on the base 200; a mask layer structure located on the substrate, the mask layer structure including a mask layer, the mask layer structure having a second opening 214 therein (as shown in fig. 8), the second opening 214 exposing the top surface of the collector region 201, the mask layer including a body region (not shown) and a surface region (not shown) located on the body region, the chemical bond of the material of the body region having a first bond energy, the surface region having doped ions therein, the chemical bond formed by the doped ions and the ions of the material of the surface region having a second bond energy, the second bond energy being greater than the first bond energy; a main base region 215 located on the surface of the collector region 201 exposed by the second opening 214.
In this embodiment, the dopant ions include fluorine ions; the chemical bonds of the bulk region material comprise silicon-nitrogen bonds and the chemical bonds of the surface region material comprise silicon-fluorine bonds.
In this embodiment, the mask layer structure further includes a dielectric layer 213 and two mutually-separated outer base regions 206 located on the surface of the dielectric layer 213, the second opening 214 is located in the dielectric layer 213 and exposes the collector region 201 and part of the surface of the outer base region 206, the mask layer is located on the top surface and the side wall of the outer base region 206, a first opening 212 is formed in the mask layer (as shown in fig. 8), and the first opening 212 is communicated with the second opening 214.
Specifically, the mask layer includes a covering layer 210 located on the top surface of the outer base region 206 and a sidewall 211 located on the sidewall of the outer base region 206.
Fig. 10 to 12 are schematic structural views of steps of a crystal growth method of a selective epitaxial process according to another embodiment of the present invention.
In this embodiment, the selective epitaxy process may be used in a main base region formation process of a sige heterojunction bipolar transistor structure, and may also be used in other selective epitaxy processes. Please refer to fig. 10 to fig. 12 for a crystal growth method of the selective epitaxial process.
Referring to fig. 10, a substrate 300 is provided; a masking material layer 301 is formed on the substrate 300, and chemical bonds of the material of the masking material layer 301 have a first bond energy.
In this embodiment, the material of the mask material layer 301 is silicon nitride.
Referring to fig. 11, the mask material layer is subjected to a surface treatment, an exposed surface region 302 is formed in the mask material layer, the surface region 302 has doped ions therein, and chemical bonds formed by the doped ions and the ions of the surface region material have a second bond energy, and the second bond energy is greater than the first bond energy.
In this embodiment, the surface treatment process includes a first treatment process, and the first treatment process includes an ion doping process and an annealing process after the ion doping process.
In this embodiment, the process parameters of the ion doping process include: the dopant ions include fluorine ions, and the dosage of the dopant ions is in the range of 1E14 atom/cm 2 To 1E16 atom/cm 2 。
In this embodiment, the process parameters of the annealing process include an annealing temperature range of 900 ℃ to 1100 ℃ and an annealing time range of 10s to 60s.
In this embodiment, the surface treatment process further includes a second treatment process, and the second treatment process includes: and a thinning process after the ion doping process.
In this embodiment, the thinning process includes a wet etching process.
Referring to fig. 12, after the surface treatment, the mask material layer is etched to form a mask layer 304 and an opening (not shown) in the mask layer 304, where the opening exposes the surface of the substrate 300; an epitaxial layer 305 is formed on the substrate 300 exposed by the opening by using the mask layer 304 as a mask and using a selective epitaxial growth process.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (19)
1. A SiGe heterojunction bipolar transistor structure comprising:
the device comprises a substrate, a first electrode and a second electrode, wherein the substrate comprises a base and a collector region positioned on the base;
the mask layer structure comprises a mask layer, a second opening is formed in the mask layer structure, the second opening is exposed out of the top surface of the collector region, the mask layer comprises a main body region and a surface region located on the main body region, a chemical bond of a material of the main body region has first bond energy, a doped ion is arranged in the surface region, a chemical bond formed by the doped ion and an ion of a material of the surface region has second bond energy, and the second bond energy is larger than the first bond energy;
and the main base region is positioned on the surface of the collector region exposed by the second opening.
2. The sige heterojunction bipolar transistor structure of claim 1, wherein said dopant ions comprise fluorine ions; the chemical bonds of the bulk region material comprise silicon-nitrogen bonds and the chemical bonds of the surface region material comprise silicon-fluorine bonds.
3. The SiGe heterojunction bipolar transistor structure of claim 1, wherein the mask layer structure further comprises a dielectric layer, two mutually discrete outer base regions located on the surface of the dielectric layer, the second opening is located in the dielectric layer and exposes the collector region and a part of the surface of the outer base region, the mask layer is located on the top surface and the side wall of the outer base region, the mask layer has a first opening therein, the first opening is communicated with the second opening, and the second opening exposes the collector region and a part of the outer base region; the mask layer comprises a covering layer located on the top surface of the outer base region and a side wall located on the side wall of the outer base region.
4. A method for forming a SiGe heterojunction bipolar transistor structure comprises the following steps:
providing a substrate, wherein the substrate comprises a base and a collector region positioned on the base;
forming a mask layer structure on the substrate, wherein the mask layer structure comprises a mask layer, a first opening is formed in the mask layer, the mask layer comprises a main body region and a surface region located on the main body region, a chemical bond of a material of the main body region has a first bond energy, a doped ion is arranged in the surface region, a chemical bond formed by the doped ion and an ion of the material of the surface region has a second bond energy, and the second bond energy is greater than the first bond energy;
and forming a main base region on the surface of the collector region under the first opening by using the mask layer as a mask and adopting a selective epitaxy process.
5. The method for forming the germanium-silicon heterojunction bipolar transistor structure according to claim 4, wherein the mask layer structure further comprises a dielectric layer and two mutually-separated outer base regions positioned on the surface of the dielectric layer, a second opening is formed in the dielectric layer, the mask layer is positioned on the top surface and the side wall of each outer base region, the first opening is communicated with the second opening, and the collector region and part of the outer base region are exposed through the second opening; the mask layer comprises a covering layer positioned on the top surface of the outer base region and a side wall positioned on the side wall of the outer base region; the main base region is positioned on the collector region exposed by the second opening and part of the surface of the outer base region.
6. The method for forming a silicon germanium heterojunction bipolar transistor structure as claimed in claim 5, wherein said method for forming a mask layer structure comprises: forming a dielectric material layer, two mutually-separated outer base regions positioned on the surface of the dielectric material layer and an initial covering layer positioned on the top surface of the outer base regions on the substrate, wherein the outer base regions and the initial covering layer are internally provided with initial first openings; forming a side wall material layer on the side wall of the initial first opening; performing surface treatment on the initial covering layer and the side wall material layer, forming the covering layer by using the initial covering layer, forming the side wall by using the side wall material layer on the side wall of the initial first opening, and taking the initial first opening between the side walls as the first opening; and after the mask layer is formed, etching the dielectric material layer by taking the mask layer as a mask to form the dielectric layer and the second opening.
7. The method for forming a sige heterojunction bipolar transistor structure according to claim 6, wherein after forming the second opening and before the selective epitaxial process, further comprising: and cleaning the surface of the collector region exposed by the second opening.
8. The method as claimed in claim 6, wherein the surface treatment process comprises a first treatment process, and the first treatment process comprises an ion doping process and an annealing process after the ion doping process.
9. The method for forming the sige heterojunction bipolar transistor structure of claim 8, wherein the process parameters of the ion doping process comprise: the dopant ions include fluorine ions, and the dosage of the dopant ions is in the range of 1E14 atom/cm 2 To 1E16 atom/cm 2 。
10. The method for forming the SiGe heterojunction bipolar transistor structure as claimed in claim 8, wherein the process parameters of the annealing process include an annealing temperature ranging from 900 ℃ to 1100 ℃ and an annealing time ranging from 10s to 60s.
11. The method for forming a sige heterojunction bipolar transistor structure according to claim 8, wherein said surface treatment process further comprises a second treatment process, said second treatment process comprising: and a thinning process after the ion doping process.
12. The method of claim 11, wherein the thinning process comprises a wet etching process.
13. The method for forming the sige heterojunction bipolar transistor structure of claim 11, wherein the spacer material layer is further located on the surface of the initial capping layer; the method further comprises the following steps: and after the first treatment and before the thinning process, etching the side wall material layer back until the surface of the medium material layer is exposed.
14. The method for forming the sige heterojunction bipolar transistor structure of claim 8, wherein the spacer material layer is further located on the surface of the initial capping layer; the method further comprises the following steps: and after the surface treatment, etching the side wall material layer again until the surface of the medium material layer is exposed.
15. The method for forming the sige heterojunction bipolar transistor structure of claim 8, wherein the spacer material layer is further located on the surface of the initial capping layer; the method further comprises the following steps: and etching the side wall material layer back until the surface of the dielectric material layer is exposed before the surface treatment.
16. The method of forming a sige heterojunction bipolar transistor structure of claim 5, further comprising: and forming an emitter region on the surface of part of the main base region, wherein the emitter region and the outer base region are mutually separated.
17. The method as claimed in claim 4, wherein the chemical bond of the material of the body region comprises a silicon-nitrogen bond, and the chemical bond of the material of the surface region comprises a silicon-fluorine bond.
18. The method for forming the SiGe heterojunction bipolar transistor structure as claimed in claim 4, wherein the material of the main base region comprises SiGe.
19. A crystal growth method of a selective epitaxial process, comprising:
providing a substrate;
forming a mask material layer on the substrate, wherein chemical bonds of the mask material layer have first bond energy;
performing surface treatment on the mask material layer, and forming an exposed surface region in the mask material layer, wherein the surface region is provided with doped ions, and chemical bonds formed by the doped ions and the ions of the surface region material have a second bond energy which is greater than the first bond energy;
after the surface treatment, etching the mask material layer to form a mask layer and an opening in the mask layer, wherein the opening exposes the surface of the substrate;
and forming an epitaxial layer on the substrate exposed by the opening by using the mask layer as a mask and adopting a selective epitaxial growth process.
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