CN115700429A - Terminal equipment and management method - Google Patents

Abstract

This application proposes a terminal device and a management method. The external unit is used to read the target codes in at least 3 memories, and if the target codes in at least 2 memories are the same, determine the first target memory; wherein, the target The code is operating system code and/or application software code, and the first target memory is any one of the memory with the same target code; the external unit is also used to send the identification of the first target memory to the processor; the processor is used to read the target code in the first target memory, and load the read target code into the first type address segment of the memory to run the target code. The target code is backed up and stored through multiple memories. When it needs to be called, the memory with the least possibility of flipping particles is selected as the target memory through comparison, so as to ensure the normal operation of the target code and the reliability of the terminal equipment.

Description

A terminal device and management method

technical field

The present application relates to the technical field of communications, and in particular, to a terminal device and a management method.

Background technique

With the development of society, people have more and more communication needs, and then need to deploy a large number of communication base stations, and the differences in the natural environment where the base stations are deployed are also increasing. In particular, as the field of wireless communication gradually extends from the ground to control, satellite communication technology begins to develop and popularize, and the number of satellite base stations deployed in high-altitude areas is also increasing.

It should be understood that the base station on the ground does not need to separately consider the influence caused by the data inversion caused by radiation noise. However, terminal equipment (such as satellite base stations and core networks) deployed in high-altitude areas will face the impact of radiation noise during operation, resulting in the possibility of flipping the stored data, affecting the normal operation of satellite base stations and core networks.

Therefore, how to overcome the influence of high radiation noise on the terminal equipment and ensure the normal operation of the terminal equipment has become a difficult problem concerned by those skilled in the art.

Contents of the invention

The purpose of the present application is to provide a terminal device and a management method, so as to at least partially improve the above problems.

In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

In the first aspect, an embodiment of the present application provides a terminal device. The terminal device includes: an external unit, a processor, a memory, and at least three memories, and the external unit is connected to the processor, the at least three a memory is connected in communication, the processor is connected in communication with the at least 3 memories, and the processor is also connected in communication with the memory;

The external unit is used to read the target codes in the at least 3 memories, and determine the first target memory when the target codes in the at least 2 memories are the same;

Wherein, the target code is operating system code and/or application software code, and the first target memory is any one of the same memory as the target code;

The external unit is further configured to send the identifier of the first target memory to the processor;

The processor is used for reading the target code in the first target memory, and loading the read target code into the first type address segment of the memory, so as to run the target code.

The target code is backed up and stored through multiple memories. When it needs to be called, the memory with the least possibility of flipping particles is selected by comparison as the target memory, so as to ensure the normal operation of the target code and the reliability of the terminal equipment.

In an optional implementation manner, after the external unit is powered on, the external unit is used to power on the at least three memories; after the first target memory is determined, the The external unit is also used to power off the non-first target memory except the first target memory. Thereby, the purpose of saving electric energy and reducing energy consumption can be achieved.

In an optional implementation manner, before sending the identifier of the first target memory to the processor, the external unit is further configured to power on the processor and the memory. Thereby, the purpose of saving electric energy and reducing energy consumption can be achieved.

In an optional implementation manner, after the target code runs, the external unit is further configured to read the target code in the at least three memories when the trigger instruction is acquired, and the at least three In the case where the target codes in the three memories are the same, any one of the at least three memories is determined as the second target memory;

The external unit is also used to adjust the object codes in the at least 3 memories when the object codes stored in any one memory are different from the object codes stored in other memories, so that the at least 3 memories The target code in is consistent, and any one of the adjusted at least 3 memories is determined as the second target memory;

The external unit is further configured to send the identifier of the second target memory to the processor;

The processor is used for reading the target code in the second target memory, and updating the memory based on the target code in the second target memory.

Based on the dynamic update, after the target code (operating system code and application software code) is running normally on the terminal device, the target code in the memory 12 and the memory 14 may be reversed and changed under the influence of radiation noise, which may affect the terminal device. , to improve the reliability of terminal equipment.

In an optional implementation manner, the processor is further configured to load the target code in the second target memory into the first type address segment of the memory.

It should be understood that by loading the object code in the second object memory into the first type address segment of the memory, the object code in the second object memory can directly overwrite the object code in the memory, so as to avoid initial loading in the memory The target code of the device is reversed to ensure the correctness of the target code and improve the reliability of the terminal equipment.

In an optional implementation manner, the processor is further configured to respectively place the target code in the second target memory in a second-type address segment and a third-type address segment of the memory;

The processor is also used to compare the target codes in the first type address segment, the second type address segment and the third type address segment of the memory, if the target code in the first type address segment is the same as the second type address segment If the object code in the address segment of the first type is different from the object code in the address segment of the third type, the object code in the address segment of the first type is corrected.

If the object code in the first type address segment is identical to any one of the object code in the second type address segment and the object code in the third type address segment, then the object in the second type address segment of the memory is code and object code in the third-class address segment are deleted.

In the same way, the target code initially loaded in the memory is prevented from being overturned, the correctness of the target code is guaranteed, and the reliability of the terminal device is improved.

In an optional implementation manner, the trigger instruction is an instruction sent by the processor at preset time intervals, or the trigger instruction is an instruction generated by the external unit at preset time intervals.

In an optional implementation manner, the trigger instruction is an instruction generated when the processor monitors that an error is reported by an application program or an error is reported by an operating system.

In the second aspect, an embodiment of the present application provides a terminal device management method, which is applied to a terminal device, and the terminal device includes: an external unit, a processor, a memory, and at least three memories, and the external unit is connected to the The processor and the at least three memories are connected in communication, the processor is connected in communication with the at least three memories, the processor is also connected in communication with the memory, and the terminal device management method includes:

The external unit reads the target codes in the at least 3 memories, and determines the first target memory when the target codes in the at least 2 memories are the same;

Wherein, the target code is operating system code and/or application software code, and the first target memory is any one of the same memory as the target code;

The external unit sends the identifier of the first target memory to the processor;

The processor reads the target code in the first target memory, and loads the read target code into the first-type address segment of the memory, so as to run the target code.

In order to make the above objects, features and advantages of the present application more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the accompanying drawings used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, so It should be regarded as a limitation on the scope, and those skilled in the art can also obtain other related drawings based on these drawings without creative work.

FIG. 1 is a schematic diagram of the operating environment of the spaceborne system provided by the embodiment of the present application;

FIG. 2 is a schematic structural diagram of a terminal device provided in an embodiment of the present application;

FIG. 3 is a schematic flowchart of a terminal device management method provided by an embodiment of the present application.

In the figure: 11-external unit; 12-memory; 13-processor; 14-memory.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the present application Examples, not all examples. The components of the embodiments of the application generally described and illustrated in the figures herein may be arranged and designed in a variety of different configurations.

Accordingly, the following detailed description of the embodiments of the application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the application. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of this application.

It should be noted that like numerals and letters denote similar items in the following figures, therefore, once an item is defined in one figure, it does not require further definition and explanation in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second" and the like are only used to distinguish descriptions, and cannot be understood as indicating or implying relative importance.

It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is a relationship between these entities or operations. There is no such actual relationship or order between them. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.

In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "inner", "outer" etc. is based on the orientation or positional relationship shown in the drawings, or the The usual orientation or positional relationship of the application product when used is only for the convenience of describing the application and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, therefore It should not be construed as a limitation of the application.

In the description of this application, it should also be noted that, unless otherwise clearly stipulated and limited, the terms "setting" and "connection" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection, or Integral connection; it can be mechanical connection or electrical connection; it can be direct connection or indirect connection through an intermediary, and it can be the internal communication of two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in this application in specific situations.

Some implementations of the present application will be described in detail below in conjunction with the accompanying drawings. In the case of no conflict, the following embodiments and features in the embodiments can be combined with each other.

In order to meet communication requirements, more and more base stations are deployed in high-altitude areas or areas near nuclear power plants. High-altitude areas or areas near nuclear power plants are areas with high radiation noise. Terminal equipment such as base stations deployed in them will face the impact of radiation noise during operation, resulting in the possibility of flipping the stored data, affecting the normal operation of satellite base stations and core networks. operation, affecting its reliability.

Please refer to FIG. 1 . FIG. 1 is a schematic diagram of an operating environment of a spaceborne system provided by an embodiment of the present application. Taking terminal equipment deployed in high-altitude areas as an example of a spaceborne system, the spaceborne system is mainly used in scenarios such as satellite communication, broadcasting, and navigation. Take the 5G satellite communication scenario as an example. The spaceborne system supports the core network function (UPF) of the HE part of the 5G base station, supports direct connection of ground satellite terminals and gateway stations to satellites, meets the mobile communication needs of areas where ground communication systems cannot cover such as seas, mountainous areas, and suburbs, and realizes full coverage of space-ground integration , can be applied to business demands such as emergency safety, surveying and mapping, maritime affairs, and daily communication.

It should be understood that the spaceborne system can support 5G communication, but compared with the terrestrial 5G communication system, the spaceborne system also needs to consider the impact of radiation noise on system stability and reliability. Space radiation noise can easily cause problems such as single event flipping and latch-up, affecting the reliability and stability of devices and systems.

In order to overcome the above problems, an embodiment of the present application provides a terminal device. The terminal device can be the spaceborne system shown in Figure 1, a satellite base station, or a base station device for deployment in a ground environment with high radiation noise. The refresh mechanism of the processor 13 (for example, CPU) and the stored memory 14 is used to improve system reliability in radiation noise scenarios.

Specifically, please refer to FIG. 2 , which is a schematic structural diagram of a terminal device provided in an embodiment of the present application. The terminal device includes: an external unit 11, a processor 13, a memory 14, and at least three memories 12, the external unit 11 is connected to the processor 13 and at least three memories 12 in communication, and the processor 13 communicates with at least three memories 12 The processor 13 is also connected to the memory 14 in communication.

In an optional implementation manner, the processor 13 may be an integrated circuit chip having a signal processing capability. Specifically, the processor 13 may be a general-purpose processor, including a central processing unit (Central Processing Unit, referred to as CPU), a network processor (Network Processor, referred to as NP), etc.; it may also be a digital signal processor (Digital Signal Processor, referred to as DSP), application specific integrated circuit (Application Specific Integrated Circuit, referred to as ASIC), field programmable gate array (Field-Programmable Gate Array, referred to as FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

The external unit 11 is also referred to as an external control unit, which may, but is not limited to, use a Field-Programmable Gate Array (Field-Programmable Gate Array, FPGA for short).

The memory 12 may include a high-speed random access memory (RAM: Random Access Memory), and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

The memory 14 can be, but not limited to, double data rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR SDRAM for short).

The memory is used to store program codes, such as object codes hereinafter, where the object codes are operating system codes and/or application software codes. Optionally, the target code includes at least one software function module that can be stored in a memory in the form of software or firmware (firmware) or solidified in an operating system (operating system, OS) of the terminal device. After receiving the execution instruction, the processor 13 may invoke and execute the target code.

Optionally, various components in the terminal device may be connected through a bus for communication, and the bus may be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus. It should be noted that only one bidirectional arrow is used in FIG. 2 , but it does not mean that there is only one bus or one type of bus.

On the basis of Figure 2, in order to overcome the problems of single event flipping and latching easily caused by space radiation noise, the embodiment of this application provides an optional implementation mode, please refer to the following.

The external unit 11 is used to read the target codes in at least three memories 12, and determine the first target memory when the target codes in at least two memories 12 are the same.

Wherein, the target code is operating system code and/or application software code, and the first target memory is any one of the memories 12 with the same target code.

Please continue to refer to FIG. 2 , the external unit 11 respectively reads the object codes stored in the specified address range in the memory 12A, the memory 12B, the memory 12C and the memory 12D. The designated address ranges of the memory 12A, the memory 12B, the memory 12C, and the memory 12D may be the same or different, and are not limited here. Assuming that the target codes in the memory 12A, the memory 12B, the memory 12C and the memory 12D are all the same, any one of the memory 12A, the memory 12B, the memory 12C and the memory 12D is determined as the first target memory. If the object codes in memory 12A, memory 12C, and memory 12D are all the same, and the object code in memory 12B is different from other object codes, then one of memory 12A, memory 12C, and memory 12D can be determined as the first object memory.

It should be understood that in a radiation noise environment, the possibility of a certain data flipping of multiple memories at the same time is lower, and by determining any one of the memories 12 with the same target code as the first target memory, the target code acquired subsequently can be guaranteed. accuracy.

In an optional real-time manner, if the object codes in the slave memory 12A, memory 12B, memory 12C, and memory 12D are not exactly the same, then a 3-modulus comparison and correction can be performed to correct the slave memory 12A, memory 12B, The object codes in the memory 12C and the memory 12D are adjusted, for example, the object codes in the memory 12B in the above example are adjusted to keep them consistent.

The external unit 11 is also configured to send the identifier of the first target memory to the processor 13 .

Optionally, the identifier of the first target storage may be a label or an ID.

The processor 13 is configured to read the target code in the first target memory, and load the read target code into the first type address segment of the memory 14 to run the target code.

Optionally, the processor 13 reads the operating system code of the first target memory, and the operating system code is placed in the first type address segment of the memory 14 to run. After the operating system runs, the processor 13 starts the software startup program, and the processor 13 imports the application software codes in the first target memory into the memory 14 for execution.

To sum up, the embodiment of the present application provides a terminal device, including: an external unit, a processor, a memory, and at least 3 memories, the external unit is connected to the processor and at least 3 memories in communication, and the processor and At least 3 memories are communicatively connected, and the processor is also connected to the memory; the external unit is used to read the target codes in at least 3 memories, and determine the first target memory when the target codes in at least 2 memories are the same ; Wherein, the target code is the operating system code and/or the application software code, and the first target memory is any one of the same memory of the target code; the external unit is also used to send the identification of the first target memory to the processor; processing The device is used to read the target code in the first target memory, and load the read target code into the first type address segment of the memory, so as to run the target code. The target code is backed up and stored through multiple memories. When it needs to be called, the memory with the least possibility of flipping particles is selected by comparison as the target memory, so as to ensure the normal operation of the target code and the reliability of the terminal equipment.

It should be understood that for terminal equipment such as on-board systems, power is very valuable. Therefore, when there is no need to work, the components are often powered off. In this case, when the terminal device needs to work, the external unit 11 is powered on first.

Optionally, after the external unit 11 is powered on, the external unit 11 is used to power on at least three memories 12 .

That is, before the external unit 11 is powered on, the memory 12 is in a power-off state to reduce power consumption.

Optionally, after the memory 12 is powered on, the external unit 11 can read the object code therein.

After the first target memory is determined, the external unit 11 is further configured to power off non-first target memories other than the first target memory.

Optionally, in order to save electric energy and reduce consumption, after the first target memory is determined, only the first target memory can be guaranteed to be in the power-on state, and the other memories are in the power-off state.

Optionally, before sending the identifier of the first target memory to the processor 13, the external unit 11 is also configured to power on the processor 13 and the memory 14.

Optionally, before the external unit 11 is powered on, the processor 13 and the memory 14 are in a power-off state to reduce energy consumption. After determining the first target memory, the external unit 11 powers on the processor 13 and the memory 14 , and sends the identifier of the first target memory to the external unit 11 .

In a possible scenario, when the terminal device runs the target code (operating system code and application software code) normally, the target code in the memory 12 and the internal memory 14 may still undergo a flip change under the influence of radiation noise, affecting the terminal device reliability. In order to deal with this problem, the embodiment of the present application also provides a possible implementation manner, please refer to the following.

In an optional implementation, after the target code runs, the external unit 11 is also used to read the target codes in at least three memories 12, and the target codes in at least three memories 12 when the trigger instruction is obtained. If the codes are the same, any one of at least three memories 12 is determined as the second target memory.

Optionally, when the external unit 11 obtains the trigger instruction, it determines whether any memory 12 is in a power-off state, and if so, it needs to be powered on, and then reads the target code therein.

The external unit 11 is also used to adjust the object codes in at least three memories 12 when the object codes stored in any one memory 12 are different from the object codes stored in other memories 12, so that at least three memories 12 The target codes are consistent, and any one of the adjusted at least three memories 12 is determined as the second target memory.

Optionally, the specific implementation manner of the adjustment may be, but not limited to: adjust the target codes in at least three memories 12 in a 3-mode contrast correction manner.

Optionally, the memory uses a fixed address to store the same operating system and application software, and the external unit compares the contents of the same address segment of the memory one by one. The different parts of the feedback comparison results will be covered based on the principle of 2>1. And the external unit 11 records the error here to form an alarm and feeds it back to the ground operation center.

Optionally, after the second target memory is determined, other non-second target memories may be powered off in order to reduce energy consumption.

The external unit 11 is also configured to send the identifier of the second target memory to the processor 13 .

The processor 13 is configured to read the target code in the second target memory, and update the memory 14 based on the target code in the second target memory.

Based on the dynamic update, after the target code (operating system code and application software code) is running normally on the terminal device, the target code in the memory 12 and the memory 14 may be reversed and changed under the influence of radiation noise, which may affect the terminal device. , to improve the reliability of terminal equipment.

Regarding how the processor 13 updates the memory 14 based on the target code in the second target memory, the embodiment of the present application also provides a possible implementation manner, please refer to the following.

In an optional implementation manner, the processor 13 is further configured to load the target code in the second target memory into the first-type address segment of the memory 14 .

It should be understood that the original code in memory is directly overwritten. This behavior causes a small amount of system disruption.

It should be understood that by loading the object code in the second object memory into the first type address segment of the memory 14, the object code in the second object memory can be directly overwritten on the object code in the memory 14, so as to avoid memory 14 The target code initially loaded in the system is reversed to ensure the correctness of the target code and improve the reliability of the terminal device.

In an optional implementation manner, the processor 13 is further configured to place the target code in the second target memory in the second type address segment and the third type address segment of the memory 14 respectively.

It should be noted that during the process of placing the target codes in the second target memory in the memory 14, the phenomenon of particle flipping may also occur. In order to avoid the flipping that occurs during the placement process and cause misjudgment, it is necessary to repeatedly place Twice, respectively placed in the second type of address segment and the third type of address segment.

Processor 13 is also used for comparing the target code in the first type address segment, the second type address segment and the third type address segment of memory 14, if the target code in the first type address segment is the same as the second type address segment If the object code in the segment is different from the object code in the third-type address segment, correct the object code in the first-type address segment.

Optionally, the operating system/application software is required to implement corresponding policies. For example: when the CPU is relatively idle, it needs to compare the codes in the three memory blocks one by one according to the 3-mode comparison principle. If the comparison results are the same, directly delete the newly imported memory blocks; if the results are not the same, perform different operations. For the same part of statistics, memory address mapping is required for programs that are being called or have a high number of calls, and temporarily map the content of this segment to the address of a memory segment in the other two blocks. Perform write overwrite operations on different parts to ensure data consistency. After the data is written, an interrupt is performed to notify the CPU, and then the address of the temporarily mapped memory segment is changed back. For the code segment with a low number of calls, the overwrite operation is directly performed to ensure data consistency. Finally, delete the newly added memory data at both ends after the data in the three memory segments are consistent.

Optionally, based on the target codes in the first type of address segment, the second type of address segment and the third type of address segment, the target code in the first type of address segment is adjusted in a 3-mode comparison correction manner.

If the object code in the first type address segment is identical to any one of the object code in the second type address segment and the object code in the third type address segment, then the object code in the second type address segment of memory 14 and the object code in the third type address segment are deleted.

Optionally, in order to save memory space, the object code in the second-type address segment and the object code in the third-type address segment can also be deleted after the correction is completed.

In an optional implementation manner, the triggering instruction is an instruction sent by the processor 13 at a preset time interval, or the triggering instruction is an instruction generated by the external unit 11 at a preset time interval.

In an optional implementation manner, the triggering instruction is an instruction generated when the processor 13 monitors that an error is reported by an application program or an error is reported by an operating system.

The embodiment of the present application also provides a terminal device management method, which may include but not limited to be applied to the terminal device shown in FIG. 2. For the specific process, please refer to FIG. 3. The implementation steps of the terminal device management method may include: S111, S112 and S131 are described in detail below:

S111. The external unit reads target codes in at least three memories, and determines a first target memory when the target codes in at least two memories are the same.

Wherein, the target code is operating system code and/or application software code, and the first target memory is any one of the same memory as the target code.

S112. The external unit sends the identifier of the first target memory to the processor.

S131. The processor reads the target code in the first target memory, and loads the read target code into the first type address segment of the memory, so as to run the target code.

It should be noted that the terminal device management method provided in this embodiment can perform the functions shown in the above terminal device embodiments to achieve corresponding technical effects. For brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding content in the foregoing embodiments.

In the embodiments provided in this application, it should be understood that the disclosed devices and methods may also be implemented in other ways. The device embodiments described above are only illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the architecture, functions and possible implementations of devices, methods and computer program products according to multiple embodiments of the present application. operate. In this regard, each block in a flowchart or block diagram may represent a module, program segment, or part of code that includes one or more Executable instructions. It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks in succession may, in fact, be executed substantially concurrently, or they may sometimes be executed in the reverse order, depending upon the functionality involved. It should also be noted that each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by a dedicated hardware-based system that performs the specified function or action , or may be implemented by a combination of dedicated hardware and computer instructions.

In addition, each functional module in each embodiment of the present application may be integrated to form an independent part, each module may exist independently, or two or more modules may be integrated to form an independent part.

If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in the various embodiments of the present application. And aforementioned storage medium comprises: U disk, mobile hard disk, read-only memory 12 (ROM, Read-Only Memory), random access memory 12 (RAM, Random Access Memory), magnetic disk or optical disk etc. can store program codes medium.

The above descriptions are only preferred embodiments of the present application, and are not intended to limit the present application. For those skilled in the art, there may be various modifications and changes in the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this application shall be included within the protection scope of this application.

It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above, but that the present application can be implemented in other specific forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be regarded as exemplary and not restrictive in all points of view, and the scope of the application is defined by the appended claims rather than the foregoing description, and it is intended that the scope of the present application be defined by the appended claims rather than by the foregoing description. All changes within the meaning and range of equivalents of the elements are embraced in this application. Any reference sign in a claim should not be construed as limiting the claim concerned.

Claims (10)

1. A terminal device, characterized in that the terminal device comprises: an external unit, a processor, a memory, and at least 3 storage devices, and the external unit communicates with the processor and the at least 3 storage devices respectively connected, the processor is connected in communication with the at least 3 memories, and the processor is also connected in communication with the memory; The external unit is used to read the target codes in the at least 3 memories, and determine the first target memory when the target codes in the at least 2 memories are the same; Wherein, the target code is operating system code and/or application software code, and the first target memory is any one of the same memory as the target code; The external unit is further configured to send the identifier of the first target memory to the processor; The processor is used for reading the target code in the first target memory, and loading the read target code into the first type address segment of the memory, so as to run the target code. 2. The terminal device according to claim 1, characterized in that, after the external unit is powered on, the external unit is used to power on the at least three memories; After determining the first target memory, the external unit is further configured to power off non-first target memories other than the first target memory. 3. The terminal device according to claim 1, wherein before sending the identifier of the first target memory to the processor, the external unit is also used to configure the processor and the The memory is powered on. 4. The terminal device according to claim 1, characterized in that, after the target code runs, the external unit is further configured to read the target code in the at least three memories when the trigger command is acquired code, when the target codes in the at least 3 memories are the same, any one of the at least 3 memories is determined as the second target memory; The external unit is also used to adjust the object codes in the at least 3 memories when the object codes stored in any one memory are different from the object codes stored in other memories, so that the at least 3 memories The target code in is consistent, and any one of the adjusted at least 3 memories is determined as the second target memory; The external unit is further configured to send the identifier of the second target memory to the processor; The processor is used for reading the target code in the second target memory, and updating the memory based on the target code in the second target memory. 5. The terminal device according to claim 4, wherein the processor is further configured to load the target code in the second target memory into the first type address segment of the memory. 6. The terminal device according to claim 4, wherein the processor is further configured to place the target code in the second target memory in the second-type address segment and the third-type address segment of the memory, respectively. address segment; The processor is also used to compare the target codes in the first type address segment, the second type address segment and the third type address segment of the memory, if the target code in the first type address segment is the same as the second type address segment If the object code in the address segment of the first type is different from the object code in the address segment of the third type, the object code in the address segment of the first type is corrected. 7. The terminal device as claimed in claim 6, wherein if the object code in the first type address segment and any one of the object code in the second type address segment and the object code in the third type address segment If they are the same, the object codes in the second-type address segment and the object code in the third-type address segment of the memory are deleted. 8. The terminal device according to claim 4, wherein the trigger instruction is an instruction sent by the processor according to a preset time interval, or the trigger instruction is an instruction sent by the external unit according to a preset time interval. Instructions generated at intervals. 9 . The terminal device according to claim 4 , wherein the trigger instruction is an instruction generated when the processor monitors that an error is reported by an application program or an error is reported by an operating system. 10. A terminal device management method, characterized in that it is applied to a terminal device, and the terminal device includes: an external unit, a processor, a memory, and at least three memories, and the external unit is connected to the processor, the The at least three memories are connected in communication, the processor is connected in communication with the at least three memories, the processor is also connected in communication with the memory, and the terminal device management method includes: The external unit reads the target codes in the at least 3 memories, and determines the first target memory when the target codes in the at least 2 memories are the same; Wherein, the target code is operating system code and/or application software code, and the first target memory is any one of the same memory as the target code; The external unit sends the identifier of the first target memory to the processor; The processor reads the target code in the first target memory, and loads the read target code into the first-type address segment of the memory, so as to run the target code.

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