CN115714127A - Semiconductor structure and forming method thereof - Google Patents

Abstract

A semiconductor structure and a method of forming the same, the method comprising: providing a substrate, wherein a grid structure is formed on the substrate, active drain doping layers are formed in the substrate on two sides of the grid structure, side walls are formed on the side walls of the grid structure, an etching stop layer is formed on the side walls of the side walls, a first interlayer dielectric layer is formed on the substrate exposed out of the grid structure, and the first interlayer dielectric layer covers the side walls of the etching stop layer; forming a first protective layer on the top of the gate structure, the side wall and the etching stop layer; after the first protective layer is formed, forming a second interlayer dielectric layer covering the first interlayer dielectric layer and the top of the first protective layer; after the second interlayer dielectric layer is formed, forming a first opening penetrating through the second interlayer dielectric layer and the first interlayer dielectric layer on the top of the source drain doping layer; and forming a source drain plug in the first opening. The method is favorable for ensuring the covering capability of the etching stop layer on the side wall, so that the risk of damage to the side wall due to exposure is reduced, and the performance of the semiconductor structure is improved.

Description

Semiconductor structures and methods of forming them

technical field

Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background technique

With the continuous development of integrated circuit manufacturing technology, people's requirements for the integration and performance of integrated circuits are becoming higher and higher. In order to improve integration and reduce costs, the critical dimensions of components are getting smaller and the circuit density inside integrated circuits is increasing. This development makes the surface of the wafer unable to provide enough area to make the required interconnection lines.

In order to meet the requirements of the interconnection line after the critical dimension is reduced, at present, the conduction between different metal layers or between the metal layer and the substrate is realized through the interconnection structure. The interconnection structure includes interconnection lines and contact hole plugs formed in the contact openings. The contact hole plugs are connected to the semiconductor devices, and the interconnection wires realize the connection between the contact hole plugs, thereby constituting a circuit. The contact hole plugs in the transistor structure include gate contact hole plugs located on the surface of the gate structure for realizing the connection between the gate structure and external circuits, and also include source-drain contact hole plugs located on the surface of the source-drain doped layer , used to realize the connection between the source-drain doped layer and the external circuit.

Contents of the invention

The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is beneficial to further improving the performance of the semiconductor structure.

In order to solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate; a gate structure located on the substrate, the gate structure includes a gate dielectric layer, and a gate electrode layer covering the gate dielectric layer ; The source-drain doped layer is located in the substrate on both sides of the gate structure; the sidewall covers the sidewall of the gate structure; the etch stop layer is located on the sidewall of the sidewall; the protection layer is located on the sidewall of the gate structure The top of the gate structure, sidewalls and etching stop layer; an interlayer dielectric layer, located on the substrate at the side of the gate structure and covering the source-drain doped layer, and the interlayer dielectric layer also covers the The top of the protection layer; the source-drain plug, which penetrates the interlayer dielectric layer at the top of the source-drain doped layer, and the bottom of the source-drain plug is electrically connected to the top of the source-drain doped layer; the gate plug A plug penetrates through the interlayer dielectric layer and the protection layer on the top of the gate structure, and the bottom of the gate plug is electrically connected to the top of the gate structure.

Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate on which a gate structure is formed, and doped source and drain layers are formed in the substrate on both sides of the gate structure, A side wall of the gate structure is formed with a side wall, an etching stop layer is formed on the side wall of the side wall, a first interlayer dielectric layer is formed on the substrate exposed by the gate structure, and the first interlayer dielectric layer is formed on the side wall of the side wall. An interlayer dielectric layer covers the sidewall of the etch stop layer; a first protective layer is formed on the top of the gate structure, sidewalls and etch stop layer; after forming the first protective layer, forming a covering The first interlayer dielectric layer and the second interlayer dielectric layer on top of the first protective layer; after forming the second interlayer dielectric layer, forming a second interlayer dielectric layer on the top of the source-drain doped layer The first opening of the inter-dielectric layer and the first inter-layer dielectric layer; forming a source-drain plug in the first opening.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following advantages:

An embodiment of the present invention provides a method for forming a semiconductor structure. A first protection layer is formed on top of the gate structure, sidewalls and etch stop layer. The top of the layer plays a protective role. During the process of forming the first opening through the second interlayer dielectric layer and the first interlayer dielectric layer on the top of the source-drain doped layer, the related etching process will The probability of damage caused by the top of the stop layer is reduced, which is conducive to ensuring the integrity of the etch stop layer. Under the common protection of the above, the risk of the sidewall being damaged due to exposure is also reduced, thereby improving the performance of the semiconductor structure.

Description of drawings

1 to 3 are structural schematic diagrams corresponding to each step in a method for forming a semiconductor structure;

4 is a schematic structural view of an embodiment of a semiconductor structure of the present invention;

5 to 17 are structural schematic diagrams corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

Detailed ways

The performance of current semiconductor structures needs to be improved. Combining with a method of forming a semiconductor structure, the reason why its performance needs to be improved is analyzed.

1 to 3 are structural schematic diagrams corresponding to each step in a method for forming a semiconductor structure.

Referring to FIG. 1 , a base is provided, the base includes a substrate 10 and fins 12 protruding from the substrate 10, a gate structure 19 is formed on the base, and the bases on both sides of the gate structure 19 A source-drain doped layer 18 is formed in the center, a gate capping layer 17 is formed on the top of the gate structure 19, sidewalls 16 are formed on the sidewalls of the gate structure 19 and the gate capping layer 17, and the sidewalls An etch stop layer 15 is formed on the sidewall of the wall 16, and the etch stop layer 15 covers the surface of the side wall 16 exposed by the gate structure 19 and the gate capping layer 17, and the exposed portion of the gate structure 19 A first interlayer dielectric layer 13 is formed on the substrate, the first interlayer dielectric layer 13 covers the sidewall of the etch stop layer 15, and the top of the first interlayer dielectric layer 13 is in contact with the etched The top of the stop layer 15 is flush.

Referring to FIG. 2 , a second interlayer dielectric layer 20 is formed on top of the first interlayer dielectric layer 13 , the etch stop layer 15 , the sidewall 16 and the gate cap layer 17 .

Referring to FIG. 3 , an opening 26 penetrating through the first interlayer dielectric layer 13 and the second interlayer dielectric layer 20 is formed on the top of the source-drain doped layer 18 , and the opening 26 exposes the etch stop layer 15 top and side walls.

It has been found through research that during the process of forming the opening 26 penetrating through the first interlayer dielectric layer 13 and the second interlayer dielectric layer 20 on the top of the source-drain doped layer 18, during the process of forming the opening 26, the Due to the influence of the overlay shift or the size deviation of the opening 26, it is easy for the opening 26 to expose the top of the etch stop layer 15, thus causing the etching process used to form the opening 26 to affect the The top of the etching stop layer 15 exposed by the opening 26 is easy to cause damage (as shown in the dotted circle in FIG. 3 ), so that the topography of the etching stop layer 15 is damaged. The ability of the etch stop layer 15 to cover the sidewall 16 is reduced, which easily leads to a greatly increased probability of the sidewall 16 being exposed, thereby increasing the risk of damage to the sidewall 16 due to exposure, thereby reducing the semiconductor performance of the structure.

In order to solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate on which a gate structure is formed, and active-drain doping is formed in the substrate on both sides of the gate structure. The sidewall of the gate structure is formed with a sidewall, the sidewall of the sidewall is formed with an etching stop layer, and a first interlayer dielectric layer is formed on the substrate exposed by the gate structure, The first interlayer dielectric layer covers the sidewalls of the etch stop layer; a first protective layer is formed on top of the gate structure, sidewalls and etch stop layer; after forming the first protective layer, forming a second interlayer dielectric layer covering the top of the first interlayer dielectric layer and the first protective layer; after forming the second interlayer dielectric layer, forming a The second interlayer dielectric layer and the first opening of the first interlayer dielectric layer; forming source and drain plugs in the first opening.

In the forming method provided by the embodiment of the present invention, the first protective layer is formed on the top of the gate structure, the sidewall and the etch stop layer, because the first protective layer can protect the top of the sidewall and the etch stop layer. Playing a protective role, during the process of forming the first opening through the second interlayer dielectric layer and the first interlayer dielectric layer on the top of the source-drain doped layer, the related etching process will affect the etching stop layer The probability of damage caused by the top is reduced, which is conducive to ensuring the integrity of the etch stop layer, and correspondingly, it is beneficial to ensure the covering ability of the etch stop layer to the sidewall, and the joint protection of the etch stop layer and the protective layer Therefore, the risk of the sidewall being damaged due to exposure is also reduced, thereby improving the performance of the semiconductor structure. .

In order to make the above objects, features and advantages of the embodiments of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

FIG. 4 is a structural schematic diagram of an embodiment of the semiconductor structure of the present invention.

The semiconductor structure includes: a substrate; a gate structure 209 located on the substrate, the gate structure 209 includes a gate dielectric layer (not shown in the figure), and a gate electrode layer (not shown in the figure) covering the gate dielectric layer ); the source-drain doped layer 208, located in the substrate on both sides of the gate structure 209; the sidewall 206, covering the sidewall of the gate structure 209; the etching stop layer 205, located on the sidewall 206 Sidewall; protective layer 228, located on the top of the gate structure 209, sidewall 206 and etch stop layer 205; interlayer dielectric layer 260, located on the substrate at the side of the gate structure 209 and covering the source and drain doping impurity layer 208, the interlayer dielectric layer 260 also covers the top of the protection layer 228; source and drain plugs 230, through the interlayer dielectric layer 260 at the top of the source and drain doped layer 208, the source and drain plugs The bottom of the plug 230 is electrically connected to the top of the source-drain doped layer 208; the gate plug 226 runs through the interlayer dielectric layer 260 and the protective layer 228 on the top of the gate structure 209, and the gate plug The bottom of the plug 230 is electrically connected to the top of the gate structure 209 .

The substrate is used to provide a process platform for subsequent process steps.

In this embodiment, the substrate is used to form a Fin Field Effect Transistor (FinFET). The base includes a substrate 200 and fins 202 protruding from the substrate 200 . In other embodiments, when the substrate is used to form a planar field effect transistor, the substrate is a planar substrate.

In this embodiment, the material of the fin portion 202 is the same as that of the substrate 200 , both being silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

In this embodiment, the semiconductor structure further includes: an isolation layer 201 located on the substrate 200 where the fin 202 is exposed, and the isolation layer 201 covers part of the sidewall of the fin 202 .

When the device is working, the gate structure 209 is used to control the conduction channel to be turned on or off.

In this embodiment, the gate structure 209 is located on the substrate 200 , the gate structure 209 crosses the fin 202 and covers part of the top and part of the sidewall of the fin 202 .

In this embodiment, the gate structure 209 includes a gate dielectric layer (not shown in the figure) and a gate electrode layer (not shown in the figure) covering the gate dielectric layer.

The gate dielectric layer is used to isolate the gate electrode layer and the channel. The material of the gate dielectric layer includes one or more of HfO ₂ , ZrO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al ₂ O ₃ , SiO ₂ and La ₂ O ₃ .

The gate electrode layer is used for subsequent electrical connection with an external interconnection structure. The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

As an example, the gate electrode layer may include a work function layer and an electrode layer located on the work function layer, wherein the work function layer is used to adjust the threshold voltage of the transistor. In other embodiments, the gate electrode layer may also only include a work function layer.

In this embodiment, the semiconductor structure further includes: a gate capping layer 207 located on the top of the gate structure 209 .

The gate capping layer 207 is used to protect the top of the gate structure 209. In the formation process of the semiconductor structure, in the process of forming the source-drain plug 230, the top of the gate structure 209 is reduced from being affected. loss, and the probability of shorting between the source-drain plug 230 and the gate structure 209 .

The gate capping layer 207 is selected from a material having etching selectivity to the sidewall 206 and the second interlayer dielectric layer 217 , so as to ensure that the gate capping layer 207 can protect the top of the gate structure 209 .

The material of the gate capping layer 207 includes one or more of SiC, SiCO, SiN and SiCN. In this embodiment, the material of the gate capping layer 207 is SiN.

The source-drain doped layer 208 is used as a source region and a drain region of a transistor.

When forming an NMOS transistor, the source-drain doped layer 208 includes a stress layer doped with N-type ions, the material of the stress layer is Si, SiC or SiP, and the stress layer provides a channel region for the NMOS transistor. The effect of tensile stress is beneficial to improve the carrier mobility of NMOS transistors, wherein the N-type ions are P ions, As ions or Sb ions; when forming a PMOS transistor, the source-drain doped layer 208 includes doped A stress layer doped with P-type ions, the material of the stress layer is Si or SiGe, and the stress layer provides a compressive stress effect for the channel region of the PMOS transistor, thereby helping to improve the carrier mobility of the PMOS transistor, wherein , the P-type ions are B ions, Ga ions or In ions.

The sidewalls 206 are used to protect the sidewalls of the gate structure 209 . The sidewall 206 can be a single-layer structure or a laminated structure, and the material of the sidewall 206 includes silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon nitride oxide, boron nitride and one or more of boron carbonitride. In this embodiment, the sidewall 206 is a single-layer structure, and the material of the sidewall 206 is silicon oxide.

In this embodiment, during the formation of the semiconductor structure, after removing part of the thickness of the gate structure 209, the gate capping layer 207 is formed in the space enclosed by the sidewall 206 and the remaining gate structure 209. Therefore, The sidewall 206 also covers the sidewall of the gate capping layer 207 .

The etch stop layer 205 is used to protect the sidewall of the sidewall layer 206, and in the formation process of the semiconductor structure, in the process of forming the source and drain plug 230, it reduces the impact of the related etching process on the sidewall layer. The probability of damage to the sidewall of 206.

The material of the etching stop layer 205 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride and boron carbonitride. As an example, the material of the etching stop layer 205 is silicon nitride.

The interlayer dielectric layer 260 is used for isolating adjacent devices, and is also used for electrically isolating between the gate plugs 226 and between the source and drain plugs 230 .

In this embodiment, the interlayer dielectric layer 260 includes: a first interlayer dielectric layer 203, located on the substrate at the side of the gate structure 209 and covering the source-drain doped layer 208, the first interlayer dielectric layer The layer 209 covers part of the sidewall of the etching stop layer 205 exposed by the protection layer 228 ; the second interlayer dielectric layer 217 covers the first interlayer dielectric layer 203 and the top of the protection layer 228 .

The first interlayer dielectric layer 203 is used to isolate adjacent devices, and is also used to electrically isolate the source and drain plugs 230 .

In this embodiment, the first interlayer dielectric layer 209 covers the part of the sidewall of the etching stop layer 205 exposed by the protective layer 228, so that during the formation of the semiconductor structure, the first interlayer dielectric layer 209 can A sacrificial layer is formed on the top of the sacrificial layer, and a protective layer is formed on the top of the gate structure, sidewalls and etching stop layer exposed by the sacrificial layer by using a selective deposition process.

The material of the first interlayer dielectric layer 203 is an insulating material, and the material of the first interlayer dielectric layer 203 includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. one or more of . As an example, the material of the first interlayer dielectric layer 203 is silicon oxide.

The second interlayer dielectric layer 217 plays an electrical isolation role between the gate plugs 226 and between the source and drain plugs 230 .

The material of the second interlayer dielectric layer 217 is an insulating material, and the material of the second interlayer dielectric layer 217 includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride. one or more of . As an example, the material of the second interlayer dielectric layer 217 is silicon oxide.

The protection layer 228 can protect the top of the sidewall 206 and the etch stop layer 205, and form the source and drain plug 230 penetrating through the interlayer dielectric layer 260 on the top of the source and drain doped layer 208. During the process, the probability of the etching process used to cause damage to the top of the etching stop layer 205 is reduced, which is conducive to ensuring the integrity of the appearance of the etching stop layer 205, and correspondingly, is conducive to ensuring that the etching stop layer 205 The covering capability of the sidewall 206, under the common protection of the etching stop layer and the protective layer, reduces the risk of the sidewall 206 being damaged due to exposure, thereby improving the performance of the semiconductor structure.

In this embodiment, the gate capping layer 207 is located on the top of the gate structure 209 , and the protective layer 228 is also located on the top of the gate capping layer 207 . In order to ensure that the depths of the adjacent gate plugs 226 passing through the interlayer dielectric layer 260 and the protective layer 228 are consistent, in the process of forming the gate plugs 226, the protective layer on the top of the gate structure 209 228 defines the etching stop position for etching the interlayer dielectric layer 260 , and then continues to etch the gate capping layer 207 .

In this embodiment, the protection layer 228 also extends to cover part of the sidewall of the etch stop layer 205 .

The protective layer 228 extends to cover part of the sidewall of the etching stop layer 205, and in the semiconductor formation process of forming the source-drain plug 230 on the top of the source-drain doped layer 208, the protective layer 228 can function as a self- The alignment effect reduces the probability that the top and sidewalls of the etch stop layer 205 are damaged, and correspondingly improves the shape integrity of the etch stop layer 205, so that the sidewalls 206 are The risk of damage from exposure is reduced, thereby improving the performance of the semiconductor structure.

It should be noted that the thickness of the protective layer 228 should not be too large, nor should it be too small. If the thickness of the protection layer 228 is too large, in the formation process of the semiconductor structure forming the gate plug 226 on the top of the gate structure 209, the protection layer 228 on the top of the gate structure 209 needs to be removed. The difficulty of the process affects the process efficiency. At the same time, it also makes the process window for forming the gate plug 226 smaller, which increases the process difficulty of forming the gate plug 226. In addition, when the protective layer 228 When extending and covering part of the sidewall of the etch stop layer 205, the thickness of the protective layer 228 is too large, and it is easy to cause the process window for forming the source and drain plugs 230 to become smaller, thereby affecting the performance of the semiconductor structure; if the If the thickness of the protective layer 228 is too small, the protective effect of the protective layer 228 on the top of the etching stop layer 205 will be easily reduced, and the semiconductor source and drain plug 230 will be formed on the top of the source and drain doped layer 208. In the structure formation process, the probability of the etching process causing damage to the top of the etching stop layer 205 is increased, and correspondingly, the risk of the sidewall 206 being damaged due to exposure is also increased, thereby affecting the semiconductor structure. performance. Therefore, in this embodiment, the protective layer 228 has a thickness of 3 nm to 4 nm.

It should also be noted that when the protective layer 228 also extends to cover part of the sidewall of the etching stop layer 205, the height of the protective layer 228 covering the etching stop layer 205 should not be too small, nor should it be too high. big. If the height of the protective layer 228 covering the etching stop layer 205 is too large, the size of the source and drain plugs 230 formed on the top of the source and drain doped layer 208 cannot meet the process requirements, so that the source and drain The contact resistance between the plug 230 and the source-drain doped layer 208 increases, thereby affecting the performance of the semiconductor structure; if the height of the protective layer 228 covering the etching stop layer 205 is too small, it is easy to cause the The protection effect of the protective layer 228 on the sidewall of the etching stop layer 205 is reduced, which increases the probability of damage to the sidewall 206 , thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the protective layer 228 covers the etching stop layer 205 at a height of 2 nm to 5 nm. For example, the protection layer 228 covers the etching stop layer 205 with a height of 3 nm or 4 nm.

In this embodiment, the material of the protection layer 228 includes one or more of TiO ₂ and HfO ₂ .

By selecting one or more of TiO ₂ and HfO ₂ , in the formation process of the semiconductor structure, the protective layer 228 can be formed by a selective deposition process, so that the material of the protective layer 228 is compatible with the selective deposition process. Specifically, before forming the protective layer 228, the surface of the sacrificial layer (not shown) will be passivated using _H2 plasma, so that the surface of the sacrificial layer is modified into dangling bonds (CH), so that During the process of the protective layer 228 , it is difficult for the sacrificial layer to react with the precursor used in the deposition process, which increases the difficulty of depositing the protective layer 228 on the top of the sacrificial layer whose surface has been passivated.

Moreover, the materials of TiO and HfO ₂ have relatively high hardness and are not easy to react with fluorocarbon gases commonly used in etching. The removal rate of the protective layer 228 is lower than the removal rate of the interlayer dielectric layer 260, so that the protective layer 228 can play a good role in protecting the top of the sidewall 206 and the etch stop layer 205 .

The source-drain plug 230 is used to realize the electrical connection between the source-drain doped layer 208 and external circuits or other interconnection structures.

In this embodiment, the material of the source-drain plug 230 is tungsten. The lower resistivity of tungsten is beneficial to improve the signal delay of the back-stage RC and improve the processing speed of the chip, and also helps to reduce the resistance of the source-drain plug 230, thereby reducing power consumption accordingly. In other embodiments, the material of the source and drain plugs may also be conductive materials such as molybdenum or ruthenium.

The gate plug 226 is used to realize the electrical connection between the gate structure 209 and external circuits or other interconnection structures.

In this embodiment, in the formation process of the semiconductor structure, the source-drain plug 230 and the gate plug 226 are formed in the same step, therefore, the material of the gate plug 226 is the same as that of the gate plug 226 The material of the source and drain plugs 230 is the same, therefore, the material of the gate plug 226 is tungsten. In other embodiments, the material of the source and drain plugs may also be conductive materials such as molybdenum or ruthenium.

In this embodiment, the gate plug 226 also penetrates through the gate capping layer 207 on top of the gate structure 209 .

The gate plug 226 penetrates through the gate capping layer 207 at the top of the gate structure 209, so that the gate plug 226 is electrically connected to the top of the gate structure 209, so as to achieve the The electrical requirements of the gate plug 226 are described above.

5 to 17 are structural schematic diagrams corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

Referring to FIG. 5 , a substrate is provided, on which a gate structure 109 is formed, source and drain doped layers 108 are formed in the substrate on both sides of the gate structure 109, and sidewalls of the gate structure 109 are formed with sidewalls. Wall 106, the side wall of the sidewall 106 is formed with an etch stop layer 105, the substrate exposed by the gate structure 109 is formed with a first interlayer dielectric layer 103, and the first interlayer dielectric layer 103 Covering the sidewalls of the etch stop layer 105 .

The substrate is used to provide a process platform for subsequent process steps.

In this embodiment, the substrate is used to form a Fin Field Effect Transistor (FinFET). The base includes a substrate 100 and fins 102 protruding from the substrate 100 . In other embodiments, when the substrate is used to form a planar field effect transistor, the substrate is a planar substrate.

In this embodiment, the material of the fin portion 102 is the same as that of the substrate 100 , both being silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

In this embodiment, the method for forming the semiconductor structure further includes: after forming the fin 102 , forming an isolation layer 101 on the substrate 100 exposed by the fin 102 , and the isolation layer 101 covers the fin 102 part of the side wall.

The isolation layer 101 is used to isolate adjacent devices. The material of the isolation layer 101 may be silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the material of the isolation layer 101 is silicon oxide.

When the device is working, the gate structure 109 is used to control the conduction channel to be turned on or off.

In this embodiment, the gate structure 109 is located on the substrate 100 , the gate structure 109 crosses the fin 102 and covers part of the top and part of the sidewall of the fin 102 .

In this embodiment, the gate structure 109 includes a gate dielectric layer (not shown in the figure) and a gate electrode layer (not shown in the figure) covering the gate dielectric layer.

The gate dielectric layer is used to isolate the gate electrode layer and the channel. The material of the gate dielectric layer includes one or more of HfO ₂ , ZrO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al ₂ O ₃ , SiO ₂ and La ₂ O ₃ .

The gate electrode layer is used for subsequent electrical connection with an external interconnection structure. The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

As an example, the gate electrode layer may include a work function layer and an electrode layer located on the work function layer, wherein the work function layer is used to adjust the threshold voltage of the transistor. In other embodiments, the gate electrode layer may also only include a work function layer.

The source-drain doped layer 108 is used as a source region and a drain region of a transistor.

When forming an NMOS transistor, the source-drain doped layer 108 includes a stress layer doped with N-type ions, the material of the stress layer is Si or SiC, and the stress layer provides tensile stress for the channel region of the NMOS transistor. role, thereby helping to improve the carrier mobility of NMOS transistors, wherein the N-type ions are P ions, As ions or Sb ions; when forming a PMOS transistor, the source-drain doped layer 108 includes doped A stress layer of P-type ions, the material of the stress layer is Si or SiGe, and the stress layer provides a compressive stress effect for the channel region of the PMOS transistor, thereby helping to improve the carrier mobility of the PMOS transistor. The P-type ions are B ions, Ga ions or In ions.

The sidewalls 106 are used to protect sidewalls of the gate structure 109 . The sidewall 106 can be a single-layer structure or a laminated structure, and the material of the sidewall 106 includes silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon nitride oxide, boron nitride and one or more of boron carbonitride. In this embodiment, the sidewall 106 is a single-layer structure, and the material of the sidewall 106 is silicon oxide.

The etch stop layer 105 is used to protect the sidewalls of the sidewalls 106 and reduce the probability of damage to the sidewalls of the sidewalls 106 caused by related etching processes during the subsequent formation of the first opening.

The material of the etching stop layer 105 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride and boron carbonitride. As an example, the material of the etching stop layer 105 is silicon nitride.

The first interlayer dielectric layer 103 is used to isolate adjacent devices, and is also used to occupy a space position for a source-drain plug and a second protective layer formed later.

The material of the first interlayer dielectric layer 103 is an insulating material, and the material of the first interlayer dielectric layer 103 includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. one or more of . As an example, the material of the first interlayer dielectric layer 103 is silicon oxide.

In this embodiment, in the step of providing the substrate, a gate capping layer 107 is further formed on the top of the gate structure 109 .

The gate capping layer 107 is used to protect the top of the gate structure 109, so as to reduce the damage of the gate structure 109 and the source-drain plug and gate structure in the subsequent process of forming the source-drain plug. 109 probability of short circuit.

The gate capping layer 107 is selected from a material having etch selectivity to the sidewall 106 and the subsequently formed second interlayer dielectric layer, so as to ensure that the gate capping layer 107 can protect the top of the gate structure 109 .

The material of the gate cap layer 107 includes one or more of SiC, SiCO, SiN and SiCN. In this embodiment, the material of the gate capping layer 107 is SiN.

Referring to FIG. 6 , part of the thickness of the first interlayer dielectric layer 103 is removed to form a groove 110 surrounded by the sidewalls of the etch stop layer 105 and the top of the remaining first interlayer dielectric layer 103 .

The groove 110 provides a space for the subsequent formation of a sacrificial layer and a protective layer.

In this embodiment, the partial thickness of the first interlayer dielectric layer 103 is etched back, thereby removing the partial thickness of the first interlayer dielectric layer 103 .

Specifically, the etching process used includes a dry etching process.

The dry etching process includes an anisotropic dry etching process, and the anisotropic dry etching process has characteristics of anisotropic etching. That is, the longitudinal etching rate is greater than the lateral etching rate, which can remove part of the thickness of the first interlayer dielectric layer 103 while ensuring the quality of the topography of the sidewall of the groove 110 .

It should be noted that the depth of the groove 110 should neither be too large nor too small. If the depth of the groove 110 is too large, the thickness of the sacrificial layer subsequently formed in the groove 110 is also too large, because the second protective layer is subsequently formed on the sidewall of the groove 110, making subsequent removal The process window of the sacrificial layer becomes smaller, which increases the process difficulty of removing the sacrificial layer, thereby affecting the performance of the semiconductor structure, and also easily causes unnecessary excessive etching, resulting in waste of process cost; if the The depth of the groove 110 is too small, and after forming a sacrificial layer in the groove 110 that meets the process size requirements, the space reserved for the second protective layer is too small, so that the second protective layer The size requirement does not meet the process requirement, thereby affecting the self-alignment function of the second protective layer in the process of forming the first opening. Therefore, in this embodiment, the depth of the groove 110 is 10 nm to 20 nm.

Referring to FIGS. 7 to 8 , a sacrificial layer 112 is formed in the groove 110 .

Specifically, a sacrificial layer 112 is formed in the groove, so that the sacrificial layer 112 exposes the tops of the etch stop layer 105, the sidewall 106 and the gate cap layer 107, which is beneficial to the subsequent formation of the etch stop layer. 105. A first protection layer is formed on the top of the sidewall 106 and the gate cap layer 107, and at the same time, in the subsequent deposition process for forming the first protection layer, by selecting the top of the sacrificial layer 112 The material used as the material of the sacrificial layer 112 reduces the probability of forming the first protective layer on the top of the sacrificial layer 112, so that the process step of removing the first protective layer formed on the top of the sacrificial layer 112 can be omitted, thereby simplifying the process steps, reducing the process cost.

In this embodiment, the top of the sacrificial layer 112 is lower than the top of the etch stop layer 105 , and the sacrificial layer 112 exposes part of the sidewall of the etch stop layer 105 .

The sacrificial layer 112 exposes a part of the sidewall of the etch stop layer 105, which facilitates subsequent formation of a second protection layer on the sidewall of the etch stop layer 105 exposed by the sacrificial layer 112, so that the source In the process of forming the first opening on the top of the drain doped layer 108, the second protection layer can play a self-alignment effect, reducing the impact of the etching process related to forming the first opening on the gate structure and The probability of damage to the top of the sidewall is caused, thereby improving the performance of the semiconductor structure.

It should be noted that the distance between the top of the sacrificial layer 112 and the top of the etching stop layer 105 should not be too small, nor should it be too large. If the distance from the top of the sacrificial layer 112 to the top of the etch stop layer 105 is too large, it is easy to cause the height of the second protective layer formed on the sidewall of the etch stop layer 105 to be too large. Correspondingly, As a result, the size of the source-drain plugs subsequently formed on the top of the source-drain doped layer 108 cannot meet the process requirements, so that the contact resistance between the source-drain plugs and the source-drain doped layer 108 increases, thereby Affect the performance of the semiconductor structure; if the distance from the top of the sacrificial layer 112 to the top of the etch stop layer 105 is too small, it will easily lead to the height of the second protective layer formed on the sidewall of the etch stop layer 105 subsequently. Correspondingly, the protective effect of the second protection layer on the sidewall of the etch stop layer 105 is reduced, which increases the probability of damage to the sidewall 106. The process of forming the first opening on the top of the impurity layer 108 also affects the etching stop function of the second protection layer, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the distance from the top of the sacrificial layer 112 to the top of the etching stop layer 105 is 10 nm to 20 nm.

In this embodiment, the step of forming the sacrificial layer 112 in the groove 110 includes: as shown in FIG. 7 , forming a sacrificial material layer 111 in the groove 110, and the sacrificial material layer 111 also covers the gate pole structure 109, sidewall 106 and the top of etch stop layer 105; as shown in FIG. Partial thickness of the sacrificial material layer 111 in the groove 110, the remaining sacrificial material layer 111 in the groove 110 is used as the sacrificial layer 112, and the sacrificial layer 112 exposes part of the side of the etching stop layer 105 wall.

In other embodiments, according to process requirements, the top of the sacrificial layer may also be flush with the top of the etch stop layer, so that the first protection layer is only formed on top of the gate structure, sidewalls and etch stop layer.

In this embodiment, in the step of forming the sacrificial layer 112 in the groove 110 , the material of the sacrificial layer 112 includes one or both of amorphous carbon and spin-on carbon.

The amorphous carbon and spin-on carbon materials have the characteristics of low material hardness, which is beneficial to the subsequent removal of the sacrificial layer 112 through an ashing process or a wet etching process, and reduces the process difficulty of removing the sacrificial layer 112 .

At the same time, before forming the first protective layer, _H2 plasma will be used to passivate the surface of the sacrificial layer 112, so that the surface of the sacrificial layer 112 is modified into dangling bonds (CH), thereby In the process of forming the first protective layer, the sacrificial layer 112 is difficult to react with the precursor used in the deposition process, which increases the deposition of the first protective layer on the top of the sacrificial layer 112 after surface passivation. difficulty. For this reason, the amorphous carbon and spin-on carbon materials are not easy to be deposited. In the process of forming the first protective layer on the top of the gate structure 109, the spacer 106 and the etch stop layer 105, the first protective layer is formed. The material of a protective layer is not easily deposited on the top of the sacrificial layer 112 , thereby reducing the process steps of removing the top of the sacrificial layer 112 to form the first protective layer, and reducing the process cost.

In this embodiment, the process of forming the sacrificial material layer 111 in the groove 110 includes a chemical vapor deposition process.

The chemical vapor deposition has the characteristics of fast deposition rate and good filling effect, and the sacrificial layer 112 formed in the groove 110 can closely adhere to the sidewall of the etch stop layer 105, so that only in the subsequent The sidewall of the etching stop layer 105 exposed by the sacrificial layer 112 forms a second protection layer.

In this embodiment, the partial thickness of the sacrificial material layer 111 is etched back, thereby removing the sacrificial material layer 111 on the top of the gate structure 109, the sidewall 106 and the etch stop layer 105, and a partial thickness of the groove 110. The sacrificial material layer 111.

Specifically, the etching process used includes a dry etching process.

Since the gate structure 109, the spacer 106 and the etch stop layer 105 have a higher etching selectivity than the sacrificial material layer 111, the dry etching process has an anisotropic dry etching characteristics, in the process of removing the sacrificial material layer 111 on the top of the gate structure 109, the spacer 106 and the etch stop layer 105, and the partial thickness of the sacrificial material layer 111 in the groove 110, the dry method is selected. The etching process can reduce damage to other layers of the semiconductor structure.

Moreover, the dry etching process has the characteristics of anisotropic etching, and can realize vertical etching, so that while reducing the thickness of the sacrificial material layer 111, it is beneficial to improve the flatness and thickness uniformity of the top surface of the sacrificial layer 112, Therefore, the height uniformity of the subsequent second protection layer covering the etching stop layer 105 is improved.

Referring to FIG. 9 , a first protective layer 115 is formed on top of the gate structure 109 , spacer 106 and etch stop layer 105 .

It should be noted that the first protection layer 115 is formed on the top of the gate structure 109, the spacer 106 and the etch stop layer 105, because the first protection layer 115 can protect the spacer 106 and the etch stop layer 105 The top of the doped source-drain layer 108 plays a protective role. In the subsequent process of forming the first opening through the second interlayer dielectric layer and the first interlayer dielectric layer on the top of the source and drain doped layer 108, the relevant etching process will The probability of damage caused by the top of the etch stop layer 105 is reduced, which is beneficial to ensure the integrity of the etch stop layer 105, and correspondingly, is beneficial to ensure the covering ability of the etch stop layer 105 to the sidewall 106, so that the The risk of damage to the sidewalls 106 due to exposure is also reduced, thereby improving the performance of the semiconductor structure.

In this embodiment, in the step of forming the first protection layer 115 on the top of the gate structure 109, the spacer 106 and the etch stop layer 105, the first protection layer 115 also covers the gate capping layer 107 the top of.

Specifically, in the subsequent process of forming the second opening on the top of the gate structure 109, in order to ensure that the etching depths of the adjacent second openings are consistent, the first protective layer on the top of the gate capping layer 107 is used first. Layer 115 acts as an etch stop before simultaneously etching the gate cap layer 107 .

In this embodiment, the step of forming the first protective layer 115 includes: using an area-selective-deposition (ASD) process to expose the gate structure 109, sidewalls 106 and A first protection layer 115 is formed on top of the etch stop layer 105 .

In this embodiment, in the selective deposition process, the difficulty of depositing the first protective layer 115 on the surface of the sacrificial layer 112 is greater than the difficulty of depositing the first protective layer 115 on the surface of the gate structure 109, the spacer 106 and the etching stop layer 105, Therefore, the first protection layer 115 can be selectively formed on the top of the gate structure 109 , the sidewall 106 and the etching stop layer 105 exposed by the sacrificial layer 112 .

Specifically, _H2 plasma is used to passivate the surface of the sacrificial layer 112. After the passivation treatment, the gate structure 109, sidewalls 106 and etchings selectively exposed on the sacrificial layer 112 are A first protective layer 115 is formed on top of the etch stop layer 105 .

Before forming the first protective layer 115, use _H2 plasma to passivate the surface of the sacrificial layer 112, so that the surface of the sacrificial layer 112 is modified into dangling bonds (CH), thereby forming the In the process of the first protective layer 115, the sacrificial layer 112 is difficult to react with the precursor used in the deposition process, that is, the deposition of the first protective layer 115 on the top of the sacrificial layer 112 after surface passivation is increased. difficulty.

Specifically, the selective deposition process has characteristics such as deposition flexibility, and its deposition rate on different materials is different, so as to meet the required process requirements. The gate exposed in the sacrificial layer 112 by the selective deposition process is In the process of forming the first protection layer 115 on the top of the pole structure 109, the sidewall 106 and the etch stop layer 105, the deposition of the first protection layer 115 on the surface of the gate structure 109, the sidewall 106 and the etch stop layer 105 The rate is much higher than the deposition rate on the surface of the sacrificial layer 112, so that a small amount of the first protective layer 115 is deposited on the surface of the sacrificial layer 112, and at the same time, in the subsequent cleaning process, the surface of the sacrificial layer 112 A small amount of the first protection layer 115 formed will be removed.

Correspondingly, by selecting a selective deposition process, the first protective layer 115 can be directly formed at the target position without patterning treatment (for example, etching treatment), which is beneficial to reduce the process of forming the first protective layer 115. The probability of causing damage to the gate structure 109 , the spacer 106 and the etch stop layer 105 .

In this embodiment, the top of the sacrificial layer 112 is lower than the top of the etch stop layer 105, and the sacrificial layer 112 exposes part of the sidewall of the etch stop layer 105, therefore, a selective deposition process is used In the step of forming the first protective layer 115 on the top of the gate structure 109, spacer 106 and etch stop layer 105 exposed by the sacrificial layer 112, the material for forming the first protective layer 115 is also selectively deposited On the sidewall of the etching stop layer 105 exposed by the sacrificial layer 112, a second protective layer 116 is formed on the sidewall of the etching stop layer 105 exposed by the sacrificial layer 112, and the second protective layer The top of the protection layer 116 is flush with the top of the first protection layer 115 , and the second protection layer 116 and the first protection layer 115 form a protection layer 128 .

By forming the second protective layer 116 on the sidewall of the etching stop layer 105 exposed by the sacrificial layer 112, and subsequently forming the first opening on the top of the source-drain doped layer 108, the second The protection layer 116 can play a self-alignment effect, which reduces the probability of damage to the top and sidewalls of the etching stop layer 105 during the etching process for forming the first opening, and accordingly improves the etching process. The integrity of the topography of the etch stop layer 105 reduces the risk of the sidewalls 106 being damaged due to exposure, thereby improving the performance of the semiconductor structure.

It should be noted that the thickness of the first protective layer 115 should not be too large, nor should it be too small. If the thickness of the first protective layer 115 is too large, the subsequent process of forming the second opening on the top of the gate structure 109 will increase the process difficulty of removing the first protective layer 115 and affect the process efficiency. At the same time, the process window for removing the sacrificial layer 112 is also reduced, which increases the difficulty of removing the sacrificial layer 112, thus affecting the performance of the semiconductor structure; if the thickness of the first protective layer 115 is too small, Then it is easy to reduce the protective effect of the first protection layer 115 on the top of the sidewall 106 and the etch stop layer 105, and subsequently increase the The probability of damage to the top of the etch stop layer 105 caused by the etching process is reduced, and correspondingly, the risk of the sidewall 106 being damaged due to exposure is also increased, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the first protective layer 115 is 2 nm to 5 nm.

In this embodiment, the material of the first protection layer 115 includes one or more of TiO ₂ and HfO ₂ .

By selecting one or more of TiO ₂ and HfO ₂ , the first protection layer 115 can be formed by a selective deposition process, so that the material of the first protection layer 115 is compatible with the selective deposition process. At the same time, the material hardness of the TiO ₂ and HfO ₂ is relatively high, and in the subsequent process of forming the first opening on the top of the source-drain doped layer 108, the removal rate of the first protective layer 115 is lower than that of the subsequent formation. The rate at which the second interlayer dielectric layer is removed enables the first protective layer 115 to play a good role in protecting the spacer 106 and the top of the etch stop layer 105 .

It should be noted that, in this embodiment, the groove is formed by etching back the first interlayer dielectric layer 103, the sacrificial layer 112 is formed by etching back the sacrificial material layer 111, and the selective deposition method is used. The first protection layer 115, that is to say, the step of etching back the first interlayer dielectric layer 103, the step of etching back the sacrificial material layer 111, and the step of forming the first protection layer 115 do not require an additional photomask, so , the forming method described in this embodiment does not add additional photomasks, which is beneficial to reduce process costs.

Referring to FIG. 10 , the sacrificial layer 112 is removed.

The sacrificial layer 112 is removed to provide a space for subsequent formation of a second interlayer dielectric layer covering the tops of the first interlayer dielectric layer 103 and the first protection layer 115 .

At the same time, since the material of the sacrificial layer 112 itself has insufficient mechanical strength, it is not suitable as a material for the dielectric layer, therefore, the sacrificial layer 112 needs to be removed.

In this embodiment, the process of removing the sacrificial layer 112 includes a wet etching process.

The wet etching process has the characteristics of an isotropic etching process, and has the characteristics of strong etching target, high etching efficiency, and strong lateral etching ability, and can remove the sidewall of the groove 110 along the lateral direction. During the sacrificial layer 112 process, the damage to the first interlayer dielectric layer 103 at the bottom of the groove 110 and the etch stop layer 105 on the sidewall of the groove 110 is reduced.

In other embodiments, the sacrificial layer may also be removed by an ashing process.

Referring to FIG. 11 , after the first protective layer 115 is formed, a second interlayer dielectric layer 117 covering the top of the first interlayer dielectric layer 103 and the first protective layer 115 is formed.

The second interlayer dielectric layer 117 provides a process basis for the subsequent formation of gate plugs and source and drain plugs, and at the same time, also plays an electrical isolation role for the subsequently formed gate plugs and source and drain plugs.

In this embodiment, the process of forming the second interlayer dielectric layer 117 includes a chemical vapor deposition process.

The material of the second interlayer dielectric layer 117 is an insulating material, and the material of the second interlayer dielectric layer 117 includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. one or more of . As an example, the material of the second interlayer dielectric layer 117 is silicon oxide.

Referring to FIG. 12 , after the second interlayer dielectric layer 117 is formed, a first opening through the second interlayer dielectric layer 117 and the first interlayer dielectric layer 103 is formed on the top of the source-drain doped layer 108 120.

The first opening 120 provides a space for subsequent formation of source and drain plugs.

In this embodiment, the step of forming the first opening 120 penetrating through the second interlayer dielectric layer 117 and the first interlayer dielectric layer 103 on the top of the source-drain doped layer 108 includes: forming a first opening 120 penetrating through the source-drain layer 108 the initial first opening 125 of the second interlayer dielectric layer 117 on the top of the doped layer 108; An initial second opening 118 penetrating through the first interlayer dielectric layer 103 and exposing the top of the source-drain doped layer 108 is formed adjacent to the second protection layer 116, and the initial second opening 125 and the initial first The opening 118 constitutes the first opening 120 .

Specifically, there is a relatively large etching selectivity ratio between the protection layer 128 and the second interlayer dielectric layer 117. During the process of forming the first opening 120, due to the removal of the protection layer 128 The rate is lower, so that the process window for forming the first opening 120 becomes larger, thereby reducing the process difficulty of forming the first opening 120 .

It should be noted that there is also a relatively large etching selectivity ratio between the protective layer 128 and the first interlayer dielectric layer 103 , as described above in detail, and will not be repeated here.

In this embodiment, the process of forming the first opening 120 penetrating through the second interlayer dielectric layer 117 and the first interlayer dielectric layer 103 on the top of the source-drain doped layer 108 includes a dry etching process.

Referring to FIG. 13 , a filling layer 119 is formed in the first opening 120 .

Form a filling layer 119 in the first opening 120, and subsequently form a second opening on the top of the gate structure 109 to reduce the source and drain exposed to the first opening 120 by the selected etching process. Damage to the top surface of the doped layer 108 improves the performance of the semiconductor structure.

In this embodiment, the step of forming the filling layer 119 in the first opening 120 includes: forming a filling material layer (not shown) on the top of the second interlayer dielectric layer 117 and in the first opening 120 ; using the top of the second interlayer dielectric layer 117 as a stop position, planarize the filling material layer higher than the top of the second interlayer dielectric layer 117, remaining in the first opening 120 The filling material layer is used as the filling layer 119.

In this embodiment, the process of forming the filling layer 119 in the first opening 120 includes a chemical vapor deposition process. In other embodiments, the process of forming the filling layer in the first opening may further include one or both of an atomic layer deposition process and a physical vapor deposition process.

In order to facilitate the subsequent removal of the filling layer 119 formed in the first opening 120, it is necessary to select an easy-to-remove material as the material of the filling layer 119. Therefore, in this embodiment, the material of the filling layer 119 includes One or more of ODL (organic dielectric layer, organic dielectric layer) material, spin-on carbon (Spin-on carbon, SOC) and APF (Advanced Patterning Film, advanced pattern film) material.

Referring to FIGS. 14 to 16 , a second opening 123 penetrating through the second interlayer dielectric layer 117 and the first passivation layer 115 is formed on the top of the gate structure 109 .

The second opening 123 provides a space for subsequent formation of gate plugs.

In this embodiment, the step of forming the second opening 123 penetrating through the second interlayer dielectric layer 117 and the first protective layer 115 on the top of the gate structure 109 includes: as shown in FIG. 14 , etching the The second interlayer dielectric layer 117 on the top of the gate structure 109 until an initial third opening 121 exposing the top surface of the first protection layer 115 is formed; as shown in FIGS. The first protection layer 115 and the gate capping layer 107 exposed by the three openings 121 form an initial fourth opening 122 exposing the top of the gate structure 109, and the initial third opening 121 and the initial fourth opening 122 constitute the first Two openings 123.

In this embodiment, in the step of forming the second opening 123 penetrating through the second interlayer dielectric layer 117 and the first protection layer 115 on the top of the gate structure 109, the second opening 123 penetrates through the The gate capping layer 107 on top of the gate structure 109 .

The second opening 123 penetrates through the gate capping layer 107 at the top of the gate structure 109, so that the gate plug formed in the second opening 123 and the gate structure 109 can be electrically connected. connect.

It should be noted that there is an etching selectivity ratio between the sidewall 106 and the gate capping layer 107, therefore, during the process of forming the second opening 123, the sidewall 106 can play a role of self-alignment. The function of alignment reduces the probability of damage to the top of the source-drain doped layer 108 on both sides of the gate structure 109 .

In this embodiment, the process of forming the second opening 123 penetrating through the second interlayer dielectric layer 117 and the first protection layer 115 on the top of the gate structure 109 includes a dry etching process.

In this embodiment, after the first opening 120 penetrating through the second interlayer dielectric layer 117 and the first interlayer dielectric layer 103 is formed on the top of the source-drain doped layer 108, the gate structure 109 A second opening 123 penetrating through the second interlayer dielectric layer 117 and the first protection layer 115 is formed at the top.

It should be noted that the first opening 120 is formed first, and then the second opening 123 is formed, which omits the step of removing the top filling layer of the gate structure 109, and correspondingly reduces the impact on the top of the gate structure 109. damage probability, thereby improving the performance of the semiconductor structure, and at the same time, by forming the first opening 120 and the second opening 123 in different steps, it is beneficial to reduce the damage caused by the gate structure 109 and the source-drain doping The influence caused by the too small distance between the miscellaneous layers 108 is also beneficial to reduce the influence caused by deviations in overlay accuracy.

It should be noted that, in this embodiment, after forming the second opening 123, before forming the source-drain plug and the gate plug, further include: removing the filling layer in the first opening 120 119.

In this embodiment, the process of removing the filling layer 119 includes a wet etching process.

Referring to FIG. 17 , source and drain plugs 130 are formed in the first opening 120 .

The source-drain plug 130 is used to realize the electrical connection between the source-drain doped layer 108 and external circuits or other interconnection structures.

In this embodiment, the step of forming the source-drain plug 130 in the first opening 120 includes: forming a conductive material layer (not shown in the figure) in the first opening 120, and the conductive material layer also covers the The top of the second interlayer dielectric layer 117; using the top of the second interlayer dielectric layer 117 as a stop position, the conductive material layer higher than the top of the second interlayer dielectric layer 117 is planarized, and the rest located at the top of the second interlayer dielectric layer 117 The conductive material layer in the first opening 120 serves as the source-drain plug 130 .

In this embodiment, the process of planarizing the conductive material layer higher than the top of the second interlayer dielectric layer 117 includes a chemical mechanical polishing process.

In this embodiment, the material of the source-drain plug 130 is tungsten. The lower resistivity of tungsten is beneficial to improve the signal delay of the back-end RC and increase the processing speed of the chip, and at the same time, it is also beneficial to reduce the resistance of the source-drain plug 130 and reduce power consumption accordingly. In other embodiments, the material of the source and drain plugs may also be conductive materials such as molybdenum or ruthenium.

In this embodiment, in the step of forming the source-drain plug 130 in the first opening 120 , a gate plug 126 is also formed in the second opening 123 .

The gate plug 126 is used to realize the electrical connection between the gate structure 109 and external circuits or other interconnection structures.

Specifically, the source-drain plug 130 and the gate plug 126 are formed in the same step, which reduces process steps and reduces process cost. In other embodiments, the source and drain plugs may also be formed first, and then the gate plugs, or, the gate plugs are formed first, and then the source and drain plugs are formed.

In this embodiment, in the same step, the source-drain plug 130 is formed in the first opening 120, and the gate plug 126 is formed in the second opening 123. Therefore, the gate plug 126 The material is the same as that of the source and drain plugs 130 , therefore, the material of the gate plug 126 is tungsten. In other embodiments, the material of the source and drain plugs may also be conductive materials such as molybdenum or ruthenium.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (21)

1. A semiconductor structure, characterized in that, comprising: base; a gate structure located on the substrate, the gate structure comprising a gate dielectric layer and a gate electrode layer covering the gate dielectric layer; a source-drain doped layer located in the substrate on both sides of the gate structure; a side wall covering the side wall of the gate structure; an etch stop layer located on the sidewall of the sidewall; a protective layer on top of the gate structure, sidewalls and etch stop layer; an interlayer dielectric layer, located on the substrate at the side of the gate structure and covering the source-drain doped layer, and the interlayer dielectric layer also covers the top of the protection layer; a source-drain plug that penetrates the interlayer dielectric layer at the top of the source-drain doped layer, and the bottom of the source-drain plug is electrically connected to the top of the source-drain doped layer; A gate plug penetrates through the interlayer dielectric layer and the protection layer on the top of the gate structure, and the bottom of the gate plug is electrically connected to the top of the gate structure. 2 . The semiconductor structure according to claim 1 , wherein the passivation layer also extends to cover a part of the sidewall of the etch stop layer. 3 . 3. The semiconductor structure according to claim 1, further comprising: a gate capping layer located on the top of the gate structure; the protection layer is located on top of the gate capping layer; The gate plug also penetrates the gate capping layer on top of the gate structure. 4. The semiconductor structure according to claim 1, wherein the interlayer dielectric layer comprises: a first interlayer dielectric layer located on the substrate at the side of the gate structure and covering the source-drain doped layer, The first interlayer dielectric layer covers part of the sidewall of the etching stop layer exposed by the protection layer; The second interlayer dielectric layer covers the top of the first interlayer dielectric layer and the protective layer. 5. The semiconductor structure according to claim 1, wherein the protective layer has a thickness of 2 nm to 5 nm. 6. The semiconductor structure according to claim 1, wherein the material of the protective layer comprises one or both of TiO ₂ and HfO ₂ . 7. The semiconductor structure according to claim 1, wherein the material of the sidewall comprises silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon nitride oxide, boron nitride and one or more of boron carbonitride. 8. The semiconductor structure according to claim 1, wherein the material of the gate dielectric layer comprises HfO ₂ , ZrO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al ₂ O ₃ , SiO ₂ and La ₂ One or more of O ₃ ; the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC. 9. A method for forming a semiconductor structure, comprising: A substrate is provided, a gate structure is formed on the substrate, source and drain doped layers are formed in the substrate on both sides of the gate structure, side walls of the gate structure are formed with side walls, and the side walls of the side walls An etch stop layer is formed on the wall, a first interlayer dielectric layer is formed on the substrate exposed by the gate structure, and the first interlayer dielectric layer covers the sidewall of the etch stop layer; forming a first protection layer on top of the gate structure, sidewalls and etch stop layer; After forming the first protective layer, forming a second interlayer dielectric layer covering the top of the first interlayer dielectric layer and the first protective layer; After forming the second interlayer dielectric layer, forming a first opening through the second interlayer dielectric layer and the first interlayer dielectric layer on the top of the source-drain doped layer; A source-drain plug is formed in the first opening. 10 . The method for forming a semiconductor structure according to claim 9 , further comprising: forming a second plug on the top of the gate structure before forming a source-drain plug in the first opening. the second opening of the interlayer dielectric layer and the first protective layer; In the step of forming a source-drain plug in the first opening, a gate plug is also formed in the second opening. 11. The method for forming a semiconductor structure according to claim 9, further comprising: before forming the first protective layer, removing a part of the thickness of the first interlayer dielectric layer, forming a layer formed by the etching a groove enclosed by the sidewall of the stop layer and the top of the remaining first interlayer dielectric layer; forming a sacrificial layer in the groove; The step of forming the first protection layer includes: using a selective deposition process to form a first protection layer on top of the gate structure, sidewalls and etch stop layer exposed by the sacrificial layer. 12. The method for forming a semiconductor structure according to claim 11, wherein in the step of forming a sacrificial layer in the groove, the top of the sacrificial layer is lower than the top of the etch stop layer, and The sacrificial layer exposes part of the sidewall of the etch stop layer; In the step of forming a first protection layer on top of the gate structure, sidewalls and etch stop layer exposed by the sacrificial layer by using a selective deposition process, the material of the first protection layer is also selectively deposited on the The sidewall of the etching stop layer exposed by the sacrificial layer, a second protective layer is formed on the sidewall of the etching stop layer exposed by the sacrificial layer, and the top of the second protective layer is connected with the first The tops of the protective layers are flush with each other, and the second protective layer and the first protective layer constitute the protective layer. 13. The method for forming a semiconductor structure according to claim 12, wherein the step of forming a sacrificial layer in the groove comprises: forming a sacrificial material layer in the groove, and the sacrificial material layer also covers the top of the gate structure, sidewalls and etch stop layer; removing the sacrificial material layer on top of the gate structure, sidewalls and etch stop layer, and a partial thickness of the sacrificial material layer in the groove, and the remaining sacrificial material layer in the groove serves as the A sacrificial layer, the sacrificial layer exposing a part of the sidewall of the etching stop layer. 14. The method for forming a semiconductor structure according to claim 12, wherein a first opening penetrating through the second interlayer dielectric layer and the first interlayer dielectric layer is formed on the top of the source-drain doped layer The steps include: forming an initial first opening through the second interlayer dielectric layer at the top of the source-drain doped layer; after forming the initial first opening, using the sidewall of the second protection layer as a lateral etching stop position, an initial second opening that penetrates the first interlayer dielectric layer and exposes the top of the source-drain doped layer is formed between adjacent second protective layers, the initial second opening and the initial first An opening constitutes the first opening. 15. The method for forming a semiconductor structure according to claim 10, wherein in the step of providing a base, a gate cap layer is further formed on the top of the gate structure; In the step of forming a first protection layer on top of the gate structure, sidewalls and etch stop layer, the first protection layer also covers the top of the gate capping layer; In the step of forming a second opening through the second interlayer dielectric layer and the first protection layer on the top of the gate structure, the second opening also penetrates the gate located at the top of the gate structure Cap layer. 16. The method for forming a semiconductor structure according to claim 10, wherein a first opening penetrating through the second interlayer dielectric layer and the first interlayer dielectric layer is formed on the top of the source-drain doped layer Afterwards, a second opening penetrating through the second interlayer dielectric layer and the first protection layer is formed on the top of the gate structure. 17. The method for forming a semiconductor structure according to claim 10, wherein after forming the first opening on the top of the source-drain doped layer and before forming the second opening on the top of the gate structure, further comprising: forming a filling layer in the first opening; After forming the second opening and before forming the source-drain plug and the gate plug, the method further includes: removing the filling layer in the first opening. 18. The method for forming a semiconductor structure according to claim 11, wherein in the step of forming a sacrificial layer in the groove, the material of the sacrificial layer includes one of amorphous carbon and spin-on carbon or two. 19. The method for forming a semiconductor structure according to claim 11, wherein after forming a first protection layer on top of the gate structure, sidewalls and etch stop layer, after forming the second interlayer Before the dielectric layer, it also includes: removing the sacrificial layer. 20. The method for forming a semiconductor structure according to claim 9, wherein the material of the first protective layer comprises one or more of TiO ₂ and HfO ₂ . 21. The method for forming a semiconductor structure according to claim 9, wherein the material of the sidewall comprises silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon nitride oxide, One or more of boron nitride and carbon boron nitride.

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