CN115715086A - Memory cell structure and forming method thereof - Google Patents

Abstract

A memory cell structure and a method for forming the same, wherein the method includes: using the first sidewall and the second sidewall as a mask, etching the transition floating gate layer until the surface of the substrate is exposed, to form two storage gate structures separated from each other on the substrate and an opening between the two storage structures, each storage gate structure includes a floating gate, a control gate dielectric layer on the floating gate, and a control gate dielectric layer on the floating gate. The control gate on the control gate dielectric layer, the floating gate includes a first region and a second region located on the first region, the first region includes opposite first sidewalls and second sidewalls, so The first sidewall faces the adjacent storage gate structure, the second sidewall protrudes by a first dimension relative to the sidewall of the control gate, and the first sidewall protrudes by a second dimension relative to the sidewall of the control gate. Size, the second size is larger than the first size; forming an erasing gate in the opening to improve the erasing efficiency of the formed memory cell structure.

Description

Memory cell structure and method of forming the same

technical field

The invention relates to the technical field of semiconductor manufacturing, in particular to a memory cell structure and a forming method thereof.

Background technique

Flash Memory (Flash Memory) is widely used in System-on-Chip (SOC) as an electrically programmable and erasable non-volatile memory device. From a structural point of view, flash memory devices can be mainly divided into a stacked gate structure and a split gate structure. The traditional stacked gate flash memory structure has reliability problems such as programming/erasing interference, over-erasing, charge retention characteristics, and durability of erasing and writing. The application of the two-tube cell structure in the split-gate flash memory structure can effectively avoid the reliability problem of the stacked-gate flash memory.

The split-gate flash memory structure includes an erase gate, a control gate and a floating gate. Among them, the control gate is located above the floating gate and is separated by a dielectric layer; the erasing gate is located between two pairs of control gates and floating gates, which is a common erasing gate, and the two word lines are respectively located between the two pairs of control gates and floating gates. side, and are separated by a dielectric layer, and the oxide layer between the erasing gate and the floating gate is a tunneling dielectric layer. A part of the floating gate extends below the erase gate to form a wrap round structure. This unique structure can improve the erasing capability and efficiency. Because the split-gate structure of the above-mentioned structure has the advantages of high reliability, good manufacturing process compatibility, low start-up voltage, and prevention of over-erasing, the above-mentioned split-gate flash memory structure is widely used as an embedded flash memory.

However, the erasing capability and efficiency of the existing split-gate flash memory structure need to be further improved.

Contents of the invention

The technical problem solved by the present invention is to provide a storage unit structure and its forming method, so as to improve the performance of the formed storage unit structure.

In order to solve the above technical problems, the technical solution of the present invention provides a memory cell structure, including: a substrate; two memory gate structures separated from each other on the substrate, with an opening between the two memory structures, Each storage gate structure includes a floating gate, a control gate dielectric layer on the floating gate, and a control gate on the control gate dielectric layer, and the floating gate includes a first region and a second region on the first region. In the second region, the first region includes opposite first sidewalls and second sidewalls, the first sidewalls face adjacent storage gate structures, and the second sidewalls protrude relative to the control gate sidewalls The first dimension, the first sidewall protrudes relative to the control gate sidewall by a second dimension, the second dimension is larger than the first dimension; the erase gate located in the opening; respectively located in the the storage gate structure and the word lines on both sides of the erasing gate; The sidewall surface of the first sidewall is co-vertical to the first sidewall of the first region; The second side wall in between, the side wall surface of the second side wall is co-vertical with the second side wall of the first zone.

Optionally, a ratio of the second size to the size of the first region along the normal direction of the substrate ranges from 1.2:1 to 2:1.

Optionally, the second sidewall is also located between the second region, the sidewall of the control gate, and the sidewall of the erase gate; the first sidewall includes A second sidewall between the sidewall of the control gate and the sidewall of the erase gate, and a surface of the second sidewall located between the sidewall of the control gate and the sidewall of the erase gate in the second region the third side wall.

Optionally, the substrate has a source region and a drain region; the source region is located in the substrate below the erasing gate, and the drain region is located on the side of the word line away from the control gate structure within the substrate.

Optionally, the control gate dielectric layer includes a first dielectric layer, a second dielectric layer located on the surface of the first dielectric layer, and a third dielectric layer located on the surface of the second dielectric layer; the first dielectric layer The material of the second dielectric layer includes silicon oxide; the material of the second dielectric layer includes silicon nitride; the material of the third dielectric layer includes silicon oxide.

Correspondingly, the technical solution of the present invention also provides a method for forming a memory cell structure, including: providing a substrate; forming a floating gate material layer and a control gate dielectric material layer on the surface of the substrate and the control gate material layer on the control gate dielectric material layer; etching the control gate material layer, the control gate dielectric material layer and the floating gate material layer to form a transition floating gate layer, the transition floating gate Two transition storage structures on the layer and initial openings in the two transition storage structures, each of the transition storage structures includes a second region of the floating gate, a control gate dielectric layer on the second region, and the control The control gate on the gate dielectric layer, the transition storage structure has a third sidewall exposed by the sidewall of the initial opening, and a fourth sidewall opposite to the third sidewall; on the third sidewall A first side wall is formed on the surface; a second side wall is formed on the surface of the fourth side wall, and the size of the first side wall along the normal direction of the first side wall is larger than that of the second side wall along the The dimension in the normal direction of the second sidewall; using the first sidewall and the second sidewall as a mask, etch the transition floating gate layer until the surface of the substrate is exposed, so as to form the Two storage gate structures separated from each other on the substrate and an opening between the two storage structures, each storage gate structure includes a floating gate, a control gate dielectric layer on the floating gate, and a control gate dielectric layer on the control gate A control gate on a dielectric layer, the floating gate includes a first region and a second region located on the first region, the second region is formed with the transition floating gate layer, the first region includes an opposite A first sidewall and a second sidewall, the first sidewall faces the adjacent storage gate structure, the second sidewall protrudes by a first dimension relative to the control gate sidewall, and the first sidewall A second dimension protrudes relative to the sidewall of the control gate, and the second dimension is larger than the first dimension; an erasing gate in the opening is formed; words on both sides of the storage gate structure and the erasing gate are formed Wire.

Optionally, the second side wall is formed first, and then the first side wall is formed, the second side wall is also located on the third side wall, and the first side wall includes The second side wall of the wall and the third side wall located on the surface of the second side wall of the third side wall; the forming method of the first side wall includes: after forming the second side wall, The surface of the transition floating gate layer, the top and sidewall surfaces of the transition storage structure form a first sidewall material layer; the first sidewall material layer is etched back until the surface of the transition floating gate layer and the transition On the top surface of the storage structure, the third side wall is formed on the side wall surface of the transition storage structure; and the third side wall on the fourth side wall surface is removed.

Optionally, the method for removing the third sidewall on the surface of the fourth sidewall includes: forming a second mask layer on the surface of the substrate, the second mask layer exposing the fourth sidewall The top surface of the third sidewall; using the second mask layer as a mask, etching the third sidewall of the fourth sidewall.

Optionally, the method for forming the second sidewall includes: after forming the initial opening, forming a second sidewall material layer on the surface of the transition floating gate layer, the top of the transition memory structure, and the sidewall surface; The second spacer material layer is removed until the surface of the transition floating gate layer and the top surface of the transition memory structure are exposed.

Optionally, before forming the second sidewall material layer and after forming the initial opening, a dielectric material layer is formed on the surface of the transition floating gate layer, the top of the transition storage structure, and the sidewall surface; The dielectric material layer is etched to form a fourth side wall.

Optionally, after forming the third spacer and before forming the first spacer, further comprising: implanting ions into the substrate on both sides of the transition storage gate structure, so as to A critical voltage layer is formed within the substrate.

Optionally, the process parameters of the ion implantation process include: the dopant ions include P-type ions, the energy range is 30KeV to 90KeV, and the implantation dose ranges from 1E12atom/cm ² to 3E14atom/cm ² .

Optionally, before forming the floating gate material layer, a floating gate oxide material layer is further formed on the surface of the substrate.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following beneficial effects:

In a method for forming a memory cell structure provided by the technical solution of the present invention, the floating gate includes a first region and a second region located on the first region, and the first region includes opposite first side walls and The second sidewall, the first sidewall faces the adjacent storage gate structure, the second sidewall protrudes by a first dimension relative to the control gate sidewall, and the first sidewall protrudes relative to the control gate The sidewall protrudes by a second size, the second size is greater than the first size, so that the part of the floating gate that penetrates into the erasing gate increases, and the coupling area between the floating gate and the erasing gate increases, which is beneficial to the floating gate. The electrons tunnel into the erasing gate, improving the erasing efficiency of the formed memory cell structure.

Further, ions are implanted into the substrate on both sides of the transition storage gate structure to form a critical voltage layer in the substrate, the memory cell structure is also a MOS device, and the critical voltage layer is set on the device Between the source and drain of the device, the threshold voltage of the device can be adjusted through the critical voltage layer to control the on or off of the formed device.

In a memory cell structure provided by the technical solution of the present invention, the floating gate includes a first region and a second region located on the first region, and the first region includes opposite first side walls and second sides wall, the first sidewall faces the adjacent storage gate structure, the second sidewall protrudes relative to the control gate sidewall by a first dimension, and the first sidewall protrudes relative to the control gate sidewall The second size is greater than the first size, so that the part of the floating gate that penetrates into the erasing gate increases, and the coupling area between the floating gate and the erasing gate increases, which is conducive to the electron tunneling in the floating gate. The erasing gate is penetrated to improve the erasing efficiency of the formed memory cell structure.

Description of drawings

1 to 4 are structural schematic diagrams of a process of forming a memory cell structure;

FIG. 5 to FIG. 13 are structural schematic diagrams of each step of a method for forming a memory cell structure in an embodiment of the present invention.

Detailed ways

It should be noted that the "surface" and "upper" in this specification are used to describe the relative positional relationship in space, and are not limited to direct contact.

As mentioned in the background, the erasing capability and efficiency of the existing split-gate flash memory structure need to be further improved. Now combined with a storage unit structure for description and analysis.

1 to 4 are structural schematic diagrams of a process of forming a memory cell structure.

Please refer to FIG. 1 , a substrate 101 is provided; a floating gate oxide material layer 102 is formed on the substrate 101; a floating gate material layer 103 is formed on the surface of the floating gate oxide material layer 102; Several control gate structures are formed on the surface, and each control gate structure includes two mutually separated control gates. The control gates include a dielectric layer 104, a control gate layer 105 on the dielectric layer 104, and a In each of the control gate structures, each control gate includes a first sidewall adjacent to another control gate, and a second sidewall opposite to the first sidewall.

Please refer to FIG. 2, a first sidewall 107 is formed on the sidewall of each control gate; after forming the first sidewall 107, a second sidewall 108 is formed on the first sidewall of the control gate, and the second sidewall A wall 108 is located between the first side wall and the first side wall 107 .

Referring to FIG. 3, the floating gate material layer 103 is etched using the first spacer 107, the second sidewall 108 and the control gate as a mask until the floating gate oxide material layer 102 is exposed, forming The floating gate layer 109 ; forming a third sidewall 110 on the sidewall of the floating gate layer 109 .

Referring to FIG. 4, an erasing gate 111 is formed on the surface of the substrate 101 between adjacent control gate layers 105 in each of the control gate structures; Word lines 112 are formed on the surface of the bottom 101 .

The method described above is used to form a split-gate flash memory structure. In each of the control gate structures, the sidewall of the floating gate layer 109 adjacent to another floating gate layer 109 is formed by using the first sidewall 107 and the second sidewall 108 as a mask. The other side of the floating gate layer 109 has a longer floating gate cantilever. The floating gate cantilever refers to a portion of the floating gate layer 109 protruding relative to the control gate layer 105 in a direction parallel to the surface of the substrate 100 . As shown in FIG. 3 , the height a of the floating gate cantilever in the direction along the normal to the surface of the substrate 100 is 350 angstroms, and the length of the floating gate cantilever in the direction parallel to the surface of the substrate 100 is b is 260 angstroms. During the erasing operation of the formed split-gate flash memory structure, the larger the aspect ratio of the floating gate cantilever, that is, the more the part of the floating gate cantilever penetrates into the erasing gate 111, the easier it is for electrons in the floating gate layer 109 to pass through the floating gate. The cantilever tunnels into the erase gate for higher erase efficiency.

The length of the floating gate cantilever formed by the above method depends on the thickness of the first sidewall 107 and the thickness of the second sidewall 108, and the height of the floating gate cantilever depends on the method of the floating gate layer 109 on the surface of the substrate 100. The size of the line and the improvement of the floating gate cantilever structure are limited, which is not conducive to improving the erasing capability and efficiency of the formed split-gate flash memory structure.

In order to solve the above problems, in a method for forming a memory cell structure provided by the present invention, the floating gate includes a first region and a second region located on the first region, and the first region includes an opposite first sidewalls and second sidewalls, the first sidewall faces the adjacent storage gate structure, the second sidewall protrudes by a first dimension relative to the control gate sidewall, and the first sidewall protrudes relative to the storage gate structure The sidewall of the control gate protrudes by a second size, and the second size is greater than the first size, so that the part of the floating gate that penetrates into the erasing gate increases, and the increase in the coupling area between the floating gate and the erasing gate is beneficial to The electrons in the floating gate tunnel into the erase gate, improving the erase efficiency of the formed memory cell structure.

In order to make the above objects, features and beneficial effects of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

FIG. 5 to FIG. 13 are structural schematic diagrams of each step of a method for forming a memory cell structure in an embodiment of the present invention.

Referring to FIG. 5 , a substrate 200 is provided.

In this embodiment, the material of the substrate 200 includes silicon. In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, multiple semiconductor materials composed of III-V group elements, silicon-on-insulator (SOI) or germanium-on-insulator (GOI). Wherein, the multiple semiconductor materials composed of III-V group elements include InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

Subsequently, two storage gate structures separated from each other on the substrate and an opening between the two storage structures are formed, each storage gate structure includes a floating gate and a control gate located on the floating gate, the floating The gate includes a first region and a second region on the first region, the first region includes opposite first sidewalls and second sidewalls, the first sidewall faces an adjacent storage gate structure, so The second sidewall protrudes relative to the sidewall of the control gate by a first dimension, the first sidewall protrudes relative to the sidewall of the control gate by a second dimension, and the second dimension is greater than the first dimension . Please refer to FIG. 5 to FIG. 11 for the formation method of the storage gate structure and the opening.

Please continue to refer to FIG. 5 , a floating gate material layer 201 , a control gate dielectric material layer 205 on the floating gate material layer 201 and a control gate material layer 202 on the floating gate material layer 201 are formed on the surface of the substrate 200 .

The floating gate material layer 201 is used for subsequently forming a floating gate; the control gate material layer 202 is used for subsequently forming a control gate; the control gate dielectric material layer 205 is used for subsequently forming a control gate dielectric layer.

In this embodiment, before forming the floating gate material layer 201 , a floating gate oxide material layer 204 is further formed on the surface of the substrate 200 .

In this embodiment, the control gate dielectric material layer 205 includes a first dielectric material layer (not shown in the figure), a second dielectric material layer (not shown in the figure) located on the surface of the first dielectric material layer, And a third dielectric material layer (not shown in the figure) located on the surface of the second dielectric material layer; the material of the first dielectric material layer includes silicon oxide; the material of the second dielectric material layer includes silicon nitride ; The material of the third dielectric material layer includes silicon oxide.

Referring to FIG. 6, the control gate material layer 202, the control gate dielectric material layer 205, and the floating gate material layer 201 are etched to form a transition floating gate layer 300, and the transition floating gate layer 300. Two transition storage structures and initial openings 207 in the two transition storage structures, each transition storage structure includes the second region II of the floating gate, the control gate dielectric layer 210 on the second region II, and the control gate For the control gate 206 on the dielectric layer 210 , the transition storage structure has a third sidewall 208 exposed from the sidewall of the initial opening 207 , and a fourth sidewall 209 opposite to the third sidewall 208 .

In this embodiment, the method for etching the control gate material layer 202, the control gate dielectric material layer 205 and the floating gate material layer 201 further includes: forming a first mask on the surface of part of the control gate material layer 202 film layer 203 , using the first mask layer 203 as a mask to etch the control gate material layer 202 , the control gate dielectric material layer 205 and the floating gate material layer 201 .

In this embodiment, the method for forming the first mask layer 203 includes: forming a first mask material layer (not shown in the figure) on the surface of part of the control gate material layer 202; A patterned photoresist layer (not shown in the figure) is formed on the surface of the layer; the first mask layer is etched using the photoresist layer as a mask to form the first mask layer 203 .

The transition floating gate layer 300 is used to subsequently form the first region of the floating gate.

Subsequently, a first side wall is formed on the surface of the third side wall 208; a second side wall is formed on the surface of the fourth side wall 209, and the first side wall is formed along the normal direction of the first side wall The size is larger than the size of the second side wall along the normal direction of the second side wall.

In this embodiment, the second side wall is formed first, and then the first side wall is formed, and the second side wall is also located on the third side wall 208, and the first side wall includes The second side wall of the three side walls 208 and the third side wall located on the surface of the second side wall of the third side wall 208 . Specifically, please refer to FIG. 7 to FIG. 10 for the forming method of the first side wall and the second side wall. More specifically, please refer to FIG. 7 for the formation method of the second side wall.

Please refer to FIG. 7, after the initial opening 207 is formed, a second sidewall material layer (not shown in the figure) is formed on the surface of the transition floating gate layer 300, the top and sidewall surfaces of the transition storage structure; The second sidewall material layer is until the surface of the transition floating gate layer 300 and the top surface of the transition memory structure are exposed.

Specifically, the second spacer material layer is also located on the surface of the first mask layer 203; the second sidewall material layer is etched back until the surface of the transition floating gate layer 300 and the first mask are exposed. layer 203 top surface to form the second sidewall 211 .

In this embodiment, before forming the second sidewall material layer and after forming the initial opening 207, a dielectric material is formed on the surface of the transition floating gate layer 300, the top and sidewall surfaces of the transition storage structure Layer 212. More specifically, the dielectric material layer 212 is also located on the surface of the first mask layer 203; the second spacer material layer is etched back until the surface of the transition floating gate layer 300 and the transition memory structure are exposed. A layer of dielectric material 212 on the top surface to form the second side wall 211 .

The material of the second sidewall material layer includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride . In this embodiment, the material of the second sidewall material layer is silicon nitride.

The dielectric material layer 212 is used to form the fourth sidewall.

Please refer to FIG. 8, after forming the second sidewall 211, a first sidewall material layer (not shown in the figure) is formed on the surface of the transition floating gate layer 300, the top of the transition storage structure and the sidewall surface; The first sidewall material layer is etched back until the surface of the transition floating gate layer 300 and the top surface of the transition storage structure are exposed, and the third spacer 213 is formed on the sidewall surface of the transition storage structure.

Specifically, the first sidewall material layer is also located on the surface of the first mask layer 203 . More specifically, the first side wall material layer is also located on the surface of the dielectric material layer 212 .

Specifically, the first sidewall material layer is etched back until the sidewall surface of the transition storage structure and the top surface of the first mask layer 203 are exposed. More specifically, etching back the first spacer material layer until the dielectric material layer 212 on the transition floating gate layer 300 and the dielectric material layer 212 on the top of the first mask layer 203 are exposed . The material of the first sidewall material layer includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride . In this embodiment, the material of the first sidewall material layer is silicon oxide.

The second side wall 211 located on the third side wall 208 and the third side wall 213 located on the surface of the second side wall 211 of the third side wall 208 are used to subsequently form the first side wall.

Please refer to FIG. 9 , after forming the third sidewall 213 and before forming the first sidewall, it also includes: implanting ions into the substrate 200 on both sides of the transition storage gate structure, so as to A threshold voltage layer 214 is formed in the substrate 200 .

In this embodiment, the method for forming the threshold voltage layer 214 further includes: forming a third mask layer (not shown in the figure) on the surface of the substrate 200, the top surface of the transition memory structure and the opening 207. ), the third mask layer exposes the substrate 200 on both sides of the transition storage gate structure; using the third mask layer as a mask, ions are implanted in the substrate 200 to form the The adjacent voltage layer 214 is described above.

Specifically, the third mask layer exposes the transition floating gate layer 300 on both sides of the transition storage gate structure. More specifically, the third mask layer exposes the surface of the dielectric material layer 212 on the transition floating gate layer 300 on both sides of the transition storage gate structure.

The dielectric material layer 212 is conducive to improving the uniformity of ion implantation and improving the performance of the threshold voltage layer 214 .

The process parameters of the ion implantation process include: the dopant ions include P-type ions, the energy range is 30KeV to 90KeV, and the implantation dose ranges from 1E12atom/cm ² to 3E14atom/cm ² .

The memory cell structure is also a MOS device, the critical voltage layer is arranged between the source and drain of the device, and the threshold voltage of the device can be adjusted through the critical voltage layer to control the on or off of the formed device.

Referring to FIG. 10 , the third sidewall 213 on the surface of the fourth sidewall 209 is removed.

In this embodiment, the method for removing the third sidewall 213 on the surface of the fourth sidewall 209 includes: forming a second mask layer (not shown in the figure) on the surface of the substrate 200, the first The second mask layer exposes the top surface of the third sidewall 213 of the fourth sidewall 209; using the second mask layer as a mask, etch the third side of the fourth sidewall 209 Wall 213.

The first side wall 215 includes a second side wall 211 located on the third side wall 208 and a third side wall 213 located on a surface of the second side wall 211 of the third side wall 208 . Subsequently, the first spacer 215 is used as a mask to form the first region of the floating gate. The first sidewall 215 can be formed by using multiple sidewall processes to increase the size of the sidewall of the subsequent first region protruding relative to the sidewall of the control gate.

In this embodiment, the dielectric material layer 212 is etched to form a fourth spacer 216 .

Referring to FIG. 11 , using the first sidewall 215 and the second sidewall 211 as a mask, the transition floating gate layer 300 is etched until the surface of the substrate 200 is exposed to form the liner. Two storage gate structures separated from each other on the bottom 200 and an opening 217 between the two storage structures, each storage gate structure includes a floating gate, a control gate dielectric layer 210 located on the floating gate, and a control gate dielectric layer 210 located on the control gate. The control gate 206 on the gate dielectric layer 210, the floating gate includes a first region I and a second region II located on the first region I, the second region II is formed with the transition floating gate layer 300 , the first region I includes opposite first sidewall a and second sidewall b, the first sidewall a faces the adjacent storage gate structure, and the second sidewall b is opposite to the side of the control gate A wall protrudes by a first dimension m, said first sidewall a protrudes relative to said control gate sidewall by a second dimension n, said second dimension n being greater than said first dimension m.

The second dimension n is greater than the first dimension m, so the formed memory cell structure increases the part of the floating gate that penetrates into the erasing gate, and increases the coupling area between the floating gate and the erasing gate, which is beneficial to the floating gate. The electrons in the tunnel tunnel into the erasing gate, improving the erasing efficiency of the formed memory cell structure.

The ratio of the second dimension n to the dimension of the first region I along the normal direction of the substrate ranges from 1.2:1 to 2:1. Specifically, in this embodiment, the size range of the first region I along the normal direction of the substrate 200 is 150 angstroms to 300 angstroms; the second size n, that is, the first side wall a is opposite to The length of the protruding portion on the sidewall of the control gate 206 ranges from 280 angstroms to 360 angstroms.

Referring to FIG. 12 , an erase gate 218 is formed in the opening 217 .

In this embodiment, before the erasing gate 218 is formed, a source region 219 is formed in the substrate at the bottom of the opening 217 .

In this embodiment, the method for forming the source region 219 includes: forming a fourth mask layer on the surface of the substrate 200, the fourth mask layer is also located on the top and sidewalls of the storage gate structure, and the The fourth mask layer exposes the bottom surface of the opening 217; using the fourth mask layer as a mask, implant dopant ions at the bottom of the opening 217 to form the source region 219; remove the fourth mask layer mask layer.

In this embodiment, the method for forming the erasing gate 218 includes: forming an erasing gate material layer on the opening 217, the surface of the storage structure, and the surface of the substrate 200; forming an erasing gate material layer on the surface of the erasing gate material layer Forming a fifth mask layer, the fifth mask layer exposes the erasing gate material layer on the surface of the opening 217; using the fifth mask layer as a mask, etching the erasing gate material layer until The top surface of the memory structure and the surface of the substrate 200 are exposed.

In this embodiment, after the source region 219 is formed, an erasing gate material layer (not shown in the figure) is formed in the opening 217 and on the surface of the fourth mask layer, and the erasing gate material layer is etched back. layer until the fourth mask layer is exposed.

In other embodiments, the formation methods of the erasing gate 218 and the source region 219 are not limited thereto. In another embodiment, the source region may also be pre-formed in the substrate, and then two storage gate structures and an opening between the two storage structures separated from each other are formed on the substrate, so that The opening exposes the source region.

Referring to FIG. 13 , word lines 220 on both sides of the storage gate structure and the erasing gate 218 are formed.

In this embodiment, after the word line 220 is formed, the drain region 221 is further formed in the substrate 200 on both sides of the storage gate structure, the erasing gate 218 and the word line 220 .

In this embodiment, the method for forming the drain region 221 includes: forming a sixth mask layer on the surface of the substrate 200, the storage gate structure, the erasing gate 218, and the word line 220, so that The sixth mask layer exposes the storage gate structure, the erasing gate 218 and the substrate 200 on both sides of the word line 220; doping ions are implanted in the substrate 200 to form the drain region 221 .

Correspondingly, an embodiment of the present invention also provides a memory cell structure formed by the above method, please continue to refer to FIG. 13 , including: a substrate 200; two memory gate structures separated from each other on the substrate 200 , there is an opening 217 between the two storage structures (as shown in FIG. 11 ), and each storage gate structure includes a floating gate, a control gate dielectric layer on the floating gate, and a control gate dielectric layer on the control gate dielectric layer. Gate 206, the floating gate includes a first region I and a second region II located on the first region I, the first region I includes opposite first sidewalls a and second sidewalls b, the The first sidewall a faces the adjacent storage gate structure, the second sidewall b protrudes by a first dimension m relative to the sidewall of the control gate 206 , and the first sidewall a protrudes relative to the sidewall of the control gate 206 The wall protrudes by a second dimension n, and the second dimension n is greater than the first dimension m; the erasing gate 217 located in the opening 217; the words located on both sides of the storage gate structure and the erasing gate 217 respectively Line 220; the first sidewall 215 located between the second region II, the control gate 206, the sidewall of the control gate dielectric layer 210 and the sidewall of the erase gate 217, the first sidewall 215 sidewall surface is co-vertical to the first sidewall 215 of the first region I; located in the second region II, the control gate 206, the sidewall of the control gate dielectric layer 210 and the word line 220 The second side wall 211 between the side walls, the side wall surface of the second side wall 211 is co-vertical with the second side wall b of the first zone I.

The structure of the memory cell increases the portion of the floating gate deep into the erasing gate, and the increase in the coupling area between the floating gate and the erasing gate is conducive to the tunneling of electrons in the floating gate into the erasing gate, improving the formed memory cell. The erasure efficiency of the structure.

The ratio of the second dimension n to the dimension of the first region I along the normal direction of the substrate ranges from 1.2:1 to 2:1. Specifically, in this embodiment, the size range of the first region I along the normal direction of the substrate 200 is 150 angstroms to 300 angstroms; The length of the protrusion ranges from 280 Angstroms to 360 Angstroms.

In this embodiment, the second sidewall 211 is also located between the second region II, the sidewall of the control gate 206 and the sidewall of the erase gate 218; the first sidewall 215 includes The second region II, the second sidewall 211 between the sidewall of the control gate 206 and the sidewall of the erase gate 218 and the second region II, the sidewall of the control gate 206 and the eraser The third sidewall 213 on the surface of the second sidewall 211 between the sidewalls of the grid 218 is removed (as shown in FIG. 9 ).

The substrate 200 has a source region 219 and a drain region 221; the source region 219 is located in the substrate 200 below the erasing gate 218, and the drain region 221 is located in the storage gate structure, the erasing gate 218 and in the substrate 200 on both sides of the word line 220 .

The control gate dielectric layer 210 includes a first dielectric layer (not shown in the figure), a second dielectric layer (not shown in the figure) located on the surface of the first dielectric layer, and a second dielectric layer located on the surface of the second dielectric layer The third dielectric layer (not shown in the figure); the material of the first dielectric layer includes silicon oxide; the material of the second dielectric layer includes silicon nitride; the material of the third dielectric layer includes silicon oxide.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (13)

1. A memory cell structure, comprising:

a substrate;

two mutually-separated storage gate structures positioned on the substrate, wherein an opening is formed between the two storage structures, each storage gate structure comprises a floating gate, a control gate dielectric layer positioned on the floating gate and a control gate positioned on the control gate dielectric layer, each floating gate comprises a first area and a second area positioned on the first area, each first area comprises a first side wall and a second side wall which are opposite, each first side wall faces to the adjacent storage gate structure, each second side wall protrudes relative to the corresponding control gate side wall by a first size, each first side wall protrudes relative to the corresponding control gate side wall by a second size, and each second size is larger than the corresponding first size;

an erase gate positioned within the opening;

word lines respectively positioned at two sides of the storage gate structure and the erasing gate;

the first side wall is positioned among the second region, the control gate, the side wall of the control gate dielectric layer and the side wall of the erasing gate, and the surface of the side wall of the first side wall and the first side wall of the first region are in a common vertical plane;

and the second side wall is positioned among the second area, the control gate, the side wall of the control gate dielectric layer and the side wall of the word line, and the surface of the side wall of the second side wall is in a common vertical plane with the second side wall of the first area.

2. The memory cell structure of claim 1, wherein a ratio of the second dimension to the first region in a dimension along the substrate normal direction is in a range of 1.2.

3. The memory cell structure of claim 1, wherein the second sidewall spacers are further located between the second region, the control gate sidewall, and the erase gate sidewall; the first side wall comprises a second side wall located between the second region, the control grid side wall and the erasing grid side wall and a third side wall located on the surface of the second side wall between the second region, the control grid side wall and the erasing grid side wall.

4. The memory cell structure of claim 1, wherein the substrate has a source region and a drain region therein; the source region is positioned in the substrate below the erasing gate, and the drain region is positioned in the substrate of the word line at one side far away from the control gate structure.

5. The memory cell structure of claim 1, wherein the control gate dielectric layer comprises a first dielectric layer, a second dielectric layer on a surface of the first dielectric layer, and a third dielectric layer on a surface of the second dielectric layer; the material of the dielectric layer comprises silicon oxide; the material of the second dielectric layer comprises silicon nitride; the material of the third dielectric layer comprises silicon oxide.

6. A method for forming a memory cell structure, comprising:

providing a substrate;

forming a floating gate material layer, a control gate dielectric material layer on the floating gate material layer and a control gate material layer on the control gate dielectric material layer on the surface of the substrate;

etching the control gate material layer, the control gate dielectric material layer and the floating gate material layer to form a transition floating gate layer, two transition storage structures on the transition floating gate layer and initial openings in the two transition storage structures, wherein each transition storage structure comprises a second region of a floating gate, a control gate dielectric layer on the second region and a control gate on the control gate dielectric layer, and the transition storage structure is provided with a third side wall exposed from the side wall of the initial opening and a fourth side wall opposite to the third side wall;

forming a first side wall on the surface of the third side wall;

forming a second side wall on the surface of the fourth side wall, wherein the size of the first side wall in the direction along the normal of the first side wall is larger than that of the second side wall in the direction along the normal of the second side wall;

etching the transitional floating gate layer by taking the first side wall and the second side wall as masks until the surface of the substrate is exposed to form two storage gate structures which are separated from each other on the substrate and an opening between the two storage structures, wherein each storage gate structure comprises a floating gate, a control gate dielectric layer positioned on the floating gate and a control gate positioned on the control gate dielectric layer, the floating gate comprises a first area and a second area positioned on the first area, the transitional floating gate layer forms the second area, the first area comprises a first side wall and a second side wall which are opposite, the first side wall faces to the adjacent storage gate structure, the second side wall protrudes by a first size relative to the control gate side wall, the first side wall protrudes by a second size relative to the control gate side wall, and the second size is larger than the first size;

forming an erasing gate in the opening;

and forming word lines on two sides of the storage gate structure and the erasing gate.

7. The method according to claim 6, wherein the second sidewall is formed first, and then the first sidewall is formed, wherein the second sidewall is further located on the third sidewall, and the first sidewall comprises the second sidewall located on the third sidewall and a third sidewall located on a surface of the second sidewall of the third sidewall; the method for forming the first side wall comprises the following steps: after the second side wall is formed, forming a first side wall material layer on the surface of the transition floating gate layer, the top of the transition storage structure and the surface of the side wall; etching back the first side wall material layer until the surface of the transition floating gate layer and the top surface of the transition storage structure are exposed, and forming a third side wall on the surface of the side wall of the transition storage structure; and removing the third side wall on the surface of the fourth side wall.

8. The method of forming a memory cell structure of claim 7, wherein the method of removing the third sidewall of the fourth sidewall surface comprises: forming a second mask layer on the surface of the substrate, wherein the second mask layer exposes the top surface of the third side wall of the fourth side wall; and etching the third side wall of the fourth side wall by taking the second mask layer as a mask.

9. The method for forming the memory cell structure according to claim 8, wherein the method for forming the second sidewall spacer comprises: after the initial opening is formed, forming a second side wall material layer on the surface of the transition floating gate layer, the top of the transition storage structure and the surface of the side wall; and etching back the second side wall material layer until the surface of the transition floating gate layer and the top surface of the transition storage structure are exposed.

10. The method of claim 9, wherein a dielectric material layer is formed on the surface of the transition floating gate layer, the top of the transition memory structure and the sidewall surface before forming the second sidewall material layer and after forming the initial opening; and etching the dielectric material layer to form a fourth side wall.

11. The method for forming a memory cell structure according to claim 9, further comprising, after forming the third sidewall and before forming the first sidewall: and implanting ions into the substrate on two sides of the transitional storage gate structure so as to form a critical voltage layer in the substrate.

12. The method of claim 11, wherein the ion implantation process comprises the following process parameters: the dopant ions include P-type ions with energy ranging from 30KeV to 90KeV and implantation dosage ranging from 1E12atom/cm ² To 3E14atom/cm ² 。

13. The method for forming a memory cell structure according to claim 6, wherein a floating gate oxide material layer is further formed on the surface of the substrate before the floating gate material layer is formed.

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