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CN115728623A - Loss de-embedding method and system for high-speed integrated circuit test loading plate calibration device - Google Patents

Loss de-embedding method and system for high-speed integrated circuit test loading plate calibration device Download PDF

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CN115728623A
CN115728623A CN202211434456.XA CN202211434456A CN115728623A CN 115728623 A CN115728623 A CN 115728623A CN 202211434456 A CN202211434456 A CN 202211434456A CN 115728623 A CN115728623 A CN 115728623A
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calibration
integrated circuit
calibration instrument
board
loss
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CN115728623B (en
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孙崇钧
刘倩
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709th Research Institute of CSSC
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Abstract

The invention provides a loss de-embedding method and a system of a high-speed integrated circuit test loading plate calibration device, belonging to the technical field of microelectronic test and measurement, wherein the loss de-embedding system comprises the following steps: the auxiliary verification board and the data processing module; two interfaces are reserved on the upper surface and the lower surface of the auxiliary verification plate, one interface is matched with the signal input device, the other interface is matched with the bonding pad interface matched with the microwave probe, the auxiliary verification plate forms a measurement loop for removing the loaded plate, the data processing module is used for comparing signals of a first calibration instrument and a second calibration instrument before and after the auxiliary verification plate is connected to the high-speed integrated circuit test loading plate calibration device, and the de-embedding of time domain parameters in the calibration process of the high-speed integrated circuit test loading plate is calculated. The invention can accurately calculate the loss introduced by the integrated circuit interface adapter.

Description

高速集成电路测试加载板校准装置的损耗去嵌方法及系统Loss de-embedding method and system for high-speed integrated circuit test loading board calibration device

技术领域technical field

本发明属于微电子测试与计量技术领域,更具体地,涉及一种高速集成电路测试加载板校准装置的损耗去嵌方法及系统。The invention belongs to the technical field of microelectronic testing and measurement, and more specifically relates to a loss de-embedding method and system for a calibration device of a high-speed integrated circuit test loading board.

背景技术Background technique

对于高速集成电路测试加载板需要使用专用的标准夹具才能实现校准,这是因为被校准的加载板的接口通常是非SMA或BNC等通用接口,而测试仪器如示波器(OSC)、矢网分析仪(VNA)等仪器的接口通常都是SMA或BNC等标准类型的,因此被校准加载板和校准仪器之间的连接需要辅助夹具,对于高速信号,校准夹具的使用一定会给被测件的校准结果带来影响,需要消除或尽量减小标准夹具对校准结果的影响。For the high-speed integrated circuit test load board, it is necessary to use a special standard fixture to achieve calibration. This is because the interface of the calibrated load board is usually a general-purpose interface such as non-SMA or BNC, and testing instruments such as oscilloscope (OSC), vector network analyzer ( The interfaces of instruments such as VNA) are usually standard types such as SMA or BNC. Therefore, the connection between the calibrated loading board and the calibration instrument requires an auxiliary fixture. For high-speed signals, the use of the calibration fixture will definitely give the calibration result of the DUT. It is necessary to eliminate or minimize the influence of the standard fixture on the calibration results.

发明内容Contents of the invention

针对现有技术的缺陷,本发明的目的在于提供一种高速集成电路测试加载板校准装置的损耗去嵌方法及系统,旨在解决现有的对高速集成电路测试加载板采用的标准夹具将给被测件的校准结果带来一定的损耗,导致对加载板校准精度较差的问题。Aiming at the defects of the prior art, the object of the present invention is to provide a loss de-embedding method and system of a high-speed integrated circuit test load board calibration device, aiming to solve the problem that the existing standard fixtures used for high-speed integrated circuit test load boards will give The calibration result of the DUT brings a certain loss, which leads to the problem of poor calibration accuracy of the loading board.

为实现上述目的,一方面,本发明提供了一种高速集成电路测试加载板校准装置的损耗去嵌系统,包括:辅助验证板和数据处理模块;To achieve the above object, on the one hand, the present invention provides a loss de-embedding system for a high-speed integrated circuit test loading board calibration device, including: an auxiliary verification board and a data processing module;

其中,高速集成电路测试加载板校准装置包括第一校准仪表、信号输入装置、集成电路接口适配器、微波探针、射频线缆和第二校准仪表;集成电路接口适配器、微波探针、射频线缆和第二校准仪表顺次连接;第一校准仪表的输出端与信号输入装置相连;信号输入装置的输出端与加载板相连;集成电路接口适配器的输入端与加载板相连;Among them, the high-speed integrated circuit test loading board calibration device includes a first calibration instrument, a signal input device, an integrated circuit interface adapter, a microwave probe, a radio frequency cable and a second calibration instrument; an integrated circuit interface adapter, a microwave probe, a radio frequency cable Connect with the second calibration instrument in sequence; the output end of the first calibration instrument is connected with the signal input device; the output end of the signal input device is connected with the loading board; the input end of the integrated circuit interface adapter is connected with the loading board;

信号输入装置用于将高速数字信号或快沿信号传递至加载板上;集成电路适配器用于探测加载板上各焊盘上的输出信号;微波探针用于移动至目标焊盘位置处,将目标焊盘上对应的输出信号通过射频线缆传输至第二校准仪表上;The signal input device is used to transmit high-speed digital signals or fast edge signals to the loading board; the integrated circuit adapter is used to detect the output signals on each pad on the loading board; the microwave probe is used to move to the target pad position, and the The corresponding output signal on the target pad is transmitted to the second calibration instrument through the radio frequency cable;

辅助验证板上下表面预留两种接口,一面为与信号输入装置适配的接口,一面为与微波探针适配的焊盘接口;数据处理模块与第一校准仪表和第二校准仪表相连;Two interfaces are reserved on the upper and lower surfaces of the auxiliary verification board, one is an interface adapted to the signal input device, and the other is a pad interface adapted to the microwave probe; the data processing module is connected to the first calibration instrument and the second calibration instrument;

第一校准仪表用于提供高速数字信号或者快沿信号;第二校准仪表用于获取加载板上的输出信号;辅助验证板用于形成除被较加载板的测量回路,数据处理模块用于对辅助验证板接入高速集成电路测试加载板校准装置前后第一校准仪表和第二校准仪表的信号进行对比,计算高速集成电路测试加载板校准过程中时域参数的去嵌。The first calibration instrument is used to provide high-speed digital signals or fast edge signals; the second calibration instrument is used to obtain the output signal on the loading board; the auxiliary verification board is used to form a measurement circuit except the loaded board, and the data processing module is used for The signals of the first calibration instrument and the second calibration instrument are compared before and after the auxiliary verification board is connected to the calibration device of the high-speed integrated circuit test load board, and the de-embedding of the time domain parameters during the calibration process of the high-speed integrated circuit test load board is calculated.

进一步优选地,辅助验证板为PCB板。Further preferably, the auxiliary verification board is a PCB board.

进一步优选地,集成电路接口适配器包括正面探针位阵列和背面探针位阵列;正面探针位阵列和背面探针位阵列分别固定至加载板的两侧;正面探针位阵列和背面探针位阵列的形状为扇形。Further preferably, the integrated circuit interface adapter includes a front probe position array and a back probe position array; the front probe position array and the back probe position array are respectively fixed to both sides of the loading board; the front probe position array and the back probe position array The shape of the bit array is a fan.

进一步优选地,微波探针为GSG-DX微波探针,带宽为50G。Further preferably, the microwave probe is a GSG-DX microwave probe with a bandwidth of 50G.

进一步优选地,第一校准仪表为高速采样示波器TDR模块;第二校准仪表为示波器。Further preferably, the first calibration instrument is a high-speed sampling oscilloscope TDR module; the second calibration instrument is an oscilloscope.

进一步优选地,射频线缆为带宽18G的SMA-SMA线缆。Further preferably, the radio frequency cable is an SMA-SMA cable with a bandwidth of 18G.

另一方面,本发明提供了一种高速集成电路测试加载板校准装置的损耗去嵌方法,包括以下步骤:In another aspect, the present invention provides a loss de-embedding method for a high-speed integrated circuit test loading board calibration device, comprising the following steps:

将辅助验证板接入信号输入装置与微波探针之间,采用第一校准仪表输入高速数字信号,采用第二校准仪表采集加载板输出波形形成的眼图;Connect the auxiliary verification board between the signal input device and the microwave probe, use the first calibration instrument to input high-speed digital signals, and use the second calibration instrument to collect the eye diagram formed by the output waveform of the loading board;

根据眼图高度与高速数字信号幅度之差计算眼高的补偿值;Calculate the compensation value of the eye height according to the difference between the height of the eye diagram and the amplitude of the high-speed digital signal;

根据眼图宽度与高速数字信号脉宽之差计算眼宽的补偿值;Calculate the compensation value of the eye width according to the difference between the eye diagram width and the pulse width of the high-speed digital signal;

将眼高的补偿值和眼宽的补偿值,结合眼图上升时间,计算校准加载板在最高传输速率下的眼图面积。Combine the eye height compensation value and eye width compensation value with the eye diagram rise time to calculate the eye diagram area of the calibration loading board at the highest transmission rate.

另一方面,本发明提供了一种高速集成电路测试加载板校准装置的损耗去嵌方法,包括以下步骤:In another aspect, the present invention provides a loss de-embedding method for a high-speed integrated circuit test loading board calibration device, comprising the following steps:

在辅助验证板接入信号输入装置与微波探针之间前后,分别采用第一校准仪表输入高速数字信号,采用第二校准仪表采集输出波形幅值;Before and after the auxiliary verification board is connected to the signal input device and the microwave probe, the first calibration instrument is used to input the high-speed digital signal, and the second calibration instrument is used to collect the output waveform amplitude;

结合在辅助验证板接入信号输入装置与微波探针之间前后第一校准仪表所发送信号的峰峰值与第二校准仪表采集输出波形的峰峰值,计算幅值的补偿值与补偿后的加载板幅值衰减值。Combining the peak-to-peak value of the signal sent by the first calibration instrument and the peak-to-peak value of the output waveform collected by the second calibration instrument before and after the access signal input device of the auxiliary verification board and the microwave probe, calculate the compensation value of the amplitude and the load after compensation Plate amplitude attenuation value.

另一方面,本发明提供了一种高速集成电路测试加载板校准装置的损耗去嵌方法,包括以下步骤:In another aspect, the present invention provides a loss de-embedding method for a high-speed integrated circuit test loading board calibration device, comprising the following steps:

将辅助验证板接入信号输入装置与微波探针之间,采用第一校准仪表发送快沿信号,采用第二校准仪表采集输出波形并测量输出信号的上升时间;Connect the auxiliary verification board between the signal input device and the microwave probe, use the first calibration instrument to send the fast edge signal, and use the second calibration instrument to collect the output waveform and measure the rise time of the output signal;

结合微波探针的上升时间与射频线缆的上升时间,计算高速集成电路测试加载板校准装置中除微波探针和射频线缆外其他器件的上升时间的补偿值;Combining the rise time of the microwave probe and the rise time of the RF cable, calculate the compensation value of the rise time of other components in the high-speed integrated circuit test loading board calibration device except the microwave probe and the RF cable;

同时结合辅助验证板未接入信号输入装置与微波探针之间时第二校准仪表采集输出信号的上升时间,计算补偿后的加载板的上升时间。At the same time, when the auxiliary verification board is not connected between the signal input device and the microwave probe, the rise time of the output signal collected by the second calibration instrument is used to calculate the rise time of the loaded board after compensation.

总体而言,通过本发明所构思的以上技术方案与现有技术相比,具有以下Generally speaking, compared with the prior art, the above technical solution conceived by the present invention has the following

有益效果:Beneficial effect:

本发明提供了一种高速集成电路测试加载板校准装置的损耗去嵌系统及方法,设计了辅助验证板来完成信号输入装置与微波探针之间的理想对接,目前,针对时域参数主要使用的是基于夹具的去嵌方法,即将夹具带入的损耗量带入校准结果中,针对各型高速集成电路测试加载板校准过程的差异性和不确定性,现有的方法无法对测量回路中的引脚插座、无源组件、传输线等组件的损耗量一一评估,本发明采用辅助验证板形成除被较加载板的测量回路,数据处理模块只需对辅助验证板接入高速集成电路测试加载板校准装置前后第一校准仪表和第二校准仪表的信号进行对比,即可计算高速集成电路测试加载板校准过程中时域参数的去嵌;计算简单且可以准确计算集成电路接口适配器引入的损耗量,对高速集成电路测试加载板校准装置在集成电路测试系统中的应用和推广有一定的参考价值,确保高速集成电路测试过程准确可靠。The invention provides a loss de-embedding system and method for a high-speed integrated circuit test loading board calibration device, and an auxiliary verification board is designed to complete the ideal docking between the signal input device and the microwave probe. At present, the time domain parameters are mainly used The most important is the de-embedding method based on the fixture, that is, the loss brought by the fixture is brought into the calibration result. In view of the differences and uncertainties in the calibration process of various types of high-speed integrated circuit test load boards, the existing methods cannot accurately measure the The loss of pin sockets, passive components, transmission lines and other components is evaluated one by one. The present invention uses the auxiliary verification board to form a measurement circuit except for the loaded board. The data processing module only needs to connect the auxiliary verification board to the high-speed integrated circuit test By comparing the signals of the first calibration instrument and the second calibration instrument before and after the loading board calibration device, the de-embedding of the time domain parameters in the calibration process of the high-speed integrated circuit test loading board can be calculated; the calculation is simple and can accurately calculate the input of the integrated circuit interface adapter The amount of loss has a certain reference value for the application and promotion of the high-speed integrated circuit test loading board calibration device in the integrated circuit test system, ensuring the accuracy and reliability of the high-speed integrated circuit test process.

附图说明Description of drawings

图1是本发明实施例提供的高速集成电路测试加载板校准装置损耗去嵌系统示意图;FIG. 1 is a schematic diagram of a loss de-embedding system for a high-speed integrated circuit test load board calibration device provided by an embodiment of the present invention;

图2是本发明实施例提供的高速集成电路测试加载板校准装置损耗去嵌方法中的辅助验证板布线图;FIG. 2 is a wiring diagram of an auxiliary verification board in the loss de-embedding method of the high-speed integrated circuit test load board calibration device provided by the embodiment of the present invention;

标记说明:Mark Description:

1-加载板校准装置;10-第一校准仪表;11-信号输入装置;12-集成电路接口适配器;13-微波探针;14-射频线缆;15-第二校准仪表;16-辅助验证板;17-数据处理模块。1-loading board calibration device; 10-first calibration instrument; 11-signal input device; 12-integrated circuit interface adapter; 13-microwave probe; 14-radio frequency cable; 15-second calibration instrument; 16-auxiliary verification board; 17-data processing module.

具体实施方式Detailed ways

为了使本发明的目的、技术方案及优点更加清楚明白,以下结合附图及实施例,对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅仅用以解释本发明,并不用于限定本发明。In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

本发明的基本原理是在进行加载板校准时,由于加载板校准装置中包含有集成电路接口适配器,集成电路接口适配器自身会引入一些损耗误差,使得对加载板校准的效果欠佳,所以采用在信号输入装置与微波探针之间设置辅助验证板,将集成电路接口适配器与加载板滤除,单独在信号输入装置、辅助验证板和微波探针之间构建测量回路,将集成电路接口适配器引入的损耗去嵌参数进行量化并补偿校准量。数据处理模块对辅助验证板接入高速集成电路测试加载板校准装置前后第一校准仪表和第二校准仪表的信号进行对比,可以计算高速集成电路测试加载板校准过程中时域参数的去嵌。时域参数包括:高速集成电路测试加载板校准装置中除微波探针和射频线缆外其他器件的上升时间的补偿值、补偿后的加载板的上升时间、幅值的补偿值与补偿后的加载板幅值衰减值、校准加载板在最高传输速率下的眼图面积。The basic principle of the present invention is that when calibrating the loading board, since the IC interface adapter is included in the loading board calibrating device, the IC interface adapter itself will introduce some loss errors, which makes the effect of calibrating the loading board unsatisfactory. An auxiliary verification board is set between the signal input device and the microwave probe, the integrated circuit interface adapter and the loading board are filtered out, and a measurement circuit is separately constructed between the signal input device, the auxiliary verification board and the microwave probe, and the integrated circuit interface adapter is introduced into the The loss de-embedding parameters are quantized and compensated for the calibration amount. The data processing module compares the signals of the first calibration instrument and the second calibration instrument before and after the auxiliary verification board is connected to the calibration device of the high-speed integrated circuit test load board, and can calculate the de-embedding of the time domain parameters during the calibration process of the high-speed integrated circuit test load board. The time domain parameters include: the compensation value of the rise time of other devices in the high-speed integrated circuit test loading board calibration device except the microwave probe and the radio frequency cable, the rise time of the loaded board after compensation, the compensation value of the amplitude and the compensated The amplitude attenuation value of the loaded board, and the eye diagram area of the calibrated loaded board at the highest transmission rate.

更为具体地,如图1所示,本发明提供了一种高速集成电路测试加载板校准装置的损耗去嵌系统,包括:如图2所示的信号辅助验证板16和数据处理模块17;加载板校准装置1包括第一校准仪表10、第二校准仪表15、信号输入装置11、集成电路接口适配器12、微波探针13和射频线缆14;More specifically, as shown in FIG. 1 , the present invention provides a loss de-embedding system for a high-speed integrated circuit test loading board calibration device, including: a signal auxiliary verification board 16 and a data processing module 17 as shown in FIG. 2 ; The loading plate calibration device 1 includes a first calibration instrument 10, a second calibration instrument 15, a signal input device 11, an integrated circuit interface adapter 12, a microwave probe 13 and a radio frequency cable 14;

集成电路接口适配器12、微波探针13、射频线缆14和第二校准仪表15顺次连接;第一校准仪表10的输出端与信号输入装置11相连;信号输入装置11的输出端与加载板相连;集成电路接口适配器的输入端与加载板相连;The integrated circuit interface adapter 12, the microwave probe 13, the radio frequency cable 14 and the second calibration instrument 15 are connected in sequence; the output end of the first calibration instrument 10 is connected with the signal input device 11; the output end of the signal input device 11 is connected with the loading plate connected; the input end of the integrated circuit interface adapter is connected with the loading board;

辅助验证板16上下表面预留两种接口,一面为与信号输入装置11适配的接口,一面为与微波探针13适配的焊盘接口,上下连接后形成除了被较加载板后的测量回路,能够满足高速集成电路测试加载板校准过程中时域参数的去嵌;Two types of interfaces are reserved on the upper and lower surfaces of the auxiliary verification board 16, one side is an interface adapted to the signal input device 11, and the other side is a pad interface adapted to the microwave probe 13. After the upper and lower connections, the measurement of the loaded board is formed. The circuit can meet the de-embedding of time domain parameters in the calibration process of high-speed integrated circuit test loading board;

第一校准仪表10用于提供高速数字信号或者快沿信号;信号输入装置11用于将高速数学信号或快沿信号传递至加载板上;集成电路接口适配器12用于探测加载板上各焊盘上的输出信号;微波探针13用于移动至目标焊盘位置处,将目标焊盘上对应的输出信号通过射频线缆14传输至第二校准仪表15上;第二校准仪表15用于输出加载板上焊盘对应的输出信号;辅助验证板16用于形成除被较加载板的测量回路,实现高速集成电路测试加载板校准过程中时域参数的去嵌;数据处理模块17用于对辅助验证板接入高速集成电路测试加载板校准装置前后第一校准仪表和第二校准仪表的信号进行对比,计算高速集成电路测试加载板校准过程中时域参数的去嵌。The first calibration instrument 10 is used to provide high-speed digital signals or fast edge signals; the signal input device 11 is used to transmit high-speed mathematical signals or fast edge signals to the loading board; the integrated circuit interface adapter 12 is used to detect each pad on the loading board The output signal on the target pad; the microwave probe 13 is used to move to the position of the target pad, and the corresponding output signal on the target pad is transmitted to the second calibration instrument 15 through the radio frequency cable 14; the second calibration instrument 15 is used to output The output signal corresponding to the pad on the loading board; the auxiliary verification board 16 is used to form a measurement circuit except the loaded board to realize the de-embedding of the time domain parameters in the high-speed integrated circuit test loading board calibration process; the data processing module 17 is used for The signals of the first calibration instrument and the second calibration instrument are compared before and after the auxiliary verification board is connected to the calibration device of the high-speed integrated circuit test load board, and the de-embedding of the time domain parameters during the calibration process of the high-speed integrated circuit test load board is calculated.

进一步优选地,辅助验证板为PCB板。Further preferably, the auxiliary verification board is a PCB board.

进一步优选地,集成电路接口适配器包括正面探针位阵列和背面探针位阵列;正面探针位阵列和背面探针位阵列分别固定至加载板的两侧;正面探针位阵列和背面探针位阵列的形状为扇形。Further preferably, the integrated circuit interface adapter includes a front probe position array and a back probe position array; the front probe position array and the back probe position array are respectively fixed to both sides of the loading board; the front probe position array and the back probe position array The shape of the bit array is a fan.

进一步优选地,微波探针为GSG-DX微波探针,带宽为50G。Further preferably, the microwave probe is a GSG-DX microwave probe with a bandwidth of 50G.

进一步优选地,第一校准仪表为高速采样示波器TDR模块;第二校准仪表为示波器。Further preferably, the first calibration instrument is a high-speed sampling oscilloscope TDR module; the second calibration instrument is an oscilloscope.

进一步优选地,射频线缆为带宽18G的SMA-SMA线缆。Further preferably, the radio frequency cable is an SMA-SMA cable with a bandwidth of 18G.

另一方面,本发明提供的高速集成电路测试加载板校准装置的损耗去嵌方法,包括以下步骤:On the other hand, the loss de-embedding method of the high-speed integrated circuit test loading board calibration device provided by the present invention includes the following steps:

S1:采用第一校准仪表10输入高速数字信号,第二校准仪表15采集输出波形形成的眼图,根据眼高与高速信号幅度之差计算出眼高的补偿值h,根据眼宽与高速数字信号脉宽之差计算出眼宽的补偿值W,根据眼图上升时间得到上升时间补偿值t,被校准加载板在最高传输速率下的眼图面积为:SEYE=[(WEYE+W)-(Tr+t)]×(HEYE+h);其中,WEYE为眼图宽度;HEYE为眼图高度;Tr为眼图上升时间;W为眼宽补偿值;t为上升时间补偿值;h为眼高补偿值;S1: Use the first calibration instrument 10 to input the high-speed digital signal, and the second calibration instrument 15 collects the eye pattern formed by the output waveform, calculates the compensation value h of the eye height according to the difference between the eye height and the high-speed signal amplitude, and calculates the eye height compensation value h according to the eye width and high-speed digital signal. The compensation value W of the eye width is calculated from the difference of the signal pulse width, and the rise time compensation value t is obtained according to the rise time of the eye diagram. The eye diagram area of the calibrated loading board at the highest transmission rate is: S EYE = [( WEYE +W )-(T r +t)]×(H EYE +h); Among them, WEYE is the width of the eye diagram; HEYE is the height of the eye diagram; T r is the rise time of the eye diagram; W is the eye width compensation value; t is Rise time compensation value; h is eye height compensation value;

S2:采用第一校准仪表10输入高速数字信号,第二校准仪表15采集输出波形幅值,幅值的补偿值为ΔVc=20lg(V0c/Vmc);其中,V0c为辅助验证板16回路下第一校准仪表所发送的信号峰峰值;Vmc为辅助验证板16回路下第二校准仪表15采集信号的峰峰值;补偿后的加载板幅值衰减为ΔVL=20lg(V0Vmc/Vm V0c);其中,V0为辅助验证板未接入信号输入装置11与微波探针13之间时第一校准仪表所发送信号的峰峰值;Vm为辅助验证板未接入信号输入装置11与微波探针13之间时第二校准仪表15采集信号的峰峰值;S2: Use the first calibration instrument 10 to input a high-speed digital signal, and the second calibration instrument 15 collects the output waveform amplitude, and the compensation value of the amplitude is ΔV c =20lg(V 0c /V mc ); wherein, V 0c is an auxiliary verification board The peak-to-peak value of the signal sent by the first calibration instrument under 16 loops; V mc is the peak-to-peak value of the second calibration instrument 15 acquisition signal under the auxiliary verification board 16 loops; the amplitude attenuation of the loaded plate after compensation is ΔV L =20lg ( V V mc /V m V 0c ); Wherein, V 0 is the peak-to-peak value of the signal sent by the first calibration instrument when the auxiliary verification board is not connected between the signal input device 11 and the microwave probe 13; V m is the auxiliary verification board not connected When connecting between the signal input device 11 and the microwave probe 13, the second calibration instrument 15 collects the peak-to-peak value of the signal;

S3:采用第一校准仪表发送标准的快沿信号t0,第二校准仪表15采集输出波形并测量该信号的上升时间t1,校准装置中除了微波探针13和射频线缆14其他部分上升时间的补偿值为

Figure BDA0003946568500000061
其中,tp为微波探针13的上升时间;tc为射频线缆14的上升时间;补偿后的被校准加载板的上升时间为
Figure BDA0003946568500000062
其中,tr为辅助验证板未接入信号输入装置11与微波探针13之间时第二校准仪表采集的上升时间。S3: Use the first calibration instrument to send the standard fast-edge signal t 0 , the second calibration instrument 15 collects the output waveform and measures the rise time t 1 of the signal, and other parts of the calibration device except the microwave probe 13 and the radio frequency cable 14 rise The offset value of the time is
Figure BDA0003946568500000061
Wherein, t p is the rise time of microwave probe 13; t c is the rise time of radio frequency cable 14; The rise time of the calibrated loading board after compensation is
Figure BDA0003946568500000062
Wherein, t r is the rise time collected by the second calibration instrument when the auxiliary verification board is not connected between the signal input device 11 and the microwave probe 13 .

实施例Example

本发明提供了一种高速集成电路测试加载板校准装置损耗去嵌方法,本实施例选用GTL40-500型GSG-DX微波探针,带宽为50G,上升时间tp=0.35/50G=7ps,选用带宽18G的SMA-SMA线缆,高速电缆的上升时间tc=0.35/18G=19.4ps,选用泰克DSA8200型高速采样示波器TDR模块发送标准的快沿信号上升时间为:t0=30ps,上升时间可由其标称带宽BW3dB计算,其中,t=K/BW3dB,取K=0.35;第一校准仪表10选择MP1800高速码型发生器,第二校准仪表2选择DSA71254C高速实时示波器。The present invention provides a method for de-embedding the loss of a calibration device for a high-speed integrated circuit test loading board. In this embodiment, the GTL40-500 type GSG-DX microwave probe is selected, the bandwidth is 50G, and the rise time tp =0.35/50G=7ps is selected. For SMA-SMA cables with a bandwidth of 18G, the rise time of the high-speed cable is t c =0.35/18G=19.4ps, and the rise time of the standard fast-edge signal sent by the Tektronix DSA8200 high-speed sampling oscilloscope TDR module is: t 0 =30ps, the rise time It can be calculated from its nominal bandwidth BW 3dB , where t=K/BW 3dB , take K=0.35; the first calibration instrument 10 selects MP1800 high-speed pattern generator, and the second calibration instrument 2 selects DSA71254C high-speed real-time oscilloscope.

本领域的技术人员容易理解,以上所述仅为本发明的较佳实施例而已,并不用以限制本发明,凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等,均应包含在本发明的保护范围之内。It is easy for those skilled in the art to understand that the above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention, All should be included within the protection scope of the present invention.

Claims (6)

1. A loss de-embedding system of a high-speed integrated circuit test load plate calibration device is characterized by comprising: an auxiliary verification board (16) and a data processing module (17);
the calibration device for the high-speed integrated circuit test loading plate comprises a first calibration instrument (10), a signal input device (11), an integrated circuit interface adapter (12), a microwave probe (13), a radio frequency cable (14) and a second calibration instrument (15); the integrated circuit interface adapter (12), the microwave probe (13), the radio frequency cable (14) and the second calibration instrument (15) are connected in sequence; the output end of the first calibration instrument (10) is connected with the signal input device (11); the output end of the signal input device (11) is connected with the loading plate; the input end of the integrated circuit interface adapter (12) is connected with the loading plate;
two interfaces are reserved on the upper surface and the lower surface of the auxiliary verification board (16), one interface is an interface adaptive to the signal input device (11), the other interface is a pad interface adaptive to the microwave probe (13), and the data processing module is connected with the first calibration instrument (10) and the second calibration instrument (15);
the first calibration meter (10) is used for providing a high-speed digital signal or a fast-edge signal; the second calibration instrument (15) is used for acquiring an output signal on the loading plate; the auxiliary verification board (16) is used for forming a measurement loop for removing the loaded board, and the data processing module (17) is used for comparing signals of the first calibration instrument (10) and the second calibration instrument (15) before and after the auxiliary verification board (16) is connected to the high-speed integrated circuit test loading board calibration device, and calculating de-embedding of time domain parameters in the calibration process of the high-speed integrated circuit test loading board.
2. The loss de-embedding system of claim 1, wherein the integrated circuit interface adapter (12) includes a front side probe bit array and a back side probe bit array; the front probe position array and the back probe position array are respectively fixed to two sides of the loading plate; the front probe bit array and the back probe bit array are in fan shapes.
3. The loss de-embedding system of claim 3, wherein the microwave probe (13) is a GSG-DX microwave probe with a bandwidth of 50G;
the first calibration instrument is a high-speed sampling oscilloscope TDR module; the second calibration instrument is an oscilloscope;
the radio frequency cable (14) is an SMA-SMA cable with a bandwidth of 18G.
4. A loss de-embedding method based on the loss de-embedding system of claim 1, comprising the steps of:
an auxiliary verification board (16) is connected between a signal input device (11) and a microwave probe (13), a first calibration instrument (10) is used for inputting high-speed digital signals, and a second calibration instrument (15) is used for collecting an eye pattern formed by output waveforms of a loading board;
calculating an eye height compensation value according to the difference between the eye pattern height and the high-speed digital signal amplitude;
calculating a compensation value of the eye width according to the difference between the eye pattern width and the pulse width of the high-speed digital signal;
and calculating the eye pattern area of the calibration loading plate at the highest transmission rate by combining the eye pattern rising time with the eye height compensation value and the eye width compensation value.
5. A loss de-embedding method based on the loss de-embedding system of claim 1, comprising the steps of:
before and after the auxiliary verification board (16) is connected between the signal input device (11) and the microwave probe (13), a first calibration instrument (10) is adopted to input high-speed digital signals, and a second calibration instrument (15) is adopted to collect and output waveform amplitude values;
and calculating a compensation value of the amplitude and a compensated load plate amplitude attenuation value by combining the peak-to-peak value of a signal sent by a first calibration instrument before and after the auxiliary verification plate (16) is connected between the signal input device (11) and the microwave probe (13) and the peak-to-peak value of an output waveform collected by a second calibration instrument (15).
6. A loss de-embedding method based on the loss de-embedding system of claim 1, comprising the steps of:
the auxiliary verification board (16) is connected between the signal input device (11) and the microwave probe (13), a first calibration instrument (10) is adopted to send a fast edge signal, a second calibration instrument (15) is adopted to collect an output waveform, and the rise time of the output signal is measured;
calculating the compensation value of the rise time of other devices except the microwave probe (13) and the radio frequency cable (14) in the high-speed integrated circuit test loading plate calibration device by combining the rise time of the microwave probe (13) and the rise time of the radio frequency cable (14);
and meanwhile, the rise time of the output signal collected by the second calibration instrument (15) when the auxiliary verification board (16) is not accessed between the signal input device (11) and the microwave probe (13) is combined, and the rise time of the compensated load board is calculated.
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