CN115731886A - Special-shaped display substrate and display device - Google Patents

Abstract

The invention provides a special-shaped display substrate and a display device, which relate to the field of display technology. In order to solve the problem of manually placing and adjusting all the gate drive circuits step by step in the layout of the gate drive circuits for special-shaped display products, it takes a long time , the efficiency is low, which is not conducive to the production schedule and production capacity. The heterogeneous layout area in the heterogeneous display substrate includes multi-level gate drive circuits, and the multi-level gate drive circuits include at least two Nth gate drive circuits located in the Nth region and at least two Nth gate driver circuits located in the N+1th region. For N+1 gate drive circuits, there is a first angle between the connection line between the target parts of at least two Nth gate drive circuits and the first direction, and the edge between two adjacent Nth gate drive circuits is The second direction is staggered by a distance a; there is a second angle between the connection line between the target parts of at least two N+1th gate drive circuits and the first direction, and two adjacent N+1th gate drive circuits There is a distance b staggered along the second direction.

Description

Special-shaped display substrate and display device

technical field

The invention relates to the field of display technology, in particular to a special-shaped display substrate and a display device.

Background technique

With the continuous development of display technology, GOA (Gate on Array) technology has been widely used. This GOA technology is to integrate the gate drive circuit on the substrate of the display product, so that the display product can realize a narrow frame design.

Display products generally include rectangular display products. For such display products, four gate drive circuit units are generally designed first, and then the four gate drive circuits are arrayed to obtain a full column of gates located in the frame area. Drive circuit.

For special-shaped display products, because the left and right borders of the frame area used to lay out the gate drive circuit of the display product are of special shape, it is impossible to use software to perform array operations on the gate drive circuit, and the gate drive circuits can only be placed manually step by step and adjusted. Side routing. This method is also applicable to low-resolution special-shaped display products, but for high-resolution display products, manually placing and adjusting all gate drive circuits step by step takes a long time and is inefficient, which is not conducive to production progress and production capacity.

Contents of the invention

The purpose of the present invention is to provide a special-shaped display substrate and a display device, which are used to solve the problem of manually placing and adjusting all the gate drive circuits step by step when laying out the gate drive circuits for special-shaped display products, which takes a long time. The efficiency is low, which is not conducive to the production schedule and production capacity.

In order to achieve the above object, the present invention provides the following technical solutions:

The first aspect of the present invention provides a heterogeneous display substrate, including: a display area and a non-display area surrounding the display area; the non-display area includes a heterogeneous layout area, and the heterogeneous layout area includes sequentially arranged multi-level In the electrode drive circuit, the heterogeneous layout area further includes an Nth region and an N+1th region arranged in sequence, and N is greater than or equal to 1;

The multi-level gate drive circuit includes at least two Nth gate drive circuits arranged in sequence in the Nth region, and the connection lines between the target parts of the at least two Nth gate drive circuits, There is a first included angle with the first direction, and a distance a is staggered between two adjacent Nth gate drive circuits along the second direction; the second direction intersects the first direction;

The multi-stage gate drive circuit further includes at least two N+1th gate drive circuits arranged in sequence in the N+1th region, and the targets of the at least two N+1th gate drive circuits are The connecting line between the parts has a second included angle with the first direction, and the second included angle is different from the first included angle, between two adjacent N+1th gate drive circuits Staggered by a distance b along the second direction, a and b are not equal.

Optionally, the heterogeneous layout region further includes a connection region, at least part of the connection region is located between the Nth region and the N+1th region, and the connection region includes at least one connection gate drive circuit ;

The connecting gate driving circuit and the adjacent Nth gate driving circuit are staggered by a distance c along the second direction, and c is equal to or not equal to a;

and / or,

The connecting gate driving circuit and the adjacent (N+1)th gate driving circuit are staggered by a distance d along the second direction, and d and b are equal or not equal.

Optionally, the distance a is proportional to the first included angle, and the distance b is proportional to the second included angle.

Optionally, the Nth gate drive circuit includes an Nth output transistor, and in two adjacent Nth gate drive circuits, the gates of the Nth output transistors are staggered by a distance a along the second direction;

The N+1th gate drive circuit includes an N+1th output transistor, and in two adjacent N+1th gate drive circuits, the gates of the N+1th output transistors are staggered along the second direction distance b.

Optionally, the display area includes a circular display area, the special-shaped layout area includes an arc-shaped layout area, and the opposite sides of the display area along the second direction are provided with the arc-shaped layout area, The arc layout area includes the Nth area, the connection area and the N+1th area.

Optionally, the arc-shaped layout area includes a first area to an N+Xth area, where X is greater than or equal to 2;

The arc-shaped layout area is divided into three parts, the first part area includes the first area to the Mth area, the second part area includes the M+1th area to the M+Cth area, and the third part area includes the M+Cth area +1 area to N+X area, 1≤M<N+X, M+1≤M+C<N+X, M+C+1≤N+X;

In the first partial area, the angle between the connection line between the target parts of the gate driving circuit in each area and the first direction is between 60° and 80°;

In the second partial area, the angle between the connection line between the target parts of the gate driving circuit in each area and the first direction is between 10° and 25°;

In the third partial area, the angle between the connection line between the target parts of the gate driving circuit in each area and the first direction is between 60° and 80°.

Optionally, in the first partial region, from the first region to the Mth region, the staggered distance between the gate drive circuits in each region along the second direction becomes gradually smaller;

In the third partial area, in the M+C+1 th area to the N+X th area, the distances between the gate driving circuits in each area along the second direction gradually become larger.

Optionally, in the first partial region, the gate drive circuits in each region are staggered along the second direction by a distance between 150 microns and 300 microns;

In the second partial area, the distance between the gate drive circuits in each area is staggered along the second direction between 30 microns and 60 microns;

In the third partial area, the gate drive circuits in each area are staggered along the second direction by a distance between 150 microns and 300 microns.

Optionally, the arc-shaped layout area includes: Y clock signal lines and the multi-stage gate drive circuit; each stage of the gate drive circuit includes a gate drive signal output terminal, a clock signal input terminal, and an input signal terminal and reset terminal;

The clock signal input end of the Y×(B-1)+F stage gate drive circuit is coupled to the F clock signal line, Y is an integer greater than or equal to 2, F is a positive integer less than or equal to Y, and B is an integer greater than or equal to 1.

Optionally, in the multi-level gate drive circuit: the gate drive signal output terminal of the A-level gate drive circuit is connected to the input signal terminal of the A+E-th level gate drive circuit and the A-E-level gate drive circuit respectively. The reset terminal of the drive circuit is coupled, A is an integer greater than or equal to 3, and E is a positive integer smaller than A;

The multi-stage gate drive circuit is divided into multiple groups of gate drive circuits arranged in sequence, each group of gate drive circuit groups includes at least two adjacent stages of gate drive circuits; the Nth region includes at least one group of gate drive circuits. Pole driving circuit group, the at least one group of gate driving circuit groups includes the Nth gate driving circuit; the N+1th region includes at least one group of gate driving circuit groups, and the at least one group of gate driving circuits The group includes the N+1th gate driving circuit.

Optionally, the Nth region includes a plurality of Nth subregions, and the Nth subregion includes the corresponding Nth gate drive circuit and signal line; the Nth gate drive circuit connected to the same clock signal line The layout structure in the Nth sub-region where the circuit is located is exactly the same;

The N+1th region includes a plurality of N+1th subregions, and the N+1th subregion includes the corresponding N+1th gate drive circuit and signal lines; the N+1th subregions connected to the same clock signal line The layout structure in the N+1th sub-region where the N+1 gate driving circuit is located is exactly the same.

Optionally, in each of the Nth subregions where the Nth gate drive circuits connected to different clock signal lines are located, the layout of different clock signal lines is different;

In each of the N+1th sub-regions where the N+1th gate driving circuit connected to different clock signal lines is located, different clock signal lines are laid out in different ways.

Optionally, the layout structures of the gate driving circuits at all levels are completely the same, and the layout of the signal lines in the Nth sub-region and the N+1 sub-region is not completely the same.

Optionally, the Nth gate drive circuit, the connection region and the N+1th gate drive circuit both include:

The input subcircuit is used to input a carry signal to the pull-up node;

an output sub-circuit for inputting a clock signal to the drive signal output end;

a first pull-up node reset subcircuit, configured to input a first reset signal to the pull-up node;

a second pull-up node reset subcircuit, configured to input a second reset signal to the pull-up node;

a pull-down node reset subcircuit, configured to input the second reset signal to the pull-down node;

an output reset subcircuit, configured to input the second reset signal to the drive signal output terminal;

A storage sub-circuit, the storage sub-circuit is respectively coupled to the pull-up node and the drive signal output end.

Based on the above-mentioned technical solution of the special-shaped display substrate, a second aspect of the present invention provides a display device, including the above-mentioned special-shaped display substrate.

In the technical solution provided by the present invention, by setting the connection line between the target parts of the at least two Nth gate drive circuits in the Nth region, there is a first included angle with the first direction, and two adjacent The Nth gate driving circuits are staggered by a distance a along the second direction; and the connection line between the target parts of the at least two N+1th gate driving circuits in the N+1th area is set to be connected with the Nth gate driving circuits. There is a second included angle between the first directions, and the second included angle is different from the first included angle, and the distance between two adjacent N+1th gate drive circuits is staggered along the second direction by a distance b, a is not equal to b; so that the layout structures in the Nth area and the N+1th area can well match the shape of the heterogeneous layout area.

Moreover, in the technical solution provided by the present invention, by setting the Nth region to include at least two Nth gate drive circuits, the connection lines between the target parts of the at least two Nth gate drive circuits and the first There is a first angle between one direction, and a distance a is staggered between two adjacent Nth gate drive circuits along the second direction; so that the layout of each Nth gate drive circuit is the same, and each Nth gate drive circuit The layout of at least part of the signal lines around the driving circuit is the same. In this way, when the Nth region is laid out, the same at least two Nth gate drive circuits can be copied directly in the Nth region, and then only the signal lines with different layout methods around each Nth gate drive circuit can be adjusted. .

In the technical solution provided by the present invention, by setting the N+1th region to include at least two N+1th gate drive circuits, the connection between the target parts of the at least two N+1th gate drive circuits The line has a second angle with the first direction, and the distance b is staggered between two adjacent N+1th gate drive circuits along the second direction; so that the layout of each N+1th gate drive circuit Similarly, at least part of the signal lines arranged around each N+1th gate driving circuit are laid out in the same way. In this way, when the N+1th region is laid out, the same at least two N+1th gate drive circuits can be directly copied in the N+1th region, and then only the periphery of each N+1th gate drive circuit can be adjusted Signal lines with different layout methods are sufficient.

Therefore, in the technical solution provided by the present invention, when the layout of the gate drive circuit is carried out in the special-shaped layout area, the layout of the gate drive circuit is effectively improved by sub-area layout without the need for step-by-step placement and adjustment of a large number of signal lines. Efficiency reduces layout time and improves production schedule and capacity.

Description of drawings

The accompanying drawings described here are used to provide a further understanding of the present invention, and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention, and do not constitute improper limitations to the present invention. In the attached picture:

FIG. 1 is a schematic structural diagram of a special-shaped display substrate provided by an embodiment of the present invention;

FIG. 2 is a schematic diagram of the first layout of the Nth region and the N+1th region provided by the embodiment of the present invention;

FIG. 3 is a schematic diagram of a second layout of the Nth region and the N+1th region provided by the embodiment of the present invention;

4 is a schematic layout diagram of a gate drive circuit and its surrounding signals provided by an embodiment of the present invention;

FIG. 5 is a schematic diagram of a cascade connection of a multi-level gate drive circuit provided by an embodiment of the present invention;

6 is a schematic layout diagram of a first clock signal line coupled to a gate drive circuit in an Nth region according to an embodiment of the present invention;

7 is a schematic layout diagram of a second clock signal line coupled to a gate drive circuit in an Nth region according to an embodiment of the present invention;

8 is a schematic layout diagram of a third clock signal line coupled to a gate drive circuit in an Nth region according to an embodiment of the present invention;

9 is a schematic layout diagram of a fourth clock signal line coupled to a gate drive circuit in an Nth region according to an embodiment of the present invention;

10 is a schematic layout diagram of the first clock signal line coupled to the gate drive circuit in the N+1th region according to an embodiment of the present invention;

11 is a schematic layout diagram of the second clock signal line coupled to the gate drive circuit in the N+1th region provided by an embodiment of the present invention;

12 is a schematic layout diagram of a third clock signal line coupled to a gate drive circuit in the N+1th region according to an embodiment of the present invention;

13 is a schematic layout diagram of a fourth clock signal line coupled to the gate drive circuit in the N+1th region provided by an embodiment of the present invention;

14 is a circuit diagram of a gate drive circuit with a 4T1C structure provided by an embodiment of the present invention;

FIG. 15 is a working timing diagram of a gate drive circuit with a 4T1C structure provided by an embodiment of the present invention;

FIG. 16 is a working diagram of a gate drive circuit with a 4T1C structure provided by an embodiment of the present invention during an input period;

FIG. 17 is a working diagram of a gate drive circuit with a 4T1C structure in an output period according to an embodiment of the present invention;

FIG. 18 is a working diagram of a gate drive circuit with a 4T1C structure provided in an embodiment of the present invention during a reset period;

FIG. 19 is a circuit diagram of a gate drive circuit with a 11T1C structure provided by an embodiment of the present invention.

Detailed ways

In order to further illustrate the special-shaped display substrate and display device provided by the embodiments of the present invention, a detailed description will be given below in conjunction with the accompanying drawings.

Referring to FIGS. 1 to 4 , an embodiment of the present invention provides a special-shaped display substrate, including: a display area 10 and a non-display area surrounding the display area 10, the non-display area includes a special-shaped layout area 21, the The heterogeneous layout area 21 includes multi-level gate drive circuits arranged in sequence, and the heterogeneous layout area 21 also includes an Nth region 30 and an N+1th region 40 arranged in sequence, where N is greater than or equal to 1;

The multi-level gate drive circuit includes at least two Nth gate drive circuits arranged in sequence in the Nth region 30, and the connection lines between the target parts of the at least two Nth gate drive circuits , has a first angle θ1 with the first direction, and a distance a is staggered between two adjacent Nth gate drive circuits along the second direction; the second direction intersects the first direction;

The multi-level gate drive circuit further includes at least two N+1th gate drive circuits arranged in sequence in the N+1th region 40, the at least two N+1th gate drive circuits The connection line between the target parts has a second included angle θ2 with the first direction, the second included angle is different from the first included angle, and two adjacent N+1th gate drive circuits There is a distance b staggered along the second direction, and a and b are not equal.

Exemplarily, the heterogeneous layout area 21 located on one side of the display area 10 includes N+X areas, and among at least two gate drive circuits arranged sequentially in the same area, the two gate drive circuits located at both ends The connecting line between the target parts has a certain angle with the first direction.

Exemplarily, one area includes 8 gate drive circuits arranged in sequence, among these 8 gate drive circuits, the target part in the first gate drive circuit and the target part in the eighth gate drive circuit The connecting line between has a certain angle with the first direction. It should be noted that the target part of the second gate driving circuit to the target part of the seventh gate driving circuit are all located on the connecting line.

Exemplarily, the target portion may be a designated position of a specific structure. For example: the central part of the gate of each output transistor (ie the third transistor M3 mentioned later). Since the gate area of the output transistor is relatively large, it is easy to identify and measure with the gate of the output transistor as a reference, thereby reducing test errors.

It should be noted that FIG. 1 also shows a driver chip IC, a flexible circuit board FPC, and a fan-out area 22 . 301-CLK1 in FIG. 3 represents that the gate driving circuit in the Nth sub-region is coupled to the first clock signal line. 301-CLK2 in FIG. 3 represents that the gate driving circuit in the Nth sub-region is coupled to the second clock signal line. 301-CLK3 in FIG. 3 represents that the gate driving circuit in the Nth sub-region is coupled to the third clock signal line. 301-CLK4 in FIG. 3 represents that the gate driving circuit in the Nth sub-region is coupled to the fourth clock signal line. 401-CLK1 in FIG. 3 represents that the gate driving circuit in the N+1th sub-region is coupled to the first clock signal line. 401-CLK2 in FIG. 3 represents that the gate driving circuit in the N+1th sub-region is coupled to the second clock signal line. 401-CLK3 in FIG. 3 represents that the gate driving circuit in the N+1th sub-region is coupled to the third clock signal line. 401-CLK4 in FIG. 3 represents that the gate driving circuit in the N+1th sub-region is coupled to the fourth clock signal line. 50-CLK2 in FIG. 3 represents that the gate driving circuit in the connection area is coupled to the second clock signal line.

Exemplarily, the multi-stage gate drive circuits are cascaded, and each stage of the gate drive circuit is used to provide a gate drive signal for a corresponding scan line.

Exemplarily, the heterogeneous layout area 21 includes an area with a boundary having a certain arc.

Exemplarily, the Nth gate drive circuit and the N+1th gate drive circuit include the same circuit structure, such as including 4T1C (4 transistors and 1 capacitor), 8T1C (8 transistors and 1 capacitor ), 10T1C (10 transistors and 1 capacitor), 11T1C (11 transistors and 1 capacitor), 17T1C (17 transistors and 1 capacitor), or 21T1C (21 transistors and 1 capacitor).

Exemplarily, the layout of the circuit structure in the Nth gate driving circuit and the N+1th gate driving circuit is the same, and the Nth gate driving circuit and the N+1th gate driving circuit The layout of the signal lines in the circuit is not exactly the same.

It should be noted that the same layout of the two gate drive circuits means that the size and shape of the devices included in the two gate drive circuits are the same, and the relative positions of the devices are the same. The same layout of the signal lines around the two gate drive circuits means that the size and shape of the signal lines are the same, and the layout positions of the signal lines relative to the gate drive circuits are the same.

The layout of the signal lines in the Nth gate driving circuit and the N+1th gate driving circuit are not exactly the same means: in the Nth gate driving circuit and the N+1th gate driving circuit Some of the signal lines have different layouts (such as clock signal lines), and the other part of the signal lines have the same layout (such as other signal lines except the clock signal lines).

Exemplarily, taking the gate drive circuit including a 11T1C structure as an example, in the Nth subregion 301 and the N+1th subregion 401, the signal lines include: a first frame start signal line for inputting the A frame start signal STV1; a second frame start signal line, used to input the second frame start signal STV2; an input control signal line, used to input the input control signal Input; a carry signal line, used to input the carry signal VDS, The first pull-down control line is used to input the first pull-down control signal GCH; the clock signal line is used to input the clock signal CLK; the first reset control line is used to input the first reset control signal Reset; the second reset control line , for inputting the second reset control signal STV0; the third reset control line, for inputting the third reset control signal GCL; the first reset signal line, for inputting the first reset signal VSD; the second reset signal line, for The second reset signal VGL is input.

Exemplarily, the target part of the Nth gate driving circuit and the target part of the N+1th gate driving circuit are the same reference part. For example: both are parts of transistors with specific functions, or are all parts of capacitors.

Exemplarily, the distance a is staggered along the second direction between two adjacent Nth gate drive circuits, and the target parts of the at least two Nth gate drive circuits can be connected to a straight line, and the straight line is the same as the first Nth gate drive circuit. There is a first included angle between one direction.

Exemplarily, two adjacent N+1th gate driving circuits are staggered by a distance b along the second direction, and the target parts of the at least two N+1th gate driving circuits can be connected in a straight line, There is a second included angle between the straight line and the first direction.

Exemplarily, the display area of the heterogeneous display substrate includes data lines and gate lines, the data lines include at least a portion extending along the first direction, and the gate lines include at least a portion extending along the second direction. . Exemplarily, the first direction is perpendicular to the second direction.

According to the specific structure of the above-mentioned special-shaped display substrate, in the special-shaped display substrate provided by the embodiment of the present invention, the special-shaped layout region 21 is set to include the Nth region 30 and the N+1th region 40 arranged in sequence, and the Nth region 30 The distance a is staggered along the second direction between adjacent Nth gate drive circuits; the connection line between the target parts of each Nth gate drive circuit has a first angle with the first direction; the N+th 1. The adjacent N+1th gate driving circuits in the area 40 are staggered by a distance b along the second direction; there is a distance b between the connection lines between the target parts of each N+1th gate driving circuits and the first direction. Two included angles.

In the special-shaped display substrate provided by the embodiment of the present invention, by setting the connection line between the target parts of the at least two Nth gate drive circuits in the Nth region 30, there is a first included angle with the first direction , the distance a is staggered along the second direction between two adjacent Nth gate drive circuits; The connecting line has a second included angle with the first direction, the second included angle is different from the first included angle, and the distance between two adjacent N+1th gate drive circuits is along the second direction The staggered distance b, a and b are not equal; so that the layout structure in the Nth region 30 and the N+1th region 40 can well match the shape of the special-shaped layout region 21 .

Moreover, in the special-shaped display substrate provided by the embodiment of the present invention, by setting the Nth region 30 to include at least two Nth gate drive circuits, the connection between the target parts of the at least two Nth gate drive circuits The line has a first angle with the first direction, and the distance a between two adjacent Nth gate drive circuits is staggered along the second direction; so that the layout of each Nth gate drive circuit is the same, and each The layout of at least part of the signal lines in the peripheral layout of the Nth gate driving circuit is the same. In this way, when the Nth region 30 is laid out, the same at least two Nth gate drive circuits can be directly duplicated in the Nth region 30, and then only the signal lines with different layout modes around each Nth gate drive circuit can be adjusted. That's it.

To be more specific, take the example that the heterogeneous layout area 21 on one side of the display area 10 includes Y clock signal lines. In one area (such as the Nth area), Y gate driving circuits are used as a group, and this area includes k groups. Y gate drive circuits in a group of gate drive circuits are coupled to Y clock signal lines in one-to-one correspondence. In this area, each group of gate drive circuits has the same layout and can be copied directly. It is only necessary to stagger the gate drive circuits by a preset distance between adjacent groups during layout (the stagger distance a when corresponding to the Nth area). Can. This improves the operating efficiency of the wiring gate drive circuit,

Exemplarily, Y is equal to 4, and the first region includes 8 gate drive circuits arranged in sequence. Among the 8 gate drive circuits, the first gate drive circuit is connected to the first clock signal line, and the second gate drive circuit connected to the second clock signal line, the third gate drive circuit is connected to the third clock signal line, the fourth gate drive circuit is connected to the fourth clock signal line, the fifth gate drive circuit is connected to the first clock signal line, The sixth gate driving circuit is connected to the second clock signal line, the seventh gate driving circuit is connected to the third clock signal line, and the eighth gate driving circuit is connected to the fourth clock signal line.

Among the eight gate drive circuits, the first gate drive circuit and the second gate drive circuit are staggered by a distance a along the second direction, and when connecting the first gate drive circuit to the fourth gate drive circuit After being arranged, the arrangement of the fifth gate driving circuit to the eighth gate driving circuit can directly copy the arrangement of the first gate driving circuit to the fourth gate driving circuit, and set the fifth gate driving circuit relatively to the eighth gate driving circuit. The fourth gate driving circuit is staggered by a distance a. It should be noted that since both the fifth gate drive circuit and the first gate drive circuit are connected to the first clock signal line, the layout of the first clock signal line connected to the fifth gate drive circuit and the first gate drive circuit is the same . Similarly, the layout of the second clock signal line connected to the second gate driving circuit and the sixth gate driving circuit is the same. The layout of the third clock signal line connected to the third gate driving circuit and the seventh gate driving circuit is the same. The layout of the fourth clock signal line connected to the fourth gate driving circuit and the eighth gate driving circuit is the same. The layout methods of the first clock signal line to the fourth clock signal line are different, and the specific layout methods need to be set separately according to the edge of the special-shaped layout area.

Similarly, in the special-shaped display substrate provided by the embodiment of the present invention, by setting the N+1th region 40 to include at least two N+1th gate drive circuits, the at least two N+1th gate drive circuits The connection line between the target parts has a second angle with the first direction, and the distance b between adjacent two N+1th gate drive circuits is staggered along the second direction; so that each N+1th The layout of the gate driving circuits is the same, and the layout of at least part of the signal lines arranged around each N+1th gate driving circuit is the same. In this way, when the N+1th region 40 is laid out, the same at least two N+1th gate driving circuits can be directly copied in the N+1th region 40, and then only the N+1th gate driving circuits can be adjusted. Signal lines with different layouts around the circuit are sufficient.

Therefore, in the special-shaped display substrate provided by the embodiment of the present invention, when the gate drive circuit is laid out in the special-shaped layout area 21, the gate driving circuit is effectively improved by sub-area layout without the need for step-by-step arrangement and adjustment of a large number of signal lines. The layout efficiency of the driving circuit reduces the layout time and improves the production schedule and production capacity.

The special-shaped display substrate provided by the embodiment of the present invention adopts the GOA design, which is conducive to narrowing the frame of the special-shaped display substrate.

In addition, when the special-shaped display substrate provided by the embodiment of the present invention is applied to a small-sized display device, since the length of the signal line in the small-sized display device is relatively short, there is almost no probability of ESD (electrostatic discharge). The special-shaped display substrate provided by the embodiment of the invention does not include an electrostatic ring design, which can provide a larger layout space for the gate drive circuit, and is conducive to better realization of narrow frame design.

As shown in FIG. 1 to FIG. 4 , in some embodiments, the heterogeneous layout region 21 further includes a connection region 50, at least part of the connection region 50 is located in the Nth region 30 and the N+1th region 40, the connection area 50 includes at least one connection gate drive circuit;

The connecting gate driving circuit and the adjacent Nth gate driving circuit are staggered by a distance c along the second direction, and c is equal to or not equal to a;

and / or,

The connecting gate driving circuit and the adjacent (N+1)th gate driving circuit are staggered by a distance d along the second direction, and d and b are equal or not equal.

Exemplarily, the connecting gate driving circuit has the same circuit structure as that included in the Nth gate driving circuit and the N+1th gate driving circuit.

Exemplarily, the layout of the connecting gate driving circuit is the same as that of the circuit structures in the Nth gate driving circuit and the N+1th gate driving circuit, and the connecting gate driving circuit and the The layout of the signal lines in the Nth gate driving circuit and the N+1th gate driving circuit are not exactly the same.

Exemplarily, the connecting gate driving circuit is the same as the Nth gate driving circuit and the N+1th gate driving circuit, and can be coupled to corresponding scanning lines in the display area, which is a coupled scanning line provides the gate drive signal.

Exemplarily, the gate drive circuit connecting the regions is used to connect two adjacent regions. The two adjacent areas are arranged according to their respective slopes. The layout of the clock signal lines coupled to the gate drive circuit in the connection area may be different from that of the clock signal lines in other areas connected to it, so as to adjust the appropriate wiring layout position according to the layout of adjacent areas.

In the heterogeneous display substrate provided in the above embodiment, the connection region 50 is provided between the Nth region 30 and the N+1th region 40, and the connecting gate drive circuit and the adjacent The distance c is staggered between the N gate drive circuits along the second direction, and the distance d is staggered between the connecting gate drive circuit and the adjacent N+1th gate drive circuit along the second direction, so that the connection region 50 The connecting gate driving circuit in can play the role of adjusting the staggered distance, which not only ensures the staggered distance between the adjacent Nth gate driving circuits, but also ensures the distance between the adjacent N+1th gate driving circuits. Staggering the distance also enables the layout position between the Nth gate driving circuit and the N+1th gate driving circuit to achieve a smoother transition through the connecting gate driving circuit, which can be compared with the special-shaped layout area 21 A better match of the boundaries.

As shown in FIG. 3 , in some embodiments, the distance a is set to be proportional to the first included angle, and the distance b is set to be proportional to the second included angle.

The above arrangement enables the layout of the Nth gate driving circuit and the N+1th gate driving circuit to better match the layout space of the heterogeneous layout region 21, so that the Nth gate driving circuit and the Nth gate driving circuit The layout boundary of the N+1th gate driving circuit is better matched with the boundary of the irregular layout region 21 , thereby more effectively improving the utilization rate of the layout space of the irregular layout region 21 .

In some embodiments, the Nth gate drive circuit includes an Nth output transistor, and in two adjacent Nth gate drive circuits, the gates of the Nth output transistors are staggered by a distance a along the second direction ;

The N+1th gate drive circuit includes an N+1th output transistor, and in two adjacent N+1th gate drive circuits, the gates of the N+1th output transistors are staggered along the second direction distance b.

Exemplarily, the Nth output transistor and the N+1th output transistor have the same structure and the same layout.

Exemplarily, taking the gate of the Nth output transistor away from the boundary of the display area as a reference, the distance between the gates of adjacent Nth output transistors along the second direction is calculated. Exemplarily, taking the gate of the Nth output transistor close to the boundary of the display area as a reference, the distance between the gates of adjacent Nth output transistors along the second direction is calculated.

Exemplarily, taking the gate of the N+1th output transistor away from the boundary of the display area as a reference, the distance between the gates of the adjacent N+1th output transistors along the second direction is calculated. Exemplarily, taking the gate of the N+1th output transistor close to the boundary of the display area as a reference, the staggered distance between the gates of the adjacent N+1th output transistors along the second direction is calculated.

It should be noted that, except that the gates of adjacent Nth output transistors are staggered by a distance a along the second direction, in adjacent Nth gate drive circuits, the same other elements are also staggered by a distance along the second direction a. Except that the gates of the adjacent N+1th output transistors are staggered by a distance b along the second direction, in the adjacent N+1th gate drive circuit, the same other elements are also staggered along the second direction distance b.

As shown in Figures 1 to 4, in some embodiments, the display area is set to include a circular display area, the irregular layout area 21 includes an arc-shaped layout area, and the display areas are opposite along the second direction Both sides are provided with the arc-shaped layout area, and the arc-shaped layout area includes the N th area 30 , the connection area 50 and the N+1 th area 40 .

Exemplarily, the two arc-shaped layout areas located on both sides of the display area are symmetrically arranged, and the symmetry axes of the two arc-shaped layout areas pass through the center of the circular display area, and along the Extend in one direction.

Exemplarily, each arc-shaped layout area includes the multi-level gate driving circuit.

Exemplarily, in the heterogeneous display substrate, scanning signals may be provided to the scanning lines from opposite sides of the display area along the second direction.

Exemplarily, each scan line can simultaneously receive scan signals on opposite sides of the display area along the second direction.

Exemplarily, the odd number of scan lines can receive scan signals provided by the gate drive circuit on the left side of the display area along the second direction. The even scanning lines can receive the scanning signal provided by the gate driving circuit on the right side of the display area along the second direction.

The above arrangement is also beneficial to further improve the layout efficiency of the irregular layout area 21 .

In some embodiments, the arc layout area is set to include the first area to the N+Xth area, where X is greater than or equal to 2;

The arc-shaped layout area is divided into three parts, the first part area includes the first area to the Mth area, the second part area includes the M+1th area to the M+Cth area, and the third part area includes the M+Cth area +1 area to N+X area, 1≤M<N+X, M+1≤M+C<N+X, M+C+1≤N+X;

In the first partial area, the angle between the connection line between the target parts of the gate driving circuit in each area and the first direction is between 60° and 80°, which may include the endpoint value;

In the second partial area, the angle between the connection line between the target parts of the gate drive circuit in each area and the first direction is between 10° and 25°, which may include the endpoint value;

In the third partial area, the angle between the connection line between the target parts of the gate driving circuit in each area and the first direction is between 60° and 80°, which may include the endpoint value.

Exemplarily, the arc-shaped layout area includes a first area to an N+X-th area sequentially arranged along the arc-shaped extending direction. The arc-shaped layout area is divided into three partial areas, wherein the second partial area is located between the first partial area and the third partial area.

Exemplarily, in the first region to the Mth region, the angles between the connection lines between the target parts of the gate driving circuit in each region and the first direction are all between 60° and 80°. In the M+1th region to the M+Cth region, the angle between the connection line between the target parts of the gate driving circuit in each region and the first direction is between 10° and 25°. In the M+C+1th region to the N+Xth region, the connection line between the target parts of the gate driving circuit in each region has an angle between 60° and 80° with the first direction .

Exemplarily, N+X is equal to 9, M is equal to 3, and M+C is equal to 6.

Exemplarily, in the first region to the N+Xth region, there are at least two regions where the gate drive circuit forms the same angle with the first direction.

The arrangement above can make the multi-level gate driving circuit better match the layout space of the arc-shaped layout area, and achieve a good layout of the multi-level gate driving circuit in the arc-shaped layout area.

In some embodiments, in the first partial region, from the first region to the Mth region, the staggered distance between the gate drive circuits in each region along the second direction becomes gradually smaller;

In the third partial area, in the M+C+1 th area to the N+X th area, the distances between the gate driving circuits in each area along the second direction gradually become larger.

Exemplarily, from the first region to the N+Xth region, gate drive circuits in at least two regions are staggered by the same distance along the second direction.

Exemplarily, N+X is equal to 9. A staggered distance along the second direction between adjacent gate driving circuits in the ninth region includes 170 micrometers. A staggered distance along the second direction between adjacent gate driving circuits in the eighth region includes 110 micrometers. A staggered distance along the second direction between adjacent gate driving circuits in the seventh region includes 80 microns. A staggered distance along the second direction between adjacent gate driving circuits in the sixth region includes 45 microns. The staggered distance along the second direction between adjacent gate driving circuits in the fifth region includes 0 μm. The staggered distance along the second direction between adjacent gate driving circuits in the fourth region includes 45 microns. A staggered distance along the second direction between adjacent gate driving circuits in the third region includes 90 microns. A staggered distance along the second direction between adjacent gate driving circuits in the second region includes 160 microns. A staggered distance along the second direction between adjacent gate driving circuits in the first region includes 300 microns.

The arrangement above can make the multi-level gate driving circuit better match the layout space of the arc-shaped layout area, and achieve a good layout of the multi-level gate driving circuit in the arc-shaped layout area.

In some embodiments, in the first partial region, the gate drive circuits in each region are staggered along the second direction by a distance between 150 microns and 300 microns, which may include endpoint values;

In the second partial area, the distance between the gate drive circuits in each area along the second direction is between 30 microns and 60 microns, which may include endpoint values;

In the third partial area, the gate driving circuits in each area are staggered along the second direction by a distance between 150 microns and 300 microns, which may include endpoint values.

Exemplarily, in the first region to the Mth region, the gate driving circuits in each region are staggered along the second direction by a distance between 30 microns and 60 microns. In the M+1 th area to the M+C th area, the gate driving circuits in each area are staggered along the second direction by a distance between 30 microns and 60 microns. In the M+C+1 th area to the N+X th area, the gate driving circuits in each area are staggered along the second direction by a distance between 150 microns and 300 microns.

The arrangement above can make the multi-level gate driving circuit better match the layout space of the arc-shaped layout area, and achieve a good layout of the multi-level gate driving circuit in the arc-shaped layout area.

In some embodiments, the arc-shaped layout area includes: Y clock signal lines and the multi-level gate drive circuit; each level of gate drive circuit includes a gate drive signal output terminal, a clock signal input terminal, Input signal terminal and reset terminal;

The clock signal input end of the Y×(B-1)+F stage gate drive circuit is coupled to the F clock signal line, Y is an integer greater than or equal to 2, F is a positive integer less than or equal to Y, and B is an integer greater than or equal to 1.

In some embodiments, in the multi-level gate drive circuit: the gate drive signal output terminal of the A-level gate drive circuit is connected to the input signal terminal of the A+E-th level gate drive circuit and the A-E level The reset terminal of the gate drive circuit is coupled, A is an integer greater than or equal to 3, and E is a positive integer smaller than A;

The multi-stage gate drive circuit is divided into multiple groups of gate drive circuits arranged in sequence, each group of gate drive circuit groups includes at least two adjacent stages of gate drive circuits; the Nth region 30 includes at least one A gate driving circuit group, the at least one group of gate driving circuit groups includes the Nth gate driving circuit; the N+1th region 40 includes at least one group of gate driving circuit groups, and the at least one group of gate driving circuits The driving circuit group includes the N+1th gate driving circuit.

Exemplarily, the clock signal input end of the Y×(B-1)+F stage gate driving circuit is coupled to the Fth clock signal line, and receives the Fth clock signal provided by the Fth clock signal line.

Exemplarily, Y is equal to 4, and F has values of 1, 2, 3, and 4.

Exemplarily, in the multi-level gate drive circuit: the input signal terminal of the first-level gate drive circuit is coupled to the first frame start signal line included in the arc-shaped layout area; the second-level gate The input signal end of the driving circuit is coupled to the second frame start signal line included in the arc-shaped layout area.

Exemplarily, the gate drive signal output terminal of the A-level gate drive circuit is coupled to the input signal terminal of the A+E-th level gate drive circuit, and the gate drive signal output terminal of the A-level gate drive circuit The output gate driving signal is used as an input signal of the A+E-th stage gate driving circuit. The gate drive signal output terminal of the A-level gate drive circuit is coupled to the reset terminal of the A-E level gate drive circuit, and the gate drive signal output by the gate drive signal output terminal of the A-level gate drive circuit, As the reset signal of the A-E stage gate drive circuit.

As shown in Figure 5, it is shown in Figure 5 that the odd number of scan lines receive the gate drive signal (i.e. the scan signal) provided by the gate drive circuit in the right special-shaped layout area, and the even number of scan lines receive the gate drive signal (ie, scan signal) provided by the left special-shaped layout area. The gate drive circuit provides the gate drive signal.

Gate-1 to Gate480 represent scan lines. Dummy-1 to Dummy-4 represent virtual scan lines.

Gate-1 to Gate480 and Dummy-1 to Dummy-4 marked in the squares in FIG. 5 are coupled to correspondingly labeled scan lines for providing gate driving signals to the correspondingly marked scan lines.

The first frame start signal line STV1 and the second frame start signal line STV2 are included in the left-side heterogeneous layout area. The right irregular layout area includes a third frame start signal line STV3 and a fourth frame start signal line STV4 . The fifth clock signal line CLK5 , the sixth clock signal line CLK6 , the seventh clock signal line CLK7 and the eighth clock signal line CLK8 are included in the right irregular layout area.

Exemplarily, the multi-stage gate driving circuits are divided into multiple gate driving circuit groups arranged in sequence, and each stage of gate driving circuits only belongs to one group of gate driving circuit groups.

Exemplarily, the Nth region 30 includes at least one set of gate drive circuit groups, and the gate drive circuits included in the at least one set of gate drive circuit groups are the Nth gate drive circuits; The N+1 region 40 includes at least one group of gate driving circuits, and the gate driving circuit included in the at least one group of gate driving circuits is the N+1th gate driving circuit.

Cascading the multi-level gate drive circuits according to the above method not only ensures the working performance of the multi-level gate drive circuits, but also helps to reduce the layout space occupied by the multi-level gate drive circuits, which is beneficial to special-shaped Narrow bezel of the display substrate.

In some embodiments, the gate drive circuit includes a gate drive signal output terminal, an input terminal and a reset terminal; the A-H level gate drive circuit is used to drive the A level gate through its gate drive signal output terminal. The circuit provides an input signal, and the A+H+1th pole gate drive circuit is used to provide a reset signal for the A-level gate drive circuit through its gate drive signal output terminal.

Exemplarily, four clock signal lines are laid out in the special-shaped layout area located on one side of the display area as an example. The first gate drive circuit is used to provide an input signal to the third stage gate drive circuit through its gate drive signal output terminal. The sixth-level gate drive circuit is used to provide a reset signal to the third-level gate drive circuit through its gate drive signal output terminal.

It should be noted that the reset can be set according to actual needs, without limitation, for example, the fourth gate driving circuit can reset the first gate driving circuit, or the fifth gate driving circuit can reset the first gate driving circuit.

As shown in FIG. 3, in some embodiments, the Nth region 30 includes a plurality of Nth subregions 301, and the Nth subregions 301 include corresponding Nth gate drive circuits and signal lines; The layout structure in the Nth sub-region 301 where the Nth gate drive circuit connected to the same clock signal line is located is the same;

The N+1th region 40 includes a plurality of N+1th subregions 401, and the N+1th subregion 401 includes the corresponding N+1th gate drive circuit and signal line; the same clock signal is connected The layout structure in the N+1th sub-region 401 where the N+1th gate driving circuit of the line is located is the same.

As shown in FIG. 6, for example, the first clock signal line CLK1 includes three sections of connection lines, the first section of connection lines extends along the first direction, the third section of connection lines extends along the second direction, and the The first direction is perpendicular to the second direction, and the second connecting line is coupled to the first connecting line and the third connecting line respectively. In the same area (such as the Nth area), in each sub-area including the first clock signal line: the first clock signal lines are all laid out in this manner.

As shown in FIG. 8 , for example, the layout of the third clock signal line CLK3 is different from that of the first clock signal line CLK1 , so as to meet the layout requirements of the special-shaped layout area.

Exemplarily, the width of the Nth sub-region 301 along the first direction is substantially the same as the width of the layout area occupied by one sub-pixel in the display region. The width of the N+1th sub-region 401 along the first direction is approximately the same as the width of the layout area occupied by one sub-pixel in the display area. It should be noted that theoretically, the width of the Nth sub-region 301 along the first direction is set to be the same as the width of the layout area occupied by one sub-pixel in the display area, and the width of the N+1th sub-region 401 along the first direction is equal to The width of the layout area occupied by one sub-pixel in the display area is the same. However, due to the process error in the production process of the special-shaped display substrate, there may be a certain error between the actual width during actual production and the theoretically set width. Considering the process error, the above width is limited to be roughly the same.

Exemplarily, the Nth region 30 includes a plurality of Nth subregions 301 arranged in sequence, and the Nth subregions 301 correspond to the Nth gate drive circuits one by one, and the Nth subregions 301 It includes the corresponding Nth gate drive circuit and the signal line coupled to the Nth gate drive circuit.

As shown in FIG. 4, FIG. 5 and FIG. 19, for example, the types and numbers of signal lines in the Nth subregion 301 and the N+1th subregion 401 are related to the specific structure of the gate drive circuit. relevant. Taking the gate drive circuit including the 11T1C structure as an example, in the Nth subregion 301 and the N+1th subregion 401, the signal lines include: a first frame start signal line for inputting the A frame start signal STV1; a second frame start signal line, used to input the second frame start signal STV2; an input control signal line, used to input the input control signal Input; a carry signal line, used to input the carry signal VDS, The first pull-down control line is used to input the first pull-down control signal GCH; the clock signal line is used to input the clock signal CLK; the first reset control line is used to input the first reset control signal Reset; the second reset control line , for inputting the second reset control signal STV0; the third reset control line, for inputting the third reset control signal GCL; the first reset signal line, for inputting the first reset signal VSD; the second reset signal line, for The second reset signal VGL is input.

Exemplarily, the input control signal line is used to connect the input signal terminal of the gate driving circuit in the current sub-region and the gate driving signal output terminal of the previous E-stage gate driving circuit. The first reset control line is used to connect the reset terminal of the gate driving circuit in the current sub-region and the gate driving signal output terminal of the subsequent E-level gate driving circuit.

The above setting method enables the Nth subregion 301 where the Nth gate drive circuit connected to the same clock signal line is located to be directly copied, and the N+1th subregion 401 where the N+1th gate drive circuit connected to the same clock signal line is located It can be copied directly, avoiding the time-consuming and low-efficiency problems of manually placing and adjusting all gate drive circuits step by step. The production progress and production capacity of special-shaped display substrates have been effectively improved.

In some embodiments, as shown in FIG. 6 to FIG. 9 , in each Nth sub-region 301 where the Nth gate drive circuit connected to different clock signal lines is located, the layout of different clock signal lines is different;

As shown in FIG. 10 to FIG. 13 , in each N+1th sub-region 401 where the N+1th gate driving circuit connected to different clock signal lines is located, the layout of different clock signal lines is different.

It should be noted that the different layout modes of the different clock signal lines refer to different shapes and sizes of the clock signal lines, and/or different layout positions of the clock signal lines relative to the gate driving circuit.

As shown in FIG. 6 to FIG. 13 , in some embodiments, the layout structures of the gate drive circuits at all levels are completely the same, and the layout of the signal lines in the Nth sub-region 301 and the N+1 sub-region is Not exactly the same.

It should be noted that the different layout methods of the signal lines refer to different shapes and sizes of the signal lines, and/or different layout positions of the signal lines relative to the gate driving circuit.

The above arrangement enables the layout structures in the Nth region 30 and the N+1th region 40 to be well matched with the shape of the heterogeneous layout region 21 .

When the above-mentioned setting is used to layout the gate drive circuit in the special-shaped layout area 21, only a small number of signal lines (such as clock signal lines) need to be adjusted through the sub-area layout, and there is no need to arrange step by step and adjust a large number of signal lines. The layout efficiency of the gate drive circuit is effectively improved, the layout time is reduced, and the production schedule and production capacity are improved.

In some embodiments, the Nth gate drive circuit, the connection region 50 and the N+1th gate drive circuit all include:

The input sub-circuit is used to input the carry signal to the pull-up node PU;

an output sub-circuit for inputting a clock signal to the drive signal output end;

a first pull-up node reset subcircuit, configured to input a first reset signal to the pull-up node PU;

a second pull-up node reset subcircuit, configured to input a second reset signal to the pull-up node PU;

a pull-down node reset subcircuit, configured to input the second reset signal to the pull-down node PD;

an output reset subcircuit, configured to input the second reset signal to the drive signal output terminal;

A storage sub-circuit, the storage sub-circuit is respectively coupled to the pull-up node PU and the drive signal output end.

As shown in FIG. 19 , for example, the input sub-circuit includes a first transistor M1. The output sub-circuit includes a third transistor M3. The first pull-up node reset subcircuit includes a second transistor M2. The second pull-up node reset subcircuit includes a fourth transistor M4 and a tenth transistor M10. The pull-down node reset subcircuit includes a fifth transistor M5. The sixth transistor M6, the eighth transistor M8 and the ninth transistor M9. The output reset sub-circuit includes a seventh transistor M7 and an eleventh transistor M11. The storage sub-circuit includes a storage capacitor C.

The gate of the first transistor M1 is coupled to the input control line, the first pole of the first transistor M1 is coupled to the carry signal line, and the second pole of the first transistor M1 is coupled to the pull-up node PU coupling.

The gate of the second transistor M2 is coupled to the first reset control line, the first pole of the second transistor M2 is coupled to the pull-up node PU, and the second pole of the second transistor M2 coupled with the first reset signal line.

The gate of the third transistor M3 is coupled to the pull-up node PU, the first pole of the third transistor M3 is coupled to the clock signal line, and the second pole of the third transistor M3 is coupled to the pull-up node PU. The gate driving signal output terminal is coupled.

The gate of the fourth transistor M4 is coupled to the second reset control line, the first pole of the fourth transistor M4 is coupled to the pull-up node PU, the second pole of the fourth transistor M4 is coupled to the first The two reset signal lines are coupled.

The gate of the fifth transistor M5 is coupled to the second pole of the ninth transistor M9, the first pole of the fifth transistor M5 is coupled to the first pull-down control line, and the second pole of the fifth transistor M5 pole is coupled to the pull-down node PD.

The gate of the sixth transistor M6 is coupled to the pull-up node PU, the first pole of the sixth transistor M6 is coupled to the pull-down node PD, and the second pole of the sixth transistor M6 is coupled to the pull-up node PU. The second reset signal line is coupled.

The gate of the seventh transistor M7 is coupled to the third reset control line, the first pole of the third transistor M3 is coupled to the output end of the gate drive signal, and the first electrode of the seventh transistor M7 The two poles are coupled to the second reset signal line.

The gate of the eighth transistor M8 is coupled to the pull-up node PU, the first pole of the eighth transistor M8 is coupled to the second pole of the ninth transistor M9, and the eighth transistor M8 The second pole is coupled to the second reset signal line.

Both the gate and the first electrode of the ninth transistor M9 are coupled to the first pull-down control line.

The gate of the tenth transistor M10 is coupled to the pull-down node PD, the first pole of the tenth transistor M10 is coupled to the pull-up node PU, and the second pole of the tenth transistor M10 is coupled to the pull-up node PU. The second reset signal line is coupled.

The gate of the eleventh transistor M11 is coupled to the pull-down node PD, the first pole of the eleventh transistor M11 is coupled to the gate drive signal output terminal, and the eleventh transistor M11 The second pole is coupled to the second reset signal line.

The gate driving circuit provided by the above embodiments can realize forward and reverse scanning functions, effectively reduce noise, and can solve the problem of high-temperature reliability scanning end stripes at the same time.

Referring to FIG. 14 , taking the gate drive circuit including a 4T1C structure as an example, the gate drive circuit includes: an input subcircuit, an output subcircuit, a pull-up node reset subcircuit, an output reset subcircuit and a storage subcircuit. The input subcircuit includes a first transistor M1, the output subcircuit includes a third transistor M3, the pull-up node reset subcircuit includes a second transistor M2, and the output reset subcircuit includes a seventh transistor M7. The storage sub-circuit includes a storage capacitor C, a first end of the storage capacitor C is coupled to the pull-up node PU, and a second end of the storage capacitor C is coupled to the gate drive signal output end.

Both the gate of the first transistor M1 and the first pole of the first transistor M1 receive the input control signal Input, and the second pole of the first transistor M1 is coupled to the pull-up node PU. The gate of the second transistor M2 receives the first reset control signal Reset, the first pole of the second transistor M2 is coupled to the pull-up node PU, and the second pole of the second transistor M2 is connected to the negative Power supply signal VSS. The gate of the third transistor M3 is coupled to the pull-up node PU, the first pole of the third transistor M3 receives the clock signal CLK, the second pole of the third transistor M3 is connected to the gate drive signal output Terminal Output coupling. The gate of the seventh transistor M7 receives the first reset control signal Reset, the first pole of the seventh transistor M7 is coupled to the gate drive signal output terminal Output, and the second pole of the seventh transistor M7 is connected to Negative supply signal VSS.

M1 acts as a carry signal input, raises the potential of the pull-up node PU to open M3; M2 acts as a pull-up node PU reset after the end of the output of the line; M3 acts as a control gate drive signal output terminal Output to output the clock row by row The signal CLK is used to provide scanning signals for the corresponding scanning lines in the display area; M4 is used to reset the output terminal Output of the gate drive signal after the output of this line is completed.

As shown in Figure 15 to Figure 18, the working principle is: first M1 is turned on: Input is at high level, PU is at high level; M3 is turned on: CLK is at low level, and Output is at low level; then M1 is turned off; M3 continues to be turned on: CLK is high level, Output is high level; finally M2 and M4 are turned on, PU and Output are connected to VSS; M3 is turned off; Output is low level.

4T1C can realize the basic function of the gate drive circuit and has a simple structure.

An embodiment of the present invention also provides a display device, including the special-shaped display substrate provided in the above embodiments.

Exemplarily, the display device includes a small round watch.

Exemplarily, the display device includes a liquid crystal display device.

Exemplarily, the display device may be any product or component with a display function such as a TV, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane wait.

In the heterogeneous display substrate provided in the above embodiment, the heterogeneous layout region 21 is set to include the Nth region 30 and the N+1th region 40 arranged in sequence, and the edge between the adjacent Nth gate driving circuits in the Nth region 30 is The second direction is staggered by a distance a; the connection line between the target parts of each Nth gate drive circuit has a first angle with the first direction; the adjacent N+1th region 40 in the N+1th region 40 The gate driving circuits are staggered by a distance b along the second direction; the connection line between the target parts of each N+1th gate driving circuits has a second included angle with the first direction.

In the special-shaped display substrate provided in the above embodiment, by setting the connection line between the target parts of the at least two Nth gate drive circuits in the Nth region 30 to have a first angle with the first direction, A distance a is staggered along the second direction between two adjacent Nth gate drive circuits; The line has a second included angle with the first direction, the second included angle is different from the first included angle, and two adjacent N+1th gate drive circuits are staggered along the second direction The distances b, a and b are not equal; so that the layout structures in the Nth region 30 and the N+1th region 40 can well match the shape of the irregular layout region 21 .

Moreover, in the special-shaped display substrate provided by the above-mentioned embodiments, by setting the Nth region 30 to include at least two Nth gate drive circuits, the connection lines between the target parts of the at least two Nth gate drive circuits , has a first angle with the first direction, and the distance a between two adjacent Nth gate drive circuits is staggered along the second direction; so that the layout of each Nth gate drive circuit is the same, and each Nth gate drive circuit The layout of at least part of the signal lines around the layout of the N gate driving circuit is the same. In this way, when the Nth region 30 is laid out, the same at least two Nth gate drive circuits can be directly duplicated in the Nth region 30, and then only the signal lines with different layout modes around each Nth gate drive circuit can be adjusted. That's it.

Similarly, in the special-shaped display substrate provided in the above embodiment, by setting the N+1th region 40 to include at least two N+1th gate drive circuits, the at least two N+1th gate drive circuits The connection line between the target parts has a second included angle with the first direction, and a distance b is staggered between two adjacent N+1th gate drive circuits along the second direction; so that each N+1th gate The layout of the pole driving circuits is the same, and the layout of at least part of the signal lines around each N+1th gate driving circuit is the same. In this way, when the N+1th region 40 is laid out, the same at least two N+1th gate driving circuits can be directly copied in the N+1th region 40, and then only the N+1th gate driving circuits can be adjusted. Signal lines with different layouts around the circuit are sufficient.

Therefore, in the special-shaped display substrate provided by the above-mentioned embodiments, when the gate drive circuit is laid out in the special-shaped layout area, the gate drive circuit is effectively improved by sub-area layout without the need for step-by-step arrangement and adjustment of a large number of signal lines. The layout efficiency is reduced, the layout time is reduced, and the production schedule and production capacity are improved.

Therefore, when the display device provided by the embodiment of the present invention includes the above-mentioned special-shaped display substrate, it also has the above-mentioned beneficial effects, which will not be repeated here.

It should be noted that each embodiment in this specification is described in a progressive manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the product embodiments, the description is relatively simple, and for relevant parts, please refer to part of the description of the product embodiments.

Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the usual meanings understood by those skilled in the art to which the present invention belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Comprising" or "comprising" and similar words mean that the elements or items appearing before the word include the elements or items listed after the word and their equivalents, without excluding other elements or items. Words such as "connected", "coupled" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "Down", "Left", "Right" and so on are only used to indicate the relative positional relationship. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element, Or intervening elements may be present.

In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in any one or more embodiments or examples in an appropriate manner.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (15)

1. A special-shaped display substrate, characterized in that it includes: a display area and a non-display area surrounding the display area; the non-display area includes a heterogeneous layout area, and the heterogeneous layout area includes multi-level gates arranged in sequence A driving circuit, the heterogeneous layout area further includes an Nth region and an N+1th region arranged in sequence, and N is greater than or equal to 1; The multi-level gate drive circuit includes at least two Nth gate drive circuits arranged in sequence in the Nth region, and the connection lines between the target parts of the at least two Nth gate drive circuits, There is a first included angle with the first direction, and a distance a is staggered between two adjacent Nth gate drive circuits along the second direction; the second direction intersects the first direction; The multi-stage gate drive circuit further includes at least two N+1th gate drive circuits arranged in sequence in the N+1th region, and the targets of the at least two N+1th gate drive circuits are The connecting line between the parts has a second included angle with the first direction, and the second included angle is different from the first included angle, between two adjacent N+1th gate drive circuits Staggered by a distance b along the second direction, a and b are not equal. 2. The heterogeneous display substrate according to claim 1, wherein the heterogeneous layout region further comprises a connection region, at least part of the connection region is located between the Nth region and the N+1th region , the connection area includes at least one connection gate drive circuit; The connecting gate driving circuit and the adjacent Nth gate driving circuit are staggered by a distance c along the second direction, and c is equal to or not equal to a; and / or, The connecting gate driving circuit and the adjacent (N+1)th gate driving circuit are staggered by a distance d along the second direction, and d and b are equal or not equal. 3. The special-shaped display substrate according to claim 1, wherein the distance a is proportional to the first included angle, and the distance b is proportional to the second included angle. 4. The special-shaped display substrate according to claim 1, characterized in that, The Nth gate drive circuit includes an Nth output transistor, and in two adjacent Nth gate drive circuits, the gates of the Nth output transistors are staggered by a distance a along the second direction; The N+1th gate drive circuit includes an N+1th output transistor, and in two adjacent N+1th gate drive circuits, the gates of the N+1th output transistors are staggered along the second direction distance b. 5. The special-shaped display substrate according to claim 2, wherein the display area comprises a circular display area, the special-shaped layout area comprises an arc-shaped layout area, and the display areas are opposite to each other along the second direction. Both sides are provided with the arc-shaped layout area, and the arc-shaped layout area includes the Nth area, the connection area and the N+1th area. 6. The special-shaped display substrate according to claim 5, wherein the arc-shaped layout area includes the first area to the N+Xth area, and X is greater than or equal to 2; The arc-shaped layout area is divided into three parts, the first part area includes the first area to the Mth area, the second part area includes the M+1th area to the M+Cth area, and the third part area includes the M+Cth area +1 area to N+X area, 1≤M<N+X, M+1≤M+C<N+X, M+C+1≤N+X; In the first partial area, the angle between the connection line between the target parts of the gate driving circuit in each area and the first direction is between 60° and 80°; In the second partial area, the angle between the connection line between the target parts of the gate driving circuit in each area and the first direction is between 10° and 25°; In the third partial area, the angle between the connection line between the target parts of the gate driving circuit in each area and the first direction is between 60° and 80°. 7. The special-shaped display substrate according to claim 6, characterized in that, In the first partial area, from the first area to the Mth area, the distance between the gate drive circuits in each area along the second direction is gradually reduced; In the third partial area, in the M+C+1 th area to the N+X th area, the distances between the gate driving circuits in each area along the second direction gradually become larger. 8. The special-shaped display substrate according to claim 6, characterized in that, In the first partial area, the distance between the gate drive circuits in each area is staggered along the second direction between 150 microns and 300 microns; In the second partial area, the distance between the gate drive circuits in each area is staggered along the second direction between 30 microns and 60 microns; In the third partial area, the gate drive circuits in each area are staggered along the second direction by a distance between 150 microns and 300 microns. 9. The special-shaped display substrate according to claim 5, wherein the arc-shaped layout area includes: Y clock signal lines and the multi-stage gate drive circuit; each stage of the gate drive circuit includes a gate Pole drive signal output terminal, clock signal input terminal, input signal terminal and reset terminal; The clock signal input end of the Y×(B-1)+F stage gate drive circuit is coupled to the F clock signal line, Y is an integer greater than or equal to 2, F is a positive integer less than or equal to Y, and B is an integer greater than or equal to 1. 10. The special-shaped display substrate according to claim 9, characterized in that, In the multi-level gate drive circuit: the gate drive signal output terminal of the A-level gate drive circuit is connected to the input signal terminal of the A+E-level gate drive circuit and the reset of the A-E-level gate drive circuit respectively. Terminal coupling, A is an integer greater than or equal to 3, and E is a positive integer less than A; The multi-stage gate drive circuit is divided into multiple groups of gate drive circuits arranged in sequence, each group of gate drive circuit groups includes at least two adjacent stages of gate drive circuits; the Nth region includes at least one group of gate drive circuits. Pole driving circuit group, the at least one group of gate driving circuit groups includes the Nth gate driving circuit; the N+1th region includes at least one group of gate driving circuit groups, and the at least one group of gate driving circuits The group includes the N+1th gate driving circuit. 11. The special-shaped display substrate according to claim 9, wherein the Nth region includes a plurality of Nth subregions, and the Nth subregion includes the corresponding Nth gate drive circuit and signal line; the layout structure in the Nth sub-region where the Nth gate drive circuit connected to the same clock signal line is located is the same; The N+1th region includes a plurality of N+1th subregions, and the N+1th subregion includes the corresponding N+1th gate drive circuit and signal lines; the N+1th subregions connected to the same clock signal line The layout structure in the N+1th sub-region where the N+1 gate driving circuit is located is the same. 12. The special-shaped display substrate according to claim 11, characterized in that, In each Nth sub-region where the Nth gate drive circuit connected to different clock signal lines is located, the layout of different clock signal lines is different; In each of the N+1th sub-regions where the N+1th gate driving circuit connected to different clock signal lines is located, different clock signal lines are laid out in different ways. 13. The special-shaped display substrate according to claim 11, wherein the layout structures of the gate drive circuits at all levels are completely the same, and the layout of the signal lines in the Nth sub-region and the N+1 sub-region is Not exactly the same. 14. The special-shaped display substrate according to claim 2, wherein the Nth gate drive circuit, the connection region and the N+1th gate drive circuit all comprise: The input subcircuit is used to input a carry signal to the pull-up node; an output sub-circuit for inputting a clock signal to the drive signal output end; a first pull-up node reset subcircuit, configured to input a first reset signal to the pull-up node; a second pull-up node reset subcircuit, configured to input a second reset signal to the pull-up node; a pull-down node reset subcircuit, configured to input the second reset signal to the pull-down node; an output reset subcircuit, configured to input the second reset signal to the drive signal output terminal; A storage sub-circuit, the storage sub-circuit is respectively coupled to the pull-up node and the drive signal output end. 15. A display device, characterized by comprising the special-shaped display substrate according to any one of claims 1-14.

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