CN115758969B - An FPGA that uses built-in long-line modules to achieve long-distance wiring - Google Patents
An FPGA that uses built-in long-line modules to achieve long-distance wiring Download PDFInfo
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Abstract
本申请公开了一种利用内置长线模块实现长距离布线的FPGA，涉及FPGA领域，该FPGA在阵列中内置长线模块，并利用高层金属走线的连续长线实现长线模块之间的信号互连从而形成长线模块组，不会过多的额外面积增加，长线模块之间的连续长线的跨越距离可以较大，且由于采用高层金属走线具有较宽较厚、间距较大、阻抗小、时延小，可以更好地达成布线需求，尤其适用于FPGA特别是大规模FPGA内部距离较远的资源模块之间的布线需求，从而加快FPGA的设计。
The present application discloses an FPGA that utilizes a built-in long-line module to realize long-distance wiring, and relates to the field of FPGA. The FPGA has a built-in long-line module in an array, and utilizes continuous long lines of high-level metal routing to realize signal interconnection between the long-line modules to form a long-line module group, without excessive additional area increase. The spanning distance of the continuous long lines between the long-line modules can be relatively large, and because the high-level metal routing is wider and thicker, has a larger spacing, a smaller impedance, and a smaller delay, the wiring requirements can be better met. The FPGA is particularly suitable for the wiring requirements between resource modules that are far apart inside the FPGA, especially a large-scale FPGA, thereby accelerating the design of the FPGA.
Description
Technical Field
The invention relates to the field of FPGA, in particular to an FPGA for realizing long-distance wiring by using a built-in long-line module.
Background
The FPGA (Field Programmable GATE ARRAY ) internally comprises a large number of resource modules such as CLB, BRAM, DSP, IOB, interconnection modules INT are distributed around the resource modules, and the input and output of each resource module are connected with other resource modules through the corresponding interconnection modules INT, so that a wiring framework of which the plane is unfolded to the whole FPGA is formed.
In the most common wiring architecture of the FPGA at present, each interconnection module INT is in a rectangular structure and includes four wires in four directions, so that each interconnection module INT can be connected with other interconnection modules INT in four directions through the wires in a vertical direction or a horizontal direction. Each direction of the interconnection module INT includes a plurality of line segments with different lengths, so that the interconnection module INT can reach other interconnection modules INT with different distances. Then, through the serial connection and steering effect of the switch boxes in the interconnection module INT, a plurality of line segments can form a required wiring path, so that the connection of any two resource modules can be realized.
In FPGAs, especially high-capacity FPGAs, due to the various types and numbers of resource modules, the user design is complex, even after various layout optimization algorithms are processed, the situation that the path distance between the resource modules is larger to be achieved is unavoidable, especially when the path involves a specific module (if a large IP core at a specific position is blocked and needs to be bypassed), the distance between two resource modules can reach 200 unit lengths, if the path is achieved only through the line segments of the unit length of the interconnection module INT, the line segments of 200 unit lengths need to be connected in series, the path delay obtained through many times of series connection is larger, and the problem that the path time sequence is difficult to meet during wiring is often caused.
In order to avoid this problem, it is necessary to configure the interconnection module INT to support long-distance line segments, so as to reduce the number of serial connection times, and if the interconnection module INT can support line segments with a length of 200 units in an ideal state, a path can be realized without going through serial connection, thereby solving the above problem. But for ease of implementation, the interconnect modules INT are identical at any location in the FPGA so that the wiring can be spread out flat across the full slice of the FPGA in the same uniform manner. Under the constraint that each interconnection module INT needs to be designed to be the same, long-distance line segments need to be realized by adopting a mode of staggered twisted wire (wire-twisting), and each line segment with a length of L needs to occupy L metal line channels (Track). For example, taking a line segment with a length of 4 as an example, it is required to implement the method by using staggered twisted lines as shown in fig. 1, each dashed box represents a range of interconnection modules INT, where a distance from a start point S to an end point T is 4, and each interconnection module INT has a start point that can be connected to an end point with a distance of 4. Similarly, to support a line segment of length 12, 12 wire traces are required. The more occupied metal lines Track occupy a larger area, and the above assumption that the interconnect module INT supports line segments with a length of 200 units is too costly to be implemented. Therefore, in order to balance the area cost, the maximum length of the line segments is generally limited, for example, the line segments with the maximum implementation length of 18 are usually implemented at present, and a plurality of long-distance line segments are still required to be connected in series between the long-distance resource modules to obtain paths, for example, 20 line segments with the length of 10 units are required to be connected in series to implement the paths with the length of 200 units, so that the problem that the path time sequence is difficult to meet still exists, and the design period of the FPGA is prolonged.
Disclosure of Invention
The inventor provides an FPGA for realizing long-distance wiring by using a built-in long-line module aiming at the problems and the technical requirements, and the technical scheme of the application is as follows:
An FPGA for realizing long-distance wiring by utilizing a built-in long-line module is provided with at least two long-line modules which are connected through continuous long lines of high-layer metal wiring, wherein one long-line access end of the long-line module serving as an access module is connected to a starting point of the continuous long line through a stacking hole, and the other long-line output end of the long-line module serving as an output module is connected to an end point of the continuous long line through the stacking hole;
In the process of wiring each original net in the user input netlist, for any net to be wired which meets a preset condition, connecting a net start point of the net to be wired to a long line module serving as an access module, connecting a net end point of the net to be wired to a corresponding long line module serving as an exit module, and connecting a net start point of the net to be wired to a net end point of the net to be wired through a wiring path realized by the access module, the continuous long line and the exit module.
The further technical scheme is that two long-line modules with connection relation are arranged in the same row or the same column in the FPGA, and continuous long lines for realizing connection of the two long-line modules are in a linear wiring mode.
The further technical scheme is that two long-line modules with connection relation are arranged in different rows and different columns in the FPGA, and continuous long lines for realizing connection of the two long-line modules are in a broken line wiring mode.
The further technical scheme is that a long wire access end of at least one long wire module serving as an access module exists in the FPGA, is connected to the starting points of different continuous long wires through stacking holes, and is connected to the long wire outlet ends of different long wire modules serving as outlet modules through different continuous long wires.
The technical scheme is that the FPGA is internally provided with a plurality of long-line modules, and the plurality of long-line modules are randomly and discretely arranged at different positions in the FPGA or are arranged at different positions in the FPGA according to a preset arrangement structure.
The method for determining the network to be wired meeting the preset condition in the process of wiring each original network in the user input netlist comprises the following steps of, for any traversed original network:
Estimating a first delay when connecting a net start point of an original net to a net end point of the original net via a wiring path implemented by an interconnection module INT;
When the first time delay exceeds a time delay threshold value and the original wire net has a corresponding long wire module group meeting wiring conditions, determining the original wire net as a wire net to be wired meeting preset conditions, and realizing the wiring path of the wire net to be wired by utilizing the corresponding long wire module group meeting the wiring conditions; a long wire module group comprises two long wire modules which are connected through continuous long wires of high-layer metal wires.
The further technical scheme is that for any traversed original net:
When the first time delay T1 of the original wire network exceeds a time delay threshold value, a corresponding long wire module group meeting wiring conditions exists in the wire network to be wired, and the time delay difference T1-T2 between the second time delay T2 of the original wire network and the first time delay T1 reaches a preset threshold value, determining the original wire network as the wire network to be wired meeting the preset conditions, and realizing the wiring path of the wire network to be wired by utilizing the corresponding long wire module group meeting the wiring conditions;
The second time delay T2 of the original net is the time delay when the net start point of the original net is connected to the net end point of the original net through the corresponding long line module group meeting the wiring condition.
The method comprises the further technical scheme that the distance between an access module in a long-line module group which corresponds to any one original line net and meets the wiring condition and the line net starting point of the original line net does not exceed a first preset distance, and the distance between an access module in the long-line module group which corresponds to the original line net and meets the wiring condition and the line net ending point of the original line net does not exceed a second preset distance.
The method for determining the long line module group meeting the wiring condition corresponding to any one original line net comprises the following steps:
When the access module does not exist in the range of the first preset distance of the net start point of the original net and/or the access module does not exist in the range of the second preset distance of the net end point of the original net, determining that the original net does not exist a corresponding long line module group meeting the wiring condition, otherwise:
traversing an ith access module positioned in a range of a first preset distance of a wire network starting point of an original wire network, wherein i is a parameter and the starting value of i is 1;
traversing a j-th output module positioned in a range of a second preset distance of a net end point of the original net, wherein j is a parameter and the initial value of j is 1;
when the ith access module is connected with the jth access module through a continuous long line Lij, determining that a long line module group which corresponds to an original wire net and meets wiring conditions comprises the ith access module, the continuous long line Lij and the jth access module;
When the ith access module and the jth exit module are not connected and all the exit modules within the range of the second preset distance of the net end point of the original net are not traversed, enabling j=j+1 and executing the step of traversing the jth exit module within the range of the second preset distance of the net end point of the original net again;
Resetting j=1 when the i-th access module and the j-th access module are not connected and all the access modules within the range of the second preset distance of the net end point of the original net are traversed and all the access modules within the range of the first preset distance of the net start point of the original net are not traversed, enabling i=i+1 and executing the step of traversing the i-th access module within the range of the first preset distance of the net start point of the original net again;
When the ith access module and the jth access module are not connected, traversing all the access modules within the range of the second preset distance of the net end point of the original net, and traversing all the access modules within the range of the first preset distance of the net start point of the original net, determining that the original net does not have a corresponding long line module group meeting wiring conditions.
The further technical scheme is that when traversing all access modules positioned in a range of a first preset distance from the network starting point of an original network, the access modules are sequentially traversed according to the sequence from near to far from the network starting point; while traversing all the pickup modules that are within a second predetermined distance from the net end of the original net, the traversing is sequentially performed in order of near to far distance from the net end.
The beneficial technical effects of the application are as follows:
The application discloses an FPGA for realizing long-distance wiring by utilizing a built-in long-line module, which is internally provided with the long-line module in an array, and utilizes continuous long lines of high-layer metal wiring to realize signal interconnection among the long-line modules so as to form a long-line module group, so that the spanning distance of the continuous long lines among the long-line modules can be larger without excessive extra area increase, and the wiring requirement can be better finished due to the fact that the high-layer metal wiring has wider and thicker spacing, small impedance and small time delay, and the FPGA is particularly suitable for the wiring requirement among resource modules with longer internal distance in the FPGA, so that the design of the FPGA is accelerated.
Drawings
FIG. 1 is a schematic diagram of a conventional FPGA for implementing long-distance line segments using staggered twisted-pair lines.
FIG. 2 is a schematic layout of a long line module within an FPGA and a schematic connection before a portion of the long line module in an embodiment of the application.
Fig. 3 is a schematic layout diagram of a long line module inside an FPGA and a schematic connection diagram before a part of the long line module according to another embodiment of the present application.
Fig. 4 is a schematic diagram of the structure of a single filament module in one embodiment of the application.
Fig. 5 is a schematic diagram of connection of the long wire module a, the long wire module B, and the long wire module C in fig. 2.
FIG. 6 is a flow chart of a routing process for implementing a network to be routed based on a long wire module in one embodiment of the application.
FIG. 7 is a flow chart of a method for determining a set of long wire modules corresponding to an original net in accordance with one embodiment of the present application.
Detailed Description
The following describes the embodiments of the present application further with reference to the drawings.
The application discloses an FPGA for realizing long-distance wiring by utilizing a built-in long-line module, wherein the FPGA internally comprises various resource modules and interconnection modules INT around the resource modules, and additional hardware resources, namely the long-line module, are added. The long line module can be newly added at a required position on the basis of the original internal array scale of the FPGA. Or in order not to change the original scale of the FPGA, the resource module at the required position in the original internal array scale of the FPGA is replaced by the long-line module, and the CLB module can be replaced by the long-line module, so that the long-line module is fused into the original wiring architecture of the FPGA. Referring to fig. 2 for example, the resource modules in the FPGA are generally arranged to form a row-column structure, fig. 2 is an example of replacing CLB modules at specific positions in the row-column structure with long-line modules, the hatched modules in fig. 2 are long-line modules, and the other modules are original resource modules in the FPGA, and fig. 2 is only for illustration, so that the size distinction between different resource modules is not shown.
The FPGA has at least two long-line modules, and there are generally more, and fig. 2 illustrates that 9 long-line modules are built in. The plurality of long-line modules arranged in the FPGA are randomly and discretely arranged at different positions in the FPGA, or are arranged at different positions in the FPGA according to a preset arrangement structure. The predetermined arrangement may be varied, such as one of the possible arrangements shown in fig. 2, with equidistant spacing between the long wire modules. Fig. 3 is another possible layout structure, where long-line modules are arranged in columns, and one or more columns of long-line modules are built into the FPGA, and fig. 3 is an example of a two-column long-line module built into the FPGA.
Each long wire module is connected with at least one other long wire module through continuous long wires of high-layer metal wires. For any two long wire modules which are connected through continuous long wires of high-level metal wires, one long wire access end of the long wire module serving as an access module is connected to a starting point of the continuous long wire through a stacking hole (via stack), and the other long wire outlet end of the long wire module serving as an outlet module is connected to an ending point of the continuous long wire through the stacking hole. Referring to fig. 2 and 5 in combination, the long wire module a and the long wire module B are connected through a continuous long wire L1 of a high-level metal wire, the long wire module a is used as an access module, a long wire access end of the long wire module a is connected to a high-level metal layer through a stacking hole (via stack), and is connected to the long wire module B through the continuous long wire L1, and then connected to a metal layer of the long wire module B and a long wire outlet end of the long wire module B, which is used as an outlet module, in fig. 5, the long wire module a and the long wire module B are located in the same metal layer.
In order to facilitate the long-line module to be better integrated into the original winding framework of the FPGA, the long-line module is obtained based on structural improvement of the interconnection module INT, the interconnection module INT is internally provided with a full-intercommunication switch array, wires are led out in the upper, lower, left and right directions, and bidirectional wires are led out in each direction. The long-line module is obtained by adding a long-line outlet end and/or a long-line inlet end on the basis of the interconnection module INT, and the long-line outlet end and/or the long-line inlet end can realize the switching of the communication line through the built-in full-intercommunication switch array as the original externally-led connection line of the interconnection module INT, and please refer to the schematic diagram shown in fig. 4. Because the long-line module is based on the structural design of the interconnection modules INT, the long-line module can be connected with the surrounding interconnection modules INT in a traditional connection mode between the interconnection modules INT. One long wire module may be added with only a long wire outlet end and may be implemented as only an outlet module, or one long wire module may be added with only a long wire inlet end and may be implemented as only an inlet module, or one long wire module may be added with both a long wire outlet end and a long wire inlet end to form an inlet module or an outlet module according to actual needs, as illustrated in fig. 4. For example, in fig. 2, the long wire module a is connected to the long wire module B as an access module, and is connected to the long wire module D as an exit module.
In addition, one or more long wire access ends can be added to one long wire module, and one or more long wire access ends can also be added to one long wire module. The structures of different long-line modules can be the same or different, that is, different long-line modules can be added with different numbers of long-line outgoing ends and/or long-line incoming ends, but for convenience of unified manufacturing, all long-line modules are generally designed into the same module structure, for example, fig. 5 uses the module structure of the long-line module A, B, C as the same, and each long-line module is added with one long-line outgoing end and one long-line incoming end on the basis of the structure of the interconnection module INT. Since the long wire outgoing end and/or the long wire incoming end are continuous long wires connected to the high-level metal layer through the stacking holes, the positions and directivities of the long wire outgoing end and the long wire incoming end on the long wire module are not greatly affected, and fig. 5 is only a schematic case.
In one embodiment, two long line modules with connection relationship are arranged in the same row or column in the FPGA, such as the long line module a and the long line module B in fig. 2 and 5, and the long line module a and the long line module D in fig. 2. The continuous long line L1 for realizing the connection of the two long line modules is in a linear wiring form, and the continuous long line L1 in the linear wiring form can realize the shortest path of the long line module a and the long line module B, so that the delay is smaller. It should be noted that, in fig. 2, the continuous long line L3 between the long line module a and the long line module D spans multiple resource modules and other long line modules, but the continuous long line and the modules are not in the same metal layer, so there is no connection relationship in practice.
In another embodiment, two long line modules in a connection relationship are arranged in different rows and in different columns within the FPGA, such as long line module a and long line module C in fig. 2 and 5. The continuous long line for connecting the two long line modules is in the form of a broken line, typically consisting of a run along the rows and a run along the columns, but is also continuous and uninterrupted, please refer to the continuous long line L2 in fig. 2 and 5, which is in the form of a broken line. The specific routing of the continuous long wire is configured according to the actual situation, but since the continuous long wire is used for realizing the routing, the distance should be reduced as much as possible to reduce the transmission delay. Likewise, the continuous long line L2 between the long line module a and the long line module C in fig. 2 is not connected to other modules through which it passes.
In another embodiment, one long line module may be further connected to different other long line modules through a plurality of different continuous long lines, typically one access module is connected to different outgoing modules through a plurality of different continuous long lines, that is, the long line access end of at least one long line module as an access module in the FPGA is connected to the starting point of the different continuous long lines through the stacking hole, and is connected to the long line outgoing end of the different long line modules as an outgoing module through the different continuous long lines. For example, in fig. 5, the long wire access end of the long wire module a is simultaneously connected to the start points of the continuous long wire L1 and the continuous long wire L2 through the stacking hole, so as to be connected to the long wire outlet end of the long wire module B through the continuous long wire L1, and to be connected to the long wire outlet end of the long wire module C through the continuous long wire L2.
The continuous long wire in the application is continuous and uninterrupted between the long wire access end of the corresponding access module and the long wire outlet end of the outlet module, so as to realize point-to-point direct connection no matter in a straight line or broken line wiring mode. The continuous long wire adopts a high-layer metal wire, the length of the continuous long wire is not limited, the long wire can span a larger distance, and the large area cost caused by occupying too many metal wire channels like the long-distance wire segment of the interconnection module INT is avoided, and the high-layer metal wire is wider and thicker, has larger spacing, small impedance and small time delay, so that the continuous long wire has better connection performance.
For the FPGA with the built-in long wire module, based on the excellent characteristics of the long wire module and the continuous long wires among the long wire modules, the long wire module can be utilized to realize long-distance wiring, so that a better wiring result can be quickly achieved, and the realized wiring process is as follows:
In the process of wiring each original net in the user input netlist, for any net to be wired which meets a predetermined condition, a net start point Ns of the net to be wired is connected to a long line module serving as an access module, a net end point Nt of the net to be wired is connected to a corresponding long line module serving as an exit module, and a net start point Ns of the net to be wired is connected to the net end point Nt of the net to be wired through wiring paths realized by the access module, the continuous long lines and the exit module. Whether net start Ns or net end Nt, one case may be directly connected to the long line module, and the other case may require connection to the long line module via the other interconnect module INT. For example, referring to fig. 3, the net start Ns of the to-be-wired net is connected to the long wire module G, and is connected to the long wire module J via the continuous long wire L6, and then connected to the net end Nt of the to-be-wired net, so as to implement wiring.
Two long wire modules connected through continuous long wires of high-level metal wiring form a long wire module group, one long wire module group can be used for realizing one wiring path, but resources of the long wire module group in the FPGA are limited, so that the long wire module group is generally utilized for realizing the related wiring path, and other common wiring paths are still realized in a conventional manner through the interconnection module INT. It is therefore necessary to determine which nets are routed using the set of long wire modules and which are routed using the set of long wire modules, then in performing the routing algorithm, please refer to the flowchart shown in FIG. 6 for any one of the original nets traversed:
firstly, a first time delay T1 when a wire network starting point of the original wire network is connected to a wire network end point of the original wire network through a wire network route realized by an interconnection module INT is estimated, when the first time delay T1 exceeds a time delay threshold Tmax, namely T1 is more than Tmax, and when the original wire network is determined to have a corresponding long wire module group meeting the wire network condition, the original wire network is determined to be the wire network to be wired, which meets the preset condition, and the wire network route of the wire network to be wired is realized by utilizing the corresponding long wire module group meeting the wire network condition.
In another embodiment, when T1 > Tmax is determined and the original net has a corresponding set of long line modules that meet the routing condition, the original net is not routed directly with the set of long line modules, but rather the second delay T2 is further estimated when the net start point Ns of the original net is connected to the net end point Nt of the original net via the corresponding set of long line modules that meet the routing condition. When it is further determined that the delay difference T1-T2 between the second delay T2 and the first delay T1 of the original net reaches a predetermined threshold Δt, that is, T1-T2 > - Δt, the original net is determined to be the net to be wired that satisfies the predetermined condition, and the wiring path of the net to be wired is implemented by using the corresponding long line module group that satisfies the wiring condition. If T1-T2 is less than or equal to DeltaT, the time delay can be optimized to a small extent only when the wiring path of the network to be wired is realized by using the long wire module group, and the valuable long wire module group is considered to be not worth to be used for wiring, and the wiring path of the network to be wired is still realized in a conventional manner by using the interconnection module INT instead.
In either of the above embodiments, the distance between the access module in the set of long line modules that meet the routing condition corresponding to any one of the original nets and the net start Ns of that original net does not exceed a first predetermined distance, and the distance between the access module in the set of long line modules that meet the routing condition corresponding to that original net and the net end Nt of that original net does not exceed a second predetermined distance. Thus, the time delay between the network start point Ns and the access module and the time delay between the network end point Nt and the access module can be controlled, and the overall time delay from the network start point Ns to the network end point Nt can be reduced. The method for determining the long wire module group meeting the wiring condition corresponding to any one of the original nets includes the following steps, please refer to fig. 7:
(1) An access module within a first predetermined distance of net start point Ns of the original net and an access module within a second predetermined distance of net end point Nt of the original net are first determined.
(2) And directly determining that the original wire net does not have a corresponding long wire module group meeting wiring conditions when no access module exists in the range of the first preset distance of the wire net starting point Ns of the original wire net and/or no access module exists in the range of the second preset distance of the wire net ending point Nt of the original wire net.
(3) When at least one access module exists in the range of the first preset distance of the net start point Ns of the original net and at least one access module exists in the range of the second preset distance of the net end point Nt of the original net, the traversal process of the following steps (4) - (9) is executed.
(4) Traversing an ith access module located within a first predetermined distance of a net start point Ns of the original net, i being a parameter and a start value of i being 1.
(5) Traversing a j-th output module positioned in a range of a second preset distance of a net end point Nt of the original net, wherein j is a parameter and the initial value of j is 1;
(6) When the ith access module is connected with the jth access module through a continuous long line Lij, determining that the long line module group which corresponds to the original wire net and meets the wiring condition comprises the ith access module, the continuous long line Lij and the jth access module, and then finishing traversing.
(7) When the ith access module is not connected with the jth access module and all the access modules in the range of the second preset distance of the net end point Nt of the original net are not traversed, enabling j=j+1 and executing the step of traversing the jth access module in the range of the second preset distance of the net end point of the original net again, and continuing traversing the next access module near the net end point Nt.
(8) When the i-th access module and the j-th access module are not connected and all the access modules within the range of the second preset distance from the net end Nt of the original net are traversed, but all the access modules within the range of the first preset distance from the net start Ns of the original net are not traversed, resetting j=1, enabling i=i+1 and executing the step of traversing the i-th access module within the range of the first preset distance from the net start of the original net again, and continuing traversing the next access module near the net start Ns.
(9) When the ith access module and the jth access module are not connected and all the access modules within the range of the second preset distance of the net end Nt of the original net are traversed, and all the access modules within the range of the first preset distance of the net start Ns of the original net are traversed, determining that the original net does not have a corresponding long line module group meeting wiring conditions.
In the above process, when there are a plurality of access modules within the range of the first predetermined distance from the net start Ns, each of the access modules may be sequentially traversed in a random order, or sequentially traversed in an order from near to far from the net start. Similarly, when there are multiple outbound modules within a second predetermined distance from the net endpoint Nt, each outbound module may be traversed sequentially in a random order, or sequentially in a near-to-far order with respect to the distance from the net endpoint Nt. The traversal order of the plurality of long line modules at the same distance may be randomly selected.
For example, in the example shown in fig. 3, a continuous long line L4 is provided between the long line module E and the long line module H, a continuous long line L5 is provided between the long line module F and the long line module I, a continuous long line L6 is provided between the long line module G and the long line module J, and a continuous long line L7 is provided between the long line module K and the long line module L. The range of the first preset distance of the net starting point Ns comprises three long-line modules serving as access modules, namely a long-line module E, a long-line module F and a long-line module G. The second preset distance range of the net endpoint Nt comprises two long-line modules which are taken as the outgoing modules, namely a long-line module J and a long-line module L. Then first traverse the longline module F closest to the net start Ns and traverse the longline module J closest to the net end Nt. Since there is no continuous long line between the long line module F and the long line module J, the next long line module L closest to the net endpoint Nt is traversed, and there is no continuous long line between the next long line module L and the long line module F.
Then the next long line module closest to the net start Nt is traversed, and the long line module G is randomly selected at this time, since the distance between the long line module E and the long line module G at the net start Nt is the same. And traversing a long line module J closest to the net endpoint Nt, and determining that a continuous long line L6 exists between the long line module G and the long line module J, wherein the long line module group which corresponds to the original net and meets wiring conditions comprises the long line module G, the continuous long line L6 and the long line module J.
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