CN115768129B - Method for forming MRAM device and MRAM device - Google Patents
Method for forming MRAM device and MRAM device Download PDFInfo
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- CN115768129B CN115768129B CN202211682071.5A CN202211682071A CN115768129B CN 115768129 B CN115768129 B CN 115768129B CN 202211682071 A CN202211682071 A CN 202211682071A CN 115768129 B CN115768129 B CN 115768129B
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Abstract
The invention relates to a method for forming an MRAM device and the MRAM device. In the forming method, an MTJ (magnetic resonance circuit) layer is formed above a lower metal layer on a semiconductor substrate, an MTJ component is formed through first etching, a part of bottom electrode layer or a part of via hole below the MTJ layer is exposed, then conductive redeposition of the side wall of the MTJ component and a part of the bottom electrode layer or a part of via hole which is exposed around the MTJ component are oxidized through oxidation treatment, then second etching with an incident etching angle smaller than 45 DEG is performed, an oxide layer formed on the side wall of the MTJ component is removed, the incident etching angle of the second etching is smaller, and the oxide layer on the side wall of the MTJ component and a side wall damage part which possibly affects the performance of the MTJ component are conveniently and fully removed, so that the reliability of the MTJ component is ensured.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and in particular, to a method for forming an MRAM device and an MRAM device.
Background
A magnetoresistive random access memory (hereinafter referred to as MRAM device) is a new type of nonvolatile memory, and a core component (component) thereof is a magnetic tunnel junction (MagneticTunnelJunction, hereinafter referred to as MTJ component). MTJ components mainly include stacked fixed, tunneling barrier, and free layers, typically with fixed (or "pinned") magnetic orientations and free layers with varying (or "free") magnetic orientations that can be switched between two or more different magnetic polarities. Due to magnetic tunneling, the resistance of the MTJ element varies with the variable magnetic polarity, and in operation, the Spin Transfer Torque (STT) effect can be used to change or switch magnetic polarities and enable storage of information.
In forming MTJ devices, a stack for fabricating the MTJ device is typically formed over a metal layer formed on a semiconductor substrate and then etched to form discrete MTJ devices, some of the metal material resulting from the etching process may be deposited to the sidewalls of the MTJ device, possibly causing the fixed and free layers of the MTJ device to communicate across the tunneling barrier layer, resulting in a short circuit point for the MRAM device. To avoid shorting problems caused by redeposited metal material to the MTJ element sidewalls, US11031548B2 discloses a method for reducing MTJ element sidewall material intermixing by oxidation, wherein the metal material redeposited to the MTJ element sidewalls is oxidized and then the MTJ element sidewalls are etched using ion beam etching (ionbeametch, IBE) at a large angle of incidence etch (e.g., 50 ° -90 °) to remove the MTJ element sidewall oxide and the MTJ element sidewall damage.
However, in the MRAM device of the advanced process node, the distance (pitch) between the MTJ elements laterally arranged on the semiconductor substrate is small, and the shadow barrier (shadow) exists on the side wall of the MTJ element etched at a large incident etching angle, which makes it difficult to remove the side wall oxide layer and the side wall damaged portion of the MTJ element by the above method, and is detrimental to the reliability of the MTJ element.
Disclosure of Invention
In order to reduce the risk of the MRAM device creating a short circuit point while ensuring the reliability of the MTJ components, the present invention provides a method of forming an MRAM device and an MRAM device.
In one aspect, the present invention provides a method of forming at least one MRAM device, the method comprising:
forming a first dielectric layer over a lower metal layer on a semiconductor substrate;
Forming a via hole penetrating through the first dielectric layer and a bottom electrode layer, wherein the bottom electrode layer is filled in the via hole and covers the first dielectric layer, and the bottom electrode layer is connected with the lower metal layer through the via hole;
Forming an MTJ stack on the bottom electrode layer;
Performing first etching on the MTJ (magnetic tunnel junction) stack layer to form an MTJ component corresponding to the via hole and expose part of the bottom electrode layer around the MTJ component, wherein conductive redeposition is formed on the side wall of the MTJ component through the first etching;
Performing an oxidation treatment to form a sidewall oxide layer on the sidewall of the MTJ element by oxidizing the conductive redeposit, and forming a bottom oxide layer around the MTJ element by oxidizing the exposed portion of the bottom electrode layer, the bottom electrode layer under the MTJ element and the bottom oxide layer not oxidized forming a bottom electrode, and
And performing second etching to remove the side wall oxide layer, wherein the incident etching angle of the second etching is smaller than 45 degrees.
In another aspect, the present invention provides an MRAM device formed by the above method, the MRAM device comprising:
A first dielectric layer formed over a lower metal layer on a semiconductor substrate;
a via hole penetrating the first dielectric layer;
the bottom electrode layer is filled in the via hole and covers the first dielectric layer, and is connected with the lower metal layer through the via hole;
an MTJ element formed on the bottom electrode layer;
A hard mask formed over the MTJ element;
a top electrode formed on the hard mask and connected to the MTJ element;
a cladding material layer formed on the side wall of the MTJ part, the exposed surface of the bottom electrode layer and the exposed surface of the first dielectric layer, and
And a second dielectric layer formed on the cladding material layer, the second dielectric layer covering the MTJ element and filling a gap around the MTJ element.
In yet another aspect, the present invention provides a method of forming at least one MRAM device, the method comprising:
Forming a first dielectric layer above a lower metal layer on a semiconductor substrate, and forming a via hole penetrating through the first dielectric layer;
forming an MTJ stack on the first dielectric layer;
Performing first etching on the MTJ stack to form an MTJ component corresponding to a central region of the via hole and expose a portion of the via hole around the MTJ component, wherein, through the first etching, a conductive redeposition is formed on a side wall of the MTJ component;
Performing an oxidation treatment to form a sidewall oxide layer on the sidewall of the MTJ element by oxidizing the conductive redeposit, and forming a bottom oxide layer around the MTJ element by oxidizing the exposed portion of the via hole around the MTJ element, and
And performing second etching to remove the side wall oxide layer, wherein the incident etching angle of the second etching is smaller than 45 degrees.
In the method for forming the MRAM device, the MTJ stack layer is stacked above the lower metal layer on the semiconductor substrate, after the MTJ component is formed through first etching, part of the bottom electrode layer or part of the via hole below the MTJ stack layer is exposed, then conductive redeposits formed on the side wall of the MTJ component and part of the bottom electrode layer or part of the via hole exposed around the MTJ component are oxidized through oxidation treatment, then second etching with an incident etching angle smaller than 45 degrees is performed, the oxide layer formed on the side wall of the MTJ component is removed, the incident etching angle of the second etching is smaller, the oxide layer on the side wall of the MTJ component and the damage part which possibly affects the performance of the MTJ component are conveniently and fully removed, and the reliability of the MTJ component is ensured. In addition, since the exposed bottom electrode layer portion or via hole portion around the MTJ element is oxidized, the etching product redeposited to the side wall of the MTJ element through the second etching is not conductive, and the risk of generating a short-circuit point of the MRAM device can be reduced.
Drawings
FIG. 1 is a flow chart of a method of forming an MRAM device in accordance with an embodiment of the invention.
Fig. 2A-2J are schematic cross-sectional views of steps of a method of forming an MRAM device in accordance with an embodiment of the present invention.
Fig. 3A-3I are schematic cross-sectional views illustrating steps of a method of forming an MRAM device in accordance with another embodiment of the present invention.
Detailed Description
The magnetoresistive random access memory and the method of forming the same of the present invention are described in further detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the drawings in the specification are in a very simplified form and are all to a non-precise scale, merely for the purpose of facilitating a clear assistance in describing embodiments of the invention. Furthermore, spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the structure in the figures is inverted or otherwise oriented (e.g., rotated), the exemplary term "under" and other positional relationships may also be included. If the components in the drawings are the same as those already labeled, the components will be easily recognized in all the drawings, but for the sake of clarity of the labeled description, the drawings and the following description will not label and describe all the same components.
In an MRAM device, MTJ elements may be formed between adjacent metal layers on a semiconductor substrate, and a plurality of MTJ elements may be formed laterally arranged between adjacent metal layers. The distance between the plurality of MTJ elements is scaled down under an advanced process node. The aspect ratio of the MTJ element is related to the height of the MTJ element. In this case, due to the shadow blocking at the time of ion beam etching, it is difficult to remove the oxide layer and the damaged portion of the sidewall formed on the sidewall of the MTJ element by a large incident etching angle (e.g., 50 ° to 90 °, which is defined as an angle between the incident direction of the ion beam and the normal direction of the semiconductor substrate). On the other hand, if the incident etching angle is reduced, the metal material exposed at the bottom surface of the gaps between the MTJ elements is excessively etched, and the conductive etching product is redeposited to the MTJ element sidewall, so that the risk of generating a short-circuit point of the MRAM device increases.
In the method for forming at least one MRAM device according to the embodiments of the present invention, after the MTJ stack is etched to form the MTJ device, a portion of the bottom electrode layer or a portion of the via hole located under the MTJ stack is exposed, and then oxidation treatment is performed first, so that not only the conductive redeposit of the MTJ device sidewall but also the exposed portion of the bottom electrode layer or the exposed portion of the via hole is oxidized, and then the MTJ device sidewall is etched with a smaller incident etching angle (less than 45 °), so that even if the gap around the MTJ device is narrower, the ion beam is easy to be incident, thereby being beneficial to removing the oxide layer and the damaged portion of the sidewall formed on the MTJ device sidewall, and ensuring the reliability of the MTJ device at the advanced process node. In addition, the oxidation treatment oxidizes part of the bottom electrode layer or part of the via hole around the MTJ element, and the MTJ element is basically free of exposed metal material, so that after the second etching with a smaller angle, the etching product deposited on the side wall of the MTJ element is mainly insulating material, and the risk of generating a short circuit point of the MRAM device is reduced.
FIG. 1 is a flow chart of a method of forming an MRAM device in accordance with an embodiment of the invention. Fig. 2A-2J are schematic cross-sectional views of steps of a method of forming an MRAM device in accordance with an embodiment of the present invention. A method of forming an MRAM device according to an embodiment is described below with reference to fig. 1 and 2A to 2J. The MRAM device is, for example, sandwiched between two adjacent metal layers on a semiconductor substrate. In the following embodiments, the adjacent two metal layers are referred to as a lower metal layer and an upper metal layer, respectively.
As shown in fig. 2A, first, a first dielectric layer 10, a via hole 11 penetrating the first dielectric layer 10, and a bottom electrode layer 12 are formed over a lower metal layer M x on a semiconductor substrate (not shown), the bottom electrode layer 12 being filled in the via hole 11 and covering the first dielectric layer 10. The bottom electrode layer 12 is connected to the lower metal layer M x through the via hole 11.
The lower metal layer M x may be a metal interconnect layer over the semiconductor substrate, and is denoted by the subscript x. The first dielectric layer 10 may be made of, for example, undoped silicate glass or oxide (e.g., silicon oxide) or other suitable materials. The size of the via 11 may be determined according to the design of the MRAM device, where the via 11 is, for example, a small-aperture via. To avoid that the metal material in the via 11 is exposed and etched during a subsequent second etching process, the aperture of the via 11 is for example smaller than the lateral dimensions of the MTJ element or bottom electrode to be formed on the via 11. The bottom electrode layer 12 may include one or a combination of two or more of titanium nitride, tantalum nitride, titanium, tantalum, and aluminum.
As shown in fig. 2B, an MTJ stack 13 is then stacked on the first dielectric layer 10, the MTJ stack 13 being used to form an MTJ element including the functional layers of the MTJ element. Illustratively, the MTJ stack 13 includes a seed Layer 131 (SEEDLAYER, SL), a pinned Layer 132 (Pin Layer, PL), a tunneling barrier 133, a free Layer 134 (FREELAYER, FL), and a Cap Layer 135 (Cap), and the functional layers may be made of known materials, for example, magnesium oxide (MgO) is used for the tunneling barrier 133. After stacking MTJ stack layer 13, a hard mask layer 14 (HM) may further be deposited on MTJ stack layer 13, the hard mask layer 14 being, for example, a metallic material.
As shown in fig. 2C, the hard mask layer 14 is then patterned by a photolithography process and an etching process, such as Reactive Ion Etching (RIE), to define the extent of the MTJ element. The patterned hard mask layer 14 may be used herein as a top electrode for connection to MTJ elements in MRAM devices. In another embodiment, a top electrode may be formed on the hard mask layer 14, and the top electrode is connected to the MTJ element.
As shown in fig. 2D, a first etching (which may include a moderate over-etching) is performed using the patterned hard mask layer 14 as a mask, so as to remove a portion of the MTJ stack layer 13, and an MTJ element 13a is formed corresponding to the via hole 11, and a portion of the bottom electrode layer 12 located outside the coverage area of the MTJ element 13a is exposed by the first etching. The first etch may employ Reactive Ion Etching (RIE) or Ion Beam Etching (IBE), which is preferred because of the less chemical gas introduced by ion beam etching. The incident etching angle of the first etching is, for example, less than 30 °, for example, vertical etching (i.e., the incident etching angle is equal to 0 °), so that the side wall of the MTJ element 13a is perpendicular or nearly perpendicular to the main surface of the semiconductor substrate. The first etch may remove a portion of the thickness of bottom electrode layer 12. During etching, portions of the metal material removed from MTJ stack layer 13 and bottom electrode layer 12, as well as some other etch products, may deposit on the MTJ element 13a and hard mask layer 14 sidewalls, forming redeposition, conductive redeposition 15 on MTJ element 13a sidewalls, and damage to the MTJ element 13a sidewalls due to the first etch. The conductive redeposit 15 and the damaged portion of the side wall of the MTJ element 13a need to be removed, which is otherwise prone to cause shorting and reliability problems as described in the background.
Alternatively, a plurality of via holes 11 are formed in the first dielectric layer 10 on the lower metal layer M x, and a plurality of MTJ parts 13a may be formed corresponding to the respective via holes 11 through the first etching. A portion of the bottom electrode layer 12 around each MTJ element 13a is exposed to gaps between a plurality of the MTJ elements 13a. In order to avoid that the first dielectric layer 10 is excessively etched during the subsequent second etching process, which affects the overall process on the semiconductor substrate, the bottom electrode layer 12 between the MTJ parts 13a remains in a state of not being etched through after the first etching is completed. Referring to fig. 2D, the portion of the bottom electrode layer 12 exposed around the MTJ element 13a, which is farther from the corresponding MTJ element 13a, is relatively thinner in thickness, and the portion of the bottom electrode layer 12 that is relatively thinner surrounds the corresponding MTJ element 13a, is subjected to the first etching. Illustratively, the thinnest area of bottom electrode layer 12 has a thickness (i.e., minimum thickness) less than or equal to 10nm, and more specifically, for example, about 5nm.
As shown in fig. 2E, an oxidation treatment is then performed, for example, heating or non-heating treatment is performed on the semiconductor substrate after the completion of the above-described first etching using oxygen (O 2), ozone (O 3), an inert gas or plasma containing oxygen (O 2) or ozone (O 3), so that the conductive redeposits 15 located on the side walls of the MTJ parts 13a and the magnetic material of the side walls of the MTJ parts 13a exposed to the oxidizing atmosphere are oxidized, forming a side wall oxide layer 16 on the side walls of the MTJ parts 13 a. The oxidation treatment may also be completed in the first etching process described above. The oxidation process oxidizes the exposed bottom electrode layer 12 around the MTJ element 13a from the surface to the inner partial depth, and forms a bottom oxide layer 17 around the MTJ element 13 a. In the present embodiment, at least the bottom electrode layer 12 in the thin region is entirely oxidized in the exposed bottom electrode layer 13a around the MTJ element 13a by the oxidation treatment, and thus, the connection of the bottom electrode layers 13a between the adjacent MTJ elements 13a is blocked. The bottom electrode layer 13a of the exposed thicker region may not be entirely oxidized, but only the surface layer may be oxidized. After the oxidation treatment, the bottom electrode layer 12 which is not oxidized is positioned below the MTJ element 13a and the bottom surface oxide layer 17, and this portion of the bottom electrode layer 12 constitutes the bottom electrode 12a corresponding to the MTJ element 13 a.
As shown in fig. 2F, a second etch is then performed to remove the sidewall oxide layer 16, the second etch having an incident etch angle of less than 45 °. The second etch is, for example, ion Beam Etching (IBE). The incident etching angle of the second etching is smaller, so that the ion beam is easy to irradiate the gaps around the MTJ component 13a, shadow blocking is avoided, and the method can be applied to MRAM device processes of different process nodes.
Optionally, the incident etching angle of the second etching is larger than that of the first etching so as to etch the side wall of the MTJ element 13a, and in addition, the etching power of the second etching may be smaller than that of the first etching so as to avoid damaging the MTJ element 13a. After the second etching, the sidewall oxide layer 16 located on the sidewall of the MTJ element 13a is substantially removed, and the damaged portion of the sidewall of the MTJ element 13a can also be removed, enabling the reliability of the MTJ element 13a to be improved.
In this embodiment, the second etching simultaneously etches the bottom oxide layer 17 around the MTJ element 13a, so that at least a portion of the bottom oxide layer 17 is removed, for example, a portion of the bottom oxide layer 17 may be etched through to expose the first dielectric layer 10, and during this process, at least a portion of the etching product formed by etching the bottom oxide layer 17 may be deposited on the sidewall of the MTJ element 13a, forming redeposited oxide 17a. Since the bottom oxide layer 17 is an insulating material, the redeposition caused by etching the bottom oxide layer 17 does not increase the risk of forming a short-circuit point in the MRAM device. After this second etch, a thinner bottom oxide layer 17 (e.g., less than 5 nm) may remain around MTJ element 13 a.
As shown in fig. 2G, optionally, after the second etching is completed, an etching may be further added, that is, a third etching, where an incident etching angle of the third etching is, for example, greater than that of the second etching, and the incident etching angle of the third etching may be greater than 45 ° to remove the redeposited oxide 17a formed on the sidewall of the MTJ element 13a after the second etching. The etching power of the third etching may be less than or equal to the etching power of the second etching. In the third etching process, the bottom oxide layer 17 remaining around the MTJ element 13a is etched, and a small amount of deposition is formed on the side wall of the MTJ element 13 a. Since the bottom oxide layer 17 is an insulating material, the risk of forming a short-circuit point of the MRAM device is not increased. By the third etching, the coverage area of the bottom electrode 12a under the MTJ element 13a is reduced, and the reliability of an interlayer dielectric layer (ILD) that is subsequently filled in the gap between the MTJ elements 13a can be ensured.
The MTJ element 13a may then be subjected to a cladding process. As shown in fig. 2H, a capping material layer 18 is formed conformally along the top surface of the semiconductor substrate after the second etching (or the third etching) is completed, the capping material layer 18 may be SiN x、SiON、SiOx, siC, siCN, or other suitable material, and then a second dielectric layer 19 is formed on the capping material layer 18, the second dielectric layer 19 covers the MTJ element 13a and fills the gap around the MTJ element 13a, and then a planarization process (e.g., chemical mechanical polishing, CMP) is performed on the top surface of the second dielectric layer 19.
As shown in fig. 2I, an opening 19a exposing the top electrode is then formed on the surface of the second dielectric layer 19 by using a photolithography process and an etching process, where the hard mask layer 14 is used as the top electrode. The width of the opening 19a may be greater than the width of the MTJ element 13 a. The cladding material layer 18 may also be exposed by the opening 19a, and the exposed face of the cladding material layer 18 is substantially flush with the exposed face of the top electrode.
As shown in fig. 2J, a metal material is then deposited in the opening 19a and on the top surface of the second dielectric layer 19, and a planarization process is performed to remove the excess metal material, and the metal material in the opening 19a remains. The metal material in the opening 19a is an upper metal layer M x+1, and the upper metal layer M x+1 can be used as an upper contact terminal of the MTJ device 13 a.
Fig. 3A-3I are schematic cross-sectional views illustrating steps of a method of forming an MRAM device in accordance with another embodiment of the present invention. A method of forming an MRAM device according to this further embodiment is described below with reference to fig. 3A to 3I. Hereinafter, descriptions of components or processes substantially identical to those of the above-described embodiments will not be repeated.
As shown in fig. 3A, first, a first dielectric layer 20 and a via hole 21 penetrating the first dielectric layer 20 are formed over a lower metal layer M x on a semiconductor substrate (not shown). In this embodiment, the aperture of the via hole 21 is larger than the lateral dimension of the MTJ element to be formed above it. The via hole 21 includes, for example, tantalum nitride (TaN) filled in the through hole. The MTJ element to be formed is formed corresponding to the central area of the via hole 21 and is in electrical contact with the via hole 21.
As shown in fig. 3B, an MTJ stack 22 is then stacked on the first dielectric layer 20, the MTJ stack 22 being used to form an MTJ element including the functional layers of the MTJ element. In another embodiment, the MTJ stack 22 may comprise a bottom electrode layer between the seed layer 221 and the first dielectric layer 20. After MTJ stack layer 22 is stacked, a hard mask layer 23 (HM) may further be deposited on MTJ stack layer 22.
As shown in fig. 3C, the hard mask layer 23 is then patterned by a photolithography process and an etching process, such as Reactive Ion Etching (RIE), to define the extent of the MTJ element. As shown in fig. 3D, a first etch (which may include a moderate over etch) is then performed using the patterned hard mask layer 23 as a mask, and specifically the layers of material of MTJ stack 22 and the bottom electrode layer selectively formed between MTJ stack 22 and first dielectric layer 21 may be etched layer by layer to remove portions of MTJ stack 22 and form MTJ element 22a corresponding to a central region of via 21, the other region of via 21 not being covered by MTJ element 22a and thus being exposed. The first etch may be a reactive ion etch or an ion beam etch, such as an ion beam etch. The incident etch angle of the first etch is, for example, less than 30 °, such as a vertical etch (i.e., the incident etch angle is equal to 0 °), and the sidewalls of the MTJ element 22a are formed perpendicular or nearly perpendicular to the major surface of the semiconductor substrate. Conductive redeposits 24 are formed on the sidewalls of MTJ element 22a via a first etch.
As shown in fig. 3E, an oxidation process is then performed, for example, heating or non-heating the semiconductor substrate after the first etching is completed using oxygen, ozone, an inert gas containing oxygen or ozone, or plasma, so that the conductive redeposits 24 located on the side walls of the MTJ element 22a and the magnetic material of the side walls of the MTJ element 22a exposed to the oxidizing atmosphere are oxidized, thereby forming a side wall oxide layer 25 on the side walls of the MTJ element 22 a. The oxidation treatment may also be completed in the first etching process described above. The oxidation treatment oxidizes the exposed via hole 21 from the surface to the inside by a certain depth, and forms a bottom oxide layer 26 (thickness of about 5nm to 10nm, for example) around the MTJ element 22 a. Since the exposed portion of the via 21 is oxidized, there is no exposed metal material around the MTJ element 22 a.
As shown in fig. 3F, a second etch is then performed to remove the sidewall oxide layer 25, the second etch having an incident etch angle of less than 45 °. The second etching is, for example, ion beam etching. The incident etching angle of the second etching is smaller, so that the ion beam easily enters the gap around the MTJ component 22a and irradiates the side wall of the MTJ component 22a, shadow blocking is avoided, and the method can be applied to the formation of MRAM devices of different process nodes. Optionally, the second etching has a larger incident etching angle than the first etching so as to etch the side wall of the MTJ element 22a, and in addition, the etching power of the second etching may be smaller than that of the first etching so as to reduce the risk of damaging the MTJ element 22 a.
After the second etching, the sidewall oxide layer 25 is substantially removed, and the damaged portion of the sidewall of the MTJ element 22a can also be removed, enabling the reliability of the MTJ element 22a to be improved. In this embodiment, the second etching causes the bottom oxide layer 26 around the MTJ element 22a to be etched, so that at least a portion of the thickness of the bottom oxide layer 26 is removed, and during this process, etching products generated by etching the bottom oxide layer 26 may be deposited on the sidewalls of the MTJ element 22a, forming redeposited oxide 26a. Since bottom oxide layer 26 is an insulating material, redeposition by etching bottom oxide layer 26 does not increase the risk of forming a shorting point for the MRAM device. After the second etching, a portion of the bottom oxide layer 26 (e.g., about 5nm thick) may remain around the MTJ element 22a, and the portion of the bottom oxide layer 26 may cover the bottom of the MTJ element 22a in a sidewall manner.
Optionally, after the second etching is completed, an incident etching angle may be further increased, and a third etching may be performed, where the incident etching angle of the third etching is, for example, greater than 45 °, to remove the redeposited oxide 26a formed on the side wall of the MTJ element 22a after the second etching. The etching power of the third etching may be less than or equal to the etching power of the second etching.
The MTJ element 22a may then be subjected to a cladding process. As shown in fig. 3G, a cladding material layer 27 is formed conformally along the top surface of the semiconductor substrate after the second etching (or the third etching) is completed, then a second dielectric layer 28 is formed on the cladding material layer 27, such that the second dielectric layer 28 covers the MTJ element 22a and fills the gap around the MTJ element 22a, and then a planarization process (e.g., chemical mechanical polishing, CMP) is performed on the upper surface of the second dielectric layer 28.
As shown in fig. 3H, an opening 28a exposing the top electrode is then formed on the top surface of the second dielectric layer 28 by a photolithography process and an etching process. Hard mask layer 23 is used here as the top electrode of MTJ element 22 a. The width of the opening 28a may be greater than the width of the MTJ element 22 a. The cladding material layer 27 may also be exposed by the opening 28a, and the exposed face of the cladding material layer 27 is substantially flush with the exposed face of the top electrode.
As shown in fig. 3I, a metal material is then deposited in the opening 28a and on the top surface of the second dielectric layer 28, and a planarization process is performed to remove the excess metal material, and the metal material in the opening 28a remains. The metal material within the opening 28a is an upper metal layer M x+1, which upper metal layer M x+1 may serve as an upper contact terminal for the MTJ component 22 a.
The embodiment of the invention provides a method for forming at least one MRAM device, wherein an MTJ stack is stacked above a lower metal layer M x on a semiconductor substrate, after an MTJ component is formed through first etching, a part of bottom electrode layer 12 or a part of via 21 below the MTJ stack is exposed, then conductive redeposition of the side wall of the MTJ component and a part of the bottom electrode layer or a part of via exposed around the MTJ component are oxidized through oxidation treatment, then second etching with an incident etching angle smaller than 45 degrees is performed to remove an oxide layer of the side wall of the MTJ component, the incident etching angle of the second etching is smaller, the influence of shadow blocking is small, the oxide layer of the side wall of the MTJ component and a side wall damage part which possibly affects the performance of the MTJ component are conveniently and fully removed, and the reliability of the component is ensured. In addition, as the oxide of the bottom electrode layer or the via hole is arranged around the MTJ element, the etching product of the second etching deposited on the side wall of the MTJ element is not conductive, and the risk of generating a short circuit point of the MRAM device can be reduced.
It should be noted that, in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and the same and similar parts between the embodiments may be referred to for understanding.
The foregoing description is only illustrative of the preferred embodiments of the present invention, and is not intended to limit the scope of the claims, and any person skilled in the art may make any possible variations and modifications to the technical solution of the present invention using the method and technical content disclosed above without departing from the spirit and scope of the invention, so any simple modification, equivalent variation and modification made to the above embodiments according to the technical matter of the present invention fall within the scope of the technical solution of the present invention.
Claims (11)
1. A method of forming at least one MRAM device, the method comprising:
forming a first dielectric layer over a lower metal layer on a semiconductor substrate;
Forming a via hole penetrating through the first dielectric layer and a bottom electrode layer, wherein the bottom electrode layer is filled in the via hole and covers the first dielectric layer, and the bottom electrode layer is connected with the lower metal layer through the via hole;
Forming an MTJ stack on the bottom electrode layer;
Performing first etching on the MTJ (magnetic tunnel junction) stack layer to form an MTJ component corresponding to the via hole and expose part of the bottom electrode layer around the MTJ component, wherein conductive redeposition is formed on the side wall of the MTJ component through the first etching;
Performing an oxidation treatment to form a sidewall oxide layer on the sidewall of the MTJ element by oxidizing the conductive redeposit, and forming a bottom oxide layer around the MTJ element by oxidizing the exposed portion of the bottom electrode layer, the bottom electrode layer under the MTJ element and the bottom oxide layer not oxidized forming a bottom electrode, and
And performing second etching to remove the side wall oxide layer, wherein the incident etching angle of the second etching is smaller than 45 degrees.
2. The method of claim 1, wherein after completing the second etch, the method comprises:
And performing third etching to remove etching products redeposited on the side wall of the MTJ component through the second etching, wherein the incident etching angle of the third etching is larger than that of the second etching.
3. The method of claim 1, wherein after completing the second etch, the method comprises:
Forming a coating material layer along the top surface of the semiconductor substrate after the second etching is completed;
forming a second dielectric layer on the cladding material layer, wherein the second dielectric layer covers the MTJ component and fills gaps around the MTJ component;
Flattening the top surface of the second dielectric layer;
Forming an opening in the second dielectric layer, the opening exposing a top electrode formed over and connected to the MTJ element, and
An upper metal layer is formed within the opening.
4. The method of claim 1, wherein a plurality of the via holes are formed in the first dielectric layer, a plurality of the MTJ elements are formed corresponding to the plurality of via holes through the first etching, a portion of the bottom electrode layer is exposed to gaps between the plurality of MTJ elements, and a metal material exposed to the gaps between the plurality of MTJ elements is oxidized through the oxidation treatment.
5. The method of claim 1, wherein a minimum thickness of the bottom electrode layer is less than or equal to 10nm prior to the oxidation treatment.
6. The method of claim 1, wherein a pore size of the via is less than a lateral dimension of the bottom electrode.
7. An MRAM device formed by the method of claim 1, the MRAM device comprising:
A first dielectric layer formed over a lower metal layer on a semiconductor substrate;
a via hole penetrating the first dielectric layer;
the bottom electrode layer is filled in the via hole and covers the first dielectric layer, and is connected with the lower metal layer through the via hole;
an MTJ element formed on the bottom electrode layer;
A hard mask formed over the MTJ element;
a top electrode formed on the hard mask and connected to the MTJ element;
a cladding material layer formed on the side wall of the MTJ part, the exposed surface of the bottom electrode layer and the exposed surface of the first dielectric layer, and
And a second dielectric layer formed on the cladding material layer, the second dielectric layer covering the MTJ element and filling a gap around the MTJ element.
8. A method of forming at least one MRAM device, the method comprising:
Forming a first dielectric layer above a lower metal layer on a semiconductor substrate, and forming a via hole penetrating through the first dielectric layer;
forming an MTJ stack on the first dielectric layer;
Performing first etching on the MTJ stack to form an MTJ component corresponding to a central region of the via hole and expose a portion of the via hole around the MTJ component, wherein, through the first etching, a conductive redeposition is formed on a side wall of the MTJ component;
Performing an oxidation treatment to form a sidewall oxide layer on the sidewall of the MTJ element by oxidizing the conductive redeposit, and forming a bottom oxide layer around the MTJ element by oxidizing the exposed portion of the via hole around the MTJ element, and
And performing second etching to remove the side wall oxide layer, wherein the incident etching angle of the second etching is smaller than 45 degrees.
9. The method of claim 8, wherein after completing the second etch, the method comprises:
And performing third etching to remove etching products redeposited on the side wall of the MTJ component through the second etching, wherein the incident etching angle of the third etching is larger than that of the second etching.
10. The method of claim 8, wherein after completing the second etch, the forming method comprises:
Forming a coating material layer along the top surface of the semiconductor substrate after the second etching is completed;
forming a second dielectric layer on the cladding material layer, wherein the second dielectric layer covers the MTJ component and fills gaps around the MTJ component;
Flattening the top surface of the second dielectric layer;
Forming an opening in the second dielectric layer, the opening exposing a top electrode formed over and connected to the MTJ element, and
An upper metal layer is formed within the opening.
11. The method of claim 8, wherein a plurality of the via holes are formed in the first dielectric layer, a plurality of the MTJ parts are formed corresponding to the plurality of via holes through the first etching, a portion of each of the via holes is exposed to a gap between the plurality of MTJ parts, and a metal material exposed to the gap between the plurality of MTJ parts is oxidized through the oxidation treatment.
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