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CN115763439A - Partition electromagnetic shielding module, preparation method, circuit board and electronic product - Google Patents

Partition electromagnetic shielding module, preparation method, circuit board and electronic product Download PDF

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CN115763439A
CN115763439A CN202211394540.3A CN202211394540A CN115763439A CN 115763439 A CN115763439 A CN 115763439A CN 202211394540 A CN202211394540 A CN 202211394540A CN 115763439 A CN115763439 A CN 115763439A
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shielding
substrate
arc
wire
flip chip
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蒋品方
张磊
徐衔
张鑫垚
张华�
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Beijing Weijie Chuangxin Precision Measurement Technology Co ltd
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Abstract

本发明公开了一种分区电磁屏蔽的模组、制备方法及电路板和电子产品。该模组包括基板、接地连接垫、倒装芯片、芯片或元器件、屏蔽线弧、塑封体以及电磁屏蔽层,倒装芯片的远离基板的表面设置有可焊线金属层,接地连接垫位于基板上,并且位于倒装芯片和芯片或元器件之间,塑封体覆盖接地连接垫、倒装芯片、芯片或元器件、屏蔽线弧,电磁屏蔽层位于塑封体的表面,屏蔽线弧设置在倒装芯片和芯片或元器件之间,并且屏蔽线弧的一端连接可焊线金属层,另一端连接电磁屏蔽层。本发明可以降低屏蔽线弧高度,提高封装质量,简化工艺难度,在一定程度上提高封装集成度。

Figure 202211394540

The invention discloses a partition electromagnetic shielding module, a preparation method, a circuit board and electronic products. The module includes a substrate, a ground connection pad, a flip chip, a chip or a component, a shielding wire arc, a plastic package, and an electromagnetic shielding layer. On the substrate, and between the flip chip and the chip or component, the plastic package covers the ground connection pad, the flip chip, the chip or component, and the shielding arc. The electromagnetic shielding layer is located on the surface of the plastic package, and the shielding arc is set on the Between the flip chip and the chip or component, and one end of the shielding arc is connected to the weldable metal layer, and the other end is connected to the electromagnetic shielding layer. The invention can reduce the arc height of the shielding line, improve the packaging quality, simplify the process difficulty, and improve the packaging integration degree to a certain extent.

Figure 202211394540

Description

一种分区电磁屏蔽的模组、制备方法及电路板和电子产品Partition electromagnetic shielding module, preparation method, circuit board and electronic product

技术领域technical field

本发明涉及一种分区电磁屏蔽的模组,同时也涉及一种分区电磁屏蔽的模组的制备方法,还涉及具有该分区电磁屏蔽的模组的电路板和电子产品,属于芯片封装技术领域。The invention relates to a partitioned electromagnetic shielding module, a preparation method of the partitioned electromagnetic shielding module, a circuit board and an electronic product with the partitioned electromagnetic shielding module, and belongs to the technical field of chip packaging.

背景技术Background technique

随着电子元器件的集成度越来越高,集成电路中各组件之间的距离越来越小,导致组件之间的相互干扰问题日益严重。为了防止芯片间,或芯片和元器件互相产生电磁干扰现象的发生,通常利用打线的方式或者在塑封体上开槽填充屏蔽介质等方式来实现分区电磁屏蔽。具体地打线方式有:在基板上打线形成金属网、金属栅栏和金属垂直线等,使塑封体表面覆盖的电磁屏蔽层与屏蔽线弧相连,以实现电磁屏蔽。As the integration of electronic components is getting higher and higher, the distance between components in integrated circuits is getting smaller and smaller, resulting in increasingly serious problems of mutual interference between components. In order to prevent the occurrence of electromagnetic interference between chips, or between chips and components, the electromagnetic shielding of partitions is usually realized by bonding wires or slotting and filling shielding media on the plastic package. The specific wire bonding methods include: wire bonding on the substrate to form metal mesh, metal fences, and metal vertical lines, etc., so that the electromagnetic shielding layer covered on the surface of the plastic package is connected to the shielding wire arc to achieve electromagnetic shielding.

在专利号为ZL 202110202607.8的中国发明专利中,公开了一种电磁屏蔽封装结构和电磁屏蔽封装方法。该电磁屏蔽封装结构包括基板、至少两个贴装在基板上的芯片、设置在基板上的屏蔽线弧、覆盖在芯片和屏蔽线弧外的塑封体以及覆盖在塑封体表面的金属屏蔽层,其中,屏蔽线弧是打在芯片周围的接地焊盘上。但是,这种打线方法所用线弧高度高,导致打线作业难度大,线弧稳定性差。In the Chinese invention patent with the patent number ZL 202110202607.8, an electromagnetic shielding packaging structure and an electromagnetic shielding packaging method are disclosed. The electromagnetic shielding packaging structure includes a substrate, at least two chips mounted on the substrate, a shielding wire arc arranged on the substrate, a plastic package covering the chip and the shielding wire arc, and a metal shielding layer covering the surface of the plastic package, Wherein, the shielding wire arc is punched on the ground pad around the chip. However, the height of the wire arc used in this wire bonding method is high, which makes the wire bonding operation difficult and the stability of the wire arc is poor.

发明内容Contents of the invention

本发明所要解决的首要技术问题在于提供一种分区电磁屏蔽的模组。The primary technical problem to be solved by the present invention is to provide a module for partitioning electromagnetic shielding.

本发明所要解决的另一技术问题在于提供一种分区电磁屏蔽的模组的制备方法。Another technical problem to be solved by the present invention is to provide a method for preparing a partitioned electromagnetic shielding module.

本发明所要解决的又一技术问题在于提供一种具有该分区电磁屏蔽的模组的电路板。Another technical problem to be solved by the present invention is to provide a circuit board with the electromagnetic shielding module of the partition.

本发明所要解决的再一技术问题在于提供一种具有该分区电磁屏蔽的模组的电子产品。Another technical problem to be solved by the present invention is to provide an electronic product with the electromagnetically shielded modules of the partitions.

为实现上述技术目的,本发明采用以下的技术方案:For realizing above-mentioned technical purpose, the present invention adopts following technical scheme:

根据本发明实施例的第一方面,提供一种分区电磁屏蔽的模组,包括基板、接地连接垫、倒装芯片、芯片或元器件、屏蔽线弧、塑封体以及电磁屏蔽层,According to the first aspect of the embodiments of the present invention, there is provided a module for partitioned electromagnetic shielding, including a substrate, a ground connection pad, a flip chip, a chip or a component, a shielded wire arc, a plastic package, and an electromagnetic shielding layer,

所述倒装芯片的远离所述基板的表面设置有可焊线金属层,The surface of the flip chip away from the substrate is provided with a wire-bondable metal layer,

所述接地连接垫位于所述基板上,并且位于所述倒装芯片和所述芯片或元器件之间,The ground connection pad is located on the substrate and between the flip chip and the chip or component,

所述塑封体覆盖所述接地连接垫、倒装芯片、芯片或元器件、屏蔽线弧,The plastic package covers the ground connection pad, flip chip, chip or component, and shielding arc,

所述电磁屏蔽层位于所述塑封体的表面,The electromagnetic shielding layer is located on the surface of the plastic package,

所述屏蔽线弧设置在所述倒装芯片和芯片或元器件之间,并且屏蔽线弧的一端连接所述可焊线金属层,另一端连接所述电磁屏蔽层。The shielding arc is arranged between the flip chip and the chip or component, and one end of the shielding arc is connected to the wire-weldable metal layer, and the other end is connected to the electromagnetic shielding layer.

其中较优地,所述屏蔽线弧包括第一线弧和第二线弧,所述第一线弧连接所述可焊线金属层和所述电磁屏蔽层;所述第二线弧连接所述接地连接垫和所述电磁屏蔽层。Preferably, the shielding arc includes a first arc and a second arc, the first arc is connected to the weldable metal layer and the electromagnetic shielding layer; the second arc is connected to the ground connection pads and the electromagnetic shield.

其中较优地,所述可焊线金属层覆盖所述倒装芯片的整个背面,或者覆盖所述倒装芯片的外周缘。Preferably, the wire-bondable metal layer covers the entire backside of the flip chip, or covers the outer periphery of the flip chip.

其中较优地,所述屏蔽线弧是直线状、L形状或口字形状。Wherein preferably, the shielded wire arc is straight, L-shaped or square-shaped.

其中较优地,在所述屏蔽线弧为直线状或L形状时,所述可焊线金属层覆盖所述倒装芯片的外周缘;在所述屏蔽线弧为口字形状时,所述可焊线金属层覆盖所述倒装芯片的整个背面。Preferably, when the shielding arc is straight or L-shaped, the wire-bondable metal layer covers the outer periphery of the flip chip; when the shielding arc is in the shape of a square, the A wire-bondable metal layer covers the entire backside of the flip chip.

根据本发明实施例的第二方面,提供一种分区电磁屏蔽的模组的制备方法,包括以下步骤:According to the second aspect of the embodiments of the present invention, there is provided a method for preparing a partitioned electromagnetic shielding module, comprising the following steps:

S1:在基板上形成接地连接垫;S1: forming a ground connection pad on the substrate;

S2:在基板上安装倒装芯片和芯片或元器件;S2: Install flip chips and chips or components on the substrate;

S3:在所述倒装芯片的背面形成可焊线金属层;S3: forming a wire-bondable metal layer on the backside of the flip chip;

S5:在所述接地连接垫和可焊线金属层之间打线,以形成屏蔽线弧;S5: making a wire between the ground connection pad and the weldable metal layer to form a shielded wire arc;

S5:在所述基板上形成塑封体,使屏蔽线弧的顶端暴露于塑封体表面;S5: forming a plastic package on the substrate, exposing the top of the shielding arc to the surface of the plastic package;

S6:在所述塑封体背面形成电磁屏蔽层,使所述电磁屏蔽层与所述屏蔽线弧电连接;S6: forming an electromagnetic shielding layer on the back of the plastic package, and electrically connecting the electromagnetic shielding layer to the shielding arc;

S7:对所述基板进行切单。S7: performing singulation on the substrate.

根据本发明实施例的第三方面,提供一种分区电磁屏蔽的模组的制备方法,包括以下步骤:According to a third aspect of the embodiments of the present invention, there is provided a method for preparing a partitioned electromagnetic shielding module, including the following steps:

S1:在基板上形成接地连接垫;S1: forming a ground connection pad on the substrate;

S2:在基板上安装倒装芯片和芯片或元器件;S2: Install flip chips and chips or components on the substrate;

S3:在所述倒装芯片的背面形成可焊线金属层;S3: forming a wire-bondable metal layer on the backside of the flip chip;

S5:在所述接地连接垫和可焊线金属层之间打线,以形成屏蔽线弧;S5: making a wire between the ground connection pad and the weldable metal layer to form a shielded wire arc;

S5:在所述基板上形成塑封体,并对所述塑封体进行减薄,以截断打线形成屏蔽线弧并暴露出屏蔽线弧;S5: forming a plastic package on the substrate, and thinning the plastic package to cut off the bonding wire to form a shielding arc and expose the shielding arc;

S6:在所述塑封体背面形成电磁屏蔽层,使所述电磁屏蔽层与所述屏蔽线弧电连接;S6: forming an electromagnetic shielding layer on the back of the plastic package, and electrically connecting the electromagnetic shielding layer to the shielding arc;

S7:对所述基板进行切单。S7: performing singulation on the substrate.

根据本发明实施例的第四方面,提供一种分区电磁屏蔽的模组的制备方法,包括以下步骤:According to a fourth aspect of the embodiments of the present invention, there is provided a method for preparing a partitioned electromagnetic shielding module, comprising the following steps:

S1:在基板上形成接地连接垫;S1: forming a ground connection pad on the substrate;

S2:在基板上安装倒装芯片和芯片或元器件;S2: Install flip chips and chips or components on the substrate;

S3:在所述倒装芯片的背面形成可焊线金属层;S3: forming a wire-bondable metal layer on the backside of the flip chip;

S5:在所述接地连接垫和可焊线金属层之间打线,以形成屏蔽线弧;S5: making a wire between the ground connection pad and the weldable metal layer to form a shielded wire arc;

S5:在所述基板上形成塑封体,使屏蔽线弧的顶端暴露于塑封体表面;S5: forming a plastic package on the substrate, exposing the top of the shielding arc to the surface of the plastic package;

S6:对所述基板进行切单;S6: Singling the substrate;

S7:对单个封装体形成电磁屏蔽层,使所述电磁屏蔽层与所述屏蔽线弧电连接。S7: Form an electromagnetic shielding layer on a single package, and electrically connect the electromagnetic shielding layer to the shielding arc.

根据本发明实施例的第五方面,提供一种分区电磁屏蔽的模组的制备方法,包括以下步骤:According to a fifth aspect of the embodiments of the present invention, there is provided a method for preparing a partitioned electromagnetic shielding module, including the following steps:

S1:在基板上形成接地连接垫;S1: forming a ground connection pad on the substrate;

S2:在基板上安装倒装芯片和芯片或元器件;S2: Install flip chips and chips or components on the substrate;

S3:在所述倒装芯片的背面形成可焊线金属层;S3: forming a wire-bondable metal layer on the backside of the flip chip;

S5:在所述接地连接垫和可焊线金属层之间打线,以形成屏蔽线弧;S5: making a wire between the ground connection pad and the weldable metal layer to form a shielded wire arc;

S5:在所述基板上形成塑封体,并对所述塑封体进行减薄,以截断打线形成屏蔽线弧并暴露出屏蔽线弧;S5: forming a plastic package on the substrate, and thinning the plastic package to cut off the bonding wire to form a shielding arc and expose the shielding arc;

S6:对所述基板进行切单;S6: Singling the substrate;

S7:对单个封装体形成电磁屏蔽层,使所述电磁屏蔽层与所述屏蔽线弧电连接。S7: Form an electromagnetic shielding layer on a single package, and electrically connect the electromagnetic shielding layer to the shielding arc.

根据本发明实施例的第六方面,提供一种电路板,其中包含如前述的分区电磁屏蔽的模组。According to a sixth aspect of the embodiments of the present invention, there is provided a circuit board, which includes the aforementioned partitioned electromagnetic shielding module.

根据本发明实施例的第七方面,提供一种电子产品,包含如前述的分区电磁屏蔽的模组。According to a seventh aspect of the embodiments of the present invention, there is provided an electronic product, including the aforementioned partitioned electromagnetic shielding module.

与现有技术相比较,本发明具有以下技术效果:通过在倒装芯片背面及其周围的接地连接垫上打线,以实现芯片与元器件之间或芯片与芯片之间的电磁屏蔽。通过这种打线方法,可以降低屏蔽线弧高度,提高封装质量,简化工艺难度,在一定程度上,对基板的空间利用率进行了改善,达到提高封装集成度的需求。Compared with the prior art, the present invention has the following technical effects: the electromagnetic shielding between chips and components or between chips is realized by bonding wires on the back of the flip chip and the ground connection pads around it. Through this wire bonding method, the height of the shielding wire arc can be reduced, the packaging quality can be improved, and the difficulty of the process can be simplified. To a certain extent, the space utilization rate of the substrate is improved to meet the requirement of increasing the packaging integration.

附图说明Description of drawings

图1~图7为本发明第一实施例中,分区电磁屏蔽的模组的制备方法流程图;1 to 7 are flow charts of a method for preparing a partitioned electromagnetic shielding module in the first embodiment of the present invention;

图8~图9为本发明第二实施例中,分区电磁屏蔽的模组的制备方法与第一实施例中的不同步骤的示意图;8 to 9 are schematic diagrams of different steps in the method for preparing a module for partitioned electromagnetic shielding in the second embodiment of the present invention and in the first embodiment;

图10为本发明实施例中,倒装芯片的可焊线金属层的示意图;10 is a schematic diagram of a wire-bondable metal layer of a flip chip in an embodiment of the present invention;

图11(a)为图10中的可焊线金属层的一种形式的示意图;Fig. 11 (a) is a schematic diagram of a form of the wire-bondable metal layer in Fig. 10;

图11(b)为图10中的可焊线金属层的另一种形式的示意图;Figure 11(b) is a schematic diagram of another form of the wire-bondable metal layer in Figure 10;

图12(a)~图12(b)为本发明第三实施例中,分区电磁屏蔽的模组的一种实现方式的结构示意图;Fig. 12(a) to Fig. 12(b) are structural schematic diagrams of an implementation mode of a partitioned electromagnetic shielding module in the third embodiment of the present invention;

图13(a)~图13(b)为本发明第三实施例中,分区电磁屏蔽的模组的另一种实现方式的结构示意图;Fig. 13(a) to Fig. 13(b) are structural schematic diagrams of another implementation of the partitioned electromagnetic shielding module in the third embodiment of the present invention;

图14~图16为本发明第四实施例中,分区电磁屏蔽的模组的制备方法的流程图;14 to 16 are flow charts of a method for preparing a partitioned electromagnetic shielding module in the fourth embodiment of the present invention;

图17~图18为本发明第四实施例中,分区电磁屏蔽的模组的制备方法的替代方案的不同步骤的示意图。17 to 18 are schematic diagrams of different steps of an alternative method for preparing a partitioned electromagnetic shielding module in the fourth embodiment of the present invention.

具体实施方式Detailed ways

下面结合附图和具体实施例对本发明的技术内容进行详细具体的说明。The technical content of the present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

<第一实施例><First embodiment>

如图1~图7所示,本发明的第一实施例公开了一种分区电磁屏蔽的模组的制备方法,包括以下步骤:As shown in Figures 1 to 7, the first embodiment of the present invention discloses a method for preparing a partitioned electromagnetic shielding module, including the following steps:

S1:在基板12上形成接地连接垫11。S1: Form the ground connection pad 11 on the substrate 12 .

如图1所示,所述基板12包括基材121、功能电路122、基板侧壁接地线123。所述基材121为陶瓷、PP、环氧树脂等介电材料,优选为多层设置。所述功能电路122分布于所述多层基材121。所述功能电路122布局为本领域技术人员所理解的根据具体应用场景而有所不同,故在此不赘述。所述基板侧壁接地线123分布于基板12的侧壁,一端接地,一端裸露于基板12的侧壁,便于与覆盖在基板12侧壁表面的电磁屏蔽层17连接,防止外部电磁干扰。As shown in FIG. 1 , the substrate 12 includes a substrate 121 , a functional circuit 122 , and a ground wire 123 on the sidewall of the substrate. The base material 121 is a dielectric material such as ceramics, PP, epoxy resin, etc., and is preferably multi-layered. The functional circuits 122 are distributed on the multi-layer substrate 121 . The layout of the functional circuit 122 is understood by those skilled in the art to be different according to specific application scenarios, so details are not described here. The substrate sidewall grounding wire 123 is distributed on the sidewall of the substrate 12, one end is grounded, and the other end is exposed on the sidewall of the substrate 12, which is convenient to connect with the electromagnetic shielding layer 17 covering the surface of the sidewall of the substrate 12 to prevent external electromagnetic interference.

所述接地连接垫11位于基板12上表面,用于为后续打线封装提供电性连接,其材料可以是Cu、Al、Au、Ag、Sn等材料中的一种或多种,也可以是其合金。接地连接垫11可以在基板12的制程中形成,也可以将金属块通过SMT(表面贴装技术)或其他方式粘贴到基板12上形成。接地连接垫11可以相互独立分布,也可以部分连接成一条状,或全部连接为一整条。The ground connection pad 11 is located on the upper surface of the substrate 12 and is used to provide electrical connection for the subsequent wire-bonding package. Its material can be one or more of Cu, Al, Au, Ag, Sn and other materials, or it can be its alloy. The ground connection pad 11 can be formed during the manufacturing process of the substrate 12 , or can be formed by pasting a metal block on the substrate 12 by SMT (Surface Mount Technology) or other methods. The ground connection pads 11 can be distributed independently of each other, or partly connected into a strip, or all connected into a whole strip.

S2:在基板12上安装倒装芯片13和芯片或元器件14。S2: Install flip chip 13 and chips or components 14 on substrate 12 .

如图2所示,在本实施例中,倒装芯片13为SAW、BAW等对抗电磁干扰有要求的芯片,其为电磁干扰敏感器件。芯片或元器件14为电磁干扰源,对倒装芯片13形成干扰。因此,需要利用打线将倒装芯片13屏蔽,保护其不受芯片或元器件14的干扰。As shown in FIG. 2 , in this embodiment, the flip chip 13 is a chip such as SAW, BAW, etc. that has requirements against electromagnetic interference, and is an electromagnetic interference sensitive device. The chip or component 14 is a source of electromagnetic interference, which interferes with the flip chip 13 . Therefore, the flip chip 13 needs to be shielded by wire bonding to protect it from interference from chips or components 14 .

所述倒装芯片13的正面(朝向基板的表面)包括凸点21,其背面具有可焊线金属层22(后文详述)。所述倒装芯片13可利用FC封装方式或者SMT贴装方式,将凸点21与基板12进行焊接。凸点21材料为可进行焊接与电性连接的材料,一般为锡球。所述可焊线金属层22其厚度需大于1um,用于增加倒装芯片13和屏蔽线弧15的结合力,便于后续打线作业。The front side of the flip chip 13 (the surface facing the substrate) includes bumps 21 , and its back side has a wire-bondable metal layer 22 (details will be described later). The flip chip 13 can be packaged by FC or SMT, and the bumps 21 are soldered to the substrate 12 . The material of the bump 21 is a material that can be soldered and electrically connected, and is generally a solder ball. The thickness of the wire-bondable metal layer 22 needs to be greater than 1 um, which is used to increase the bonding force between the flip-chip 13 and the shielded wire arc 15, and facilitate subsequent wire-bonding operations.

所述芯片或元器件14与基板12的电连接方式可以是引线键合(WB)、倒装(FC)或表面贴装(SMT)等半导体封装常用制程。The electrical connection between the chip or component 14 and the substrate 12 can be wire bonding (WB), flip chip (FC) or surface mount (SMT) and other common semiconductor packaging processes.

接地连接垫11位于两个相互干扰的器件之间,即位于倒装芯片13和芯片或元器件14之间,可根据电路走线需求灵活设计。The ground connection pad 11 is located between two mutually interfering devices, that is, between the flip chip 13 and the chip or component 14 , and can be flexibly designed according to circuit routing requirements.

S3:在所述倒装芯片13的背面形成可焊线金属层22。S3: forming a wire-bondable metal layer 22 on the back surface of the flip chip 13 .

形成可焊线金属层22,在本实施例中采用蒸镀技术,但是也可以采用其他技术,例如溅射工艺等。以下以蒸镀为例进行说明。To form the wire-bondable metal layer 22 , in this embodiment, evaporation technology is used, but other technologies, such as sputtering technology, can also be used. Hereinafter, vapor deposition is taken as an example for description.

可焊线金属层22是三层金属工艺结构,按照其功能可分别为粘附层、过渡层和导电层。上粘附层(接触层):一般选用粘附性良好,与晶圆材料的热膨胀系数接近,且与其欧姆接触系数小的材料;在本实施例中,晶圆材料是硅片,所以可以选择铬或钛,在此采用钛金属。The wire-bondable metal layer 22 is a three-layer metal process structure, which can be respectively an adhesion layer, a transition layer and a conductive layer according to its functions. Upper adhesion layer (contact layer): Generally, a material with good adhesion, close to the thermal expansion coefficient of the wafer material, and a small ohmic contact coefficient with it is selected; in this embodiment, the wafer material is a silicon wafer, so it can be selected Chrome or titanium, here titanium is used.

下粘附层(保护层):为芯片背面的最外层,性能稳定、不易氧化、易于焊料层焊接,且导电、导热性能良好。可以选用例如金、银等金属。在本实施例中选择银。Lower adhesion layer (protective layer): It is the outermost layer on the back of the chip, which has stable performance, is not easy to oxidize, is easy to solder with the solder layer, and has good electrical and thermal conductivity. Metals such as gold and silver can be used. Silver is chosen in this example.

阻挡层(填充层):在接触层与导电层之间起过渡作用,不能将金、银膜直接做在铬、钛金属膜上。由于金、银膜很容易溶于锡、银等焊料,造成焊料直接与钛、铬金属膜接触,但这些金属又是难焊金属,导致芯片焊接性能很差;因此需在这两层金属之间设置阻挡层,通常采用镍。Barrier layer (filling layer): It plays a transitional role between the contact layer and the conductive layer, and the gold and silver films cannot be directly made on the chromium and titanium metal films. Since the gold and silver films are easily soluble in solder such as tin and silver, the solder is directly in contact with the titanium and chromium metal films, but these metals are difficult to solder, resulting in poor chip soldering performance; A barrier layer is provided between them, usually nickel.

在本实施例中,先蒸镀钛层(1KA),再蒸镀镍层(2KA),最后蒸镀银层(10KA)。In this embodiment, the titanium layer (1KA) is evaporated first, then the nickel layer (2KA) is evaporated, and finally the silver layer (10KA) is evaporated.

S4:在所述接地连接垫11和可焊线金属层22之间打线,以形成屏蔽线弧15。S4: Make a wire between the ground connection pad 11 and the wire-weldable metal layer 22 to form a shielded wire arc 15 .

如图3所示,所述屏蔽线弧15的第一端151打在接地连接垫11上,第二端152打在倒装芯片13的可焊线金属层22上。打线所用焊线可以是Au,Cu,Al等导电焊线种的一种或多种。As shown in FIG. 3 , the first end 151 of the shielding arc 15 is hit on the ground connection pad 11 , and the second end 152 is hit on the wire-bondable metal layer 22 of the flip chip 13 . The bonding wire used for bonding may be one or more of conductive bonding wires such as Au, Cu, and Al.

由于倒装芯片13的高度较高,所以第一端151到打线的顶端A的距离L1小于第二端152到打线的顶端A的距离L2(即,L1<L2)。在常规技术中,打线的第一端和第二端均是从基板或接地连接垫上引出,因此第一端到打线的顶端的距离与第二端到打线的顶端的距离基本相同,这样使得整条打线长度L≈2*L2。然而,本发明实施例中,整条打线长度L=L1+L2<2*L2,因此使得整条打线的长度L缩短。众所周知,细长的打线的长度越大,其承受塑封制程中的模压的能力越差,越容易发生位置偏移或塌落,这就会导致电磁屏蔽效果变差。因此,本发明实施例利用倒装芯片的高度,缩短了L1的长度,也就缩短了整条打线长度L,有利于提高电磁屏蔽效果。Since the height of the flip chip 13 is high, the distance L1 from the first end 151 to the top A of the bonding wire is smaller than the distance L2 from the second end 152 to the top A of the bonding wire (ie, L1<L2). In the conventional technology, the first end and the second end of the bonding wire are drawn from the substrate or the ground connection pad, so the distance from the first end to the top of the bonding wire is basically the same as the distance from the second end to the top of the bonding wire, In this way, the entire bonding wire length L≈2*L2. However, in the embodiment of the present invention, the entire bonding wire length L=L1+L2<2*L2, thus shortening the entire bonding wire length L. As we all know, the longer the slender bonding wire is, the worse its ability to withstand the molding pressure in the plastic encapsulation process, and the easier it is to shift or collapse, which will lead to poor electromagnetic shielding effect. Therefore, the embodiment of the present invention utilizes the height of the flip-chip to shorten the length of L1, which shortens the length L of the entire bonding wire, which is beneficial to improve the electromagnetic shielding effect.

而且,整条打线长度L缩短,打线作业难度也随之降低。Moreover, the length L of the entire wire bonding is shortened, and the difficulty of the wire bonding operation is also reduced accordingly.

S5:在所述基板12上形成塑封体16,并对所述塑封体16进行减薄,以截断打线形成屏蔽线弧15并暴露出屏蔽线弧15。S5: forming a plastic package 16 on the substrate 12, and thinning the plastic package 16, so as to cut off the bonding wire to form the shielding arc 15 and expose the shielding arc 15.

如图4所示,在所述基板12上形成包覆所述倒装芯片13、所述芯片或元器件14、所述屏蔽线弧15和所述接地连接垫11的塑封体16。此时,屏蔽线弧15并未裸露于塑封体16,即塑封体16的高度明显大于屏蔽线弧15顶端A的高度。As shown in FIG. 4 , a plastic package 16 covering the flip chip 13 , the chip or component 14 , the shielding arc 15 and the ground connection pad 11 is formed on the substrate 12 . At this time, the shielded wire arc 15 is not exposed to the plastic package 16 , that is, the height of the plastic package 16 is obviously greater than the height of the top A of the shielded wire arc 15 .

然后,如图5所示,利用背磨工艺等对塑封体16进行减薄,使得打线的顶端被截断并形成两段屏蔽线弧15,而且两段屏蔽线弧15的顶端均从暴露出塑封体16的背面(远离基板的表面)露出。Then, as shown in FIG. 5 , the plastic package body 16 is thinned by back grinding process, etc., so that the top of the bonding wire is truncated and two sections of shielding arcs 15 are formed, and the tops of the two sections of shielding arcs 15 are exposed from the The back side (the surface away from the substrate) of the plastic package 16 is exposed.

S6:在所述塑封体16背面形成电磁屏蔽层17,使所述电磁屏蔽层17与所述屏蔽线弧15电连接。S6: Form an electromagnetic shielding layer 17 on the back of the plastic package 16, and electrically connect the electromagnetic shielding layer 17 to the shielding arc 15.

如图6所示,利用溅镀、涂敷等工艺在所述塑封体16背面形成金属的电磁屏蔽层17。并且,电磁屏蔽层17与屏蔽线弧15暴露的顶端电连接。在本实施例中,是对整条(striplevel,也称为“板级”)封装结构的表面,通过电镀、溅射等方式将电磁屏蔽层17覆盖于塑封体16表面,形成屏蔽层。并且,通过裸露于塑封体16表面的屏蔽线弧15与接地连接垫11或可焊线金属层22相连,以此实现电磁屏蔽。As shown in FIG. 6 , a metal electromagnetic shielding layer 17 is formed on the back of the plastic package 16 by sputtering, coating and other processes. Moreover, the electromagnetic shielding layer 17 is electrically connected to the exposed top end of the shielding arc 15 . In this embodiment, the electromagnetic shielding layer 17 is covered on the surface of the plastic package 16 by means of electroplating, sputtering, etc. to form a shielding layer on the surface of the entire strip level (also referred to as “board level”) packaging structure. Furthermore, electromagnetic shielding is realized by connecting the shielding wire arc 15 exposed on the surface of the plastic package 16 to the ground connection pad 11 or the wire-weldable metal layer 22 .

可焊线金属层22为倒装芯片13上的屏蔽线弧15做机械连接以及电路导通,干扰信号通过屏蔽线弧15传导电磁屏蔽层17,再通过电磁屏蔽层17传导至接地连接垫11,从而实现电磁屏蔽。The wire-weldable metal layer 22 is used for mechanical connection and circuit conduction of the shielding arc 15 on the flip chip 13, and the interference signal is transmitted to the electromagnetic shielding layer 17 through the shielding arc 15, and then to the ground connection pad 11 through the electromagnetic shielding layer 17 , so as to achieve electromagnetic shielding.

在本实施例中,所述电磁屏蔽层17为金属层,包括三层结构,分别为不锈钢层,铜层和不锈钢层,覆盖在塑封体16表面。In this embodiment, the electromagnetic shielding layer 17 is a metal layer, including a three-layer structure, namely a stainless steel layer, a copper layer and a stainless steel layer, covering the surface of the plastic package 16 .

S7:对所述基板12进行切单。S7: performing singulation on the substrate 12 .

如图7所示,对已完成电磁屏蔽的基板12进行切割,形成单个分区电磁屏蔽的模组。As shown in FIG. 7 , the electromagnetic-shielded substrate 12 is cut to form a single-partitioned electromagnetic-shielded module.

<第二实施例><Second Embodiment>

作为替代方案,在经过了第一实施例中的S1~S5所述的步骤后,即对塑封体16进行背磨后,如图8所示,先对基板12进行切单,然后如图9所示,在单个封装体(unit level)下进行电磁屏蔽层17的覆盖。此种方式电磁屏蔽层17覆盖于除单颗模组的底表面的所有表面,电磁屏蔽层17不仅可以通过屏蔽线弧15与接地线相连,还可以与基板侧壁接地线123相连。As an alternative, after the steps described in S1 to S5 in the first embodiment, that is, after backgrinding the plastic package 16, as shown in FIG. As shown, the covering of the electromagnetic shielding layer 17 is performed under a single unit level. In this manner, the electromagnetic shielding layer 17 covers all surfaces except the bottom surface of a single module, and the electromagnetic shielding layer 17 can not only be connected to the ground wire through the shielding arc 15, but also can be connected to the ground wire 123 on the side wall of the substrate.

<第三实施例><Third Embodiment>

本实施例提供一种采用前述分区电磁屏蔽的模组制备方法得到的模组。This embodiment provides a module obtained by adopting the aforementioned module preparation method of partitioned electromagnetic shielding.

如图7和图9所示,该分区电磁屏蔽的模组包括接地连接垫11、基板12、倒装芯片13、芯片或元器件14、屏蔽线弧15、塑封体16以及电磁屏蔽层17。As shown in FIG. 7 and FIG. 9 , the partitioned electromagnetic shielding module includes a ground connection pad 11 , a substrate 12 , a flip chip 13 , a chip or component 14 , a shielding arc 15 , a plastic package 16 and an electromagnetic shielding layer 17 .

在倒装芯片13和芯片或元器件14之间设置屏蔽线弧15。屏蔽线弧15包括第一线弧15A和第二线弧15B。其中,第一线弧15A具有第一端151和第一顶端151A;第二线弧15B具有第二端152和第二顶端152B。第一线弧15A的第一端151与倒装芯片13上的可焊线金属层22连接,第一顶端151A与电磁屏蔽层17相连;第二线弧152的第二端152与接地连接垫11连接,第二顶端152B与电磁屏蔽层17相连。由此,形成接地的屏蔽线弧15。Shielding loops 15 are arranged between flip chip 13 and chip or component 14 . The shielding loop 15 includes a first loop 15A and a second loop 15B. Wherein, the first arc 15A has a first end 151 and a first top 151A; the second arc 15B has a second end 152 and a second top 152B. The first end 151 of the first line arc 15A is connected to the wire-bondable metal layer 22 on the flip chip 13, and the first top end 151A is connected to the electromagnetic shielding layer 17; the second end 152 of the second line arc 152 is connected to the ground connection pad 11 connection, the second top end 152B is connected to the electromagnetic shielding layer 17 . As a result, a grounded shielded arc 15 is formed.

结合图10、图11(a)和图11(b),倒装芯片13背面的可焊线金属层22可以具有不同的形状。可焊线金属层22可以是覆盖倒装芯片13的整个背面,也可以只覆盖倒装芯片13的外周缘。Referring to FIG. 10 , FIG. 11( a ) and FIG. 11( b ), the wire-bondable metal layer 22 on the backside of the flip chip 13 may have different shapes. The wire-bondable metal layer 22 may cover the entire backside of the flip chip 13 , or may only cover the outer periphery of the flip chip 13 .

根据屏蔽要求的不同,屏蔽线弧15的打线形式也不同。在前述实施例中,屏蔽线弧15只是位于倒装芯片13与芯片或元器件14之间,即,屏蔽线弧15只是一条直线状。然而,根据屏蔽要求的不同,屏蔽线弧15也可以是L形状或口字形状。优选的,在屏蔽线弧15为直线状或L形状时,可焊线金属层22覆盖所述倒装芯片的外周缘;在屏蔽线弧15为口字形状时,可焊线金属层22覆盖所述倒装芯片的整个背面。According to the different shielding requirements, the wiring form of the shielding arc 15 is also different. In the foregoing embodiments, the shielding arc 15 is only located between the flip chip 13 and the chip or component 14 , that is, the shielding arc 15 is only in a straight line. However, according to different shielding requirements, the shielding arc 15 can also be L-shaped or square-shaped. Preferably, when the shielding arc 15 is linear or L-shaped, the metal layer 22 that can be bonded covers the outer periphery of the flip chip; the entire backside of the flip chip.

结合图12(a)和12(b)所示,分区电磁屏蔽的模组包括接地连接垫11、基板12、倒装芯片13、芯片或元器件14、屏蔽线弧15、塑封体16电磁屏蔽层17,以及第二元器件18。图中,倒装芯片13的右侧为芯片或元器件14,倒装芯片13的前侧为第二元器件18。As shown in Figure 12(a) and 12(b), the electromagnetic shielding module of the partition includes a ground connection pad 11, a substrate 12, a flip chip 13, a chip or component 14, a shielding wire arc 15, and a plastic package body 16 for electromagnetic shielding. Layer 17, and the second component 18. In the figure, the right side of the flip chip 13 is the chip or component 14 , and the front side of the flip chip 13 is the second component 18 .

如图12(a)所示,在倒装芯片13与第二元器件18之间,以及倒装芯片13与芯片或元器件14之间均形成有接地连接垫11,那么屏蔽线弧15打在接地连接垫11和倒装芯片13上,形成L形,将倒装芯片13与元器件18之间进行电磁屏蔽,还将倒装芯片13与芯片或元器件14之间形成电磁屏蔽。As shown in Figure 12 (a), between the flip chip 13 and the second component 18, and between the flip chip 13 and the chip or component 14, a ground connection pad 11 is formed, so the shielding arc 15 An L-shape is formed on the ground connection pad 11 and the flip chip 13 to provide electromagnetic shielding between the flip chip 13 and the component 18 , and to form an electromagnetic shield between the flip chip 13 and the chip or component 14 .

如图12(b)所示,接地连接垫11围绕在倒装芯片13四周呈环形区域,屏蔽线弧15也就分布于倒装芯片13四周,将倒装芯片13与第二元器件18、芯片或元器件14均进行电磁屏蔽。这种口字形打线形式实现的电磁屏蔽的屏蔽效果比图12(a)所示L形设置的屏蔽线弧15的屏蔽效果更好。As shown in Figure 12(b), the ground connection pad 11 forms a ring-shaped area around the flip chip 13, and the shielding arc 15 is also distributed around the flip chip 13, connecting the flip chip 13 with the second component 18, Chips or components 14 are electromagnetically shielded. The shielding effect of the electromagnetic shielding realized by this zigzag-shaped wiring form is better than that of the L-shaped shielding arc 15 shown in FIG. 12( a ).

图13(a)和图13(b)示意了倒装芯片13的左右两侧分别设置有需要进行电磁屏蔽的第二元器件19和第三元器件20,并且倒装芯片13的前侧是第一元器件18。类似的,打线方式可以是L形(图13(a)所示)或口字形(图13(b)所示)。倒装芯片13上的屏蔽线弧可以将来自第三元器件20的干扰对倒装芯片13或第二元器件19进行隔绝。类似的,来自倒装芯片13或第二元器件19的干扰,也能被倒装芯片13上的屏蔽线弧进行隔绝,以避免第三元器件20受到干扰。Fig. 13 (a) and Fig. 13 (b) have illustrated that the left and right sides of flip chip 13 are respectively provided with the second component parts 19 and the 3rd component parts 20 that need electromagnetic shielding, and the front side of flip chip 13 is The first component 18. Similarly, the wiring pattern can be L-shaped (shown in Figure 13(a)) or square-shaped (shown in Figure 13(b)). The shielding arc on the flip chip 13 can isolate the interference from the third component 20 from the flip chip 13 or the second component 19 . Similarly, the interference from the flip chip 13 or the second component 19 can also be isolated by the shielding arc on the flip chip 13 to prevent the third component 20 from being interfered.

由此,可以防止芯片或元器件之间,或芯片和元器件之间产生电磁干扰现象。Thus, electromagnetic interference between chips or components, or between chips and components can be prevented.

<第四实施例><Fourth Embodiment>

本实施例中公开了另外一种分区电磁屏蔽的模组的制备方法。本实施例与第一实施例的不同之处在于,在对芯片进行塑封时,塑封体16的高度较低,如图14所示,使得屏蔽线弧15的顶端A暴露于塑封体16的表面,无需再对塑封体16进行背磨。This embodiment discloses another manufacturing method of a partitioned electromagnetic shielding module. The difference between this embodiment and the first embodiment is that when the chip is plastic-encapsulated, the height of the plastic package 16 is relatively low, as shown in FIG. , no need to backgrind the plastic package 16.

具体而言,如图14~图16所示,该分区电磁屏蔽的模组的制备方法包括以下步骤:Specifically, as shown in Figures 14 to 16, the preparation method of the partitioned electromagnetic shielding module includes the following steps:

S1:在基板12上形成接地连接垫11;S1: forming ground connection pads 11 on the substrate 12;

S2:在基板12上安装倒装芯片13和芯片或元器件14;S2: installing flip chips 13 and chips or components 14 on the substrate 12;

S3:在所述倒装芯片13的背面形成可焊线金属层22;S3: forming a wire-bondable metal layer 22 on the back surface of the flip chip 13;

S5:在所述接地连接垫11和可焊线金属层22之间打线,以形成屏蔽线弧15;S5: Make a wire between the ground connection pad 11 and the weldable metal layer 22 to form a shielded wire arc 15;

S5:在所述基板12上形成塑封体16,使屏蔽线弧15的顶端A暴露于塑封体16表面;S5: forming a plastic package 16 on the substrate 12, exposing the top end A of the shielding arc 15 to the surface of the plastic package 16;

S6:在所述塑封体16背面形成电磁屏蔽层17,使所述电磁屏蔽层17与所述屏蔽线弧15电连接;S6: forming an electromagnetic shielding layer 17 on the back of the plastic package 16, so that the electromagnetic shielding layer 17 is electrically connected to the shielding arc 15;

S7:对所述基板12进行切单。S7: performing singulation on the substrate 12 .

作为替代方案,在经过了S1~S5所示的步骤后,如图17所示,先对基板12进行切单,然后如图18所示,对单颗模组进行电磁屏蔽层17的覆盖。同样,此种方式下,电磁屏蔽层17覆盖于除单颗模组的底表面的所有表面,电磁屏蔽层17不仅可以通过屏蔽线弧15与接地线相连,还可以与基板侧壁接地线123相连。As an alternative, after the steps shown in S1-S5, as shown in FIG. 17 , the substrate 12 is first cut into pieces, and then as shown in FIG. 18 , the single module is covered with the electromagnetic shielding layer 17 . Similarly, in this way, the electromagnetic shielding layer 17 covers all surfaces except the bottom surface of a single module, and the electromagnetic shielding layer 17 can not only be connected to the grounding wire through the shielding wire arc 15, but also can be connected to the grounding wire 123 on the side wall of the substrate. connected.

<第五实施例><Fifth Embodiment>

本发明还提供一种具有前述分区电磁屏蔽的模组的电路板。该电路板可用于智能手机、平板电脑等电子产品。The present invention also provides a circuit board with the aforementioned partitioned electromagnetic shielding module. This circuit board can be used in electronic products such as smartphones and tablets.

<第六实施例><Sixth Embodiment>

本发明还提供一种具有前述分区电磁屏蔽的模组的电子产品。该电子产品可以是智能手机、平板电脑、可穿戴电子设备、智能网联汽车等。The present invention also provides an electronic product with the aforementioned partitioned electromagnetic shielding module. The electronic product may be a smartphone, a tablet computer, a wearable electronic device, an intelligent connected car, and the like.

在本发明的多个实施例中,通过在倒装芯片背面及其周围的接地连接垫上打线,以实现芯片与元器件之间或芯片与芯片之间的电磁屏蔽。通过这种打线方法,可以降低屏蔽线弧高度,提高封装质量,简化工艺难度,在一定程度上,对基板的空间利用率进行了改善,达到提高封装集成度的需求。In multiple embodiments of the present invention, the electromagnetic shielding between chips and components or between chips is realized by bonding wires on the ground connection pads on the back of the flip chip and its surroundings. Through this wire bonding method, the height of the shielding wire arc can be reduced, the packaging quality can be improved, and the difficulty of the process can be simplified. To a certain extent, the space utilization rate of the substrate is improved to meet the requirement of increasing the packaging integration.

上面对本发明所提供的一种分区电磁屏蔽的模组、制备方法及电路板和电子产品进行了详细的说明。对本领域的一般技术人员而言,在不背离本发明实质内容的前提下对它所做的任何显而易见的改动,都将构成对本发明专利权的侵犯,将承担相应的法律责任。The module, preparation method, circuit board and electronic product provided by the present invention are described in detail above. For those of ordinary skill in the art, any obvious changes made to it without departing from the essence of the present invention will constitute an infringement of the patent right of the present invention and will bear corresponding legal responsibilities.

Claims (11)

1. The utility model provides a module of subregion electromagnetic shield, includes base plate, ground connection gasket, flip chip, chip or components and parts, shielding line arc, plastic-sealed body and electromagnetic shield layer, its characterized in that:
the surface of the flip chip remote from the substrate is provided with a solderable wire metal layer,
the ground connection pad is located on the substrate and between the flip chip and the chip or component,
the plastic package body covers the grounding connecting pad, the flip chip, the chip or the component and the shielding wire arc,
the electromagnetic shielding layer is positioned on the surface of the plastic package body,
the shielding wire arc is arranged between the flip chip and the chip or the component, one end of the shielding wire arc is connected with the weldable wire metal layer, and the other end of the shielding wire arc is connected with the electromagnetic shielding layer.
2. The partitioned electromagnetically shielded module of claim 1, wherein:
the shielding wire arcs comprise a first wire arc and a second wire arc, and the first wire arc is connected with the weldable wire metal layer and the electromagnetic shielding layer; the second wire arc is connected with the grounding connecting pad and the electromagnetic shielding layer.
3. The partitioned electromagnetically shielded module of claim 2, wherein:
the wire bondable metal layer covers the entire back surface of the flip chip or covers the outer perimeter of the flip chip.
4. A zoned electromagnetic shielding module according to claim 2, wherein:
the shielding line arc is linear, L-shaped or square.
5. The partitioned electromagnetically shielded module of claim 4, wherein:
when the shielding wire arc is in a linear shape or an L shape, the weldable wire metal layer covers the outer periphery of the flip chip; when the shielding wire arc is in a square shape, the solderable wire metal layer covers the whole back of the flip chip.
6. A preparation method of a partitioned electromagnetic shielding module is characterized by comprising the following steps:
s1: forming a ground connection pad on a substrate;
s2: mounting a flip chip and a chip or a component on a substrate;
s3: forming a solderable wire metal layer on the back surface of the flip chip;
s5: routing between the grounding connecting pad and the weldable metal layer to form a shielding wire arc;
s5: forming a plastic package body on the substrate, and exposing the top end of the shielding wire arc to the surface of the plastic package body;
s6: forming an electromagnetic shielding layer on the back of the plastic package body, so that the electromagnetic shielding layer is electrically connected with the shielding wire arc;
s7: and singulating the substrate.
7. A preparation method of a partitioned electromagnetic shielding module is characterized by comprising the following steps:
s1: forming a ground connection pad on a substrate;
s2: mounting a flip chip and a chip or a component on a substrate;
s3: forming a solderable wire metal layer on the back surface of the flip chip;
s5: routing between the grounding connecting pad and the weldable metal layer to form a shielding wire arc;
s5: forming a plastic package body on the substrate, thinning the plastic package body to cut off the routing to form a shielding line arc and expose the shielding line arc;
s6: forming an electromagnetic shielding layer on the back of the plastic package body, so that the electromagnetic shielding layer is electrically connected with the shielding wire arc;
s7: and cutting the substrate into single pieces.
8. A preparation method of a partitioned electromagnetic shielding module is characterized by comprising the following steps:
s1: forming a ground connection pad on a substrate;
s2: mounting a flip chip and a chip or a component on a substrate;
s3: forming a solderable wire metal layer on the back surface of the flip chip;
s5: routing between the grounding connecting pad and the weldable metal layer to form a shielding wire arc;
s5: forming a plastic package body on the substrate, and exposing the top end of the shielding wire arc to the surface of the plastic package body;
s6: singulating the substrate;
s7: and forming an electromagnetic shielding layer for the single packaging body, and enabling the electromagnetic shielding layer to be electrically connected with the shielding wire arc.
9. A preparation method of a partitioned electromagnetic shielding module is characterized by comprising the following steps:
s1: forming a ground connection pad on a substrate;
s2: mounting a flip chip and a chip or a component on a substrate;
s3: forming a solderable wire metal layer on the back surface of the flip chip;
s5: routing between the grounding connecting pad and the weldable wire metal layer to form a shielding wire arc;
s5: forming a plastic package body on the substrate, thinning the plastic package body to cut off the routing to form a shielding wire arc and expose the shielding wire arc;
s6: singulating the substrate;
s7: and forming an electromagnetic shielding layer for the single packaging body, and enabling the electromagnetic shielding layer to be electrically connected with the shielding wire arc.
10. A circuit board, comprising the partitioned electromagnetically shielded module as claimed in any one of claims 1 to 5.
11. An electronic product, characterized in that it comprises a partitioned electromagnetically shielded module as claimed in any one of claims 1 to 5.
CN202211394540.3A 2022-11-08 2022-11-08 Partition electromagnetic shielding module, preparation method, circuit board and electronic product Pending CN115763439A (en)

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US20070163802A1 (en) * 2006-01-19 2007-07-19 Triquint Semiconductors, Inc. Electronic package including an electromagnetic shield
US20080014678A1 (en) * 2006-07-14 2008-01-17 Texas Instruments Incorporated System and method of attenuating electromagnetic interference with a grounded top film
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