CN115798560A - Test method and test device for semiconductor structure - Google Patents

Abstract

The application relates to a testing method and testing device for a semiconductor structure. The method for testing a semiconductor structure includes the following steps: providing a memory array, the memory array includes a plurality of memory cells arranged in an array, a plurality of word lines, and a plurality of bit lines, and the plurality of bit lines are electrically connected to a plurality of sense amplifiers; Perform the following first loop step multiple times until all memory cells in the memory array are filled with 0s; the first loop step includes: selecting a word line as the first target word line, and turning on the first target word line; After a target word line is turned on and delayed for a first preset time, the sense amplifier is turned on; after the first target word line is turned on and delayed for a second preset time, the first target word line and the sense amplifier are turned off, and the first target word line is connected with the first target word line. The next word line adjacent to the word line is used as the first target word line in the next first cycle step. The present application improves the detection accuracy and detection efficiency of the short-circuit defect between the word line and the bit line.

Description

Semiconductor structure test method and test device

technical field

The present application relates to the technical field of integrated circuits, and in particular to a testing method and testing device for a semiconductor structure.

Background technique

DRAM (Dynamic Random Access Memory, DRAM) is a semiconductor device commonly used in electronic equipment such as computers, which is composed of a plurality of storage units, and each storage unit usually includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the opening and closing of the transistor, so that the stored data can be read through the bit line. Data information in the capacitor, or write data information into the capacitor.

Semiconductor structures such as DRAMs include word lines and bit lines. Most current word lines adopt Buried Word Line (BWL), and the bit line is electrically connected to the source of the transistor through a bit line plug. Due to the deviation of the manufacturing process, it may cause a short circuit between the buried word line, the bit line contact and the bit line contact plug (BLC), that is, a cross fail. The short circuit between the buried word line and the bit line contact plug will lead to the failure of the bit line and seriously affect the electrical performance of the semiconductor structure. However, currently there is no effective method for detecting the short defect between the buried word line and the bit line contact plug, thereby limiting the improvement of the semiconductor structure.

Therefore, how to effectively detect the short-circuit defect between the word line and the bit line and improve the electrical performance of the semiconductor structure is a technical problem to be solved urgently.

Contents of the invention

The semiconductor structure testing method and testing device provided by some embodiments of the present application are used to solve the problem that the short circuit defect between the word line and the bit line cannot be effectively detected, so as to improve the electrical performance of the semiconductor structure.

According to some embodiments, the present application provides a method for testing a semiconductor structure, comprising the following steps:

A memory array is provided, which includes a plurality of memory cells arranged in an array, a plurality of word lines arranged in parallel along a first direction, and a plurality of bit lines arranged in parallel along a second direction, and the plurality of The bit lines are electrically connected to a plurality of sense amplifiers, and the first direction intersects the second direction;

Execute the following first loop step multiple times until all the storage units in the storage array are filled with 0s;

The first cycle step comprises:

selecting a word line as a first target word line, and turning on the first target word line;

Turning on the sense amplifier after a delay of a first preset time since the first target word line is turned on;

After the first target word line is turned on and delayed for a second preset time, turn off the first target word line and the sense amplifier, and use the next word adjacent to the first target word line line as the first target word line for the next first cycle step.

In some embodiments, before performing the looping step, the following steps are also included:

All the memory cells in the memory array are filled with 0;

Refresh the storage array.

In some embodiments, before performing the loop step, the specific steps of writing all the memory cells in the memory array with 0s include:

Perform the following second loop step multiple times until all the storage cells in the storage array are filled with 0, the second loop step includes:

selecting a word line as a second target word line, and turning on the second target word line;

sequentially write 0 to all the memory cells connected to the second target word line;

Turning off the second target word line, and using the next word line adjacent to the second target word line as the second target word line in the next second loop step.

In some embodiments, the first cycle step comprises:

selecting a bit line as a target bit line, and turning on the target bit line;

performing the first sub-cycle step sequentially on a plurality of the word lines;

Turning off the target bit line, and using the next bit line adjacent to the target bit line as the target bit line of the next first cycle step;

Described first subcycle step comprises:

Selecting a word line as the first target word line, and turning on the first target word line, and writing 0 to the memory cells electrically connected to the first target word line and the target bit line middle;

Turning on the sense amplifier electrically connected to the target bit line after the first target word line is turned on and after a delay of a first preset time;

Turning off the first target word line and the sense amplifier electrically connected to the target bit line after the first target word line is turned on and delayed for a second preset time, and in order to communicate with the first target word line The next word line adjacent to each other is used as the first target word line in the next first cycle step.

In some embodiments, the first cycle step comprises:

selecting a word line as a first target word line, and performing a second sub-loop step on the first target word line;

After performing the second sub-loop step on the first target word line, using the next word line adjacent to the first target word line as the first target word line in the next first loop step;

Described second subcycle step comprises:

turning on the first target word line;

Turn on a plurality of the bit lines, write 0 to the plurality of memory cells connected to the first target word line and the plurality of bit lines;

Turning on the sense amplifiers electrically connected to the plurality of bit lines after the first target word line is turned on and after a delay of a first preset time;

Turning off the first target word line and the sense amplifiers electrically connected to the plurality of bit lines after the first target word line is turned on and delayed for a second preset time.

In some embodiments, the first cycle step comprises:

selecting a word line as a first target word line, and turning on the first target word line;

Turn on all the bit lines, write 0 to all the memory cells connected to the first target word line;

Turning on the sense amplifiers electrically connected to all the bit lines after the first target word line is turned on and delayed for a first preset time;

Turn off the first target word line and the sense amplifiers electrically connected to all the bit lines after the first target word line is turned on and delay for a second preset time, and communicate with the first target word line The next word line adjacent to the word line is used as the first target word line in the next first cycle step.

In some embodiments, the first preset time is 10 ns˜400 ns.

In some embodiments, the second preset time is 100 ns˜1000 ns.

In some embodiments, the number of the storage arrays is multiple; after all the storage units in one storage array are filled with 0, the following steps are also included:

refresh the storage array filled with 0;

Execute the first loop step on the next storage array until all the storage units in the next storage array are filled with 0s.

In some embodiments, after all the storage units in the storage array are filled with 0, the following steps are further included:

reading all of the memory cells in the memory array;

Judging whether the read values of all the memory cells are 0, if not, confirming that the word lines at the memory cells whose read values are not 0 are electrically connected to the bit lines.

In some embodiments, the specific steps of reading all the storage units in the storage array include:

Perform the third loop step multiple times until all the storage units in the storage array are read, the third loop step includes:

Selecting a word line as a third target word line, and reading all memory cells connected to the third target word line;

After all memory cells connected to the third target word line are read, the next word line adjacent to the third target word line is used as the third target word line in the next third loop step .

According to some other embodiments, the present application also provides a semiconductor structure testing device, including:

The writing module is used to perform the following first cycle steps multiple times until all the storage units in the storage array are filled with 0; the storage array includes a plurality of storage units arranged in an array, a plurality of storage units along the Word lines arranged in parallel in one direction, and a plurality of bit lines arranged in parallel in a second direction, the plurality of bit lines are electrically connected to a plurality of sense amplifiers, and the first direction intersects with the second direction; The first cycle step includes: selecting a word line as a first target word line, and turning on the first target word line; after the first target word line is turned on and delayed for a first preset time, turning on all the sense amplifier; after the first target word line is turned on and delayed for a second preset time, turn off the first target word line and the sense amplifier, and use the next target word line adjacent to the first target word line One of the word lines is used as the first target word line in the next first cycle step.

In some embodiments, the testing device of the semiconductor structure further includes:

A refresh module, configured to refresh the storage array filled with 0s.

In some embodiments, also include:

a reading module, configured to read all the storage units in the storage array;

The judging module is used for judging whether the read values of all the memory cells are 0, and if not, confirming that the memory array has a short-circuit defect between the bit line and the word line.

In some embodiments, the first preset time is 10 ns˜400 ns.

In some embodiments, the second preset time is 100 ns˜1000 ns.

The semiconductor structure testing method and testing device provided by some embodiments of the present application write all 0s in all the memory cells of the memory array, and use the voltage difference generated between the high potential of the word line when it is turned on and the low potential of the bit line To simulate the phenomenon of short circuit between word line and bit line. In some embodiments of the present application, the sense amplifier is turned on after the target word line is activated and delayed for a first preset time, and the target word line is turned off after the target word line is activated and delayed for a second preset time, thereby prolonging the The time from turning on the target word line to the turning on of the sense amplifier and the time when the target word line is in an active state, so that once a short circuit between the word line and the bit line occurs, the sense amplifier can fully detect the defect, The accuracy and detection efficiency of short-circuit defect detection between the word line and the bit line are improved.

Description of drawings

Accompanying drawing 1 is the test method flow chart of semiconductor structure in the specific embodiment of the present application;

Accompanying drawing 2 is a schematic structural diagram of a storage array in a specific embodiment of the present application;

Accompanying drawing 3 is a schematic diagram of the testing method of the first semiconductor structure in the specific embodiment of the present application;

Accompanying drawing 4 is a schematic diagram of the testing method of the second semiconductor structure in the specific embodiment of the present application;

Accompanying drawing 5 is the schematic diagram of the testing method of the third semiconductor structure in the specific embodiment of the present application;

FIG. 6 is a structural block diagram of a testing device for a semiconductor structure in a specific embodiment of the present application.

Detailed ways

The specific implementations of the semiconductor structure testing method and testing device provided by the present application will be described in detail below with reference to the accompanying drawings.

This specific embodiment provides a test method for a semiconductor structure. Accompanying drawing 1 is a flow chart of a test method for a semiconductor structure in a specific embodiment of the present application. Accompanying drawing 2 is a schematic structural diagram of a storage array in a specific embodiment of the present application. 3 is a schematic diagram of the testing method of the first semiconductor structure in the specific embodiment of the present application. As shown in Fig. 1, Fig. 2 and Fig. 3, the testing method of described semiconductor structure comprises the following steps:

Step S11, providing a memory array, which includes a plurality of memory cells 20 arranged in an array, a plurality of word lines WL arranged in parallel along the first direction, and a plurality of bit lines WL arranged in parallel along the second direction A line BL, a plurality of bit lines BL are electrically connected to a plurality of sense amplifiers, and the first direction intersects the second direction.

Specifically, the first direction and the second direction may intersect obliquely or perpendicularly. The semiconductor structure may be, but not limited to, a DRAM. Correspondingly, the storage array may be a storage array in a DRAM. The storage array is located on the substrate, and the substrate has a plurality of active regions arranged in an array, and each active region includes a bit line contact region and a capacitor contact region. The word line WL may be a buried word line within the substrate. The bit line BL is electrically connected to the bit line contact region in the substrate through a bit line contact plug. When the manufacturing process is deviated, the bit line contact plug may contact the word line, thereby causing a short circuit connection between the bit line BL and the word line WL. Taking the structural diagram of the memory array shown in FIG. 2 as an example, each word line WL extends along the X-axis direction, and a plurality of the word lines WL are arranged in parallel along the Y-axis direction. Each of the bit lines BL extends along the Y-axis direction, and a plurality of the bit lines BL are arranged in parallel along the X-axis direction. In the structure shown in FIG. 2 , each word line WL intersects each bit line BL to form one memory cell 20 . The multiple mentioned in this specific embodiment refers to two or more.

A plurality of sense amplifiers are electrically connected to a plurality of bit lines BL in one-to-one correspondence, and each storage area unit 20 is electrically connected to one bit line BL, and one bit line BL is parallel to the Y-axis direction. The plurality of arranged storage units are electrically connected. Therefore, one inductive amplifier is electrically connected to multiple storage units 20 , and one storage unit 20 is electrically connected to only one inductive amplifier. When the bit line BL is electrically connected to the word line WL, the sense amplifier electrically connected to the shorted bit line BL can detect the The generated leakage current realizes the detection of the short-circuit defect between the bit line BL and the word line WL. The specific electrical connection between the sense amplifier and the bit line BL can be selected by those skilled in the art according to actual needs, as long as the leakage current generated when the bit line BL and the word line WL are short-circuited can be realized. Just check.

Step S12, performing the following first loop step multiple times until all the storage units 20 in the storage array are filled with 0s;

The first cycle step comprises:

selecting a word line as a first target word line, and turning on the first target word line;

Turning on the sense amplifier after a delay of a first preset time since the first target word line is turned on;

After the first target word line is turned on and delayed for a second preset time, turn off the first target word line and the sense amplifier, and use the next word adjacent to the first target word line line as the first target word line for the next first cycle step.

Specifically, in the process of performing defect detection on the memory array, all the memory cells 20 in the memory array are filled with 0, and the difference between the high potential of the word line when it is turned on and the low potential of the bit line is used to The voltage difference generated between them can simulate the phenomenon of short circuit between the word line and the bit line. By sequentially turning on each of the word lines WL, and sequentially writing 0 into the memory cells 20 electrically connected to the word lines that are turned on, by detecting the voltage corresponding to the memory cells 20 after the write operation is completed, The leakage current detected by the connected sense amplifier can confirm whether the word line WL and the bit line BL connected to the memory cell 20 that has completed the writing operation are short-circuited (that is, short-circuited). For example, when the leakage current detected by the sense amplifier is greater than a threshold, it is confirmed that the bit line BL electrically connected to the sense amplifier is short-circuited with the word line WL that is turned on. The specific value of the threshold can be set by those skilled in the art according to actual needs, for example, according to the specific structure of the storage unit 20 .

In this specific embodiment, the sense amplifier is turned on after the target word line is started and delayed for a first preset time, and the target word line is turned off after the target word line is started and delayed for a second preset time, thereby prolonging the delay from The time from when the target word line is turned on to when the sense amplifier is turned on and when the target word line is in an active state, so that once a short circuit occurs between the word line and the bit line, the sense amplifier can fully detect the defect and improve The accuracy and detection efficiency of the short defect detection between the word line and the bit line are improved.

In some embodiments, the first preset time is 10 ns˜400 ns. For example, the first preset time is 10 ns, 50 ns, 100 ns, 200 ns, or 400 ns.

In some embodiments, the second preset time is 100 ns˜1000 ns. For example, the second preset time is 100ns, 300ns, 500ns, 700ns, or 1000ns.

In some embodiments, before performing the looping step, the following steps are also included:

All the memory cells 20 in the memory array are filled with 0, as shown in (a) in Figure 3;

The storage array is refreshed, as shown in (b) in FIG. 3 .

In some embodiments, before performing the loop step, the specific steps of writing all the memory cells 20 in the memory array with 0s include:

Perform the following second loop step multiple times until all the storage cells 20 in the storage array are filled with 0, the second loop step includes:

Selecting a word line WL as a second target word line, and turning on the second target word line;

Sequentially write 0 to all the memory cells 20 connected to the second target word line;

Turning off the second target word line, and using the next word line WL adjacent to the second target word line as the second target word line in the next second loop step.

For example, the second cycle step is performed for the first time: select the word line WL located in the first row of the memory array as the second target word line; then, turn on the second target word line And all the bit lines BL, so that all the memory cells 20 electrically connected to the second target word line are filled with 0; then, turn off the second target word line. The second cycle step is performed for the second time: selecting the word line WL located in the second row of the memory array as the second target word line; after that, turning on the second target word line and all the bit line BL so that all the memory cells 20 electrically connected to the second target word line are filled with 0; then, the second target word line is turned off. Perform the second loop step for the third time: select the word line WL located in the third row of the memory array as the second target word line; then, turn on the second target word line and all the bit line BL so that all the memory cells 20 electrically connected to the second target word line are filled with 0; then, the second target word line is turned off. By analogy, by performing the second loop step for several times, all the word lines WL in the memory array are turned on and off, so as to write 0s in the memory array.

In this specific embodiment, before entering the test mode and executing the first loop step for multiple times, the second loop step is executed multiple times to write all 0s in the storage array to avoid other defects in the storage array Influenced by the influence, it is ensured that the leakage current detected by the sense amplifier is caused by the short circuit between the word line WL and the bit line BL, thereby further improving the accuracy and reliability of the test results.

In other embodiments, the first cycle step includes:

selecting a bit line as a target bit line, and turning on the target bit line;

performing the first sub-cycle step sequentially on a plurality of the word lines;

Turning off the target bit line, and using the next bit line adjacent to the target bit line as the target bit line of the next first cycle step;

Described first subcycle step comprises:

Selecting a word line WL as the first target word line, and turning on the first target word line, and writing 0 to the storage device electrically connected to the first target word line and the target bit line in the unit;

Turning on the sense amplifier electrically connected to the target bit line after the first target word line is turned on and after a delay of a first preset time;

Turning off the first target word line and the sense amplifier electrically connected to the target bit line after the first target word line is turned on and delayed for a second preset time, and in order to communicate with the first target word line The next adjacent word line WL is used as the first target word line in the next first cycle step.

For example, after entering the test mode, the first cycle step is performed for the first time: selecting the bit line BL located in the first column of the memory array as a target bit line, and turning on the target bit line. Next, execute the first sub-cycle step for the first time: select the word line WL located in the first row of the memory array as the first target word line, turn on the first target word line, and write 0 to In one of the memory cells electrically connected to both the first target word line and the target bit line; after the first target word line is turned on and delayed for a first preset time, the target bit line is turned on The sense amplifier electrically connected to the first target word line and the sense amplifier electrically connected to the target bit line are turned off after a delay of a second preset time since the first target word line is turned on. Next, the first sub-cycle step is performed for the second time: select the word line WL located in the second row of the memory array as the first target word line, and turn on the first target word line, and write 0 to In one of the memory cells electrically connected to both the first target word line and the target bit line; after the first target word line is turned on and delayed for a first preset time, the target bit line is turned on The sense amplifier electrically connected to the first target word line and the sense amplifier electrically connected to the target bit line are turned off after a delay of a second preset time since the first target word line is turned on. By analogy, until a plurality of the word lines WL have completed the first sub-cycle step, so that all the memory cells 20 electrically connected to the target bit line have completed the operation of writing 0, as shown in Figure 3 In (c) shown.

After the target bit line is turned off, the first loop step is performed for the second time: selecting the bit line BL located in the second column of the memory array as the target bit line, and turning on the target bit line. Next, the first sub-cycle step is executed multiple times, so that all the memory cells 20 electrically connected to the target bit line complete the operation of writing 0. Wherein, the specific operation of executing the first sub-loop step multiple times is the same as the operation of executing the first sub-loop step multiple times in the first execution of the first loop step.

By analogy, after performing the first loop step several times, all the bit lines BL in the storage array have completed the first loop step in sequence, and the storage array is filled with 0s.

In other embodiments, the first cycle step includes:

Selecting a word line WL as a first target word line, and performing a second sub-loop step on the first target word line;

After performing the second sub-loop step on the first target word line, using the next word line WL adjacent to the first target word line as the first target word line in the next first loop step;

Described second subcycle step comprises:

turning on the first target word line;

Turn on a plurality of the bit lines, write 0 to the plurality of memory cells connected to the first target word line and the plurality of bit lines;

Turning on the sense amplifiers electrically connected to the plurality of bit lines after the first target word line is turned on and after a delay of a first preset time;

Turning off the first target word line and the sense amplifiers electrically connected to the plurality of bit lines after the first target word line is turned on and delayed for a second preset time.

FIG. 4 is a schematic diagram of a second semiconductor structure testing method in a specific embodiment of the present application. The operations of (a) and (b) in Fig. 4 are the same as the operations of (a) and (b) in Fig. 3, the only difference is that the first cycle step ((c) in Fig. The cycle steps ((c) in Figure 3) are different. In the embodiment shown in FIG. 4, after entering the test mode, the first cycle step is performed for the first time: selecting the word line WL located in the first row of the memory array as the first target word line . Next, perform the second sub-cycle step on the first target word line for the first time: turn on the first target word line for the first time; turn on the preset number of bit lines BL, and write 0 to and In the preset number of the memory cells 20 connected to the first target word line and a plurality of the bit lines; after the first target word line is turned on and delayed for a first preset time, the bit lines connected to the bit lines are turned on The sense amplifier electrically connected to the bit line BL; after the first target word line is turned on and delayed for a second preset time, the first target word line and the sense amplifiers electrically connected to several bit lines BL are turned off. the sense amplifier. Next, perform the second sub-cycle step on the first target word line for the second time: turn on the first target word line for the second time; The next preset number of the bit lines BL adjacent to the bit line BL that has been turned on in the second sub-cycle step, writing 0 to the first target word line and the next preset number of the bits In the next preset number of memory cells 20 connected by lines; after the first target word line is turned on and delayed for a first preset time, turn on the next preset number of the bit lines BL electrically connected the sense amplifier; after the first target word line is turned on and delayed for a second preset time, turn off the first target word line and the sense amplifier electrically connected to the next preset number of the bit lines BL amplifier. By analogy, until all the memory cells 20 connected to the first target word line are filled with 0s.

Executing the first loop step for the second time: selecting the word line WL located in the second row of the memory array as the first target word line. Next, the second sub-cycle step is executed multiple times, so that all the memory cells 20 electrically connected to the target word line complete the operation of writing 0. Wherein, the specific operation of executing the second sub-cycle step multiple times is the same as the operation of executing the second sub-cycle step multiple times in the first execution of the first cycle step.

In other embodiments, the first cycle step includes:

Selecting a word line WL as a first target word line, and turning on the first target word line;

Turn on all the bit lines, write 0 to all the memory cells connected to the first target word line;

Turning on the sense amplifiers electrically connected to all the bit lines after the first target word line is turned on and delayed for a first preset time;

Turn off the first target word line and the sense amplifiers electrically connected to all the bit lines after the first target word line is turned on and delay for a second preset time, and communicate with the first target word line The next word line adjacent to the word line is used as the first target word line in the next first cycle step.

FIG. 5 is a schematic diagram of a third semiconductor structure testing method in a specific embodiment of the present application. The (a) and (b) operations in Fig. 5 are the same as the (a) and (b) operations in Fig. 3, the only difference is that the first cycle step ((c) in Fig. The cycle steps ((c) in Figure 3) are different. In the embodiment shown in FIG. 5, after entering the test mode, the first cycle step is performed for the first time: select the word line WL located in the first row of the memory array as the first target word line, and Turn on the first target word line; turn on all the bit lines BL, write 0 to all the memory cells 20 connected to the first target word line; turn on from the first target word line to After a delay of a first preset time, turn on the sense amplifiers electrically connected to all the bit lines BL; from the turn on of the first target word line to after a delay of a second preset time, turn off the first target word line line and the sense amplifiers are electrically connected to all of the bit lines BL.

Perform the first cycle step for the second time: select the word line WL located in the second row of the memory array as the first target word line, and turn on the first target word line; turn on all the bits Line BL, write 0 to all the memory cells 20 connected to the first target word line; after the first target word line is turned on and delayed for a first preset time, turn on and all the bits the sense amplifier electrically connected to the line BL; after the first target word line is turned on and delayed for a second preset time, turn off the first target word line and the sense amplifiers electrically connected to all the bit lines BL sense amplifier. By analogy, by performing the first loop step multiple times, all the word lines WL in the memory array are turned on and off, so that the memory array is filled with 0s.

In some embodiments, the number of the storage arrays is multiple; after all the storage units in one storage array are filled with 0, the following steps are also included:

refresh the storage array filled with 0;

Execute the first loop step on the next storage array until all the storage units in the next storage array are filled with 0s.

As shown in FIG. 3 , FIG. 4 and FIG. 5 , there are multiple storage arrays, and the multiple storage arrays are arranged in parallel along the Z-axis direction. After all the memory cells in one of the memory arrays are filled with 0, exit the test mode (i.e. (d) operation in Fig. 3, (d) operation in Fig. 4 and (d) operation in Fig. 4 ), and refresh the memory array that has been filled with 0 (ie (e) operation in FIG. 3 , (e) operation in FIG. 4 and (e) operation in FIG. 4 ). Afterwards, carry out described test mode again, carry out described first cycle step (operation (c) in Fig. 3, (c) operation in Fig. 4 and (c) operation in Fig. ), until all the storage units in the next storage array are filled with 0. After the next storage array is filled with 0s, the test mode is exited, and a refresh operation is performed on the storage array filled with 0s in the test mode. By analogy, until multiple storage arrays complete the operation of writing all 0s through the first loop step for multiple times.

In some embodiments, after all the storage units 20 in the storage array are filled with 0s, the following steps are further included:

Read all the memory cells 20 in the memory array ((f) operation in FIG. 3, (f) operation in FIG. 4 and (f) operation in FIG. 4);

Judging whether the read values of all the memory cells 20 are 0, if not, confirming that the word line WL at the memory cell 20 whose read value is not 0 is electrically connected to the bit line BL.

In some embodiments, the specific steps of reading all the storage units 20 in the storage array include:

Perform the third loop step multiple times until all the storage units 20 in the storage array are read, the third loop step includes:

Selecting a word line WL as a third target word line, and reading all memory cells 20 connected to the third target word line;

After all memory cells 20 connected to the third target word line are read, the next word line WL adjacent to the third target word line is used as the third target of the next third loop step word line.

For example, after all the storage arrays have completed the operation of writing all 0s by executing the first loop step for multiple times, the third loop step is performed for the first time: selecting one of the storage arrays The word line WL of the first row is used as a third target word line, and all memory cells 20 connected to the target word line are read. Afterwards, the third cycle step is performed for the second time: select the word line WL located in the second row of a memory array as the third target word line, and read all memory storage devices connected to the target word line. Unit 20. And so on, read row by row until all the storage units 20 in all the storage arrays are read.

Since the value written in the memory cell 20 is 0 in the write operation, if the word line WL is short-circuited to the bit line BL, the leakage caused by the short-circuit of the word line WL and the bit line BL Current is transferred to a capacitor electrically connected to the bit line BL. During the read operation, the leakage current in the capacitor will be transmitted to the memory cell 20 electrically connected to both the short-circuited word line WL and the bit line BL, thereby making the memory cell 20 The read value becomes 1. Therefore, by judging whether the read values of all the memory cells 20 are 0, it can be confirmed whether the word line WL and the bit line BL at the memory cell 20 are short-circuited.

According to some other embodiments, this specific embodiment also provides a testing device for a semiconductor structure. FIG. 6 is a structural block diagram of a testing device for a semiconductor structure in a specific embodiment of the present application. The semiconductor structure testing device provided in this specific embodiment can use the methods shown in FIGS. 1-5 to test the semiconductor structure. As shown in Fig. 1-Fig. 6, the testing device of described semiconductor structure comprises:

The writing module 61 is used to execute the following first loop step multiple times until all the storage units in the storage array are filled with 0; the storage array includes a plurality of storage units arranged in an array, a plurality of edge word lines arranged in parallel in the first direction, and a plurality of bit lines arranged in parallel in the second direction, the plurality of bit lines are electrically connected to a plurality of sense amplifiers, the first direction intersects the second direction ; The first cycle step includes: selecting a word line as the first target word line, and turning on the first target word line; after the first target word line is turned on and delayed for a first preset time, turning on the sense amplifier; after the first target word line is turned on until a second preset time is delayed, the first target word line and the sense amplifier are turned off, and the first target word line is adjacent to the first target word line The next word line is used as the first target word line in the next first cycle step.

In some embodiments, the testing device of the semiconductor structure further includes:

Refresh module 62, configured to refresh the memory array filled with 0s.

In some embodiments, also include:

A reading module 63, configured to read all the storage units in the storage array;

The judging module 64 is configured to judge whether the read values of all the memory cells are 0, and if not, confirm that the memory array has a short-circuit defect between the bit line and the word line.

The test device for the semiconductor structure may also include a control module 60, the control module 60 is connected to the write module 61, the refresh module 62, the read module 63 and the judgment module 64, the control The module 60 can be a host computer, which is used to receive user's operation instructions, and control the writing module 61, the refreshing module 62, the reading module 63 and the judging module 64 to perform corresponding operations.

The test method and test device for the semiconductor structure provided in this specific embodiment are all filled with 0 in all the memory cells of the memory array, and utilize the voltage difference generated between the high potential when the word line is turned on and the low potential of the bit line to Simulates the phenomenon of a short circuit between a word line and a bit line. In some embodiments of the present application, the sense amplifier is turned on after the target word line is activated and delayed for a first preset time, and the target word line is turned off after the target word line is activated and delayed for a second preset time, thereby prolonging the The time from turning on the target word line to the turning on of the sense amplifier and the time when the target word line is in an active state, so that once a short circuit between the word line and the bit line occurs, the sense amplifier can fully detect the defect, The accuracy and detection efficiency of short-circuit defect detection between the word line and the bit line are improved.

The above description is only the preferred implementation mode of the present application, and it should be pointed out that for those of ordinary skill in the art, without departing from the principle of the application, some improvements and modifications can also be made, and these improvements and modifications should also be regarded as For the scope of protection of this application.

Claims (16)

1. A method for testing a semiconductor structure, comprising the steps of: A memory array is provided, which includes a plurality of memory cells arranged in an array, a plurality of word lines arranged in parallel along a first direction, and a plurality of bit lines arranged in parallel along a second direction, and the plurality of The bit lines are electrically connected to a plurality of sense amplifiers, and the first direction intersects the second direction; Execute the following first loop step multiple times until all the storage units in the storage array are filled with 0s; The first cycle step comprises: selecting a word line as a first target word line, and turning on the first target word line; Turn on the sense amplifier after the first target word line is turned on until a delay of a first preset time; turn off the first target word line after the first target word line is turned on and delay a second preset time and the sense amplifier, and use the next word line adjacent to the first target word line as the first target word line in the next first cycle step. 2. The method for testing a semiconductor structure according to claim 1, further comprising the steps of: All the memory cells in the memory array are filled with 0; Refresh the storage array. 3. The method for testing a semiconductor structure according to claim 2, wherein, before performing the loop step, the specific steps of writing all 0s in all the memory cells in the memory array include: performing the following second step multiple times The looping step, until all the storage cells in the storage array are filled with 0, the second looping step includes: selecting a word line as a second target word line, and turning on the second target word line; sequentially write 0 to all the memory cells connected to the second target word line; Turning off the second target word line, and using the next word line adjacent to the second target word line as the second target word line in the next second loop step. 4. The method for testing a semiconductor structure according to claim 1, wherein the first cycle step comprises: selecting a bit line as a target bit line, and turning on the target bit line; performing the first sub-cycle step sequentially on a plurality of the word lines; Turning off the target bit line, and using the next bit line adjacent to the target bit line as the target bit line of the next first cycle step; Described first subcycle step comprises: Selecting a word line as the first target word line, and turning on the first target word line, and writing 0 to the memory cells electrically connected to the first target word line and the target bit line middle; Turning on the sense amplifier electrically connected to the target bit line after the first target word line is turned on and after a delay of a first preset time; Turning off the first target word line and the sense amplifier electrically connected to the target bit line after the first target word line is turned on and delayed for a second preset time, and in order to communicate with the first target word line The next word line adjacent to each other is used as the first target word line in the next first cycle step. 5. The method for testing a semiconductor structure according to claim 1, wherein the first cycle step comprises: selecting a word line as a first target word line, and performing a second sub-loop step on the first target word line; After performing the second sub-loop step on the first target word line, using the next word line adjacent to the first target word line as the first target word line in the next first loop step; Described second subcycle step comprises: turning on the first target word line; Turn on a plurality of the bit lines, write 0 to the plurality of memory cells connected to the first target word line and the plurality of bit lines; Turning on the sense amplifiers electrically connected to the plurality of bit lines after the first target word line is turned on and after a delay of a first preset time; Turning off the first target word line and the sense amplifiers electrically connected to the plurality of bit lines after the first target word line is turned on and delayed for a second preset time. 6. The method for testing a semiconductor structure according to claim 1, wherein the first cycle step comprises: selecting a word line as a first target word line, and turning on the first target word line; Turn on all the bit lines, write 0 to all the memory cells connected to the first target word line; Turning on the sense amplifiers electrically connected to all the bit lines after the first target word line is turned on and delayed for a first preset time; Turn off the first target word line and the sense amplifiers electrically connected to all the bit lines after the first target word line is turned on and delay for a second preset time, and communicate with the first target word line The next word line adjacent to the word line is used as the first target word line in the next first cycle step. 7 . The method for testing a semiconductor structure according to claim 1 , wherein the first preset time is 10 ns˜400 ns. 8 . The method for testing a semiconductor structure according to claim 1 , wherein the second preset time is 100 ns˜1000 ns. 9. The method for testing a semiconductor structure according to claim 1, wherein the number of the memory arrays is multiple; after all the memory cells in one memory array are filled with 0s, further comprising the following steps : refresh the storage array filled with 0; Execute the first loop step on the next storage array until all the storage units in the next storage array are filled with 0s. 10. The testing method of the semiconductor structure according to claim 1, characterized in that, after all the memory cells in the memory array are filled with 0, further comprising the steps of: reading all of the memory cells in the memory array; Judging whether the read values of all the memory cells are 0, if not, confirming that the word lines at the memory cells whose read values are not 0 are electrically connected to the bit lines. 11. The method for testing a semiconductor structure according to claim 10, wherein the specific steps of reading all of the memory cells in the memory array include: Perform the third loop step multiple times until all the storage units in the storage array are read, the third loop step includes: Selecting a word line as a third target word line, and reading all memory cells connected to the third target word line; After all memory cells connected to the third target word line are read, the next word line adjacent to the third target word line is used as the third target word line in the next third loop step . 12. A testing device for a semiconductor structure, comprising: The writing module is used to perform the following first cycle steps multiple times until all the storage units in the storage array are filled with 0; the storage array includes a plurality of storage units arranged in an array, a plurality of storage units along the Word lines arranged in parallel in one direction, and a plurality of bit lines arranged in parallel in a second direction, the plurality of bit lines are electrically connected to a plurality of sense amplifiers, and the first direction intersects with the second direction; The first cycle step includes: selecting a word line as a first target word line, and turning on the first target word line; after the first target word line is turned on and delayed for a first preset time, turning on all the sense amplifier; after the first target word line is turned on and delayed for a second preset time, turn off the first target word line and the sense amplifier, and use the next target word line adjacent to the first target word line One of the word lines is used as the first target word line in the next first cycle step. 13. The testing device of semiconductor structure according to claim 12, is characterized in that, the testing device of described semiconductor structure also comprises: A refresh module, configured to refresh the storage array filled with 0s. 14. The testing device for a semiconductor structure according to claim 12, further comprising: a reading module, configured to read all the storage units in the storage array; A judging module, configured to judge whether the read values of all the memory cells are 0, and if not, confirm that the word lines at the memory cells whose read values are not 0 are electrically connected to the bit lines. 15 . The testing device for a semiconductor structure according to claim 12 , wherein the first preset time is 10 ns˜400 ns. 16 . The testing device for a semiconductor structure according to claim 12 , wherein the second preset time is 100 ns˜1000 ns.

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