CN115799330A - High-voltage-resistant HEMT device and preparation method thereof - Google Patents

Abstract

The application relates to a high-voltage resistant HEMT device and a preparation method thereof. The high-voltage resistant HEMT device includes: a semiconductor substrate and a drift layer, a buffer layer, a channel layer and a potential barrier layer which are sequentially stacked on the front side of the semiconductor substrate. The gate is disposed on the barrier layer. The Schottky metal layer is disposed on the drift layer and is in contact with the first side of the buffer layer. The source is disposed on the Schottky metal layer and is in contact with the channel layer and the barrier layer. The intermediary metal layer is disposed on the drift layer and is in contact with the second side of the buffer layer, the channel layer and the barrier layer. The drain is arranged on the back side of the semiconductor substrate. In this application, a Schottky diode with an anode connected to the source and a cathode connected to the drain through the semiconductor substrate can be constructed through the Schottky metal layer, the drift layer, and the semiconductor substrate. When a high voltage is applied to the drain and the source When the pole is on, the Schottky diode will be broken down, thereby limiting the voltage between the drain and the source, and improving the ability to withstand high voltage.

Description

High voltage resistant HEMT device and its preparation method

technical field

The application belongs to the technical field of high electron mobility transistors, and in particular relates to a high-voltage resistant HEMT device and a preparation method thereof.

Background technique

At present, gallium nitride is a new type of third-generation semiconductor material with many excellent characteristics, and it will be the mainstream of power semiconductor development in the future. High electron density can be constructed by constructing a two-dimensional electron gas (2DEG; Two-Dimensional Electron Gas). Mobility Transistor (High Electron Mobility Transistor; HEMT) device. The commonly used substrates used with gallium nitride have their own advantages and disadvantages. Among them, although silicon carbide is expensive, it can greatly reduce the lattice dislocation of gallium nitride and improve the yield and device performance.

However, the existing power switch tubes made of gallium nitride and silicon carbide still have the problem of poor high voltage resistance, and are easily broken down when a high voltage is applied.

Contents of the invention

The purpose of this application is to provide a high-voltage resistant HEMT device and its preparation method, aiming to solve the problem of poor high-voltage resistance of traditional power switch tubes made of gallium nitride and silicon carbide.

The first aspect of the embodiments of the present application provides a high-voltage resistant HEMT device, including: a semiconductor substrate; a drift layer, a buffer layer, a channel layer and a barrier layer sequentially stacked on the front side of the semiconductor substrate; a gate pole, disposed on the barrier layer; Schottky metal layer, disposed on the drift layer, and in contact with the first side of the buffer layer, between the Schottky metal layer and the drift layer A Schottky contact is formed between them; the source electrode is arranged on the Schottky metal layer, is in contact with the channel layer and the barrier layer, and is in contact with the channel layer and the barrier layer form an ohmic contact between them; an intermediary metal layer is disposed on the drift layer and is in contact with the second side of the buffer layer, the channel layer, and the barrier layer; wherein, the second side is in contact with the second side of the barrier layer The first side is opposite to the first side; the drain is arranged on the back side of the semiconductor substrate.

In one embodiment, the thickness of the Schottky metal layer is less than or equal to the sum of the thicknesses of the buffer layer and the channel layer.

In one embodiment, a P-type capping layer is further included; the P-type capping layer is disposed between the barrier layer and the gate.

In one embodiment, the source electrode includes a filling metal layer and a connection metal layer; the filling metal layer extends from the upper surface of the barrier layer to the buffer layer; the connection metal layer is arranged on the barrier layer above the barrier layer and connected to the filling metal layer.

In one embodiment, the material of the gate is Schottky metal, and the material of the source and the drain is ohmic metal.

In one embodiment, both the semiconductor substrate and the drift layer are N-type silicon carbide.

In one embodiment, the concentration of N-type dopant ions in the drift layer is smaller than the concentration of N-type dopant ions in the semiconductor substrate.

In one embodiment, the material of the channel layer is gallium nitride, and the material of the barrier layer is aluminum gallium nitride.

In one embodiment, the material of the P-type capping layer is P-type GaN.

The second aspect of the embodiment of the present application provides a method for manufacturing a high-voltage HEMT device, including: sequentially forming a drift layer, a buffer layer, a channel layer, a barrier layer, and a P-type cap layer on the front surface of a semiconductor substrate; Etching the edge of the P-type capping layer; etching the first side of the buffer layer and the channel layer and the barrier layer until the drift layer is exposed to form a first trench; Etching the buffer layer and the second side of the channel layer and the barrier layer until the drift layer is exposed to form a second trench; filling the first trench with a metal material from below A Schottky metal layer and a source electrode are sequentially formed on the top, and an intermediary metal layer is formed in the second trench filling metal material; a Schottky contact is formed between the Schottky metal layer and the drift layer, and the source An ohmic contact is formed between the electrode, the channel layer and the barrier layer; a gate is formed on the P-type cap layer, and a drain is constructed on the back of the semiconductor substrate.

Compared with the prior art, the embodiment of the present application has the beneficial effect that a two-dimensional electron gas will be formed when the channel layer is in contact with the barrier layer. In this application, the drain is arranged on the back of the semiconductor substrate, and The two-dimensional electron gas and the drift layer are connected through the intermediary metal layer, so that the source is connected to the drain through the two-dimensional electron gas, the intermediary metal layer, the drift layer and the semiconductor substrate in order to realize power transmission, so that it can be used in HEMT devices. Under the premise of high-speed on-off characteristics, the ability of the device to withstand high voltage is improved through the drift layer and the semiconductor substrate.

At the same time, this application can construct a Schottky diode with the anode connected to the source and the cathode connected to the drain through the semiconductor substrate through the Schottky metal layer, the drift layer, and the semiconductor substrate. When a high voltage is applied to the drain When connected to the source (the drain is at a high potential and the source is at a low potential), if the voltage is greater than the avalanche voltage of the Schottky diode constructed by the Schottky metal layer, the Schottky diode will be broken down, thereby The voltage between the drain and the source is limited to prevent the entire high-voltage resistant HEMT device from being burned by high voltage, and further improve the high-voltage withstand capability.

Description of drawings

FIG. 1 is a schematic structural view of a high-voltage HEMT device provided in the first embodiment of the present application;

FIG. 2 is a schematic structural view of a high-voltage HEMT device provided by another embodiment of the present application;

FIG. 3 is a schematic structural diagram of an insulating layer provided by another embodiment of the present application;

Fig. 4 is the flow chart of the preparation method of the high voltage resistant HEMT device provided by the second embodiment of the present application;

FIG. 5 is a schematic structural diagram of a high-voltage HEMT device after performing step S100 in the second embodiment of the present application;

FIG. 6 is a schematic structural diagram of a high-voltage HEMT device after performing step S200 in the second embodiment of the present application;

FIG. 7 is a schematic structural diagram of a high-voltage HEMT device after performing step S400 in the second embodiment of the present application;

8 is a flowchart of a specific preparation method for a high-voltage HEMT device provided in the second embodiment of the present application;

FIG. 9 is a schematic structural diagram of a high-voltage HEMT device after performing step S500 in the second embodiment of the present application;

FIG. 10 is a schematic structural diagram of a trapezoidal intermediary metal layer after step S500 is performed in the second embodiment of the present application;

FIG. 11 is a schematic structural diagram of the metal structure after step S500 is executed in the second embodiment of the present application.

Description of the above drawings: 100, semiconductor substrate; 200, drift layer; 300, buffer layer; 400, channel layer; 500, barrier layer; 510, first trench; 520, second trench; 600, gate pole; 610, P-type capping layer; 700, source; 710, filling metal layer; 720, connecting metal layer; 730, Schottky metal layer; 740, insulating layer; 800, intermediary metal layer; 810, first metal structure; 820, the second metal structure; 830, the third metal structure; 900, the drain.

Detailed ways

In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application, and are not intended to limit the present application.

It should be noted that when an element is referred to as being “fixed” or “disposed on” another element, it may be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

It is to be understood that the terms "length", "width", "top", "bottom", "front", "rear", "left", "right", "vertical", "horizontal", "top" , "bottom", "inner", "outer" and other indicated orientations or positional relationships are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the application and simplifying the description, rather than indicating or implying the referred device Or elements must have a certain orientation, be constructed and operate in a certain orientation, and thus should not be construed as limiting the application.

In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the present application, "plurality" means two or more, unless otherwise specifically defined.

Figure 1 shows a schematic structural view of the high-voltage HEMT device provided by the first embodiment of the present application. For the convenience of description, only the parts related to this embodiment are shown, and the details are as follows:

A high-voltage resistant HEMT device, comprising a semiconductor substrate 100, a drift layer 200, a buffer layer 300, a channel layer 400, and a barrier layer 500; wherein, the drift layer 200, the buffer layer 300, the channel layer 400, and the barrier layer 500 The channel layer 400 and the barrier layer 500 are stacked sequentially on the front surface of the semiconductor substrate 100 to form a two-dimensional electron gas. The buffer layer 300 is used to reduce lattice dislocation between the channel layer 400 and the drift layer 200 .

The high voltage HEMT device further includes a gate 600 , a Schottky metal layer 730 , a source 700 , an intervening metal layer 800 and a drain 900 .

The gate 600 is disposed on the barrier layer 500 . The Schottky metal layer 730 is disposed on the drift layer 200 and is in contact with the first side of the buffer layer 300 , forming a Schottky contact between the Schottky metal layer 730 and the drift layer 200 . The source electrode 700 is disposed on the Schottky metal layer 730 , is in contact with the channel layer 400 and the barrier layer 500 , and forms an ohmic contact with the channel layer 400 and the barrier layer 500 . The intermediary metal layer 800 is disposed on the drift layer 200 and is in contact with the second side of the buffer layer 300 as well as the channel layer 400 and the barrier layer 500 . Wherein, the second side is opposite to the first side, and the intermediary metal layer 800 is used to connect the drift layer 200 and the two-dimensional electron gas. The drain 900 is disposed on the backside of the semiconductor substrate 100 . Wherein, the material of the Schottky metal layer 730 is Schottky metal.

In this embodiment, the drain 900 is disposed on the back of the semiconductor substrate 100, and the two-dimensional electron gas and the drift layer 200 are connected through the intermediary metal layer 800, so that the source 700 passes through the two-dimensional electron gas, the intermediary metal layer 800, and the drift layer 200 sequentially. Layer 200 and semiconductor substrate 100 are connected to drain 900 . Since the drift layer 200 and the semiconductor substrate 100 have a strong ability to withstand high voltage, on the premise of still having the high-speed on-off characteristics of the HEMT device, it is avoided to apply an excessively high voltage to the two-dimensional electron gas, through the drift layer 200 and The semiconductor substrate 100 improves the ability of the device to withstand electrical high voltage.

It should be noted that, in this embodiment, by providing a Schottky metal layer 730 between the source electrode 700 and the drift layer 200, the Schottky metal layer 730 can form a Schottky contact (metal-semiconductor junction) with the drift layer 200, To construct a Schottky diode, that is, a Schottky diode with an anode connected to the source 700 and a cathode connected to the drain 900 is constructed between the source 700 and the drain 900 . When a high voltage is applied to the drain 900 and the source 700 (the drain 900 is at a high potential and the source 700 is at a low potential), if the voltage is greater than the Schottky formed by the Schottky metal layer 730 The avalanche voltage of the diode, the Schottky diode will be broken down, thereby limiting the voltage between the drain 900 and the source 700, preventing the entire high-voltage HEMT device from being burned by high voltage or preventing the high-voltage HEMT device from being misconducted. The ability to withstand high pressure is further improved.

Especially when the power device changes from the on state to the off state, if the external circuit is a circuit with high inductance, it is easy to make the power device bear a huge voltage, resulting in breakdown of the power device. However, the high-voltage HEMT device of this embodiment is provided with a Schottky diode. When the voltage between the source 700 and the drain 900 exceeds the avalanche voltage of the Schottky diode, the Schottky diode is broken down to realize a Zener diode. Therefore, the voltage between the source 700 and the drain 900 is limited, and the breakdown or false conduction of the high-voltage resistant HEMT device of this embodiment is avoided.

In this embodiment, the thickness of the Schottky metal layer 730 is less than or equal to the sum of the thicknesses of the buffer layer 300 and the channel layer 400 . In one example, as shown in FIG. 1 , the thickness of the Schottky metal layer 730 is equal to the sum of three quarters of the thickness of the channel layer 400 plus the thickness of the buffer layer 300, so that the source 700 can be directly connected to the channel. The two-dimensional electron gas between layer 400 and barrier layer 500 is sufficiently connected.

The high-voltage resistant HEMT device of this embodiment is a depletion-mode (D-mode) power device. When the voltage applied to the gate 600 is 0, the two-dimensional electron gas between the source 700 and the drain 900 is turned on. , that is, the depletion mode power device is in the conduction state. When the value of the negative voltage applied to the gate 600 is greater than the turn-on voltage of the depletion power device, the corresponding two-dimensional electron gas under the gate 600 will be cut off, and the depletion power device will be turned off.

As shown in FIG. 1, the filling metal layer 710 extends downward from the upper surface of the barrier layer 500, and the thickness of the filling metal layer 710 is greater than the thickness of the barrier layer 500, so that the filling metal layer 710 is directly connected to the formed two-dimensional electron gas. . In one example, the difference between the thicknesses of the filling metal layer 710 and the barrier layer 500 is equal to a quarter of the thickness of the channel layer 400 .

In this embodiment, the material of the gate 600 is Schottky metal, and the material of the source 700 and the drain 900 is ohmic metal. Wherein, the material of the gate 600 may be any one of nickel nitride (Ni ₃ N), aluminum (Al), and platinum (Pt), and the material of the source 700 and the drain 900 may be titanium (Ti). In an example, the drain 900 covers the entire backside of the semiconductor substrate 100 .

In this embodiment, the materials of the semiconductor substrate 100 and the drift layer 200 are both N-type silicon carbide.

Wherein, the concentration of N-type dopant ions in the drift layer 200 is smaller than the concentration of N-type dopant ions in the semiconductor substrate 100 .

The thickness of the drift layer 200 is positively related to the high voltage withstand capability of the high voltage HEMT device. In one example, the thickness of the drift layer 200 is five times the thickness of the semiconductor substrate 100 .

In this embodiment, the material of the channel layer 400 is gallium nitride (GaN). The material of the barrier layer 500 is aluminum gallium nitride (AlGaN). The material of the buffer layer 300 is aluminum nitride (AlN).

The material of the barrier layer 500 may also be any one of indium aluminum gallium nitride (InAlGaN) and indium gallium nitride (InGaN), and the corresponding material may be selected according to actual conditions.

In another embodiment, the high voltage HEMT device further includes a P-type capping layer 610 .

As shown in FIG. 2 , specifically, the P-type capping layer 610 is disposed between the barrier layer 500 and the gate 600 .

It should be noted that the power device provided with the P-type capping layer 610 is an enhanced (E-mode) power device. When a positive voltage greater than the turn-on voltage is applied to the gate 600, the source 700 to the intermediary metal layer The two-dimensional electron gas of 800 can be kept on, and the current received by the drain 900 can be transmitted to the source 700 through the semiconductor substrate 100 , the drift layer 200 , the intermediary metal layer 800 and the two-dimensional electron gas in sequence.

When the voltage applied to the gate 600 is less than the turn-on voltage or is a negative voltage, the corresponding two-dimensional electron gas under the gate 600 will be cut off, and the current received by the drain 900 will pass through the semiconductor substrate 100 and the drift layer in turn. After the 200 is transported to the intermediary metal layer 800 , it cannot continue to be transported to the source electrode 700 through the two-dimensional electron gas.

In this embodiment, the material of the P-type capping layer 610 is P-type gallium nitride (P-GaN).

In one embodiment, the thickness of the semiconductor substrate 100 is 10nm-30nm, the thickness of the drift layer 200 is 50nm-100nm, the thickness of the buffer layer 300 is 3nm-30nm, the thickness of the channel layer 400 is 3nm-30nm, the barrier The thickness of the layer 500 is 3nm-30nm.

In an example, the thickness of the semiconductor substrate 100 is 20 nm, the thickness of the drift layer 200 is 60 nm, the thickness of the buffer layer 300 is 20 nm, the thickness of the channel layer 400 is 20 nm, and the thickness of the barrier layer 500 is 20 nm. The thickness of the filling metal layer 710 is 25 nm, and correspondingly, the thickness of the Schottky metal 730 below the filling metal layer 710 is 35 nm.

In one embodiment, the thickness of the P-type capping layer 610 is 2 nm˜5 nm.

In another embodiment, as shown in FIG. 3 , an insulating layer 740 is further provided between the Schottky metal layer 730 and the buffer layer 300 and the channel layer 400. The insulating layer 740 is used to reduce the resulting leakage current.

Fig. 4 shows the flow chart of the preparation method of the high voltage resistant HEMT device provided by the third embodiment of the present application. For the convenience of explanation, only the parts related to this embodiment are shown, and the details are as follows:

A method for preparing a high-voltage resistant HEMT device, which can be used to prepare the high-voltage resistant HEMT device of any one of the above embodiments. The preparation method includes steps S100-S600.

In step S100 , a drift layer 200 , a buffer layer 300 , a channel layer 400 , a barrier layer 500 and a P-type cap layer 610 are sequentially formed on the front surface of the semiconductor substrate 100 .

A schematic structural diagram of the semiconductor substrate 100 , the drift layer 200 , the buffer layer 300 , the channel layer 400 , the barrier layer 500 and the P-type capping layer 610 is shown in FIG. 5 .

In an example, the thickness of the semiconductor substrate 100, the buffer layer 300, the channel layer 400, the barrier layer 500 and the P-type cap layer 610 is 10nm-100um, the thickness of the drift layer 200 is 20nm-500um, and the thickness of the drift layer 200 is The thickness can be 2 times to 5 times the thickness of the semiconductor substrate 100, wherein the thickness of the semiconductor substrate 100 and the thickness of the drift layer 200 determine the high voltage withstand capability of the high voltage HEMT device, the semiconductor substrate 100 and the drift layer 200 The thicker the corresponding high pressure resistance is stronger.

In step S200, the edge of the P-type capping layer 610 is etched.

The etched P-type capping layer 610 is shown in FIG. 6 , by etching the edge portion of the P-type capping layer 610 so that the P-type capping layer 610 is located in the central area of the surface of the barrier layer 500 . The P-type capping layer 610 can be used to construct the gate 600 .

In an example, the shape of the P-type capping layer 610 may be a polygon, a circle or an arc, which is not limited in this embodiment.

In step S300 , the buffer layer 300 , the first sides of the channel layer 400 and the barrier layer 500 are etched until the drift layer 200 is exposed, so as to form a first trench 510 .

In step S400 , the second sides of the buffer layer 300 , the channel layer 400 , and the barrier layer 500 are etched until the drift layer 200 is exposed, so as to form a second trench 520 .

As shown in FIG. 7 , both the first trench 510 and the second trench 520 go deep into the drift layer 200, and the second side is opposite to the first side, so that the first trench 510 and the second trench 520 are respectively located in the barrier layer. 500 (buffer layer 300 /channel layer 400 ), the P-type capping layer 610 is located on the barrier layer 500 between the first trench 510 and the second trench 520 .

In a specific application embodiment, the depths of the first trench 510 and the second trench 520 are the sum of the thicknesses of the buffer layer 300 , the channel layer 400 and the barrier layer 500 .

In step S500 , the metal material is filled in the first trench 510 from bottom to top to form the Schottky metal layer 730 and the source electrode 700 sequentially, and the metal material is filled in the second trench 520 to form the intervening metal layer 800 . A Schottky contact is formed between the Schottky metal layer 730 and the drift layer 200 , and an ohmic contact is formed between the source electrode 700 and the channel layer 400 and the barrier layer 500 .

In step S600 , a gate 600 is formed on the P-type capping layer 610 , and a drain 900 is formed on the back surface of the semiconductor substrate 100 .

Wherein, as shown in FIG. 8, step S500 and step S600 are specifically:

In step S500 , the first trench 510 is filled with a metal material from bottom to top to form a Schottky metal layer 730 to fill the metal layer 710 , and the second trench 520 is filled with a metal material to form an intervening metal layer 800 .

A schematic structural diagram of the Schottky metal layer 730 , the filling metal layer 710 and the intervening metal layer 800 is shown in FIG. 9 .

The filling metal layer 710 and the intervening metal layer 800 are located on opposite sides of the barrier layer 500, so that the gate 600 is disposed above the barrier layer 500 between the filling metal layer 710 and the intervening metal layer 800, so as to control the filling Conduction and disconnection of the two-dimensional electron gas between the metal layer 710 and the intervening metal layer 800 .

At the same time, step S500 of this embodiment will first form the Schottky metal layer 730 in the first trench 510, and then form the source electrode 700 (filling metal layer 710) on the Schottky metal layer 730, wherein the Schottky The material of the metal layer 730 is different from that of the filling metal layer 710 , the material of the Schottky metal layer 730 is Schottky metal, and the material of the filling metal layer 710 is ohmic metal.

It should be noted that the Schottky metal layer 730 can form a Schottky contact (metal-semiconductor junction) with the drift layer 200, thereby constructing a Schottky diode, the anode of the Schottky diode is connected to the source 700, The cathode is connected to the drain 900. When a high voltage is applied to the drain 900 and the source 700, if the voltage is greater than the avalanche voltage of the Schottky diode constructed by the Schottky metal layer 730, the Schottky The diode will be broken down, thereby limiting the voltage between the drain 900 and the source 700, preventing the entire high-voltage resistant HEMT device from being burned by high voltage, and further improving the high-voltage withstand capability.

In a specific application embodiment, the shape of the second trench 520 can be adjusted so that the cross-sectional shape of the intervening metal layer 800 is arc-shaped or trapezoidal. At this time, the width of the intervening metal layer 800 gradually increases from the bottom to the top. As shown in FIG. 10 , the cross-sectional shape of the intermediary metal layer 800 is trapezoidal.

As shown in FIG. 11, in a specific application embodiment, the intermediary metal layer 800 can be composed of a multi-layer metal structure, for example, the intermediary metal layer 800 can be composed of a first metal structure 810, a second metal structure 820 and a third metal structure 830, the first metal structure 810, the second metal structure 820 and the third metal structure 830 correspond to the buffer layer 300, the channel layer 400 and the barrier layer 500 one by one.

In a specific application embodiment, the widths of the first metal structure 810 , the second metal structure 820 and the third metal structure 830 gradually increase.

In a specific application embodiment, the widths of the first metal structure 810 , the second metal structure 820 and the third metal structure 830 are set according to an arithmetic difference ratio.

In a specific application embodiment, the shape of the interface between the first metal structure 810 and the buffer layer 300, the shape of the interface between the second metal structure 820 and the channel layer 400, the shape of the interface between the third metal structure 830 and the barrier layer 500 The shape of the interface between them can be different from each other.

In a specific application embodiment, the metal materials used in the first metal structure 810 , the second metal structure 820 and the third metal structure 830 may be different from each other. For example, the first metal structure 810 may be gold, and the second metal structure 820 may be copper.

In step S600, the gate 600 is formed on the P-type cap layer 610, the drain 900 is formed on the back surface of the semiconductor substrate 100, and the connection metal layer 720 connected to the filling metal layer 710 is formed above the barrier layer 500 .

The structure of the gate 600 , the drain 900 and the connection metal layer 720 is shown in FIG. 2 , the filling metal layer 710 and the connection metal layer 720 together form the source 700 , and the overall cross-section of the source 700 is L-shaped. The filling metal layer 710 is used for connecting the two-dimensional electron gas, and the connecting metal layer 720 is used for connecting with an external circuit. In an example, the shapes of the gate 600 and the connection metal layer 720 may be polygonal, circular or arc-shaped, which is not limited in this embodiment. The thicknesses of the gate 600 , the connection metal layer 720 and the drain 900 are all 10nm-100um.

In this embodiment, the drain 900 is disposed on the back of the semiconductor substrate 100, and the two-dimensional electron gas and the drift layer 200 are connected through the intermediary metal layer 800, so that the source 700 passes through the two-dimensional electron gas, the intermediary metal layer 800, and the drift layer 200 sequentially. Layer 200 and semiconductor substrate 100 are connected to drain 900 . Since the drift layer 200 and the semiconductor substrate 100 have a strong ability to withstand high voltage, the drift layer 200 and the semiconductor substrate 100 can improve the ability of the device to withstand high voltage under the premise of still having the high-speed on-off characteristics of the HEMT device. .

In this embodiment, the material of the gate 600 is Schottky metal, and the material of the source 700 and the drain 900 is ohmic metal.

In this embodiment, the materials of the semiconductor substrate 100 and the drift layer 200 are both N-type silicon carbide.

Specifically, the concentration of N-type dopant ions in the drift layer 200 is smaller than the concentration of N-type dopant ions in the semiconductor substrate 100 .

In this embodiment, the material of the channel layer 400 is gallium nitride (GaN). The material of the barrier layer 500 is aluminum gallium nitride (AlGaN).

The material of the barrier layer 500 may also be any one of indium aluminum gallium nitride (InAlGaN) and indium gallium nitride (InGaN), and the corresponding material may be selected according to actual conditions.

In one embodiment, in step S100, the drift layer 200, the buffer layer 300, the channel layer 400, the barrier layer 500 and the P-type cap layer 610 can be deposited by known methods such as chemical vapor deposition (Chemical VaporDeposition; CVD) , this embodiment does not limit the deposition methods of the drift layer 200 , the buffer layer 300 , the channel layer 400 , the barrier layer 500 and the P-type capping layer 610 .

In one embodiment, in step S200, step 300 and step S400, the buffer layer 300, the channel layer 400, the barrier layer 500 and the P-type cap can be formed using known methods such as dry etching or wet etching. The layer 610 is etched, and this embodiment does not limit the etching method of the buffer layer 300 , the channel layer 400 , the barrier layer 500 and the P-type cap layer 610 . In an example, the buffer layer 300 , the channel layer 400 , the barrier layer 500 and the P-type cap layer 610 may be etched by using an inductively coupled plasma etching method (Inductive Coupled Plasma; ICP).

In one embodiment, in step S500 and step S600, the Schottky metal layer 730, the gate 600, the source 700, the intervening metal layer 800, and the drain can be formed by known methods such as vacuum evaporation or sputtering. electrode 900 , this embodiment does not limit the specific construction methods of the Schottky metal layer 730 , the gate electrode 600 , the source electrode 700 , the intervening metal layer 800 and the drain electrode 900 .

It should be understood that the sequence numbers of the steps in the above embodiments do not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiment of the present application.

In the above-mentioned embodiments, the descriptions of each embodiment have their own emphases, and for parts that are not detailed or recorded in a certain embodiment, refer to the relevant descriptions of other embodiments.

The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still implement the foregoing embodiments Modifications to the technical solutions described in the examples, or equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the application, and should be included in the Within the protection scope of this application.

Claims (10)

1. A high voltage resistant HEMT device, characterized in that, comprising: semiconductor substrate; A drift layer, a buffer layer, a channel layer and a barrier layer are sequentially stacked on the front side of the semiconductor substrate; a gate disposed on the barrier layer; a Schottky metal layer, disposed on the drift layer and in contact with the first side of the buffer layer, forming a Schottky contact between the Schottky metal layer and the drift layer; The source electrode is disposed on the Schottky metal layer, is in contact with the channel layer and the barrier layer, and forms an ohmic contact with the channel layer and the barrier layer; an intermediary metal layer, disposed on the drift layer, and in contact with the buffer layer and the second sides of the channel layer and the barrier layer; wherein the second side is opposite to the first side ; The drain is arranged on the back side of the semiconductor substrate. 2. The high voltage resistant HEMT device according to claim 1, wherein the thickness of the Schottky metal layer is less than or equal to the sum of the thicknesses of the buffer layer and the channel layer. 3. The high voltage resistant HEMT device according to claim 1 or 2, further comprising a P-type capping layer; The P-type capping layer is disposed between the barrier layer and the gate. 4. The high voltage resistant HEMT device according to claim 1 or 2, wherein the source comprises a filling metal layer and a connecting metal layer; The filling metal layer extends from the upper surface of the barrier layer to the buffer layer; The connecting metal layer is disposed above the barrier layer and connected to the filling metal layer. 5. The high voltage HEMT device according to claim 1 or 2, characterized in that, the material of the gate is Schottky metal, and the material of the source and the drain is ohmic metal. 6. The high voltage HEMT device according to claim 1 or 2, characterized in that both the semiconductor substrate and the drift layer are N-type silicon carbide. 7. The high voltage resistant HEMT device according to claim 1 or 2, characterized in that the concentration of N-type dopant ions in the drift layer is lower than the concentration of N-type dopant ions in the semiconductor substrate. 8. The high voltage HEMT device according to claim 1 or 2, characterized in that, the material of the channel layer is gallium nitride, and the material of the barrier layer is aluminum gallium nitride. 9. The high voltage resistant HEMT device according to claim 3, characterized in that, the material of the P-type capping layer is P-type GaN. 10. A method for preparing a high-voltage resistant HEMT device, characterized in that, comprising: sequentially forming a drift layer, a buffer layer, a channel layer, a barrier layer and a P-type cap layer on the front side of the semiconductor substrate; etching the edge of the P-type capping layer; Etching the first sides of the buffer layer, the channel layer, and the barrier layer until the drift layer is exposed, so as to form a first trench; Etching the buffer layer and the second sides of the channel layer and the barrier layer until the drift layer is exposed, so as to form a second trench; A Schottky metal layer and a source electrode are sequentially formed in the first trench filling metal material from bottom to top, and an intermediary metal layer is formed in the second trench filling metal material; the Schottky metal layer and the drift A Schottky contact is formed between the layers, and an ohmic contact is formed between the source electrode, the channel layer and the barrier layer; A gate is formed on the P-type capping layer, and a drain is formed on the back of the semiconductor substrate.

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