CN115831919A - Antifuse Array Structure and Memory - Google Patents

Abstract

The embodiment of the application relates to the field of semiconductor circuit design, in particular to an antifuse array structure and a memory, comprising: a plurality of antifuse integrated structures arranged in an antifuse matrix in a bit line extending direction and a word line extending direction, the bit line extending direction and the word line extending direction being perpendicular to each other; each anti-fuse integrated structure is connected with two programming wires and two word lines; in the extending direction of the word lines, each anti-fuse integrated structure and the adjacent anti-fuse integrated structures are connected with the same programming conducting wire and the word lines in common; each anti-fuse integrated structure is connected with the adjacent anti-fuse integrated structures on one of the programming leads in the extension direction of the bit line. By providing a new layout mode of the anti-fuse array, the storage array with the same capacity only needs to occupy smaller layout area, so that the distance between anti-fuse storage units is increased on the basis of the original layout area, and the electrical isolation effect of electrical elements between the anti-fuse storage units is ensured.

Description

Antifuse Array Structure and Memory

technical field

The present application relates to the field of semiconductor circuit design, in particular to an antifuse array structure and memory.

Background technique

Semiconductor devices are essential to many modern applications. Among semiconductor devices, memory devices for storing data play an important role. With the advancement of technology, the capacity of memory devices is increasing, in other words, the density of memory arrays arranged on a substrate is increasing.

For the antifuse memory, the density of the storage array increases, and the interval between the antifuse memory units decreases, so it is difficult to ensure the electrical isolation effect of the electrical elements between the antifuse memory units.

Therefore, there is an urgent need to improve the layout of the antifuse array structure so as to ensure the electrical isolation effect of the electrical elements between the antifuse memory cells.

Contents of the invention

The embodiment of the present application provides an antifuse array structure and memory, and provides a new layout method of the antifuse array, so that the storage array with the same capacity only needs to occupy a smaller layout area, so that the original layout area Basically, the distance between the anti-fuse storage units is increased to ensure the electrical isolation effect of the electrical elements between the anti-fuse storage units.

An embodiment of the present application provides an antifuse array structure, including: a plurality of antifuse integrated structures arranged in an antifuse matrix in the extending direction of the bit line and the extending direction of the word line, and the extending direction of the bit line and the extending direction of the word line perpendicular to each other; each antifuse integrated structure is connected to two programming wires and two word lines; in the extending direction of the word line, each antifuse integrated structure is connected to the adjacent antifuse integrated structure for the same programming Wires and word lines; in the extending direction of the bit lines, each antifuse integrated structure and the adjacent antifuse integrated structure are commonly connected to one of the programming wires.

Each antifuse integrated structure is connected to two programming wires and two word lines, that is, the antifuse integrated structure includes two antifuse storage units and two switch units, and each antifuse storage unit is connected to A programming wire, each switch cell is controlled by a word line; those skilled in the art know that, in the antifuse array, the extension direction of the programming wire is the same as that of the word line, that is, the direction in which the programming wire extends It is perpendicular to the extension direction of the bit line; wherein, in the extension direction of the bit line, each antifuse integrated structure is connected to one of the adjacent antifuse integrated structures on one of the programming wires, that is, the same programming wire is used to control the same bit An antifuse memory cell in two adjacent antifuse integrated structures connected on the line, and the two antifuse memory cells respectively belong to two adjacent antifuse integrated structures, so that in the extending direction of the bit line , reducing the layout length of the anti-fuse memory array; on the basis of the original layout area and the layout of the memory array with the same capacity, the distance between the switch unit and the anti-fuse memory unit in the same active area is increased to The electrical isolation effect of the electrical components of the antifuse memory array is guaranteed.

In addition, multiple antifuse integrated structures connected by the same word line are arranged at equal intervals. That is, in the extending direction of the word line, the distances between adjacent antifuse integrated structures are equal, so as to prevent the gap between adjacent antifuse integrated structures from being small, so as to destroy the overall electrical isolation effect of the antifuse memory array.

In addition, multiple antifuse integrated structures connected by the same bit line are arranged at equal intervals. That is, in the extending direction of the bit line, the distances between adjacent antifuse integrated structures are equal, so as to prevent the gap between adjacent antifuse integrated structures from being small, so as to destroy the overall electrical isolation effect of the antifuse memory array.

In addition, each antifuse integrated structure includes: a first antifuse storage MOS tube, a first switch tube, a second switch tube and a second antifuse storage MOS tube; the gate of the first antifuse storage MOS tube The pole is connected to the first programming wire; the gate of the first switch tube is connected to the first word line, one end of the source or drain is connected to the first antifuse storage MOS tube, and the other end is connected to the bit line; the gate of the second switch tube Connected to the second word line, one end of the source or the drain is connected to the second antifuse storage MOS transistor, and the other end is connected to the bit line; the gate of the second antifuse storage MOS transistor is connected to the second programming wire.

In addition, in the extending direction of the bit line, the gate of the second antifuse storage MOS transistor of each antifuse integrated structure is connected to the gate of the first antifuse storage MOS transistor of the adjacent antifuse integrated structure same programming lead.

In addition, the antifuse integrated structure includes: an active region, and a first doped region, a second doped region, a third doped region, a fourth doped region and a fifth doped region located in the active region; The first doped region is the vacant end of the first antifuse storage MOS transistor, the second doped region is the common end of the first antifuse storage MOS transistor and the first switch transistor, and the third doped region is the first switch The common end of the tube and the second switch tube, the fourth doped area is the common end of the second switch tube and the second antifuse storage MOS tube, and the fifth doped area is the vacant end of the second antifuse storage MOS tube and an insulating layer covering the active region, the bit line is disposed on the insulating layer and is electrically connected to the third doped region.

In addition, in the extending direction of the word line, the widths of the active regions where the first switch tube, the second switch tube, the first antifuse storage MOS tube, and the second antifuse storage MOS tube are located are the same, so as to ensure that the antifuse matrix The spacing between the active devices in the antifuse matrix is the same, which further ensures the electrical isolation effect of the active devices in the antifuse matrix.

In addition, there is a conductive via hole in the insulating layer, and the conductive via hole exposes the top surface of the third doped region; the conductive layer is filled with the conductive via hole, and one end is in contact with the third doped region, and the other end is in contact with the bit line. The bit line and the conductive layer are connected through the bit line extension layer to ensure the stability of the electrical contact between the bit line and the conductive layer, and prevent the formed antifuse matrix from having conductive defects.

In addition, the conductive via hole is arranged on one side of the connected bit line, and the bit line is in contact with the conductive layer through the bit line extension layer. The bit line and the conductive layer are connected through the bit line extension layer to ensure the stability of the electrical contact between the bit line and the conductive layer, and prevent the formed antifuse matrix from having conductive defects.

In addition, the gate of the first antifuse storage MOS transistor is arranged on the top surface of the active region between the first doped region and the second doped region, and the gate of the first switch transistor is arranged on the second doped region and the top surface of the active region between the third doped region, the gate of the second switching transistor is arranged on the top surface of the active region between the third doped region and the fourth doped region, and the second antimelting The gate of the silk storage MOS transistor is arranged on the top surface of the active region between the fourth doped region and the fifth doped region.

In addition, the gate of the first antifuse storage MOS transistor is buried in the active region between the first doped region and the second doped region, and the gate of the first switch transistor is buried in the second doped region. In the active region between the second doped region and the third doped region, the gate of the second switch transistor is buried in the active region between the third doped region and the fourth doped region, and the second switch transistor is embedded in the active region between the third doped region and the fourth doped region. The gates of the two anti-fuse storage MOS transistors are embedded in the active region between the fourth doped region and the fifth doped region.

In addition, the antifuse matrix includes multiple columns of antifuse integrated structures arranged along the extending direction of the word lines, wherein the bit line connected to the first column of antifuse integrated structures is the first dummy bit line, and the last column of antifuse integrated structures The connected bit line is the second dummy bit line. By setting dummy bit lines at the edge of the antifuse matrix, it is ensured that the layout environment of the antifuse integrated structure located at the edge of the antifuse matrix is consistent with the layout environment of the antifuse integrated structure inside the matrix, so as to prevent defects in the edge antifuse memory cells and cannot normal work.

In addition, the antifuse matrix includes multiple rows of antifuse integrated structures arranged along the extending direction of the bit lines, wherein the gates of the first antifuse storage MOS transistors in the first row of antifuse integrated structures are connected to the first dummy programming The gate of the second antifuse storage MOS transistor in the last row of the antifuse integrated structure is connected to the second dummy programming wire. By setting virtual programming wires at the edge of the antifuse matrix, it is ensured that the layout environment of the antifuse integrated structure at the edge of the antifuse matrix is consistent with the layout environment of the antifuse integrated structure inside the matrix, so as to prevent defects in the edge antifuse memory cells and cannot normal work.

In addition, the gate of the first switch transistor in the antifuse integrated structure in the first row is connected to the first dummy word line, and the gate of the second switch transistor in the antifuse integrated structure in the last row is connected to the second dummy word line; wherein , the first dotted programming wire and the second dummy programming wire are located on the outermost side of the antifuse matrix, and the first dummy word line and the second dummy word line are located on the second outer side of the antifuse matrix. By setting dummy word lines at the edge of the antifuse matrix, it is ensured that the layout environment of the antifuse integrated structure located at the edge of the antifuse matrix is consistent with that of the antifuse integrated structure inside the matrix, so as to prevent defects in the edge antifuse memory cells and cannot normal work.

An embodiment of the present application further provides a memory, including a memory array, and the memory array adopts the above-mentioned antifuse array structure.

In the extension direction of the bit line, the layout length of the antifuse memory array is reduced. Therefore, on the basis of the original layout area and the layout of the memory array with the same capacity, the switch unit and the antifuse located in the same active area are increased. The distance between the memory cells is to ensure the electrical isolation effect of the electrical elements in the memory array formed by the antifuse integrated structure.

Description of drawings

FIG. 1 is a schematic circuit diagram of an antifuse integrated structure provided by an embodiment of the present application;

FIG. 2 is a schematic circuit diagram of an antifuse matrix provided by an embodiment of the present application;

3 is a schematic diagram of an antifuse memory unit connected to the same programming wire in an adjacent antifuse integrated structure provided by an embodiment of the present application;

FIG. 4 is a schematic top view of a layout structure of an antifuse integrated structure provided by an embodiment of the present application;

FIG. 5 is a schematic cross-sectional diagram of a layout structure of an antifuse integrated structure provided by an embodiment of the present application;

FIG. 6 is a schematic cross-sectional view of a layout structure of another antifuse integrated structure provided by an embodiment of the present application;

FIG. 7 is a schematic diagram of a layout structure of an antifuse matrix provided by an embodiment of the present application;

FIG. 8 is a schematic diagram of a layout structure of a bit line in an antifuse matrix provided by an embodiment of the present application;

FIG. 9 is a schematic diagram of a virtual structure of a memory provided by another embodiment of the present application;

FIG. 10 is a schematic diagram of the timing sequence of the programming phase and the reading phase of the memory provided by another embodiment of the present application.

Detailed ways

For the antifuse memory, the density of the storage array increases, and the interval between the antifuse memory units decreases, so it is difficult to ensure the electrical isolation effect of the electrical elements between the antifuse memory units.

An embodiment of the present application provides an antifuse array structure, and provides a new layout method of the antifuse array, so that a storage array with the same capacity only needs to occupy a smaller layout area, so that the original layout area Basically, the distance between the anti-fuse storage units is increased to ensure the electrical isolation effect of the electrical elements between the anti-fuse storage units.

Those skilled in the art can understand that in each embodiment of the present application, many technical details are provided for readers to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in this application can also be realized.

Figure 1 is a schematic circuit diagram of an antifuse integrated structure provided in this embodiment, Figure 2 is a schematic circuit diagram of an antifuse matrix provided in this embodiment, and Figure 3 is a schematic diagram of an adjacent antifuse integrated structure provided in this embodiment The schematic diagram of the antifuse memory unit connected to the same programming wire, FIG. 4 is a schematic top view of the layout structure of the antifuse integrated structure provided by this embodiment, and FIG. 5 is a layout structure of an antifuse integrated structure provided by this embodiment Schematic cross-sectional view, Figure 6 is a schematic cross-sectional view of the layout structure of another antifuse integrated structure provided in this embodiment, Figure 7 is a schematic layout diagram of the anti-fuse matrix provided in this embodiment, and Figure 8 is a schematic diagram of the layout structure provided in this embodiment A schematic diagram of the layout structure of the bit line in the antifuse matrix, the antifuse array structure provided in this embodiment will be further described in detail below in conjunction with the accompanying drawings, specifically as follows:

Referring to Figure 1 and Figure 2, the antifuse array structure includes:

A plurality of antifuse integrated structures 100 (refer to FIG. 1 ), are arranged in an antifuse matrix (refer to FIG. 2 ) in the extending direction of the bit line BL and the extending direction of the word line WL, and the extending direction of the bit line BL and the extending direction of the word line WL are mutually Vertically, each antifuse integrated structure 100 is connected with two programming wires PGM and two word lines WL.

In the extending direction of the word line WL, each antifuse integrated structure 100 and the adjacent antifuse integrated structure 100 are commonly connected to the same programming wire PGM and the word line WL.

In the extending direction of the bit line WL, each antifuse integrated structure 100 and the adjacent antifuse integrated structure 100 are commonly connected to one of the programming wires PGM.

It should be noted that FIG. 2 is only a partial schematic diagram of the formed antifuse matrix, which is only used to reflect the arrangement of the antifuse matrix in the embodiment of the present application, and does not constitute the bit line BL, word line WL and programming The limit on the number of wires PGM, in specific use, the number of corresponding bit lines BL, word lines WL and programming wires PGM can be selected according to the capacity of the required memory array; in addition, the values in "<>" are only used for Distinguishing between different bit lines BL, word lines WL or programming wires PGM does not constitute a limitation to this embodiment.

Each antifuse integrated structure 100 is connected to two programming wires PGM and two word lines WL, that is, the antifuse integrated structure 100 includes two antifuse storage units and two switch units, and each antifuse The memory cells are all connected to a programming wire PGM, and each switching unit is controlled by a word line WL; those skilled in the art know that, in the antifuse array, the extending direction of the programming wire PGM and the extending direction of the word line WL The same, that is, the extension direction of the programming wire PGM is perpendicular to the extension direction of the bit line BL; wherein, in the extension direction of the bit line BL, each antifuse integrated structure 100 is commonly connected to one of the adjacent antifuse integrated structures 100 On the programming wire PGM, that is, the same programming wire PGM is used to control an antifuse memory cell in two adjacent antifuse integrated structures 100 connected on the same bit line BL, that is, the same programming wire PGM is used to control the The two antifuse memory cells in the fuse integration structure 100, thereby reducing the layout length of the antifuse memory array in the direction of the bit line BL; The distance between the switch unit and the antifuse memory unit located in the same active region is increased to ensure the electrical isolation effect of the electrical elements of the antifuse memory array.

In one example, referring to FIG. 1 , each antifuse integrated structure 100 includes:

The first antifuse storage MOS transistor 101 , the first switch transistor 111 , the second switch transistor 112 and the second antifuse storage MOS transistor 102 .

Wherein, the gate of the first antifuse storage MOS transistor 101 is connected to the first programming wire PGM<1>, the gate of the first switching transistor 111 is connected to the first word line WL<1>, and one end of the source or drain is connected to The first antifuse storage MOS transistor 101, the other end is connected to the bit line BL, the gate of the second switch transistor 112 is connected to the second word line WL<2>, and one end of the source or drain is connected to the second antifuse storage MOS The other end of the transistor 102 is connected to the bit line BL, and the gate of the second antifuse storage MOS transistor 102 is connected to the second programming wire PGM<2>.

Specifically, in this example, referring to FIG. 3 , in the extending direction of the bit line BL, for any two adjacent antifuse integrated structures 100 , the gate of the second switch transistor 112 of one antifuse integrated structure 100 The pole is connected to the word line WL<n-2>, the gate of the second antifuse storage MOS transistor 102 is connected to the programming wire PGM<m>; the gate of the first antifuse storage MOS transistor 101 of another antifuse integrated structure 100 The electrode is connected to the programming wire PGM<m>, and the gate of the first switching transistor 111 is connected to the word line WL<n-1>; in the extending direction of the bit line BL, for any two adjacent antifuse integrated structures 100 Both the first switch transistor 111 and the second switch transistor 112 are connected to the bit line BL<n>.

That is, in the extending direction of the bit line BL, the gate of the second antifuse storage MOS transistor 102 of each antifuse integrated structure 100 is connected with the first antifuse storage MOS transistor 101 of the adjacent antifuse integrated structure 100. The gates of the gates are connected to the same programming wire PGM<m>, wherein n, m are positive integers greater than or equal to 1.

It should be noted that, in other examples, it may also be set as follows: in the extending direction of the bit line, the gate of the first antifuse storage MOS transistor of each antifuse integrated structure is connected to the gate of the adjacent antifuse integrated structure. The gate of the second antifuse storage MOS transistor is connected to the same programming wire.

In one example, referring to FIG. 4 , in the antifuse integrated structure 100, the first antifuse storage MOS transistor 101, the first switch transistor 111, the second switch transistor 112, and the second antifuse storage MOS transistor 102 are arranged in in the same active region 200 .

Specifically, referring to FIGS. 5-6 , the antifuse integrated structure 100 includes:

The active region 200 , and the first doped region 212 , the second doped region 222 , the third doped region 232 , the fourth doped region 242 and the fifth doped region 252 located in the active region 200 .

Wherein, the active region 200 is surrounded by an isolation region 201, the first doped region 212, the second doped region 222, the third doped region 232, the fourth doped region 242 and the fifth doped region 252 on the bit line They are arranged at intervals in the extending direction of the BL (combined with FIG. 4 ).

Wherein, the first doped region 212 is the vacant end of the first antifuse storage MOS transistor 101; the second doped region 222 is the common end of the first antifuse storage MOS transistor 101 and the first switch transistor 111; the third The doping region 232 is the common end of the first switching transistor 111 and the second switching transistor 112; the fourth doping region 242 is the common end of the second switching transistor 112 and the second antifuse storage MOS transistor 102; the fifth doping region The area 252 is a dummy end of the second antifuse storage MOS transistor 102 .

That is, the source of the first antifuse storage MOS transistor 101 is empty, the drain is connected to the drain of the first switching transistor 111, and the source of the first switching transistor 111 is connected to the bit line BL, so as to realize After being turned on, the electrical conduction between the first antifuse storage MOS transistor 101 and the bit line BL is conducted. The source of the second antifuse storage MOS transistor 102 is vacant, the drain is connected to the drain of the second switch transistor 112, and the source of the second switch transistor 112 is connected to the bit line BL, so as to realize conduction through the second switch transistor 112. After being turned on, the electrical conduction between the second antifuse storage MOS transistor 102 and the bit line BL is conducted.

Since the source connections of the first switch tube 111 and the second switch tube 112 are the same, by sharing the source, that is, by sharing the same doped region with the first switch tube 111 and the second switch tube 112, to reduce the The layout area of the antifuse integrated structure 100 .

For the anti-fuse memory cell, the anti-fuse MOS transistor is controlled by the programming line PGM to form a memory cell. The word line WL controls the switch to facilitate the bit line BL to write storage data. When the corresponding word line WL is gated, the reverse The fuse memory unit is electrically connected to the bit line BL, and the antifuse can be judged by the discharge rate of the charge of the bit line BL by the antifuse memory unit (after a preset time, by comparing the voltage of the bit line BL with the standard voltage). Whether the memory cell is broken down, so as to obtain the 1-bit binary data stored in the antifuse memory cell.

In a specific example, referring to FIG. 5 , the gate of the first antifuse storage MOS transistor 101 is disposed on the top surface of the active region 200 between the first doped region 212 and the second doped region 222 , the first The gate of a switch transistor 111 is arranged on the top surface of the active region 200 between the second doped region 222 and the third doped region 232, and the gate of the second switch transistor 112 is arranged between the third doped region 232 and the third doped region 232. The top surface of the active region 200 between the fourth doped region 242, the gate of the second antifuse storage MOS transistor 102 is arranged in the active region between the fourth doped region 242 and the fifth doped region 252 200 of the top surface. That is, the active regions of the first antifuse storage MOS transistor 101 , the first switch transistor 111 , the second switch transistor 112 and the second antifuse storage MOS transistor 102 are set by means of top gates.

In a specific example, referring to FIG. 6, the gate of the first antifuse storage MOS transistor 101 is embedded in the active region 200 between the first doped region 212 and the second doped region 222, The gate of the first switch tube 111 is buried in the active region 200 between the second doped region 222 and the third doped region 232, and the gate of the second switch tube 112 is buried in the third In the active region 200 between the doped region 232 and the fourth doped region 242, the gate of the second antifuse storage MOS transistor 102 is buried in the fourth doped region 242 and the fifth doped region 252 between the active regions 200 . That is, the active regions of the first antifuse storage MOS transistor 101 , the first switch transistor 111 , the second switch transistor 112 and the second antifuse storage MOS transistor 102 are set by buried gates.

Referring to FIG. 5 and FIG. 6 , the antifuse integrated structure 100 further includes: an insulating layer 203 covering the active region 200 , and the bit line BL ( 205 ) is disposed on the insulating layer 203 and electrically connected to the third doped region 232 .

Specifically, the insulating layer 200 has a conductive via (not shown) and a conductive layer 204, the conductive via (not shown) exposes the top surface of the third doped region 232; the conductive layer 204 fills the conductive via (not shown) As shown), one end is in contact with the third doped region 232 , and the other end is in contact with the BL ( 205 ), so that the bit line is electrically connected to the third doped region 232 .

In addition, referring to FIG. 4, in one example, in the word line extension direction, where the first antifuse storage MOS transistor 101, the first switch transistor 111, the second switch transistor 112, and the second antifuse storage MOS transistor 102 are located. The width of the source region 200 is uniform. By ensuring that the first antifuse storage MOS transistor 101, the first switch transistor 111, the second switch transistor 112, and the second antifuse storage MOS transistor 102 have the same width in the active region 200, that is to ensure that each of the antifuse matrix The spacing between the active devices is the same, which further ensures the electrical isolation effect of each active device in the antifuse matrix.

6 and 7, the antifuse matrix includes multiple rows of antifuse integrated structures 100 arranged along the extending direction of the word line WL, and multiple rows of antifuse integrated structures 100 arranged along the extending direction of the bit line BL. Column antifuse integrated structure 100. Multiple antifuse integrated structures 100 in each row of antifuse integrated structures 100 are arranged at intervals along the extending direction of WL, and multiple antifuse integrated structures 100 in each column of antifuse integrated structures 100 are arranged at intervals along the extending direction of BL. Two adjacent rows of antifuse integrated structures 100 are arranged alternately, that is, in the extending direction of BL, two adjacent antifuse integrated structures 100 are arranged alternately, and are located in two adjacent columns.

Wherein, the bit line BL (205) is connected to extend in the direction of the bit line BL, and is connected to the antifuse integrated structure 100 alternately arranged at intervals, since the conductive layers 204 of the antifuse integrated structure 100 are arranged alternately, that is, the conductive vias (not shown) is disposed on one side of the connected bit line BL. In one example, the bit line BL is in contact with the conductive layer 204 through the bit line extension layer 300 . The bit line BL and the conductive layer are connected through the bit line extension layer 300 to ensure the stability of the electrical contact between the bit line and the conductive layer and prevent the formed antifuse matrix from having conductive defects.

In one example, the antifuse integrated structures 100 connected by the same word line WL are arranged at equal intervals. That is, in the extending direction of the word line WL, the distance between adjacent antifuse integrated structures 100 is equal, so as to avoid the existence of a smaller space between adjacent antifuse integrated structures 100, so as to damage the overall electrical integrity of the antifuse memory array. isolation effect.

In one example, the antifuse integrated structures 100 connected by the same bit line BL are arranged at equal intervals. That is, in the extending direction of the bit line BL, the distance between adjacent antifuse integrated structures 100 is equal, so as to avoid the existence of a smaller space between adjacent antifuse integrated structures 100, so as to damage the overall electrical integrity of the antifuse memory array. isolation effect.

In one example, the bit line BL connected to the antifuse integrated structure 100 in the first column is the first dummy bit line Dummy1, and the bit line BL connected to the antifuse integrated structure 100 in the last column is the second dummy bit line Dummy2. By setting dummy bit lines at the edge of the antifuse matrix, it is ensured that the layout environment of the antifuse integrated structure 100 located at the edge of the antifuse matrix is consistent with the layout environment of the antifuse integrated structure inside the matrix, so as to prevent defects in the edge antifuse memory cells, can not work normally.

In one example, the gate of the first storage MOS transistor 101 in the antifuse integrated structure 100 in the first row is connected to the first dummy programming wire Dummy3, and the gate of the second storage MOS transistor in the antifuse integrated structure 100 in the last row is connected to Second dummy programming wire Dummy4. By arranging virtual programming wires at the edge of the antifuse matrix, it is ensured that the antifuse integrated structure 100 located at the edge of the antifuse matrix is consistent with the layout environment of the antifuse integrated structure inside the matrix, preventing defects in the edge antifuse memory cells, can not work normally.

Further, the gate of the first switch transistor 111 in the antifuse integrated structure 100 in the first row is connected to the first dummy word line Dummy5, and the gate of the second switch transistor 112 in the antifuse integrated structure 100 in the last row is connected to the second dummy word line. Wordline Dummy6. Wherein, the first dotted programming wire Dummy3 and the second dummy programming wire Dummy4 are located on the outermost side of the antifuse matrix, and the first dummy word line Dummy5 and the second dummy word line Dummy6 are located on the second outer side of the antifuse matrix. By setting dummy word lines at the edge of the antifuse matrix, it is ensured that the antifuse integrated structure 100 located at the edge of the antifuse matrix is consistent with the layout environment of the antifuse integrated structure inside the matrix, preventing defects in the edge antifuse memory cells, can not work normally.

The embodiment of the present application reduces the layout length of the antifuse memory array in the extending direction of the bit line. Therefore, on the basis of the original layout area and the layout of the memory array with the same capacity, the number of switches located in the same active area is increased. The distance between the unit and the antifuse memory unit is to ensure the electrical isolation effect of the electrical elements in the memory array formed by the antifuse integrated structure.

It should be noted that the above-mentioned specific connection method of "source" and "drain" does not constitute a limitation to the embodiment of the application. In other embodiments, "drain" can be used instead of "source". "Source" instead of "drain" connections. In addition, in order to highlight the innovative part of the present application, units that are not closely related to solving the technical problems proposed in the present application are not introduced in this embodiment, but this does not mean that there are no other units in this embodiment.

Another embodiment of the present application also provides a memory, wherein the storage array of the memory uses the antifuse array structure provided by the above embodiment, and by using the antifuse array structure provided by the above embodiment as the memory array, the original layout area On the basis of the storage array with the same capacity as the layout, the distance between the switch unit and the antifuse storage unit in the same active area is increased to ensure the electrical isolation effect of the electrical components in the storage array formed by the antifuse integrated structure .

FIG. 9 is a schematic diagram of the virtual structure of the memory provided by this embodiment, and FIG. 10 is a schematic diagram of the timing sequence of the programming phase and the readout phase of the memory provided by this embodiment. The memory provided by this embodiment will be further described in detail below in conjunction with the accompanying drawings, specifically as follows :

Referring to FIG. 9, the memory includes: a storage array 403, adopting the antifuse array structure provided by the above-mentioned embodiments; a control unit 401, configured to receive a row address signal Row_ADD, a program enable signal PGM_En and a word line enable signal WL_En; row select The control unit 402 is connected to the memory array 403 and the control unit 401, and is used to generate the programming strobe signal PGM<n/2:0> according to the row address signal Row_ADD and the programming enable signal PGM_En, and generate the programming strobe signal PGM<n/2:0> according to the row address signal Enabling signal WL_En generates word line strobe signal WL<n:0>; column selection control unit 404, connected to memory array 403, for turning on corresponding bit line WL of memory array 403 according to bit line strobe signal (not shown) .

Wherein, the programming enable signal PGM_En is used to indicate that the programming wire is turned on, the word line enable signal WL_En is used to indicate that the bit line is turned on; the programming strobe signal PGM<n/2:0> is used to turn on the corresponding memory array 403 programming wire PGM; the word line gate signal WL<n:0> is used to turn on the word line WL in the corresponding memory array 403 .

Specifically referring to FIG. 10, in the programming stage, the programming enable signal PGM_En and the row address signal Row_ADD are provided to generate the programming strobe signal PGM<n/2:0> to select the corresponding antifuse MOS tube to be fused to form an antifuse The memory cell is controlled by the word line strobe signal WL<n:0> to turn on the switch, and data is written into the antifuse memory cell by the corresponding bit line BL. In the read phase, the word line enable signal WL_En and the row address signal Row_ADD are provided to generate the word line gate signal WL<n:0> to select the corresponding anti-fuse memory cell to be electrically connected to the bit line BL.

Through the common control of the bit line BL and the word line WL, when the corresponding word line WL is gated, the antifuse memory unit is electrically connected to the bit line BL, and the discharge speed of the charge of the bit line BL through the antifuse memory unit (after pre-setting After a certain period of time, by comparing the voltage of the bit line BL with the standard voltage V _REF ), it can be judged whether the anti-fuse memory cell is broken down, so as to obtain the 1-bit binary data stored in the anti-fuse memory cell.

It should be noted that, since the programming wire PGM in this embodiment is connected to two antifuse memory cells controlled by different word lines WL, the duration of the high level required by the programming strobe signal PGM<n/2:0> It is necessary to cover the time when the word line select signal WL<n:0> is high level twice to complete the data programming.

It is worth mentioning that all the units involved in this embodiment are logical units. In practical applications, a logical unit can be a physical unit, or a part of a physical unit, or multiple physical units. Combination of units. In addition, in order to highlight the innovative part of the present application, units that are not closely related to solving the technical problem proposed in the present application are not introduced in this embodiment, but this does not mean that there are no other units in this embodiment.

It should be noted that, in order to highlight the innovative part of this application, in this embodiment, units that are not closely related to solving the technical problems proposed by this application are not introduced, but this does not mean that there are no other units in this embodiment. unit; those of ordinary skill in the art can understand that the above-mentioned embodiments are specific embodiments for realizing the present application, and in practical applications, various changes can be made to it in form and detail without departing from the present application spirit and scope.

Claims (15)

1. An antifuse array structure, characterized in that, comprising: A plurality of antifuse integrated structures are arranged in an antifuse matrix in the extending direction of the bit line and the extending direction of the word line, and the extending direction of the bit line and the extending direction of the word line are perpendicular to each other; Each antifuse integrated structure is connected with two programming wires and two word lines; In the extending direction of the word line, each antifuse integrated structure and the adjacent antifuse integrated structure are commonly connected to the same programming wire and the word line; In the extending direction of the bit line, each antifuse integrated structure is connected to the adjacent antifuse integrated structure on one of the programming wires. 2. The antifuse array structure according to claim 1, wherein a plurality of said antifuse integrated structures connected by the same word line are arranged at equal intervals. 3. The antifuse array structure according to claim 1, wherein a plurality of said antifuse integrated structures connected by the same bit line are arranged at equal intervals. 4. The antifuse array structure according to claim 1, wherein each antifuse integrated structure comprises: a first antifuse storage MOS transistor, a first switch transistor, a second switch transistor and a second switch transistor Anti-fuse storage MOS tube; The gate of the first antifuse storage MOS transistor is connected to the first programming wire; The gate of the first switching transistor is connected to the first word line, one end of the source or the drain is connected to the first antifuse storage MOS transistor, and the other end is connected to the bit line; The gate of the second switching transistor is connected to the second word line, one end of the source or the drain is connected to the second antifuse storage MOS transistor, and the other end is connected to the bit line; The gate of the second antifuse storage MOS transistor is connected to the second programming wire. 5. The antifuse array structure according to claim 4, characterized in that, in the extending direction of the bit line, the gate of the second antifuse storage MOS transistor of each antifuse integrated structure, The same programming wire is connected to the gate of the first antifuse storage MOS transistor adjacent to the antifuse integrated structure. 6. The antifuse array structure according to claim 4, wherein the antifuse integrated structure comprises: an active region, and a first doped region, a second doped region, a third doped region, a fourth doped region and a fifth doped region located in the active region; The first doped region is a vacant end of the first antifuse storage MOS transistor, and the second doped region is a common end of the first antifuse storage MOS transistor and the first switch transistor , the third doped region is the common end of the first switch transistor and the second switch transistor, and the fourth doped region is the second switch transistor and the second antifuse storage MOS The common end of the tube, the fifth doped region is the vacant end of the second antifuse storage MOS tube; an insulating layer covering the active region, the bit line is disposed on the insulating layer and is electrically connected to the third doped region. 7. The antifuse array structure according to claim 6, wherein, in the extending direction of the word line, the first switch transistor, the second switch transistor, and the first antifuse storage The width of the MOS transistor and the active region where the second antifuse storage MOS transistor is located is the same. 8. The antifuse array structure according to claim 6, wherein the insulating layer further has a conductive via, and the conductive via exposes the top surface of the third doped region; The conductive layer is used to fill the conductive via hole, one end is in contact with the third doped region, and the other end is in contact with the bit line. 9. The antifuse array structure according to claim 8, wherein the conductive via is arranged on one side of the connected bit line, and the bit line is connected to the conductive via through a bit line extension layer. layers are in contact. 10. The antifuse array structure according to claim 6, wherein the gate of the first antifuse storage MOS transistor is arranged between the first doped region and the second doped region the top surface of the active region between the first switching transistor and the gate of the first switching transistor are arranged on the top surface of the active region between the second doped region and the third doped region, so The gate of the second switch transistor is arranged on the top surface of the active region between the third doped region and the fourth doped region, and the gate of the second antifuse storage MOS transistor A top surface of the active region is disposed between the fourth doped region and the fifth doped region. 11. The antifuse array structure according to claim 6, wherein the gate of the first antifuse storage MOS transistor is embedded in the first doped region and the second doped region. In the active region between impurity regions, the gate of the first switch transistor is buried in the active region between the second doped region and the third doped region , the gate of the second switch transistor is embedded in the active region between the third doped region and the fourth doped region, and the second antifuse storage MOS transistor The gate is buried in the active region between the fourth doped region and the fifth doped region. 12. The antifuse array structure according to claim 1, wherein the antifuse matrix includes multiple columns of the antifuse integrated structure arranged along the extending direction of the word line, wherein the first column The bit line connected to the antifuse integrated structure is the first dummy bit line, and the bit line connected to the antifuse integrated structure in the last row is the second dummy bit line. 13. The antifuse array structure according to claim 1, wherein the antifuse matrix comprises a plurality of rows of the antifuse integrated structures arranged along the extending direction of the bit lines, wherein the first row The gate of the first antifuse storage MOS transistor in the antifuse integrated structure is connected to the first dummy programming wire, and the gate of the second antifuse storage MOS transistor in the last row of the antifuse integrated structure is connected to Second dummy programming wire. 14. The antifuse array structure according to claim 13, wherein the gates of the first switching transistors in the antifuse integrated structure in the first row are connected to the first dummy word line, and the gates of the antifuse integrated structures in the last row are connected to the first virtual word line. The gate of the second switching transistor in the fuse integrated structure is connected to the second dummy word line; wherein, the first dummy programming wire and the second dummy programming wire are located at the outermost side of the antifuse matrix, and the The first dummy word line and the second dummy word line are located on the second outer side of the antifuse matrix. 15. A memory, comprising a memory array, characterized in that: the memory array adopts the antifuse array structure according to any one of claims 1-14.

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