CN115843179A - Semiconductor structure, manufacturing method thereof and memory - Google Patents

Abstract

Embodiments of the present application relate to the field of semiconductors, and provide a semiconductor structure, a manufacturing method thereof, and a memory. The semiconductor structure may at least include: a first grating, a second grating, and a third grating stacked from bottom to top and arranged in different photoresist layers , different overlay mark areas for setting gratings in the photoresist layer overlap, the first grating, the second grating and the third grating are all periodic structures, and the adjacent periodic structures The distance between the centers of the gratings is a grating period, and the grating width and/or the grating period of the first grating and the second grating are different. The embodiments of the present application are beneficial to improving the electrical performance of the semiconductor structure.

Description

Semiconductor structure and manufacturing method thereof, memory

technical field

The embodiments of the present application relate to the field of semiconductors, and in particular to a semiconductor structure, a manufacturing method thereof, and a memory.

Background technique

The photolithography process is the process of transferring the mask pattern to the wafer through a series of steps such as alignment and exposure. In the process of semiconductor device manufacturing, it is usually necessary to use multiple photolithography processes to achieve overlay, but due to various factors in the photolithography process that cannot achieve the ideal state, it will inevitably lead to exposure and development remaining on the pattern on the wafer and on the wafer. The existing graphics cannot be completely aligned, so it is necessary to accurately measure the offset between the graphics left on the wafer after exposure and development and the existing graphics on the wafer, that is, the overlay error (overlay), so that the subsequent Effectively compensate and correct overlay errors in the process, so that the finally obtained semiconductor device has the desired effect.

Contents of the invention

Embodiments of the present application provide a semiconductor structure, a manufacturing method thereof, and a memory, which at least help to improve the electrical performance of the semiconductor structure and the memory.

According to some embodiments of the present application, an embodiment of the present application provides a semiconductor structure on the one hand, and the semiconductor structure may at least include: a first grating, a second grating, and a third grating stacked from bottom to top and arranged in different photoresist layers, The overlay marking areas used to set gratings in different photoresist layers overlap, the first grating, the second grating and the third grating are all periodic structures, and the adjacent periodic structures The center distance of the grating is the grating period, and the grating width and/or the grating period of the first grating and the second grating are different.

In addition, the first grating and the second grating are adjacent to different photoresist layers.

In addition, the first grating, the second grating and the third grating are all composed of periodically arranged gaps, bumps or holes.

In addition, the photoresist layer includes a core area and a peripheral area, the peripheral area is located between the core area and the scribe line, and the overlay mark area is located in the peripheral area.

In addition, the semiconductor structure further includes: a first pattern and a second pattern in the core area, the first pattern and the first grating are in the same photoresist layer, the second pattern and the second The grating is in another photoresist layer, the first grating and the first pattern have a grating structure with the same grating width and grating period, and the second grating and the second pattern have a grating width and/or grating Grating structures with different periods.

In addition, the first pattern includes word lines.

In addition, the second pattern includes capacitive contact holes.

In addition, the grating width and grating period of the second grating are the same as those of the third grating.

In addition, the center position of the second grating is misaligned with the center position of the first grating in the vertical direction, and the second grating and the first grating do not overlap in the vertical direction.

In addition, the grating period of the second grating is greater than the grating period of the first grating, and the center position of the second grating is used as the center position of some gratings in the first grating.

In addition, the grating width of the second grating is greater than the grating width of the first grating.

In addition, the grating width of the second grating is less than or equal to twice the grating width of the first grating.

According to some embodiments of the present application, another embodiment of the present application further provides a memory, including the semiconductor structure described in any one of the foregoing.

According to some embodiments of the present application, on the other hand, the embodiment of the present application also provides a method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure at least includes: forming a first grating stacked from bottom to top and arranged in different photoresist layers, The second grating and the third grating do not overlap with the overlay mark area used to set the grating in the photoresist layer, the first grating, the second grating and the third grating are all periodic structures, so The distance between the centers of adjacent gratings in the periodic structure is a grating period, and the grating width or the grating period of the first grating is different from that of the second grating.

In addition, it also includes: forming a second pattern, the second grating and the second pattern are in the same photoresist layer, the second pattern and the second grating are grating structures with different grating periods, the The second grating has a grating width greater than that of the second pattern.

The technical solutions provided by the embodiments of the present application have at least the following advantages:

In the above technical solution, setting the grating width and/or grating period of the first grating and the second grating to be different is beneficial to make the characteristics of the diffraction signal obtained by illuminating the first grating and the second grating different, so that the first grating The diffraction signal of the second grating is distinguished from the diffraction signal of the second grating, avoiding the whole of the diffraction signal of the first grating and the diffraction signal of the second grating as the diffraction signal of the second grating, and ensuring that the diffraction signal used to calculate the overlay error is only It is composed of the diffraction signal of the second grating and the diffraction signal of the third grating, thereby realizing accurate measurement of overlay errors.

Description of drawings

One or more embodiments are exemplified by corresponding pictures in the drawings, and these exemplifications are not construed as limiting the embodiments, unless otherwise stated, and the pictures in the drawings are not limited in scale.

1 to 4 are structural schematic diagrams of semiconductor structures provided by embodiments of the present application;

FIG. 5 to FIG. 9 are structural schematic diagrams of some steps in the manufacturing method of the semiconductor structure provided by the embodiment of the present application.

Detailed ways

The detection of overlay errors is generally divided into After Development Inspection (ADI) and After Etching Inspection (AEI). Post-development inspection refers to the measurement of critical dimension (CD) after development, which is generally used for detection The performance indicators of the exposure machine and the developing machine. After the exposure and development are completed, the qualitative inspection of the generated graphics by the ADI machine is used to judge whether the graphics are normal. Since it cannot be measured by transmitted light, ADI generally uses electron beams or scanning electron microscopes, etc. Measurement by means of etching; post-etching inspection refers to CD measurement after etching, before and after photoresist removal in the etching process, full inspection or sampling inspection is carried out on the product respectively.

The overlay error can generally be measured by image recognition-based measurement technology (Image Based Overlay, IBO), scanning electron microscope (Scanning Electron microscope, SEM) and new diffraction measurement technology (In DieMetrology, IDM). The IDM collects the zero-order diffracted light of different marking layers, and determines the overlay error of different marking layers according to the asymmetry of the light intensity distribution of the zero-order diffracting light.

The implementation of the present application provides a semiconductor structure. The first grating and the second grating have different grating widths and/or grating periods, so as to distinguish the diffraction signal corresponding to the first grating from the diffraction signal corresponding to the second grating. When there is an overlay error of the three gratings relative to the second grating, since the first grating below the second grating also has a corresponding diffraction signal, by controlling the diffraction signal corresponding to the first grating and the diffraction signal corresponding to the second grating have different The feature is beneficial to ensure that the diffraction signal used to calculate the overlay error is only composed of the diffraction signal of the second grating and the diffraction signal of the third grating, thereby realizing accurate measurement of the overlay error.

Various embodiments of the present application will be described in detail below in conjunction with the accompanying drawings. However, those of ordinary skill in the art can understand that in each embodiment of the application, many technical details are provided for readers to better understand the application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in this application can also be realized.

FIG. 1 to FIG. 4 are structural schematic diagrams of a semiconductor structure provided in an embodiment of the present application.

Referring to FIG. 1 , the semiconductor structure includes: a first grating 111, a second grating 211, and a third grating 311 stacked from bottom to top and arranged in different photoresist layers, and the overlay mark areas where the gratings are arranged in different photoresist layers overlap, The first grating 111, the second grating 211, and the third grating 311 are all periodic structures, the distance between the centers of adjacent gratings in the periodic structure is the grating period, and the grating width and/or grating width of the first grating 111 and the second grating 211 Cycles are different.

The embodiments of the present application will be described in more detail below in conjunction with the accompanying drawings.

The semiconductor structure includes a first photoresist layer 10, a second photoresist layer 20 and a third photoresist layer 30 stacked from bottom to top, the first photoresist layer 10 has a first engraved marking area 11, and the second photoresist layer 20 There is a second overlay mark area 21, the third photoresist layer 30 has a third overlay mark area 31, the first grating 111 is located in the first overlay mark area 11, and the second grating 211 is located in the second overlay mark area 21 Inside, the third grating 311 is located in the third overlay mark region 31, the first grating 111, the second grating 211 and the third grating 311 are all overlay marks, and in the stacking direction of the photoresist layer, the first overlay mark The projections of area 11 and second overlay marking area 21 are at least partially coincident.

It is understandable that due to the limited area of the chip, the overlay mark areas of different film layers often overlap in the film layer stacking direction. When using IDM to measure the overlay error of the upper film layer, the measurement result may be affected by the lower film layer. . An example scenario is as follows:

When light is illuminated above the third photoresist layer 30, part of the light passes through the third photoresist layer 30 and is reflected, and the reflected light is diffracted by the third grating 311 to form a third diffraction signal; part of the light will sequentially pass through the third The photoresist layer 30 and the second photoresist layer 20 are reflected together, and the reflected light is diffracted by the second grating 211 to form a second diffraction signal; part of the light will pass through the third photoresist layer 30, the second photoresist layer 20 and the The first photoresist layer 10 is also reflected, and the reflected light is diffracted by the first grating 111 to form a first diffraction signal. When the first grating 111 and the second grating 211 are periodic structures with the same grating width and grating period, the characteristics of the first diffraction signal and the second diffraction signal are the same, and technicians cannot effectively distinguish the first diffraction signal from the second diffraction signal , only the first diffraction signal and the second diffraction signal as a whole can be regarded as the "second diffraction signal", that is, when measuring the overlay error between the third grating 311 and the second grating 211, what is actually measured is the first The equivalent structure of the grating 111 and the second grating 112 and the overlay error of the third grating 311 .

If the first grating 111 is completely aligned with the second grating 211, then the first diffraction signal is the same as the second diffraction signal, and the first diffraction signal will not interfere with the identification of the second diffraction signal by technicians; if the first grating 111 and the second diffraction signal There is a deviation in the second grating 211, and the actual positions of the first diffraction signal and the second diffraction signal are different, but since the first diffraction signal and the second diffraction signal have the same parameters (width and spacing) except for the position, technicians cannot distinguish For the first diffraction signal and the second diffraction signal, only the whole of the first diffraction signal and the second diffraction signal can be regarded as the "second diffraction signal". At this time, there may be deviations in the measurement results.

It can be understood that, as the deviation between the first grating 111 and the second grating 211 gradually expands, the accuracy of the measurement results becomes lower and lower. Ideally, the first grating 111 and the second grating 211 are completely aligned. At this time, the measured offset is the same or close to the actual offset, for example, the difference is not more than 0.5nm; with the first grating 111 and the second The difference between the gratings 211 expands to 2.5nm or even 5nm, and the difference between the measured offset and the actual offset may expand to 1nm or even 2nm, and the measured offset is basically invalid at this time.

It should be noted that the second diffraction signal will also be transmitted through the third photoresist layer 30, and the first diffraction signal will also be transmitted through the second photoresist layer 20 and the third photoresist layer 30, but due to the first diffraction signal and the first The second diffraction signal is not parallel light, and the width of the grating is generally much larger than the grating gap. Therefore, most of the first diffraction signal and the second diffraction signal are transmitted out of the upper film layer, rather than diffracted again. Therefore, the first diffraction signal and the second diffraction signal The position of the second diffraction signal does not change or changes slightly, and the main change is the signal intensity (blocked by the film layer, the signal intensity becomes weaker). In addition, since the measured offset is a relative value (relative to zero offset), the influence caused by the second photoresist layer 20 and the third photoresist layer 30 will be eliminated by the subtraction calculation of the relative value.

In the embodiment of the present application, the third photoresist layer 30 is the photoresist layer to be tested, the second photoresist layer 20 is the reference photoresist layer, the first photoresist layer 10 is the existing interference photoresist layer, and the first photoresist layer 20 is the reference photoresist layer. Layer 10 and second photoresist layer 20 are adjacent or non-adjacent photoresist layers, and second photoresist layer 20 and third photoresist layer 30 are adjacent or non-adjacent photoresist layers.

In some embodiments, the first photoresist layer 10 and the second photoresist layer 20 are adjacent, that is, the first grating 111 and the second grating 211 are located in different photoresist layers adjacent to each other, when the first photoresist layer When 10 is adjacent to the second photoresist layer 20, the light intensity loss suffered by the first diffraction signal when it is transmitted to the top of the second photoresist layer 20 is relatively small, which has a greater impact on the second diffraction signal. The signal characteristic of the second diffraction signal is adjusted by a large amplitude to effectively distinguish the first diffraction signal from the second diffraction signal.

In some embodiments, referring to FIG. 2 , the first grating 111 and the second grating 211 are in separate different photoresist layers, and at least a fourth photoresist layer is provided between the first photoresist layer 10 and the second photoresist layer 20. The engraving layer 40, the fourth photoresist layer 40 has a fourth overlay mark area 41 and a fourth grating 411 disposed in the fourth overlay mark area 41, the fourth grating 411 is located between the first grating 111 and the second grating 211 Between, the arrangement direction of the first grating 111 is parallel to the arrangement direction of the second grating 211 , and the arrangement direction of the fourth grating 411 is perpendicular to the arrangement direction of the second grating 211 . Setting the fourth grating 411 is beneficial to reduce the light transmitted to the first photoresist layer 10, and to prevent the first diffraction signal from propagating to the second photoresist layer 20, so that the first diffraction signal of the third photoresist layer 30 is finally transmitted It has a lower light intensity, thereby weakening or even eliminating the influence of the first diffraction signal on the second diffraction signal.

It can be understood that other intermediate film layers may also be arranged between the first photoresist layer 10 and the second photoresist layer 20, and are blocked by the intermediate film layer. If the light intensity loss of the first diffraction signal during propagation is relatively small is large, the influence of the first diffraction signal is small, and the difference between the first grating 111 and the second grating 211 can be small. That is to say, the characteristic difference between the first grating 111 and the second grating 211 can be adjusted according to the loss of the first diffraction signal during transmission, and the characteristic difference includes a grating width difference and/or a grating period difference.

In different embodiments, the grating may have different appearances. The grating may consist of periodically arranged gaps, bumps or holes, or the grating may contain periodically arranged gaps, bumps or holes. It can be understood that due to the influence of the manufacturing process, the middle part of the grating generally follows a stricter periodic distribution, that is, the distance between adjacent gratings is equal, the edge part of the grating is less periodic, and the distance between adjacent gratings may gradually change. The trend of becoming larger or smaller is a phenomenon caused by the limitation of the current technological level, so it cannot be used as evidence that it does not belong to the grating.

In addition, it can be understood that there may be multiple groups of gratings in the same overlay mark area, and the multiple groups of gratings have at least two arrangement directions, so as to detect the deviation of the photoresist layer to be tested in different directions compared with the reference photoresist layer. The direction of arrangement of different groups of gratings can be vertical or oblique. The expressions of different groups of gratings can be the same or different. When the overlay mark includes a hole array, it can be considered that the overlay mark includes multiple groups of gratings arranged in different directions, and there is a common hole between the two groups of gratings.

In some embodiments, the photoresist layer includes a core region and a peripheral region, the peripheral region is located between the core region and the scribe lines, and the overlay mark region is located in the peripheral region. The peripheral area usually refers to the blank area between the core component and the dicing line. With the miniaturization of the semiconductor structure and the complexity of the core component, the area of the blank area may gradually shrink. There is a higher probability of projection coincidence in the direction. It can be understood that the first overlay mark area 11 , the second overlay mark area 21 and the third overlay mark area 31 all belong to the overlay mark area and are located in the peripheral area.

In some embodiments, the semiconductor structure further includes: a first pattern 112 and a second pattern 212 in the core area, the first pattern 112 and the first grating 111 are in the same photoresist layer, the second pattern 212 and the second grating 211 are in In another photoresist layer, the first grating 111 and the first pattern 112 have grating structures with the same grating width and grating period, and the second grating 211 and the second pattern 212 have grating structures with different grating widths and/or grating periods. That is to say, in the embodiment of the present application, by adjusting the grating width and/or grating period of the second grating 211, the diffraction signal of the second grating 211 is different from the diffraction signal of the first grating 111, so that according to the diffraction signal of the second grating 211 The offset between the second photoresist layer 20 and the third photoresist layer 30 can be accurately obtained through the diffraction signal of the third grating 311 .

In order to accurately measure the overlay error of the second photoresist layer 20 and the third photoresist layer 30, the grating width and grating period of the second grating 211 can be set to be the same as the grating width and grating period of the third grating 311. In this background Next, if the grating width and/or grating period of the second grating 211 are adjusted, the grating width and/or grating period of the third grating 311 need to be adjusted synchronously to ensure a high accuracy of overlay error measurement. Since the process steps of the peripheral area are the same as those of the core area, and the first grating 111 is at the bottom layer relative to the second grating 211 and the third grating 311, the characteristics of the first grating 111 are kept unchanged and the second grating 211 and the third grating are adjusted. The three gratings 311 are beneficial to reduce the impact on subsequent film process steps and reduce adjustment costs.

In other embodiments, the second grating 211 and the second pattern 212 are grating structures with the same grating width and grating period, and the first grating 111 and the first pattern 112 are grating structures with different grating widths and/or grating periods, that is, That is, the grating width and/or grating period of the first grating 111 are adjusted, and the grating width and grating period of the second grating 211 are kept unchanged. Since the number of film layers between the first photoresist layer 10 and the second photoresist layer 20 and between the second photoresist layer 20 and the third photoresist layer 30 may be different according to the application scene, in the actual process, it may The characteristics of the first grating 111, or the characteristics of the second grating 211 and the third grating 311 are adjusted according to actual needs, so as to reduce the impact on the overall film process and reduce the cost.

In some embodiments, referring to FIG. 3 , the center position aa of the second grating 211 is misaligned with the center position bb of the first grating 111 in the vertical direction, and the second grating 211 and the first grating 111 do not overlap in the vertical direction. In the case where the center position bb of the first grating 111 is misaligned with the center position aa of the second grating 211, by controlling the second grating 211 and the first grating 111 not to overlap in the vertical direction, it is beneficial to avoid diffraction signals caused by grating overlap overlapping, thereby accurately distinguishing the first diffraction signal and the second diffraction signal. Wherein, the vertical direction refers to the stacking direction of the first photoresist layer 10 and the second photoresist layer 20, and the central position of the grating refers to the central axis or central axis plane of each grating in the grating arrangement direction, and the multiple gratings The above-mentioned first grating 111 , second grating 211 and third grating 311 are composed.

In some embodiments, the non-overlapping of the second grating 211 and the first grating 111 in the vertical direction means that there is a gap between the first grating 111 and the second grating 211 in the arrangement direction of the first grating 111, thus, It is beneficial to further distinguish the first diffraction signal and the second diffraction signal, avoiding the indistinguishability of the first diffraction signal and the second diffraction signal due to continuity; in some other embodiments, the second grating 211 is perpendicular to the first grating 111 Non-overlap means that, in the arrangement direction of the first gratings 111 , the boundaries of the first gratings 111 and the second gratings 211 coincide.

In some embodiments, the center position of the grating in the second pattern 212 is vertically misaligned with the center position of the grating in the first pattern 112 , and the second pattern 212 and the first pattern 112 overlap at least partially in the vertical direction. It can be understood that if the grating features of the second grating 211 are different from those of the second pattern 212, the second pattern 212 and the second grating 211 cannot be formed by the same mask. Therefore, in the actual manufacturing process, it is possible to Cover the peripheral area first to form the second pattern 212 in the core area, and then form the second grating 211 in the peripheral area after covering the core area. That is to say, the second pattern 212 and the second grating 211 are respectively formed by different exposure, development and etching processes.

In some embodiments, referring to FIG. 4 , the grating period of the second grating 211 is greater than that of the first grating 111 , and the center position of the second grating 211 is used as the center position of some gratings in the first grating 111 . In the case where the center position of the second grating 211 is used as the center position of the first grating 111, controlling the first grating 111 and the second grating 211 to have different grating periods is beneficial to distinguish the The first diffraction signal and the second diffraction signal.

Continuing to refer to FIG. 4, in some embodiments, the grating width of the second grating 211 is greater than the grating width of the first grating 111, on the basis of changing the grating period of the second grating 211, further adjust the grating width of the second grating 211, It is beneficial to further distinguish the first diffraction signal and the second diffraction signal; in other embodiments, the grating width of the second grating 211 is smaller than the grating width of the first grating 111 . Taking the second grating 211 as an example, the grating width of the second grating 211 is the width d of each grating in the grating arrangement direction.

In some embodiments, the width of the second grating 211 is less than or equal to twice the width of the first grating 111 , or in other words, the width of the second grating 211 is less than or equal to twice the width of the second pattern 212 . Setting the grating width of the second grating 211 and the grating width of the second pattern 212 has the above relationship, which is conducive to utilizing the same process steps to form the second pattern 212 and the second grating 211, and reduces the adjustment of the second grating 211 to the film layer preparation process. The impact, thereby reducing the process cost of the semiconductor structure.

In some embodiments, the first pattern 112 includes a word line, for example, the word line may be a buried word line; in some embodiments, the second pattern 212 may be a bit line conductive layer or a capacitor contact hole.

In the embodiment of the present application, setting the grating width and/or grating period of the first grating and the second grating to be different is beneficial to make the characteristics of the diffraction signal obtained by illuminating the first grating and the second grating different, so that the first grating Distinguish the diffraction signal of the grating from the diffraction signal of the second grating, avoid taking the entirety of the diffraction signal of the first grating and the diffraction signal of the second grating as the diffraction signal of the second grating, and ensure the diffraction signal used to calculate the overlay error It only consists of the diffraction signal of the first grating and the diffraction signal of the second grating, thereby realizing accurate measurement of overlay errors.

Correspondingly, an embodiment of the present application further provides a memory, including the semiconductor structure described in any one of the foregoing. Since the above-mentioned semiconductor structure can accurately measure the offset between the photoresist layer where the second grating is located and the photoresist layer where the third grating is located, and then adjust and correct it through the subsequent process, the memory prepared based on the above-mentioned semiconductor structure has better performance. electrical properties.

Correspondingly, the embodiment of the present application also provides a method for manufacturing a semiconductor structure. Referring to FIG. 1 , the method for manufacturing a semiconductor structure includes: forming a first grating 111 and a second For the grating 211 and the third grating 311, the overlay marking areas used to set the grating in different photoresist layers overlap, the first grating 111, the second grating 211 and the third grating 311 are all periodic structures, and the adjacent periodic structures The center distance of the grating is the grating period, and the grating width or the grating period of the first grating 111 and the second grating 211 are different.

In some embodiments, referring to FIG. 4, the second pattern 212 and the second grating 211 are respectively formed by different exposure, development and etching processes, the second grating 211 and the second pattern 212 are in the same photoresist layer, and the second pattern 212 and the second grating 211 are grating structures with different grating periods, and the grating width of the second grating 211 is greater than the grating width of the second pattern 212 .

details as follows:

Referring to Fig. 4 and Fig. 5, different masks are used to expose and develop to form a first mask 212a and a second mask 211a respectively, the first mask 212a is used to form the second pattern 212, and the second mask 211a is used to form Second grating 211; carry out deposition process, form patterned layer 212b and grating layer 211b simultaneously, when the opening width of second mask 211a is less than or equal to the twice of the thickness of patterned layer 212b, grating layer 211b is filled with second mask 211a opening. In an exemplary embodiment, the opening width of the second mask 211a is greater than the thickness of the pattern layer 212b and less than or equal to twice the thickness of the pattern layer 212b.

Referring to FIG. 6, a maskless dry etching process is performed to remove the pattern layer 212b covering the top surface of the first mask 212a and the bottom of the opening of the first mask 212a to form the first sacrificial layer 212c, and remove the pattern layer 212b higher than the second The second sacrificial layer 211c is formed by masking the grating layer 211b on the top surface of the mask 211a.

7, an etching process is performed to remove the first mask 212a and the second mask 211a, and the first sacrificial layer 212c and the second sacrificial layer 211c are retained; a deposition process is performed to form the first sacrificial layer 212c gap filled The third mask 212d and the fourth mask 211d filling the gap of the second sacrificial layer 211c.

Since the opening width of the second mask 211a is greater than twice the thickness of the pattern layer 212b and less than or equal to twice the thickness of the pattern layer 212b, and the opening width of the first mask 212a is greater than twice the thickness of the pattern layer 212b, therefore, the first The opening width of the mask 212a is larger than the opening width of the second mask 211a. In the case of the same overall width, in order to make the opening width of the second mask 211a smaller, it is necessary to set a single mask in the second mask 211a. The width of the stripes is larger than the width of a single mask stripe in the first mask 212a, that is, the opening width of the third mask 212d is smaller than the opening width of the fourth mask 211d, and the grating width of the third mask 212d is smaller than that of the fourth mask 211d. The grating width of the mask 211d and the period of the third mask 212d are smaller than the period of the fourth mask 211d. The third mask 212d and the fourth mask 211d are used to etch the underlying conductive layer 51 to form a bit line conductive layer.

Referring to FIG. 8, the first sacrificial layer 211c and the second sacrificial layer 212c are removed, and the conductive layer 51 is etched using the third mask 212d and the fourth mask 211d to form the first bit line conductive layer located in the functional area 512 and the second bit line conductive layer 511 located in the peripheral area. Since the grating feature of the first bit line conductive layer 512 is the same as that of the third mask 212d, and the grating feature of the second bit line conductive layer 511 is the same as that of the fourth mask 211d, therefore, the first bit line conductive The opening width of the layer 512 is smaller than the opening width of the second bit line conductive layer 511 .

Referring to FIG. 9, a first spacer 513 is formed on the sidewall of the first bit line conductive layer 512, and a second spacer 514 is formed on the side wall of the second bit line conductive layer 511; The first capacitive contact hole in the gap between the layers 512 serves as the second pattern 212 , and the second capacitive contact hole filling the gap between the adjacent second bit line conductive layers 511 is formed to serve as the second grating 211 .

The first sidewall 513 and the second sidewall 514 can be formed by the same deposition process, and the thickness of the first sidewall 513 is the same as that of the second sidewall 514 . When the opening width of the first bit line conductive layer 512 is smaller than the opening width of the second bit line conductive layer 511, and the thickness of the first sidewall 513 is the same as that of the second sidewall 514, the grating width of the second pattern 212 smaller than the grating width of the second grating 211.

In addition, the first capacitance contact hole and the second capacitance contact hole can also be formed by the same deposition process. The first capacitance contact hole in the functional area is used to connect the drain of the word line for electrical connection. The second capacitor contact hole may not be connected to the drain of the word line, and is only used as an overlay mark. The buried word lines 60 in the functional area can be used as the first pattern, and the buried word lines 60 in the peripheral area can be used as the first grating.

In other embodiments, after forming the first bit line conductive layer and the second bit line conductive layer, in-situ processing is performed on the first bit line conductive layer and the second bit line conductive layer to form the first bit line conductive layer for isolation. Sidewalls and second sidewalls, such as doped polysilicon in the conductive layer of the bit line, oxidize or nitride the doped polysilicon to form silicon oxide or silicon nitride for electrical isolation; After the two sidewalls, conductive material can be filled to form the first capacitor contact hole and the second capacitor contact hole. In this case, the width of the first capacitance contact hole is equal to the thickness of the pattern layer, and the width of the second capacitance contact hole is equal to the opening width of the second mask, that is to say, the width of the second capacitance contact hole is greater than the width of the first capacitance contact hole. The width of the contact hole is less than or equal to twice the width of the first capacitor contact hole.

Wherein, the width of the first capacitance contact hole can also be equal to the width of the buried word line, in this case, the width of the second capacitance contact hole is greater than the width of the buried word line and less than or equal to the width of the buried word line twice the width.

In the embodiment of the present application, setting the grating width and/or grating period of the first grating and the second grating to be different is beneficial to make the characteristics of the diffraction signal obtained by illuminating the first grating and the second grating different, so that the first grating Distinguish the diffraction signal of the grating from the diffraction signal of the second grating, avoid taking the entirety of the diffraction signal of the first grating and the diffraction signal of the second grating as the diffraction signal of the second grating, and ensure the diffraction signal used to calculate the overlay error It only consists of the diffraction signal of the first grating and the diffraction signal of the second grating, thereby realizing accurate measurement of overlay errors.

Those of ordinary skill in the art can understand that the above-mentioned implementation modes are specific examples for realizing the present application, and in practical applications, various changes can be made to it in form and details without departing from the spirit and spirit of the present application. scope. Any person skilled in the art can make respective alterations and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be determined by the scope defined in the claims.

Claims (15)

1. A semiconductor structure, comprising:

pile up from bottom to top and set up first grating, second grating and the third grating in different photoetching layers, it is different be used for setting up the overlap mark region overlap of grating in the photoetching layer, first grating the second grating and the third grating is periodic structure, it is adjacent in the periodic structure the central distance of grating is the grating cycle, first grating with the grating width of second grating and/or the grating cycle is different.

2. The semiconductor structure of claim 1, wherein the first grating and the second grating are in different adjacent photolithographic layers.

3. The semiconductor structure of claim 1, wherein the first grating, the second grating, and the third grating are each comprised of periodically arranged gaps, bumps, or holes.

4. The semiconductor structure of claim 1, wherein the lithography layer comprises a core region and a peripheral region, the peripheral region being located between the core region and the scribe lane, the overlay mark region being located within the peripheral region.

5. The semiconductor structure of claim 4, further comprising: the grating structure comprises a first pattern and a second pattern which are positioned in the core area, the first pattern and the first grating are positioned in the same photoetching layer, the second pattern and the second grating are positioned in the other photoetching layer, the first grating and the first pattern are grating structures with the same grating width and grating period, and the second grating and the second pattern are grating structures with different grating widths and/or grating periods.

6. The semiconductor structure of claim 5, wherein the first pattern comprises a word line.

7. The semiconductor structure of claim 5, wherein the second pattern comprises a capacitive contact hole.

8. The semiconductor structure of claim 1, wherein the grating width and grating period of the second grating are the same as the grating width and grating period of the third grating.

9. The semiconductor structure of claim 1, wherein a center position of the second grating is vertically displaced from a center position of the first grating, and the second grating does not overlap the first grating in the vertical direction.

10. The semiconductor structure according to claim 1, wherein a grating period of the second grating is larger than a grating period of the first grating, and a center position of the second grating is used as a center position of a part of gratings in the first grating.

11. The semiconductor structure of claim 10, wherein a grating width of the second grating is greater than a grating width of the first grating.

12. The semiconductor structure of claim 11, wherein the grating width of the second grating is equal to or less than twice the grating width of the first grating.

13. A memory comprising the semiconductor structure of any one of claims 1 to 12.

14. A method for fabricating a semiconductor structure, comprising:

form first grating, second grating and the third grating that stacks from bottom to top and set up in different photoetching layers, it is different be used for setting up the overlap mark region overlap of grating in the photoetching layer, first grating second grating and the third grating is periodic structure, it is adjacent in the periodic structure the central distance of grating is the grating cycle, first grating with the grating width of second grating or the grating cycle is different.

15. The method of claim 14, further comprising: and forming a second pattern, wherein the second grating and the second pattern are positioned on the same photoetching layer, the second pattern and the second grating are of grating structures with different grating periods, and the grating width of the second grating is greater than that of the second pattern.

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