CN115856414A - Output stage buffer and current sensor - Google Patents

Abstract

The application relates to the field of sensors, in particular to an output stage buffer and a current sensor, wherein the output stage buffer comprises an input stage, a bias stage, a main amplification output stage and an auxiliary amplification output stage; and in the digital communication mode, the auxiliary amplification output stage is connected through the output selection terminal. The novel output stage buffer structure is used, the power consumption difference of an analog output mode and a digital communication mode is reduced, extra errors cannot be introduced in a temperature calibration stage, and the high precision of the whole system is ensured.

Description

An output stage buffer and current sensor

technical field

The present application relates to the field of sensors, in particular to an output stage buffer and a current sensor.

Background technique

Referring to Fig. 1, the current sensor in the related art is usually a three-port device: including a power supply terminal, a ground terminal and an analog output terminal/digital single-bus communication terminal; in actual production, in order to reduce the chip area, the analog output terminal and the digital single-bus communication terminal Bus communication ends usually share an output port. The sensor element can sense the magnetic field generated by the current to be measured and generate a voltage signal proportional to the strength of the magnetic field. The first-stage amplifier prevents the voltage signal from being large, and the second-stage amplifier amplifies the voltage signal that has been prevented from being large again to achieve A certain swing is finally output through the output stage buffer, which is mainly used to provide a certain load capacity. Since the sensitivity of the sensor element is different at different temperatures, in order to obtain higher accuracy, it is necessary to perform temperature calibration on the sensor element, which mainly includes temperature sensors, registers, temperature compensation logic circuits and digital communication interfaces. In the mass production test stage, The sensitivity of the sensor element is corrected by writing different values to the register at different temperatures through the digital single bus communication terminal.

However, due to the difference in power consumption in analog output mode and digital communication mode, additional errors are introduced during the temperature calibration phase.

Contents of the invention

In order to improve the extra error introduced in the temperature calibration stage, the present application provides an output stage buffer and a current sensor.

In the first aspect, the present application provides an output stage buffer, which adopts the following technical solution:

An output stage buffer including an input stage, a bias stage, a main amplifier output stage and an auxiliary amplifier output stage;

The input stage has a signal input terminal and an output selection terminal, the signal input terminal is used to receive an input voltage signal, and the input stage is used to convert the input voltage signal into a differential current signal, wherein the differential current The signal includes a first current signal and a second current signal;

The bias stage, coupled to the input stage, is used to copy the first current signal to the main amplifier output stage in the analog output mode, and copy the first current signal in the digital communication mode to the auxiliary amplifier output stage;

The main amplifying output stage is used to convert the differential current signal into a first voltage signal when turned on, and simultaneously amplify and output the first voltage signal twice;

The auxiliary amplifying output stage is used to convert the differential current signal into a second voltage signal when turned on, and simultaneously amplify the second voltage signal;

Wherein, in the analog output mode, the main amplified output stage is connected through the output selection terminal and output, and in the digital communication mode, the auxiliary amplified output stage is connected through the output selection terminal.

Optionally, the input stage includes:

The first P-type transistor PM1, the gate is the first bias control terminal Vbp1, and the source is connected to the power supply terminal VDD;

The second P-type transistor PM2, the gate is the signal input terminal Vin+, and the drain is used to output the second current signal;

The third P-type transistor PM3, the gate is the output selection terminal, and the drain is used to output the first current signal; the source is connected to the drain of the first P-type transistor PM1 and the source of the second P-type transistor PM2 pole.

Optionally, the bias stage includes:

The source of the fourth P-type transistor PM4 is connected to the power supply terminal VDD;

The sixth P-type transistor PM6, the gate is the second bias control terminal Vbp2, and the source is connected to the drain of the fourth P-type transistor PM4;

The third N-type transistor NM3, the gate is the fifth bias control terminal Vbn2, the drain is the bias output end of the bias stage and is connected to the gate of the fourth P-type transistor PM4 and the drain of the sixth P-type transistor PM6 ;

The gate of the first N-type transistor NM1 is the fourth bias control terminal Vbn1 , the drain is connected to the source of the third N-type transistor NM3 and the input stage for receiving the first current signal, and the source is grounded.

Optionally, the main amplifying output stage includes a main amplifying stage and a main output stage, the main amplifying stage is used to convert the differential current signal into a first voltage signal, and the main output stage is used to convert the first voltage signal to the first voltage signal. A voltage signal is amplified twice and output.

Optionally, the main amplification stage includes:

The source of the fifth P-type transistor PM5 is connected to the power supply terminal VDD, and the gate is connected to the bias output terminal of the bias stage;

The source of the seventh P-type transistor PM7 is connected to the drain of the fifth P-type transistor PM5, the gate is connected to the second bias control terminal Vbp2 after the fourth switch S4 is connected in series, and the gate is connected to the power supply terminal after the fifth switch S5 is connected in series VDD, the drain connected to the first input terminal of the main output stage;

The fourth N-type transistor NM4, the gate is connected in series with the tenth switch S10 and then connected to the fifth bias control terminal Vbn2, the gate is also connected in series with the eleventh switch S11 and grounded, and the drain is connected to the second input terminal of the main output stage;

The gate of the second N-type transistor NM2 is connected to the fourth bias control terminal Vbn1, the drain is connected to the source of the fourth N-type transistor NM4 and the input stage, and is used to receive the second current signal, and the source is grounded.

Optionally, the main output stage includes:

The zeroth P-type transistor PM0, the source is connected to the power supply terminal VDD, and the gate is connected to the power supply terminal VDD after the zeroth switch S0 is connected in series;

The eighth P-type transistor PM8, the gate is connected in series with the sixth switch S6 and then connected to the third bias control terminal Vbp3, and the gate is connected in series with the seventh switch S7 and then connected to the power supply terminal VDD;

The fifth N-type transistor NM5, the gate is connected in series with the eighth switch S8 and then connected to the sixth bias control terminal Vbn3, the gate is also connected in series with the ninth switch S9 and grounded, and the drain is the first input terminal of the main output stage and connected to the The source of the eighth P-type transistor PM8, the gate of the zeroth P-type transistor PM0 and one end of the zeroth capacitor C0, the other end of the zeroth capacitor C0 is connected to one end of the zeroth resistor R0;

The zeroth N-type transistor NM0, the drain is the output terminal of the main output stage and is connected to the drain of the zeroth P-type transistor PM0, the other end of the zeroth resistor R0 and one end of the first resistor R1, and the gate is the output end of the zeroth P-type transistor PM0. The second input terminal of the main output stage is connected to the source of the fifth N-type transistor NM5, the drain of the eighth P-type transistor PM8 and one end of the first capacitor C1, the gate is also connected in series with the first switch S1 and then grounded, and the source grounding, the other end of the first capacitor C1 is connected to the other end of the first resistor R1;

Wherein, the output selection end of the input stage is connected in series with the second switch S2 to the output end of the main output stage, and the output end of the main output stage is also used in series with the third switch S3 to be connected to the digital communication interface.

Optionally, the auxiliary amplifying output stage includes an auxiliary amplifying stage and an auxiliary output stage, the auxiliary amplifying stage is used for converting the differential current signal into a second voltage signal, and the auxiliary output stage is used for converting the first The second voltage signal is amplified twice.

Optionally, the auxiliary amplification stage includes:

The source of the ninth P-type transistor PM9 is connected to the power supply terminal VDD, the gate is connected to the bias output terminal of the bias stage after the fourteenth switch S14 is connected in series, and the gate is connected to the power supply terminal VDD after the fifteenth switch S15 is connected in series;

The source of the tenth P-type transistor PM10 is connected to the drain of the ninth P-type transistor PM9, the gate is connected in series with the sixteenth switch S16 and then connected to the second bias control terminal Vbp2, and the gate is also connected in series with the seventeenth switch S17 a power supply terminal VDD, the drain of which is connected to the first input terminal of the auxiliary output stage;

The sixth N-type transistor NM6, the gate is connected in series with the twenty-second switch S22 and then connected to the fifth bias control terminal Vbn2, the gate is also connected in series with the twenty-third switch S23 and grounded, and the drain is connected to the second The input terminal and the source are connected to the input stage for receiving the second current signal.

Optionally, the auxiliary output stage includes:

The source of the twelfth P-type transistor PM12 is connected to the power supply terminal VDD, and the gate is connected to the power supply terminal VDD after being connected in series with the twelfth switch S12;

The eleventh P-type transistor PM11, the gate is connected in series with the eighteenth switch S18 and then connected to the third bias control terminal Vbp3, and the gate is connected in series with the nineteenth switch S19 and then connected to the power supply terminal VDD;

The seventh N-type transistor NM7, the gate is connected in series with the twentieth switch S20 and then connected to the sixth bias control terminal Vbn3, the gate is also connected in series with the twenty-first switch S21 and grounded, and the drain is the first input terminal of the auxiliary output stage And connect the source of the eleventh P-type transistor PM11, the gate of the twelfth P-type transistor PM12, and one end of the second capacitor C2, and the other end of the second capacitor C2 is connected to one end of the second resistor R2;

The drain of the eighth N-type transistor NM8 is the output end of the auxiliary output stage and is connected to the drain of the twelfth P-type transistor PM12, the other end of the second resistor R2, and one end of the third resistor R3, and the gate is the output end of the third resistor R3. The second input terminal of the auxiliary output stage is connected to the source of the seventh N-type transistor NM7, the drain of the eleventh P-type transistor PM11 and one end of the third capacitor C3, and the gate is also connected in series with the thirteenth switch S13 and then grounded. The source is grounded, and the other end of the third capacitor C3 is connected to the other end of the third resistor R3;

Wherein, the output selection end of the input stage is connected in series with the twenty-fourth switch S24 to the output end of the auxiliary output stage.

In the second aspect, the present application also provides a current sensor, which adopts the following technical solution:

A current sensor includes sensor elements, a first-stage amplifier, a second-stage amplifier and the above-mentioned output-stage buffer sequentially connected in series.

In summary, this application uses a new output stage buffer structure. In the analog output mode, the main current is generated and output at the main amplifier output stage. In the digital communication mode, the auxiliary current is generated at the auxiliary amplifier output stage. The main current and the auxiliary current The size is similar, thereby reducing the power consumption difference between the analog output mode and the digital communication mode, and no additional error will be introduced during the temperature calibration stage, ensuring the high precision of the entire system.

Description of drawings

FIG. 1 is a schematic block diagram of a current sensor in the related art.

Figure 2 is a schematic diagram of an output stage buffer.

FIG. 3 is a schematic diagram of the output stage buffer of the present application.

Detailed ways

Referring to Figure 2, in order to ensure that there is no interference between the analog signal chain and the digital communication circuit in the output stage buffer, in the analog output mode, the switch S0 of the gate of the P-type transistor PM and the switch S1 of the gate of the N-type transistor NM are disconnected. Open, the switch S3 between the output pin and the digital communication interface is disconnected, and the switch S2 is closed to ensure the normal operation of the output stage buffer. At this time, the current flowing through the P-type transistor PM and the N-type transistor NM is Iout (in order to drive Large load, Iout usually reaches mA level). In the digital communication mode, the switch S0 and the switch S1 are closed, the switch S2 is open, and the switch S3 is closed. At this time, since the gate terminal of the P-type transistor PM is pulled high, the gate terminal of the N-type transistor NM is pulled low, and the output stage buffers The device is in a high-impedance state, the current flowing through the P-type transistor PM and the N-type transistor NM is 0, and the current of the digital communication interface circuit is very small, usually uA level.

Since the total current of the chip differs from Iout (mA level) in the analog output mode and digital communication mode, there is a large deviation in power consumption, and the internal temperature of the chip will have a large deviation, and additional temperature will be introduced during the temperature calibration phase. The error greatly affects the digital calibration accuracy. For example, if the SOT23 package is used, the Vdd of the power supply terminal is 5.5V, and the current of 5mA will cause a temperature deviation of 5°C. During the temperature calibration stage, an additional temperature error of 5°C will be introduced, and the corresponding output may deviate by 2%, which is very important for high-precision systems. is fatal. It can be understood that the output stage buffer shown in Figure 2 is to illustrate the power consumption difference between the two operating modes, and it cannot be understood that the specific structure of the output stage buffer is an existing structure. In actual production, the output Stage buffers can have many different circuit structures, but all have the problem of poor power consumption.

The embodiments of the present application will be described in detail below in conjunction with the accompanying drawings, but the embodiments should not be construed as limiting the present application.

An embodiment of the present application provides a current sensor, including a sensor element, a first-stage amplifier, a second-stage amplifier, and the following output-stage buffer sequentially connected in series. It can be understood that a temperature sensor, a register, a temperature compensation logic circuit and a digital communication interface may also be provided to perform temperature calibration. The output stage buffer described below is to reduce the additional temperature error introduced in the temperature calibration stage and ensure the high precision of the whole system.

The embodiment of the output stage buffer will be further described in detail below in conjunction with the current sensor.

An embodiment of the present application provides an output stage buffer, including an input stage, a bias stage, a main amplifier output stage, and an auxiliary amplifier output stage;

The input stage has a signal input terminal Vin+ and an output selection terminal, the signal input terminal is used to receive an input voltage signal, and the input stage is used to convert the input voltage signal into a differential current signal, wherein the differential The current signal includes a first current signal and a second current signal;

The bias stage, coupled to the input stage, is used to copy the first current signal to the main amplifier output stage in the analog output mode, and copy the first current signal in the digital communication mode to the auxiliary amplifier output stage;

The main amplifying output stage is used to convert the differential current signal into a first voltage signal when turned on, and simultaneously amplify and output the first voltage signal twice;

The auxiliary amplifying output stage is used to convert the differential current signal into a second voltage signal when turned on, and simultaneously amplify the second voltage signal;

Wherein, in the analog output mode, the main amplified output stage is connected through the output selection terminal and output, and in the digital communication mode, the auxiliary amplified output stage is connected through the output selection terminal.

Specifically, the main amplifier output stage or the auxiliary amplifier output stage can be selectively connected through the output selection terminal. In the analog output mode, the main amplifier output stage is turned on and the auxiliary amplifier output stage is turned off, so that the main current is generated in the main amplifier output stage. And output; in the digital communication mode, the auxiliary amplifier output stage is turned on, and the main amplifier output stage is turned off, so that an auxiliary current is generated in the auxiliary amplifier output stage, and the auxiliary current is similar to the main current; it can be understood that the auxiliary current is only used for It is used to generate power consumption close to the main current and is not used for actual output. In actual use, the main amplifier output stage and the auxiliary amplifier output stage can use the same batch of components from the same manufacturer, so that the main current and auxiliary current are as close as possible. It can be understood that since the circuit structure and components of the main amplifier output stage and the auxiliary amplifier output stage are the same, and the main current and the auxiliary current are similar, the magnitudes of the first voltage signal and the second voltage signal are also consistent or similar.

Therefore, the output stage buffer of the present application can generate similar power consumption in the analog output mode and the digital communication mode, reduce the power consumption difference between the analog output mode and the digital communication mode, and will not introduce additional errors in the temperature calibration stage , ensuring the high precision of the whole system.

Referring to Fig. 3, in the embodiment of the present application, the input stage includes:

The first P-type transistor PM1, the gate is the first bias control terminal Vbp1, and the source is connected to the power supply terminal VDD;

The second P-type transistor PM2, the gate is the signal input terminal Vin+, and the drain is used to output the second current signal;

The third P-type transistor PM3, the gate is the output selection terminal, and the drain is used to output the first current signal; the source is connected to the drain of the first P-type transistor PM1 and the source of the second P-type transistor PM2 pole.

The bias stage includes:

The source of the fourth P-type transistor PM4 is connected to the power supply terminal VDD;

The sixth P-type transistor PM6, the gate is the second bias control terminal Vbp2, and the source is connected to the drain of the fourth P-type transistor PM4;

The third N-type transistor NM3, the gate is the fifth bias control terminal Vbn2, the drain is the bias output end of the bias stage and is connected to the gate of the fourth P-type transistor PM4 and the drain of the sixth P-type transistor PM6 ;

The gate of the first N-type transistor NM1 is the fourth bias control terminal Vbn1, and the drain is connected to the source of the third N-type transistor NM3 and the drain of the third P-type transistor PM3 (that is, the input stage). Upon receiving the first current signal, the source is grounded.

Specifically, the main amplifying output stage includes a main amplifying stage and a main output stage, the main amplifying stage is used for converting the differential current signal into a first voltage signal, and the main output stage is used for converting the first voltage signal to the first voltage signal. A voltage signal is amplified twice and output. It can be understood that the main amplifier stage is used to convert the second current signal and the first current signal copied to the main amplifier stage into a first voltage signal.

Continue to refer to Fig. 3, described main amplification stage comprises:

The source of the fifth P-type transistor PM5 is connected to the power supply terminal VDD, and the gate is connected to the drain of the third N-type transistor NM3 (ie, the bias output end of the bias stage);

The source of the seventh P-type transistor PM7 is connected to the drain of the fifth P-type transistor PM5, the gate is connected to the second bias control terminal Vbp2 after the fourth switch S4 is connected in series, and the gate is connected to the power supply terminal after the fifth switch S5 is connected in series VDD, the drain connected to the first input terminal of the main output stage;

The fourth N-type transistor NM4, the gate is connected in series with the tenth switch S10 and then connected to the fifth bias control terminal Vbn2, the gate is also connected in series with the eleventh switch S11 and grounded, and the drain is connected to the second input terminal of the main output stage;

The gate of the second N-type transistor NM2 is connected to the fourth bias control terminal Vbn1, and the drain is connected to the source of the fourth N-type transistor NM4 and the drain of the second P-type transistor PM2 (ie, the input stage), for receiving the The second current signal, the source is grounded.

Continuing to refer to Fig. 3, the main output stage includes:

The zeroth P-type transistor PM0, the source is connected to the power supply terminal VDD, and the gate is connected to the power supply terminal VDD after the zeroth switch S0 is connected in series;

The eighth P-type transistor PM8, the gate is connected in series with the sixth switch S6 and then connected to the third bias control terminal Vbp3, and the gate is connected in series with the seventh switch S7 and then connected to the power supply terminal VDD;

The fifth N-type transistor NM5, the gate is connected in series with the eighth switch S8 and then connected to the sixth bias control terminal Vbn3, the gate is also connected in series with the ninth switch S9 and grounded, and the drain is the first input terminal of the main output stage and connected to the The source of the eighth P-type transistor PM8, the gate of the zeroth P-type transistor PM0 and one end of the zeroth capacitor C0, the other end of the zeroth capacitor C0 is connected to one end of the zeroth resistor R0;

The zeroth N-type transistor NM0, the drain is the output terminal of the main output stage and is connected to the drain of the zeroth P-type transistor PM0, the other end of the zeroth resistor R0 and one end of the first resistor R1, and the gate is the output end of the zeroth P-type transistor PM0. The second input terminal of the main output stage is connected to the source of the fifth N-type transistor NM5, the drain of the eighth P-type transistor PM8 and one end of the first capacitor C1, the gate is also connected in series with the first switch S1 and then grounded, and the source grounding, the other end of the first capacitor C1 is connected to the other end of the first resistor R1;

Wherein, the output selection end of the input stage is connected in series with the second switch S2 to the output end of the main output stage, and the output end of the main output stage is also used in series with the third switch S3 to be connected to the digital communication interface.

Specifically, the auxiliary amplifying output stage includes an auxiliary amplifying stage and an auxiliary output stage, the auxiliary amplifying stage is used for converting the differential current signal into a second voltage signal, and the auxiliary output stage is used for converting the first The second voltage signal is amplified twice. It can be understood that the auxiliary amplifier stage is used to convert the second current signal and the first current signal copied to the auxiliary amplifier stage into a second voltage signal.

Continue to refer to Fig. 3, described auxiliary amplification stage comprises:

The source of the ninth P-type transistor PM9 is connected to the power supply terminal VDD, the gate is connected in series with the drain of the third N-type transistor NM3 (that is, the bias output end of the bias stage), and the gate is also connected in series with the fourteenth switch S14 The fifteenth switch S15 is connected to the power supply terminal VDD;

The source of the tenth P-type transistor PM10 is connected to the drain of the ninth P-type transistor PM9, the gate is connected in series with the sixteenth switch S16 and then connected to the second bias control terminal Vbp2, and the gate is also connected in series with the seventeenth switch S17 a power supply terminal VDD, the drain of which is connected to the first input terminal of the auxiliary output stage;

The sixth N-type transistor NM6, the gate is connected in series with the twenty-second switch S22 and then connected to the fifth bias control terminal Vbn2, the gate is also connected in series with the twenty-third switch S23 and grounded, and the drain is connected to the seventh N-type transistor NM7 The source and the drain of the eleventh P-type transistor PM11 (that is, the second input terminal of the auxiliary output stage), the source is connected to the drain of the second P-type transistor PM2 (that is, the input stage), for receiving the second current signal.

Continuing to refer to FIG. 3, the auxiliary output stage includes:

The source of the twelfth P-type transistor PM12 is connected to the power supply terminal VDD, and the gate is connected to the power supply terminal VDD after being connected in series with the twelfth switch S12;

The eleventh P-type transistor PM11, the gate is connected in series with the eighteenth switch S18 and then connected to the third bias control terminal Vbp3, and the gate is connected in series with the nineteenth switch S19 and then connected to the power supply terminal VDD;

The seventh N-type transistor NM7, the gate is connected in series with the twentieth switch S20 and then connected to the sixth bias control terminal Vbn3, the gate is also connected in series with the twenty-first switch S21 and grounded, and the drain is the first input terminal of the auxiliary output stage And connect the source of the eleventh P-type transistor PM11, the gate of the twelfth P-type transistor PM12, and one end of the second capacitor C2, and the other end of the second capacitor C2 is connected to one end of the second resistor R2;

The drain of the eighth N-type transistor NM8 is the output end of the auxiliary output stage and is connected to the drain of the twelfth P-type transistor PM12, the other end of the second resistor R2, and one end of the third resistor R3, and the gate is the output end of the third resistor R3. The second input terminal of the auxiliary output stage is connected to the source of the seventh N-type transistor NM7, the drain of the eleventh P-type transistor PM11 and one end of the third capacitor C3, and the gate is also connected in series with the thirteenth switch S13 and then grounded. The source is grounded, and the other end of the third capacitor C3 is connected to the other end of the third resistor R3;

Wherein, the output selection end of the input stage is connected in series with the twenty-fourth switch S24 to the output end of the auxiliary output stage.

In the embodiment of the present application, the first P-type transistor PM1 is used to provide the quiescent current for the second P-type transistor PM2 and the third P-type transistor PM3, and the current determines the transconductance gm and noise characteristics of the input stage, and the second P-type transistor PM2 The P-type transistor PM2 and the third P-type transistor PM3 convert the input voltage signal into a current signal: I=Vin+*gm.

The first N-type transistor NM1 and the second N-type transistor NM2 are N-tube tail current sources, which provide quiescent current for the bias stage and the main amplifier stage in the analog working mode. The third N-type transistor NM3 , the fourth N-type transistor NM4 and the sixth N-type transistor NM6 are N-type cascode transistors, and their function is to increase the impedance from the drain end of each transistor to the ground.

The fourth P-type transistor PM4 is connected in the form of a diode, which copies the differential current signal (specifically, the first current signal) flowing through the bias stage to the main amplifier stage through the fifth P-type transistor PM5 (analog work mode), copied to the auxiliary amplifier stage (digital communication mode) through the ninth P-type transistor PM9. It can be understood that the differential current signal refers to the current difference between the second P-type transistor PM2 and the third P-type transistor PM3, for example, the current of the second P-type transistor PM2 increases by 1uA, and the current of the third P-type transistor PM3 will reduce 1uA, and the current difference between the second P-type transistor PM2 and the third P-type transistor PM3 is determined by the second P-type transistor PM2 gate voltage (ie Vin+) and the third P-type transistor PM3 gate voltage (Vout )control.

The sixth P-type transistor PM6, the seventh P-type transistor PM7 and the tenth P-type transistor PM10 are P-type cascode transistors, and their function is to increase the impedance from the drain end of each transistor to the power supply.

The eighth P-type transistor PM8, the fifth N-type transistor NM5, the zeroth P-type transistor PM0 and the zeroth N-type transistor NM0 form the main output stage of class ab, which can provide a stronger load current than the traditional class a structure Drive capability. Among them, the eighth P-type transistor PM8 and the fifth N-type transistor NM5 provide bias voltage for the zeroth P-type transistor PM0 and the zeroth N-type transistor NM0. At the same time, when the output current load changes, it can also automatically adjust the zeroth P-type transistor. Gate terminal voltages of the P-type transistor PM0 and the zeroth N-type transistor NM0. The zeroth P-type transistor PM0 and the zeroth N-type transistor NM0 serve as output transistors to provide driving capability for the chip load.

The zeroth capacitor C0, the zeroth resistor R0, the first capacitor C1, and the first resistor R1 connected in series are the compensation devices of the main output stage, so as to ensure the stable operation of the loop.

The eleventh P-type transistor PM11, the seventh N-type transistor NM7, the twelfth P-type transistor PM12 and the eighth N-type transistor NM8 form an auxiliary output stage of class ab, wherein the eleventh P-type transistor PM11 and the seventh N-type The transistor NM7 provides a bias voltage for the twelfth P-type transistor PM12 and the eighth N-type transistor NM8. The twelfth P-type transistor PM12 and the eighth N-type transistor NM8 serve as output transistors of the auxiliary output stage, and when the chip works in digital communication mode, they match the currents of the zeroth P-type transistor PM0 and the zeroth N-type transistor NM0 .

The second capacitor C2, the second resistor R2, the third capacitor C3, and the third resistor R3 connected in series are compensation devices for the auxiliary output stage. The purpose is to ensure that the loop can work stably, and it is also to further ensure The digital communication mode produces the same or similar current, thereby reducing the difference in power consumption and temperature between the analog output mode and the digital communication mode.

Using the output stage buffer of this application, in the analog output mode, the switches S2, S4, S6, S8, S10, S12, S13, S15, S17, S19, S21 and S23 are all closed, and the switches S0, S1, S3, S5 , S7, S9, S11, S14, S16, S18, S20, S22, and S24 are all disconnected, that is, the main amplifier output stage is turned on, the auxiliary amplifier output stage is turned off, and flows through the zeroth P-type transistor PM0 and the zeroth N-type transistor. The current of the transistor NM0 is Iout, and the current flowing through the twelfth P-type transistor PM12 and the eighth N-type transistor NM8 is zero. In digital communication mode, switches S2, S4, S6, S8, S10, S12, S13, S15, S17, S19, S21 and S23 are all open, switches S0, S1, S3, S5, S7, S9, S11, S14 , S16, S18, S20, S22 and S24 are all closed, that is, the auxiliary amplifier output stage is turned on, and the main amplifier output stage is turned off. The current flowing through the zeroth P-type transistor PM0 and the zeroth N-type transistor NM0 is 0, while the current flowing through The current passing through the twelfth P-type transistor PM12 and the eighth N-type transistor NM8 is Iout. In addition, since the current of the digital communication interface is uA level, which can be ignored, the deviation of power consumption in the two working modes of analog output mode and digital communication mode is very small and can be ignored, and no additional power consumption will be introduced during the temperature calibration phase. error, ensuring the high precision of the whole system.

It can be understood that, the first bias control terminal Vbp1, the second bias control terminal Vbp2, the third bias control terminal Vbp3, the fourth bias control terminal Vbn1, the fifth bias control terminal Vbn2 and the sixth bias control terminal The control terminal Vbn3 is used to receive the bias voltage signal, so as to make the output stage buffer work normally. The specific control logic and timing are well known in the art, and the technical solution of the present application does not improve it, so it will not be repeated here.

Those skilled in the art can clearly understand that for the convenience and brevity of description, only the division of the above-mentioned functional modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional modules according to needs. The internal structure of the device is divided into different functional modules to complete all or part of the functions described above. For the specific working processes of the above-described systems, devices, and units, reference may be made to the corresponding processes in the foregoing method embodiments, and details are not repeated here.

In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods may be implemented in other ways. If the integrated unit is realized in the form of a software function unit and sold or used as a separate product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or part of the contribution to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , including several instructions for causing a computer device or processor to execute all or part of the steps of the methods described in the various embodiments of the present application.

The above embodiments are only used to introduce the technical solutions of the present application in detail, but the descriptions of the above embodiments are only used to help understand the method and core idea of the present application, and should not be construed as limiting the present application. Within the technical scope disclosed in this application, changes or substitutions that can be easily conceived by those skilled in the art shall fall within the protection scope of this application.

Claims (10)

1. A kind of output stage buffer, is characterized in that: comprise input stage, bias stage, main amplification output stage and auxiliary amplification output stage; The input stage has a signal input terminal and an output selection terminal, the signal input terminal is used to receive an input voltage signal, and the input stage is used to convert the input voltage signal into a differential current signal, wherein the differential current The signal includes a first current signal and a second current signal; The bias stage, coupled to the input stage, is used to copy the first current signal to the main amplifier output stage in the analog output mode, and copy the first current signal in the digital communication mode to the auxiliary amplifier output stage; The main amplifying output stage is used to convert the differential current signal into a first voltage signal when turned on, and simultaneously amplify and output the first voltage signal twice; The auxiliary amplifying output stage is used to convert the differential current signal into a second voltage signal when turned on, and simultaneously amplify the second voltage signal; Wherein, in the analog output mode, the main amplified output stage is connected through the output selection terminal and output, and in the digital communication mode, the auxiliary amplified output stage is connected through the output selection terminal. 2. The output stage buffer of claim 1, wherein the input stage comprises: The first P-type transistor PM1, the gate is the first bias control terminal Vbp1, and the source is connected to the power supply terminal VDD; The second P-type transistor PM2, the gate is the signal input terminal Vin+, and the drain is used to output the second current signal; The third P-type transistor PM3, the gate is the output selection terminal, and the drain is used to output the first current signal; the source is connected to the drain of the first P-type transistor PM1 and the source of the second P-type transistor PM2 pole. 3. The output stage buffer of claim 1, wherein the bias stage comprises: The source of the fourth P-type transistor PM4 is connected to the power supply terminal VDD; The sixth P-type transistor PM6, the gate is the second bias control terminal Vbp2, and the source is connected to the drain of the fourth P-type transistor PM4; The third N-type transistor NM3, the gate is the fifth bias control terminal Vbn2, the drain is the bias output end of the bias stage and is connected to the gate of the fourth P-type transistor PM4 and the drain of the sixth P-type transistor PM6 ; The gate of the first N-type transistor NM1 is the fourth bias control terminal Vbn1 , the drain is connected to the source of the third N-type transistor NM3 and the input stage for receiving the first current signal, and the source is grounded. 4. The output stage buffer as claimed in claim 1, wherein the main amplified output stage comprises a main amplified stage and a main output stage, and the main amplified stage is used to convert the differential current signal into a first A voltage signal, the main output stage is used to amplify the first voltage signal twice and output it. 5. The output stage buffer as claimed in claim 4, wherein the main amplifier stage comprises: The source of the fifth P-type transistor PM5 is connected to the power supply terminal VDD, and the gate is connected to the bias output terminal of the bias stage; The source of the seventh P-type transistor PM7 is connected to the drain of the fifth P-type transistor PM5, the gate is connected to the second bias control terminal Vbp2 after the fourth switch S4 is connected in series, and the gate is connected to the power supply terminal after the fifth switch S5 is connected in series VDD, the drain connected to the first input terminal of the main output stage; The fourth N-type transistor NM4, the gate is connected in series with the tenth switch S10 and then connected to the fifth bias control terminal Vbn2, the gate is also connected in series with the eleventh switch S11 and grounded, and the drain is connected to the second input terminal of the main output stage; The gate of the second N-type transistor NM2 is connected to the fourth bias control terminal Vbn1, the drain is connected to the source of the fourth N-type transistor NM4 and the input stage, and is used to receive the second current signal, and the source is grounded. 6. The output stage buffer of claim 4, wherein the main output stage comprises: The zeroth P-type transistor PM0, the source is connected to the power supply terminal VDD, and the gate is connected to the power supply terminal VDD after the zeroth switch S0 is connected in series; The eighth P-type transistor PM8, the gate is connected in series with the sixth switch S6 and then connected to the third bias control terminal Vbp3, and the gate is connected in series with the seventh switch S7 and then connected to the power supply terminal VDD; The fifth N-type transistor NM5, the gate is connected in series with the eighth switch S8 and then connected to the sixth bias control terminal Vbn3, the gate is also connected in series with the ninth switch S9 and grounded, and the drain is the first input terminal of the main output stage and connected to the The source of the eighth P-type transistor PM8, the gate of the zeroth P-type transistor PM0 and one end of the zeroth capacitor C0, the other end of the zeroth capacitor C0 is connected to one end of the zeroth resistor R0; The zeroth N-type transistor NM0, the drain is the output terminal of the main output stage and is connected to the drain of the zeroth P-type transistor PM0, the other end of the zeroth resistor R0 and one end of the first resistor R1, and the gate is the output end of the zeroth P-type transistor PM0. The second input terminal of the main output stage is connected to the source of the fifth N-type transistor NM5, the drain of the eighth P-type transistor PM8 and one end of the first capacitor C1, the gate is also connected in series with the first switch S1 and then grounded, and the source grounding, the other end of the first capacitor C1 is connected to the other end of the first resistor R1; Wherein, the output selection end of the input stage is connected in series with the second switch S2 to the output end of the main output stage, and the output end of the main output stage is also used in series with the third switch S3 to be connected to the digital communication interface. 7. The output stage buffer as claimed in claim 1, wherein the auxiliary amplifying output stage comprises an auxiliary amplifying stage and an auxiliary output stage, and the auxiliary amplifying stage is used for converting the differential current signal into a second A voltage signal, the auxiliary output stage is used for secondarily amplifying the second voltage signal. 8. The output stage buffer as claimed in claim 7, wherein the auxiliary amplifier stage comprises: The source of the ninth P-type transistor PM9 is connected to the power supply terminal VDD, the gate is connected to the bias output terminal of the bias stage after the fourteenth switch S14 is connected in series, and the gate is connected to the power supply terminal VDD after the fifteenth switch S15 is connected in series; The source of the tenth P-type transistor PM10 is connected to the drain of the ninth P-type transistor PM9, the gate is connected in series with the sixteenth switch S16 and then connected to the second bias control terminal Vbp2, and the gate is also connected in series with the seventeenth switch S17 a power supply terminal VDD, the drain of which is connected to the first input terminal of the auxiliary output stage; The sixth N-type transistor NM6, the gate is connected to the fifth bias control terminal Vbn2 after the twenty-second switch S22 is connected in series, the gate is also connected in series with the twenty-third switch S23 and then grounded, and the drain is connected to the second The input terminal and the source are connected to the input stage for receiving the second current signal. 9. The output stage buffer of claim 7, wherein the auxiliary output stage comprises: The source of the twelfth P-type transistor PM12 is connected to the power supply terminal VDD, and the gate is connected to the power supply terminal VDD after being connected in series with the twelfth switch S12; The eleventh P-type transistor PM11, the gate is connected in series with the eighteenth switch S18 and then connected to the third bias control terminal Vbp3, and the gate is connected in series with the nineteenth switch S19 and then connected to the power supply terminal VDD; The seventh N-type transistor NM7, the gate is connected in series with the twentieth switch S20 and then connected to the sixth bias control terminal Vbn3, the gate is also connected in series with the twenty-first switch S21 and grounded, and the drain is the first input terminal of the auxiliary output stage And connect the source of the eleventh P-type transistor PM11, the gate of the twelfth P-type transistor PM12, and one end of the second capacitor C2, and the other end of the second capacitor C2 is connected to one end of the second resistor R2; The drain of the eighth N-type transistor NM8 is the output end of the auxiliary output stage and is connected to the drain of the twelfth P-type transistor PM12, the other end of the second resistor R2, and one end of the third resistor R3, and the gate is the output end of the third resistor R3. The second input terminal of the auxiliary output stage is connected to the source of the seventh N-type transistor NM7, the drain of the eleventh P-type transistor PM11 and one end of the third capacitor C3, and the gate is also connected in series with the thirteenth switch S13 and then grounded. The source is grounded, and the other end of the third capacitor C3 is connected to the other end of the third resistor R3; Wherein, the output selection end of the input stage is connected in series with the twenty-fourth switch S24 to the output end of the auxiliary output stage. 10. A current sensor, characterized in that it comprises a sensor element, a first-stage amplifier, a second-stage amplifier, and the output-stage buffer according to any one of claims 1-9, sequentially connected in series.

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