CN115878521B - Command processing system, electronic device and electronic equipment - Google Patents

Abstract

The disclosure provides a command processing system, an electronic device and electronic equipment, and aims to improve command processing efficiency. The command processing system comprises N intermediate processors and a GPU; the intermediate processor is configured to: reading a command from the buffer area, sending a reading instruction to the first target module, and executing the read command under the condition that the read command needs to be executed by the intermediate processor; if the value of N is 1, the first target module is GPU; if the value of N is greater than 1, the first target module corresponding to the last intermediate processor is GPU, and the first target modules corresponding to other intermediate processors are next intermediate processors; the GPU is configured to: after receiving the reading instruction, reading the command from the buffer, preprocessing the read command under the condition that the read command needs to be executed by the intermediate processor and then executed by the GPU, and executing the read command according to the preprocessing result after the intermediate processor finishes executing the command.

Description

Command processing system, electronic device and electronic equipment

technical field

The present disclosure relates to the field of computer technology, in particular to a command processing system, electronic device and electronic equipment.

Background technique

Based on the PCIe (peripheral component interconnect express) protocol, the internal command transmission method of the graphics processor GPU is usually implemented by combining the Doorbell and the buffer. The specific implementation plan is that the host host first writes the DMA (Direct Memory Access) command into the buffer corresponding to the application central processing unit ACPU, and notifies the ACPU through the doorbell mechanism. After the ACPU receives the doorbell interrupt, it reads the DMA command from its corresponding buffer and executes it. The ACPU notifies the host after processing the DMA command. After receiving the notification from the ACPU, the host writes the command to be processed by the GPU into the buffer corresponding to the GPU, and notifies the GPU through the doorbell mechanism. After the GPU receives the doorbell interrupt, it reads the command from its corresponding buffer and executes it. It can be seen that before the host sends a command to the GPU, it needs to wait for the ACPU to finish executing the DMA command, resulting in low command execution efficiency.

Contents of the invention

The purpose of the present disclosure is to provide a command processing system, an electronic device, and an electronic device, aiming at improving command processing efficiency.

According to one aspect of the present disclosure, a command processing system is provided, including N intermediate processors and GPUs, and when the value of N is greater than 1, there is a sequence relationship between the N intermediate processors;

The intermediate processor is configured to: after receiving the read instruction, read the command from the buffer, send the read instruction to the first target module, and execute the read command when the read command needs to be executed by the intermediate processor itself; wherein, if the value of N is 1, the first target module is a GPU; if the value of N is greater than 1, the first target module corresponding to the last intermediate processor is a GPU, and the first target modules corresponding to other intermediate processors are the next intermediate processor;

The GPU is configured to: after receiving the read instruction, read the command from the buffer, in the case that the read command needs to be executed first by the intermediate processor and executed later by the GPU, preprocess the read command, wait for the intermediate processor to execute the command, and then execute the read command according to the preprocessing result.

In a feasible implementation of the present disclosure, the buffer is a circular buffer, and the circular buffer is configured with a first offset field corresponding to the host machine, a second offset field corresponding to each intermediate processor, and a third offset field corresponding to the GPU. The first offset field is used to represent the position in the circular buffer of the command last written by the host machine into the circular buffer, the second offset field corresponding to each intermediate processor is used to represent the position in the circular buffer of the command last read by the corresponding intermediate processor from the circular buffer, and the third offset field is used to represent the position in the circular buffer of the command last read by the GPU from the circular buffer;

When the intermediate processor reads the command from the buffer, it is configured to: read the command from the circular buffer according to the offset field of the second target module, and update the second offset field of itself; wherein, if the value of N is 1, the second target module is the host computer; if the value of N is greater than 1, the second target module corresponding to the first intermediate processor is the host computer, and the second target modules corresponding to the remaining intermediate processors are the previous intermediate processor;

When the GPU reads the command from the buffer, it is configured to: read the command from the circular buffer and update the third offset field according to the second offset field of the intermediate processor sending the read instruction to it.

In a feasible implementation of the present disclosure, when the intermediate processor reads commands from the circular buffer according to the offset field of the second target module and updates its own second offset field, it is configured to read commands one by one from the circular buffer when its own second offset field is not equal to the offset field of the second target module, update its own second offset field once for each command read, and stop reading commands until its own second offset field is equal to the second target module's offset field.

In a feasible implementation manner of the present disclosure, when the intermediate processor sends the read instruction to the first target module, it is configured to: send the read instruction to the first target module when its second offset field is equal to the offset field of the second target module.

In a feasible implementation of the present disclosure, when the GPU reads a command from the circular buffer and updates the third offset field according to the second offset field of the intermediate processor that sends the read instruction to the GPU, it is configured to: when the third offset field is not equal to the second offset field of the intermediate processor that sends the read instruction to the GPU, read commands one by one from the circular buffer, update the third offset field once for each command read, and stop reading the command until the third offset field is equal to the second offset field of the intermediate processor that sends the read instruction to the GPU.

In a feasible implementation of the present disclosure, the intermediate processor is further configured to: after reading the command from the buffer, judge whether the read command needs to be executed by the corresponding first target module, and judge whether the read command needs to be executed first by itself and after the corresponding first target module, and according to the judgment result, fill the corresponding position of the command in the buffer with a first identifier and a second identifier. The first identifier is used to indicate whether the read command needs to be executed by the corresponding first target module, and the second identifier is used to indicate whether the read command needs to be executed first and executed after the corresponding first target module;

When the value of N is greater than 1, the intermediate processor is further configured to: after the circular buffer reads the command, judge whether the read command needs to be executed by itself according to the first identification of the corresponding position, and judge whether the read command needs to be executed first by the previous intermediate processor and then executed by itself according to the second identification of the corresponding position;

The GPU is also configured to: after reading the command from the circular buffer, judge whether the read command needs to be executed by the GPU according to the first identifier at the corresponding position, and judge whether the read command needs to be executed first by the intermediate processor that sends the read instruction to the GPU and then executed by the GPU according to the second identifier at the corresponding position.

In a feasible implementation manner of the present disclosure, the last intermediate processor is further configured to: for a command that needs to be executed first by the last intermediate processor and executed later by the GPU, after processing the command, update the fence status of the command and notify the GPU.

In a feasible implementation manner of the present disclosure, the system further includes a host, and the host is configured to: write one or more commands into the buffer, and send a read instruction to the first intermediate processor among the N intermediate processors.

In a feasible implementation manner of the present disclosure, when writing one or more commands into the buffer, the host is configured to: write one or more commands into the circular buffer according to the third offset field, and update the first offset field.

In a feasible implementation of the present disclosure, when the host computer writes one or more commands into the circular buffer according to the third offset field, it is configured to: write a batch of commands into the circular buffer according to the third offset field until the written position is 1 smaller than the position corresponding to the third offset field, or until a batch of commands are all written.

In a feasible implementation of the present disclosure, the host computer is further configured to: for commands that need to be executed first by the intermediate processor and executed later by the GPU, pack the execution part of the intermediate processor into the execution part of the GPU, and write the execution part of the intermediate processor and the execution part of the GPU into the circular buffer as a single command.

According to another aspect of the present disclosure, there is also provided an electronic device, which includes the command processing system described in any one of the above embodiments. In some usage scenarios, the product form of the electronic device is a graphics card; in other usage scenarios, the product form of the electronic device is a CPU motherboard.

According to another aspect of the present disclosure, there is also provided an electronic device, which includes the above-mentioned electronic device. In some usage scenarios, the product form of the electronic device is a portable electronic device, such as a smartphone, tablet computer, VR device, etc.; in some usage scenarios, the product form of the electronic device is a personal computer, a game console, etc.

Description of drawings

FIG. 1 is a schematic structural diagram of a command processing system proposed by an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a circular buffer proposed by an embodiment of the present disclosure;

FIG. 3 is a schematic structural diagram of a command processing system proposed by another embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a circular buffer proposed by another embodiment of the present disclosure;

Fig. 5 is a schematic structural diagram of a command processing system proposed by another embodiment of the present disclosure.

Detailed ways

Before introducing the embodiments of the present disclosure, it should be noted that some of the embodiments of the present disclosure are described as a processing flow, and although each operation step of the flow may be labeled with a sequential step number, the operation steps therein may be implemented in parallel, concurrently, or simultaneously.

The embodiments of the present disclosure may use the terms "first", "second" and so on to describe various features, but these features should not be limited by these terms. These terms are used only to distinguish one feature from another.

The term "and/or" may be used in the embodiments of the present disclosure, and "and/or" includes any and all combinations of one or more listed associated features.

It should be understood that when describing the connection relationship or communication relationship between two components, unless the two components are directly connected or communicated directly, otherwise, the connection or communication of the two components can be understood as a direct connection or communication, or as an indirect connection or communication through an intermediate component.

In order to make the technical solutions and advantages of the embodiments of the present disclosure clearer, the exemplary embodiments of the present disclosure will be further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than an exhaustive list of all embodiments. It should be noted that, in the case of no conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other.

Based on the PCIe (peripheral component interconnect express) protocol, the internal command transmission method of the graphics processor GPU is usually implemented by combining the Doorbell and the buffer. Before the host computer sends commands to the GPU, it needs to wait for the application central processing unit ACPU to execute the DMA command before sending commands to the GPU, resulting in low command execution efficiency.

In order to improve command execution efficiency, the present disclosure proposes at least one command processing system, electronic device and electronic equipment through the following embodiments.

Referring to FIG. 1 , FIG. 1 is a schematic structural diagram of a command processing system proposed by an embodiment of the present disclosure. As shown in FIG. 1 , the system includes a host computer, N intermediate processors (FIG. 1 only shows a case where there are multiple intermediate processors), and a GPU. Wherein, if there are multiple intermediate processors, there is a sequence relationship among the multiple intermediate processors. Exemplarily, the number of intermediate processors in FIG. 1 is three, and the sequence of the three intermediate processors is: intermediate processor A, intermediate processor B, and intermediate processor C.

Wherein, the host computer is configured to: write one or more commands into the buffer, and send a read instruction to the first intermediate processor among the N intermediate processors.

The intermediate processor is configured to: after receiving the read instruction, read the command from the buffer, send the read instruction to the first target module, and execute the read command when the read command needs to be executed by the intermediate processor itself; wherein, if the value of N is 1, the first target module is a GPU; if the value of N is greater than 1, the first target module corresponding to the last intermediate processor is a GPU, and the first target module corresponding to other intermediate processors is the next intermediate processor.

The GPU is configured to: after receiving the read instruction, read the command from the buffer, in the case that the read command needs to be executed first by the intermediate processor and executed later by the GPU, preprocess the read command, wait for the intermediate processor to execute the command, and then execute the read command according to the preprocessing result.

In the present disclosure, both the GPU and the intermediate processor (such as the ACPU) read commands from the buffer, and the GPU does not need to wait for the intermediate processor to execute the command before reading the command from the buffer, and the GPU can preprocess the read command while the ACPU executes the command, so the present disclosure can effectively improve command execution efficiency.

In some specific implementations, the number of intermediate processors is one. After the host writes a batch of commands into the buffer (this batch of commands may be one or multiple), it sends a read instruction to the intermediate processor through the doorbell interrupt. The command written by the host to the buffer may be a command that needs to be processed by the intermediate processor first and then executed by the GPU, or a command that only needs to be executed by the intermediate processor, or a command that only needs to be executed by the GPU. For such commands that need to be processed by the intermediate processor first and then executed by the GPU, the host needs to encapsulate such commands in advance before writing such commands into the buffer. The method for the host to encapsulate such commands is to package the part that needs to be executed by the intermediate processor into the part that needs to be executed by the GPU, so that the execution part of the intermediate processor and the execution part of the GPU are packaged into one command.

After the intermediate processor receives the doorbell interrupt, it reads the command from the buffer, and then sends a read instruction to the GPU through the doorbell interrupt. In addition, if the command read by the midprocessor needs to be executed by the midprocessor itself, the midprocessor executes the read command. After the GPU receives the doorbell interrupt, it reads the command from the buffer. If the command read by the GPU does not need to be executed by the intermediate processor but only needs to be executed by the GPU, the GPU can directly execute the command after reading the command. If the commands read by the GPU need to be executed first by the intermediate processor and executed later by the GPU, the GPU performs preprocessing on the read commands. When the intermediate processor processes a command that needs to be executed first by itself and executed later by the GPU, it updates the fence status of the command and notifies the GPU. After the GPU receives the notification, it executes the read command according to the preprocessing result.

Among them, the preprocessing process may be to analyze the command header in advance, and distribute the information in the command header to the processing unit inside the GPU, such as a fragment processing unit, a geometry processing unit, a general computing unit, etc., so that the processing unit can obtain the data required for processing the command in advance.

Wherein, after the intermediate processor reads out the command, it can analyze the command. By parsing the command, if the parsing result is that the execution part of the intermediate processor is included in the execution part of the GPU, it is determined that the command needs to be executed first by the intermediate processor and executed later by the GPU. If the result of the parsing is that the command only has an execution part of the GPU, it is determined that the command only requires GPU execution. If the result of the parsing is that the command has only the execution part of the intermediate processor, it is determined that the command only requires the execution of the intermediate processor.

In other specific implementation manners, there are multiple intermediate processors, and there is a sequence relationship among the multiple intermediate processors. After the host writes a batch of commands into the buffer, it sends a read instruction to the first intermediate processor through the doorbell interrupt. The command written by the host to the buffer may be a command that needs to be processed by some or all of the intermediate processors first and then executed by the GPU, or it may be a command that only needs to be executed by some or all of the intermediate processors, or it may be a command that only needs to be executed by the GPU. For such commands that need to be processed by some or all of the intermediate processors first and then executed by the GPU, the host needs to encapsulate such commands in advance before writing such commands into the buffer. The method for the host to encapsulate such commands is to package the execution part of each processor from the outside to the inside according to the execution order of the commands. For ease of understanding, taking the command processing system shown in FIG. 1 as an example, it is assumed that a command needs to be executed by an intermediate processor A first, then by an intermediate processor C, and finally by a GPU. When encapsulating commands, the host machine packs the execution part of the intermediate processor C into the execution part of the GPU, and then packages the execution part of the intermediate processor A into the execution part of the intermediate processor C, thereby packaging the execution parts of several intermediate processors and the execution part of the GPU into one command.

After the first intermediate processor receives the doorbell interrupt, it reads the command from the buffer, and then sends a read instruction to the second intermediate processor through the doorbell interrupt. The second intermediate processor also reads the command from the buffer after receiving the doorbell interrupt. If the command processing system further includes a third intermediate processor, the second intermediate processor also sends a read instruction to the third intermediate processor through a doorbell interrupt. If the command processing system does not include a third intermediate processor, the second intermediate processor sends a read instruction to the GPU through a doorbell interrupt. In short, each intermediate processor sends read instructions to the next intermediate processor in sequence according to the sequence of the intermediate processors. In addition, if the command read by each intermediate processor needs to be executed by the intermediate processor itself, the intermediate processor will execute the read command.

After the GPU receives the doorbell interrupt, it reads the command from the buffer. If the command read by the GPU does not need to be executed by the intermediate processor but only needs to be executed by the GPU, the GPU can directly execute the command after reading the command. If the commands read by the GPU require some or all of the intermediate processors to be executed first and then executed by the GPU, the GPU performs preprocessing on the read commands. After the last intermediate processor that needs to execute the command finishes processing the command, it updates the fence state of the command and notifies the GPU. After the GPU receives the notification, it executes the read command according to the preprocessing result.

If two or more intermediate processors need to execute the command, these intermediate processors also need to execute the command in order.

For ease of understanding, taking the above example as an example, assume that a command needs to be executed by the intermediate processor A first, then by the intermediate processor C, and finally by the GPU. The intermediate processor A reads the command from the buffer after receiving the read instruction from the host computer. The intermediate processor A determines that the command needs to be executed by itself by analyzing the command, so the intermediate processor A executes the command. In addition, regardless of whether the command needs to be executed by the middle processor A, the middle processor A will send a read instruction to the middle processor B. After the intermediate processor B receives the read instruction from the intermediate processor A, it reads the command from the buffer. The intermediate processor B determines that the command does not need to be executed by itself by analyzing the command. In addition, regardless of whether the command needs to be executed by the intermediate processor B, the intermediate processor B will send a read instruction to the intermediate processor C. After the intermediate processor C receives the read instruction from the intermediate processor B, it reads the command from the buffer. By analyzing the command, the intermediate processor C determines that the command needs to be executed first by the intermediate processor A and then by itself, so the intermediate processor C preprocesses the command, waits for the intermediate processor A to execute the command, and then executes the command according to the preprocessing result. In addition, regardless of whether the command needs to be executed by the intermediate processor C, the intermediate processor C will send a read instruction to the GPU. Wherein, the intermediate processor A may trigger the intermediate processor C to execute the command by sending the fence update status to the intermediate processor C. After receiving the reading instruction from the intermediate processor C, the GPU reads the command from the buffer. By parsing the command, the GPU determines that the command needs to be executed first by the intermediate processor C and then executed by itself, so the GPU preprocesses the command. And wait for the intermediate processor C to execute the command and then execute the command itself according to the preprocessing result.

Exemplarily, the intermediate processor in the present disclosure may be an application central processing unit ACPU, and a part of a command that needs to be executed by the application central processing unit ACPU may be a DMA command. It should be explained that executing a command in this disclosure includes at least the following two meanings: first, the processor executes the command internally; second, the processor submits the command to other devices for execution, such as submitting the command to a DMA controller for execution.

In the present disclosure, one or more intermediate processors and the GPU share the same buffer. For commands that need to be executed by the intermediate processor first and then executed by the GPU, the host computer writes the command into the buffer, and the host computer does not need to wait for the intermediate processor to process the command before sending the command to the GPU, which can improve the processing efficiency of the command. In addition, the GPU can start the preprocessing action at the same time as the intermediate processor executes the command, which reduces the delay of the entire command processing and can effectively improve the command processing efficiency.

In some embodiments, the buffer is a circular buffer. For example a circular buffer may be a ring buffer. The circular buffer is configured with a first offset field corresponding to the host computer, a second offset field corresponding to each intermediate processor, and a third offset field corresponding to the GPU. Wherein, the first offset field is used to represent the position in the circular buffer of the command last written by the host to the circular buffer, the second offset field corresponding to each intermediate processor is used to represent the position in the circular buffer of the command last read by the corresponding intermediate processor from the circular buffer, and the third offset field is used to represent the position in the circular buffer of the command last read by the GPU from the circular buffer.

In the present disclosure, when the host computer writes one or more commands into the buffer, it is configured to: write one or more commands into the circular buffer according to the third offset field, and update the first offset field.

When the intermediate processor reads the command from the buffer, it is configured to: read the command from the circular buffer according to the offset field of the second target module, and update the second offset field of itself; wherein, if the value of N is 1, the second target module is the host computer; if the value of N is greater than 1, the second target module corresponding to the first intermediate processor is the host computer, and the second target modules corresponding to the remaining intermediate processors are the previous intermediate processor.

For example, when the first intermediate processor reads the command from the buffer, it is configured to: read the command from the circular buffer according to the first offset field, and update its own second offset field. When the other intermediate processors except the first intermediate processor read the command from the buffer, they are configured to: read the command from the circular buffer according to the second offset field of the previous intermediate processor, and update their own second offset field.

When the GPU reads the command from the buffer, it is configured to: read the command from the circular buffer and update the third offset field according to the second offset field of the intermediate processor sending the read instruction to it. In other words, according to the second offset field of the last intermediate processor, the command is read from the circular buffer and the third offset field is updated.

For ease of understanding, taking one intermediate processor as an example, as shown in FIG. 2 , FIG. 2 is a schematic diagram of a circular buffer proposed by an embodiment of the present disclosure. In Fig. 2, multiple commands are stored in the circular buffer, and the position pointed to by the first offset field shows that the last command written by the host to the circular buffer is command n. It can be seen from the position pointed to by the second offset field that the last command read by the intermediate processor from the circular buffer is command k. It can be seen from the position pointed to by the third offset field that the last command read by the GPU from the circular buffer is the command h.

Hereinafter, taking one intermediate processor as an example, the embodiments of the present disclosure will be described in detail.

In some specific implementation manners, when the host computer writes one or more commands into the circular buffer according to the third offset field, it is configured to: write a batch of commands into the circular buffer according to the third offset field until the write position is 1 less than the position corresponding to the third offset field, or until a batch of commands are all written.

In the present disclosure, when the write position of the host is only 1 smaller than the position corresponding to the third offset field, the host determines that the state of the buffer is full at this time, so it will not continue to write commands to the ring buffer until the GPU reads new commands from the buffer and updates its third offset field forward, and the host will continue to write commands to the buffer. In the present disclosure, the buffer buffer includes a plurality of storage units, and each storage unit can be used to store at least one command, and the respective offset fields of the host machine, the intermediate processor and the GPU are used to point to a storage unit. The above write position is 1 less than the position corresponding to the third offset field. It can be understood that the storage unit of the current write command of the host is the previous storage unit pointed to by the third offset field. For ease of understanding, the storage unit storing the command g (hereinafter referred to as storage unit G) in FIG. 2 is the previous storage unit of the storage unit storing the command h (hereinafter referred to as storage unit H). If when the host computer writes the command to the storage unit G, the third offset field of the GPU also points to the storage unit H, then the host computer judges that the state of the buffer is full at this time, so it will not continue to write the command to the ring buffer.

In the present disclosure, each time the host computer writes a batch of commands to the circular buffer, each time the host computer writes a command, the value of the first offset field is increased by 1 until the value of the first offset field is equal to the third offset field, the host computer suspends writing commands to the buffer, and waits for the value of the third offset field to increase before the host computer continues to write commands to the buffer. Or, until a batch of commands are all written into the buffer, the first offset field is still not equal to the third offset field, and the host computer stops writing commands into the ring buffer. It should be noted that when the first offset field has already pointed to the last address of the circular buffer, after the value of the first offset field is increased by 1, the first offset field will point to the first address of the circular buffer again.

In some specific implementation manners, when the host computer writes the command to the circular buffer, when the value of the first offset field is equal to the third offset field, the host computer sends a read instruction to the intermediate processor. Or the host computer sends a read instruction to the intermediate processor only after all commands to be written into the circular buffer are written into the circular buffer. In this disclosure, the host computer does not send a read instruction to the intermediate processor through the doorbell mechanism every time a command is written to the circular buffer, but only sends a read instruction to the intermediate processor through the doorbell mechanism when the host computer cannot continue to write commands to the circular buffer (for example, when the first offset field is equal to the third offset field, or when a batch of commands are all written into the buffer), so as to reduce interruptions to the intermediate processor.

Or, in some other specific implementation manners, the host computer may also send a read instruction to the intermediate processor through the doorbell mechanism every time a command is written from the circular buffer.

In some specific implementation manners, when the intermediate processor reads commands from the circular buffer according to the first offset field and updates its own second offset field, it is configured to: when the second offset field is not equal to the first offset field, read commands from the circular buffer one by one, and update the second offset field every time a command is read, until the second offset field is equal to the first offset field, and stop reading the command.

In the present disclosure, each time the intermediate processor reads a command from the circular buffer, the value of the second offset field is increased by 1 until the value of the second offset field is equal to the first offset field, and the intermediate processor suspends reading commands from the circular buffer. It should be noted that when the second offset field has already pointed to the last address of the circular buffer, after the value of the second offset field is increased by 1, the second offset field will point to the first address of the circular buffer again.

In some specific implementation manners, when the intermediate processor sends the read instruction to the GPU, it is configured to: send the read instruction to the GPU when the second offset field of the intermediate processor is equal to the first offset field. In other words, when the central processor reads the command pointed to by the first offset field, that is, when the central processor reads the last command written by the host to the circular buffer (that is, the last command written by the host to the circular buffer), the central processor sends a read instruction to the GPU through the doorbell mechanism, which can reduce the disturbance of the central processor to the GPU.

Or, in other specific implementation manners, every time the intermediate processor reads a command from the circular buffer, the intermediate processor sends a read instruction to the GPU through the doorbell mechanism.

In some specific implementations, when the GPU reads commands from the circular buffer according to the second offset field of the intermediate processor, and updates the GPU offset field, it is configured to: when the third offset field is not equal to the second offset field of the last intermediate processor, read the commands one by one from the circular buffer, and update the third offset field once every time a command is read, until the third offset field is equal to the second offset field of the last intermediate processor, and stop reading the command.

In the present disclosure, every time the GPU reads a command from the circular buffer, the value of the third offset field is increased by 1 until the value of the third offset field is equal to the second offset field, and the GPU suspends reading commands from the circular buffer. It should be noted that when the third offset field has already pointed to the last address of the circular buffer, after the value of the third offset field is increased by 1, the third offset field will point to the first address of the circular buffer again.

In some specific implementations, the intermediate processor is further configured to: after reading the command from the buffer, judge whether the read command needs to be executed by the GPU, and judge whether the read command needs to be executed first by itself and then executed by the GPU. According to the judgment result, the corresponding position of the command in the buffer is filled with a first identifier and a second identifier. The first identifier is used to indicate whether the read command needs to be executed by the GPU, and the second identifier is used to indicate whether the read command needs to be executed first by itself and then executed by the GPU.

The GPU is further configured to: after reading the command from the circular buffer, judge whether the read command needs to be executed by the GPU according to the first flag, and judge whether the read command needs to be executed first by the last intermediate processor and executed by the GPU according to the second flag.

For ease of understanding, as shown in FIG. 3 , FIG. 3 is a schematic structural diagram of a command processing system according to another embodiment of the present disclosure. As shown in FIG. 3 , the command processing system includes a host machine, an intermediate processor, and a GPU, wherein the intermediate processor and the GPU share a circular buffer, and the circular buffer includes a plurality of storage areas, and each storage area is used to store a command and a first identifier and a second identifier corresponding to the command.

In FIG. 3 , the storage area pointed to by the second offset field is the storage area that the intermediate processor has just read the command at present. After the intermediate processor reads the command from the storage area, it parses the command to determine whether the command requires GPU processing, and fills the first identifier in the storage area according to the judgment result. As shown in FIG. 3 , the first identifier in some storage areas is GE, indicating that the commands in these storage areas need to be executed by the GPU. In some storage areas, the first identifier is GNE, indicating that the commands in these storage areas do not need to be executed by the GPU.

In addition, the intermediate processor also judges whether the command needs to be executed first by the intermediate processor and executed later by the GPU, and fills the second identifier in the storage area according to the judgment result. As shown in FIG. 3 , the second mark in some storage areas is W, indicating that the commands in these storage areas need to be executed first by the intermediate processor and then executed by the GPU, that is, the GPU needs to wait for the intermediate processor to execute the command before executing the command. In some buffers, the second identifier is NW, indicating that the commands in these storage areas only need to be executed by the GPU, that is, the GPU does not need to wait for the intermediate processor to execute the command first, but can directly execute the command.

Above, the present disclosure has described in detail the case that the number of intermediate processors is one through multiple specific implementation manners. Hereinafter, the present disclosure will describe in detail the situation that there are multiple intermediate processors through multiple specific implementation manners. It should be noted that some specific implementations of multiple intermediate processors are the same as some specific implementations of one intermediate processor, and to avoid repetition, the present disclosure will not describe the same specific implementations.

As shown in FIG. 4 , FIG. 4 is a schematic diagram of a circular buffer proposed by another embodiment of the present disclosure. In FIG. 4 , multiple commands are stored in the circular buffer, and the position pointed to by the first offset field shows that the last command written by the host to the circular buffer is command r. From the position pointed to by the first and second offset fields, it can be seen that the last command read by the intermediate processor A from the circular buffer is the command m. It can be seen from the position pointed to by the second second offset field that the last command read by the intermediate processor B from the circular buffer is command k. From the position pointed to by the third second offset field, it can be seen that the last command read by the intermediate processor C from the circular buffer is the command i. It can be seen from the position pointed to by the third offset field that the last command read by the GPU from the circular buffer is the command f.

In some specific implementation manners, when the host computer writes one or more commands into the circular buffer according to the third offset field, it is configured to: write a batch of commands into the circular buffer according to the third offset field until the write position is 1 less than the position corresponding to the third offset field, or until a batch of commands are all written.

In some specific implementations, the first intermediate processor reads commands one by one from the circular buffer when its own second offset field is not equal to the first offset field, and updates its own second offset field every time it reads a command, until its own second offset field is equal to the first offset field, and stops reading commands.

In some specific implementation manners, when reading commands from the buffer, the rest of the intermediate processors except the first intermediate processor are configured to: read the command from the circular buffer according to the second offset field of the previous intermediate processor, and update the second offset field of itself.

In the present disclosure, when other intermediate processors except the first intermediate processor read a command from the circular buffer, the value of the second offset field of the intermediate processor is increased by 1 until the value of the second offset field is equal to the second offset field of the previous intermediate processor of the intermediate processor, and the intermediate processor suspends reading commands from the circular buffer. For ease of understanding, following the above example, when the intermediate processor B reads a command from the circular buffer, the value of the second offset field of the intermediate processor B is increased by 1 until the value of the second offset field is equal to the second offset field of the intermediate processor A, and the intermediate processor B suspends reading the command from the circular buffer. When each of the intermediate processor C reads a command from the circular buffer, the value of the second offset field of the intermediate processor C is increased by 1 until the value of the second offset field is equal to the second offset field of the intermediate processor A, and the intermediate processor C suspends reading the command from the circular buffer.

It should be noted that when the second offset field has already pointed to the last address of the circular buffer, after the value of the second offset field is increased by 1, the second offset field will point to the first address of the circular buffer again.

In some specific implementation manners, when the last intermediate processor sends the read instruction to the GPU, it is configured to: send the read instruction to the GPU when the second offset field of the last intermediate processor is equal to the second offset field of the previous intermediate processor. In other words, when the last intermediate processor reads the command pointed to by the second offset field of the previous intermediate processor, the last intermediate processor sends a read instruction to the GPU through the doorbell mechanism, which can reduce the interruption of the intermediate processor to the GPU.

Or, in other specific implementation manners, every time the last intermediate processor reads a command from the circular buffer, the intermediate processor sends a read instruction to the GPU through the doorbell mechanism.

In some specific implementations, when the GPU reads commands from the circular buffer according to the second offset field of the last intermediate processor, and updates the GPU offset field, it is configured to: when the third offset field is not equal to the second offset field of the last intermediate processor, read the commands one by one from the circular buffer, and update the third offset field once every time a command is read, until the third offset field is equal to the second offset field of the last intermediate processor, and stop reading the command.

In some specific implementations, the last intermediate processor is further configured to: after reading the command from the buffer, judge whether the read command needs to be executed by the GPU, and judge whether the read command needs to be executed first by itself and then executed by the GPU, and according to the judgment result, fill the first identifier and the second identifier in the corresponding position of the command in the buffer, the first identifier is used to indicate whether the read command needs to be executed by the GPU, and the second identifier is used to indicate whether the read command needs to be executed first by itself and executed later by the GPU.

The GPU is further configured to: after reading the command from the circular buffer, judge whether the read command needs to be executed by the GPU according to the first flag, and judge whether the read command needs to be executed first by the last intermediate processor and executed by the GPU according to the second flag.

Referring to FIG. 5 , FIG. 5 is a schematic structural diagram of a command processing system according to another embodiment of the present disclosure. As shown in FIG. 5, the command processing system includes a host machine, an intermediate processor, and a GPU, wherein the intermediate processor and the GPU share a circular buffer, and the circular buffer includes a plurality of storage areas, and each storage area is used to store a command and N first identifiers and N second identifiers corresponding to the command. As shown by the dotted arrows in FIG. 5 , among the remaining N-1 intermediate processors except the first intermediate processor, each intermediate processor corresponds to a first identifier and a second identifier, and the GPU also corresponds to a first identifier and a second identifier. The first identifier corresponding to each intermediate processor is used to indicate whether the intermediate processor needs to execute the corresponding command. The second identifier corresponding to each intermediate processor is used to indicate whether the intermediate processor needs to wait for the previous intermediate processor to execute the command before executing the command. The first identifier corresponding to the GPU is used to indicate whether the GPU needs to execute a corresponding command. The second identifier corresponding to the GPU is used to indicate whether the GPU needs to wait for the last intermediate processor to execute the command before executing the command.

In Fig. 5, after the intermediate processor A reads a command from the circular buffer, by analyzing the command, it is judged whether the command needs to be executed by the intermediate processor B, and whether the command needs to be executed first by the intermediate processor A and then executed by the intermediate processor B. The intermediate processor A fills in the first first identifier and the first second identifier according to the judgment result. Similarly, after the intermediate processor B reads a command from the circular buffer, it parses the command to determine whether the command needs to be executed by the intermediate processor C, and judges whether the command needs to be executed first by the intermediate processor B and executed later by the intermediate processor C. The intermediate processor B fills in the second first identifier and the second second identifier according to the judgment result. After the intermediate processor C reads a command from the circular buffer, it parses the command to judge whether the command needs to be executed by the GPU, and judges whether the command needs to be executed by the intermediate processor C first and then by the GPU. The intermediate processor C fills in the third first identifier and the third second identifier according to the judgment result.

Above, the present disclosure has described in detail the case where there are multiple intermediate processors through multiple specific implementations.

Based on the same inventive concept, the present disclosure also provides another command processing system, including N intermediate processors and GPUs. When the value of N is greater than 1, there is a sequence relationship among the N intermediate processors.

In some specific implementations, the intermediate processor is configured to: after receiving the read instruction, read the command from the buffer, send the read instruction to the first target module, and execute the read command when the read command needs to be executed by the intermediate processor itself; wherein, if the value of N is 1, the first target module is a GPU; if the value of N is greater than 1, the first target module corresponding to the last intermediate processor is a GPU, and the first target module corresponding to other intermediate processors is the next intermediate processor;

The GPU is configured to: after receiving the read instruction, read the command from the buffer, in the case that the read command needs to be executed first by the intermediate processor and executed later by the GPU, preprocess the read command, wait for the intermediate processor to execute the command, and then execute the read command according to the preprocessing result.

In some specific implementations, the buffer is a circular buffer, and the circular buffer is configured with a first offset field corresponding to the host computer, a second offset field corresponding to each intermediate processor, and a third offset field corresponding to the GPU. The first offset field is used to represent the position in the circular buffer of the command last written by the host computer into the circular buffer, the second offset field corresponding to each intermediate processor is used to represent the position in the circular buffer of the command last read by the corresponding intermediate processor from the circular buffer, and the third offset field is used to represent the position in the circular buffer of the command last read by the GPU from the circular buffer;

When the intermediate processor reads the command from the buffer, it is configured to: read the command from the circular buffer according to the offset field of the second target module, and update the second offset field of itself; wherein, if the value of N is 1, the second target module is the host computer; if the value of N is greater than 1, the second target module corresponding to the first intermediate processor is the host computer, and the second target modules corresponding to the remaining intermediate processors are the previous intermediate processor;

When the GPU reads the command from the buffer, it is configured to: read the command from the circular buffer and update the third offset field according to the second offset field of the intermediate processor sending the read instruction to it.

In some specific implementations, when the intermediate processor reads commands from the circular buffer according to the offset field of the second target module, and updates its own second offset field, it is configured to: when its own second offset field is not equal to the second target module's offset field, read commands one by one from the circular buffer, each time a command is read, update its own second offset field until its own second offset field is equal to the second target module's offset field, and stop reading the command.

In some specific implementations, when the intermediate processor sends the read instruction to the first target module, it is configured to: send the read instruction to the first target module when its second offset field is equal to the offset field of the second target module.

In some specific implementations, when the GPU reads the command from the circular buffer according to the second offset field of the intermediate processor that sends the read instruction to it, and when updating the third offset field, it is configured to: when the third offset field is not equal to the second offset field of the intermediate processor that sends the read instruction to the GPU, read the commands one by one from the circular buffer, and update the third offset field every time a command is read, until the third offset field is equal to the second offset field of the intermediate processor that sends the read instruction to the GPU, and stop reading the command.

In some specific implementations, the intermediate processor is further configured to: after reading the command from the buffer, judge whether the read command needs to be executed by the corresponding first target module, and judge whether the read command needs to be executed first by itself and after the corresponding first target module, and according to the judgment result, fill the corresponding position of the command in the buffer with a first identifier and a second identifier, the first identifier is used to indicate whether the read command needs to be executed by the corresponding first target module, and the second identifier is used to indicate whether the read command needs to be executed first and executed after the corresponding first target module;

When the value of N is greater than 1, the intermediate processor is further configured to: after the circular buffer reads the command, judge whether the read command needs to be executed by itself according to the first identification of the corresponding position, and judge whether the read command needs to be executed first by the previous intermediate processor and then executed by itself according to the second identification of the corresponding position;

The GPU is also configured to: after reading the command from the circular buffer, judge whether the read command needs to be executed by the GPU according to the first identifier at the corresponding position, and judge whether the read command needs to be executed first by the intermediate processor that sends the read instruction to the GPU and then executed by the GPU according to the second identifier at the corresponding position.

In some specific implementation manners, the last intermediate processor is further configured to: for a command that needs to be executed first by the last intermediate processor and executed later by the GPU, after processing the command, update the fence status of the command, and notify the GPU.

In the present disclosure, both the GPU and the intermediate processor (such as the ACPU) read commands from the buffer, and the GPU does not need to wait for the intermediate processor to execute the command before reading the command from the buffer, and the GPU can preprocess the read command while the ACPU executes the command, so the present disclosure can effectively improve command execution efficiency.

Embodiments of the present disclosure further provide an electronic device, which includes the command processing system described in any one of the above embodiments. In some usage scenarios, the product form of the electronic device is a graphics card; in other usage scenarios, the product form of the electronic device is a CPU motherboard.

An embodiment of the present disclosure also provides an electronic device, where the electronic device includes the above-mentioned electronic device. In some usage scenarios, the product form of the electronic device is a portable electronic device, such as a smartphone, tablet computer, VR device, etc.; in some usage scenarios, the product form of the electronic device is a personal computer, a game console, a workstation, a server, etc.

While preferred embodiments of the present disclosure have been described, additional changes and modifications can be made to these embodiments by those skilled in the art once the basic inventive concept is appreciated. Therefore, it is intended that the appended claims be construed to cover the preferred embodiment and all changes and modifications which fall within the scope of the present disclosure.

It is obvious that those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and equivalent technologies thereof, the present disclosure also intends to include these modifications and variations.

Claims (13)

1. A command processing system, comprising N intermediate processors and GPUs, where the value of N is greater than 1, there is a sequence relationship between the N intermediate processors; The intermediate processor is configured to: after receiving the read instruction, read the command from the buffer, send the read instruction to the first target module, and execute the read command when the read command needs to be executed by the intermediate processor itself; wherein, if the value of N is 1, the first target module is the GPU; if the value of N is greater than 1, the first target module corresponding to the last intermediate processor is the GPU, and the first target module corresponding to other intermediate processors is the next intermediate processor; The intermediate processor is further configured to: after reading the command from the buffer, judge whether the read command needs to be executed by the corresponding first target module, and judge whether the read command needs to be executed first by itself and after the corresponding first target module, and according to the judgment result, fill the corresponding position of the command in the buffer with a first identifier and a second identifier, the first identifier is used to indicate whether the read command needs to be executed by the corresponding first target module, and the second identifier is used to indicate whether the read command needs to be executed first and executed after the corresponding first target module; The GPU is configured to: after receiving the read instruction, read the command from the buffer, and when the read command needs to be executed first by the intermediate processor and executed later by the GPU, preprocess the read command, wait for the intermediate processor to execute the command, and then execute the read command according to the preprocessing result; The GPU is further configured to: after reading the command from the buffer, judge whether the read command needs to be executed by the GPU according to the first identifier at the corresponding position, and judge whether the read command needs to be executed first by the intermediate processor that sends the read instruction to the GPU and then executed by the GPU according to the second identifier at the corresponding position. 2. The system according to claim 1, wherein the buffer is a circular buffer, and the circular buffer is configured with a first offset field corresponding to the host computer, a second offset field corresponding to each of the intermediate processors, and a third offset field corresponding to the GPU, the first offset field is used to represent the position in the circular buffer of the command last written by the host computer into the circular buffer, the second offset field corresponding to each intermediate processor is used to represent the position in the circular buffer of the command last read by the corresponding intermediate processor from the circular buffer, and the third offset field is used to represent the last command read by the GPU from the circular buffer in the circular buffer location; When the intermediate processor reads the command from the buffer, it is configured to: read the command from the circular buffer according to the offset field of the second target module, and update the second offset field of itself; wherein, if the value of N is 1, the second target module is the host computer; if the value of N is greater than 1, the second target module corresponding to the first intermediate processor is the host computer, and the second target modules corresponding to the remaining intermediate processors are the previous intermediate processor; When the GPU reads the command from the buffer, it is configured to: read the command from the circular buffer according to the second offset field of the intermediate processor sending the read instruction to it, and update the third offset field. 3. The system according to claim 2, when the intermediate processor reads commands from the circular buffer according to the offset field of the second target module and updates its own second offset field, it is configured to: in the case that its second offset field is not equal to the offset field of the second target module, read commands one by one from the circular buffer, and update the second offset field of itself every time a command is read, until the second offset field of itself is equal to the offset field of the second target module, and stop reading the command. 4. The system according to claim 2, when the intermediate processor sends the read instruction to the first target module, it is configured to: send the read instruction to the first target module when its second offset field is equal to the offset field of the second target module. 5. The system according to claim 2, when the GPU reads a command from the circular buffer according to the second offset field of the intermediate processor that sends the read instruction to it, and when updating the third offset field, it is configured to: when the third offset field is not equal to the second offset field of the intermediate processor that sends the read instruction to the GPU, read commands one by one from the circular buffer, and update the third offset field once every time a command is read, until the third offset field is equal to the second offset field of the intermediate processor that sends the read instruction to the GPU, and stop reading commands. 6. The system according to claim 1 or 2, when the value of N is greater than 1, the intermediate processor is further configured to: after reading the command from the buffer, judge whether the read command needs to be executed by itself according to the first identifier at the corresponding position, and judge whether the read command needs to be executed first by the previous intermediate processor and executed after itself according to the second identifier at the corresponding position. 7. The system according to claim 1, wherein the last intermediate processor is further configured to: for a command that needs to be executed first by the last intermediate processor and executed later by the GPU, after processing the command, update the fence status of the command, and notify the GPU. 8. The system according to claim 2, further comprising a host machine configured to: write one or more commands into the buffer, and send a read instruction to the first intermediate processor among the N intermediate processors. 9. The system according to claim 8, when the host computer writes one or more commands into the buffer, it is configured to: write one or more commands into the circular buffer according to the third offset field, and update the first offset field. 10. The system according to claim 9, when the host machine writes one or more commands into the circular buffer according to the third offset field, it is configured to: write a batch of commands into the circular buffer according to the third offset field until the written position is 1 smaller than the position corresponding to the third offset field, or until the batch of commands are all written. 11. The system according to claim 8, wherein the host machine is further configured to: for commands that require the intermediate processor to execute first and the GPU to execute later, pack the execution part of the intermediate processor into the execution part of the GPU, and write the execution part of the intermediate processor and the execution part of the GPU into the circular buffer as a single command. 12. An electronic device comprising the system according to any one of claims 1-11. 13. An electronic device comprising the electronic device according to claim 12.