CN115879555B - Quantum modulus rapid multiplication operation method, device and modulus arithmetic component - Google Patents
Quantum modulus rapid multiplication operation method, device and modulus arithmetic component Download PDFInfo
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Abstract
The invention discloses a quantum modulus rapid multiplication method, a device and a modulus arithmetic component, which are characterized in that two target data to be operated are obtained and converted into two first target quantum states; performing quantum state evolution corresponding to modulus rapid multiplication operation on the two first target quantum states to obtain a second target quantum state of the evolved storage modulus rapid multiplication operation result; and outputting the finally obtained second target quantum state as a modulus rapid multiplication operation result of the two target data to be operated, so that the modulus rapid multiplication operation in a quantum circuit is realized, and the blank of the related technology is filled.
Description
Technical Field
The invention belongs to the technical field of quantum computing, and particularly relates to a quantum modulus rapid multiplication method and device and a modulus arithmetic component.
Background
The quantum computer is a kind of physical device which performs high-speed mathematical and logical operation, stores and processes quantum information according to the law of quantum mechanics. When a device processes and calculates quantum information and operates on a quantum algorithm, the device is a quantum computer. Quantum computers are a key technology under investigation because of their ability to handle mathematical problems more efficiently than ordinary computers, for example, to accelerate the time to crack RSA keys from hundreds of years to hours.
In the implementation process of the decryption quantum algorithm, the quantum algorithm is generally required to be built by means of various quantum logic gates, but when the quantum algorithm is built by means of various quantum logic gates, there is no quantum logic gate which corresponds to the operation of the modular basic arithmetic operation of classical modular operations such as modular addition, modular multiplication, modular squaring and modular inversion. Therefore, there is an urgent need to provide a technique capable of realizing the operation of the analog-to-digital basic arithmetic operation in the quantum wire, so as to fill the gap of the related art.
Disclosure of Invention
The invention aims to provide a quantum modulus rapid multiplication method, a device, an electronic device and a modulus arithmetic component, which aim to realize modulus rapid multiplication operation in a quantum circuit so as to fill the blank of the related technology.
One embodiment of the invention provides a quantum modulus fast multiplication method, which comprises the following steps:
Acquiring two target data to be operated, and converting the two target data to be operated into two first target quantum states;
Performing quantum state evolution corresponding to modulus rapid multiplication operation on the two first target quantum states to obtain a second target quantum state of the evolved storage modulus rapid multiplication operation result;
And outputting the finally obtained second target quantum state as a modulus rapid multiplication operation result of the two target data to be operated.
Optionally, in the aspect of performing quantum state evolution corresponding to the modular rapid multiplication operation on the two first target quantum states, obtaining a second target quantum state of the evolved storage modular rapid multiplication operation result, the method includes:
obtaining a modulus adder module and a modulus multiplier module;
cascading the modulus adder module and the modulus multiplier module to generate a target quantum circuit corresponding to the modulus fast multiplier;
and carrying out modular rapid multiplication operation on each quantum bit of the two first target quantum states through the target quantum circuit to generate a second target quantum state.
Optionally, the number of modulo-adder modules is the same as the number n of qubits of the first target quantum state; the number of the modulus multiplier modules is one less than the number n of the quantum bits of the first target quantum state; in the aspect of cascading the modulus adder module and the modulus multiplier module to generate a target quantum circuit corresponding to a modulus fast multiplier, the method comprises the following steps:
And alternately cascading the n modulus adder modules and the n-1 modulus multiplier modules to generate a target quantum circuit corresponding to the modulus fast multiplier.
Optionally, the modulus adder module includes four input terms and four output terms, and the modulus multiplier module includes two input terms and two output terms; in the aspect of alternately cascading n modulus adder modules and n-1 modulus multiplier modules to generate a target quantum circuit corresponding to a modulus fast multiplier, the method comprises the following steps:
taking two output items of the current modulus adder module as two input items of the current modulus multiplier module, and taking the other two output items of the current modulus adder and the two output items of the current modulus multiplier as four input items of the next modulus adder module;
and alternately cascading the n modulus adder modules and the n-1 modulus multiplier modules to generate a target quantum circuit corresponding to the modulus fast multiplier.
Optionally, the four input items of the modulus adder module include two quantum state input items to be operated, a modulus fast multiplication result input item and an auxiliary input item; the four output items of the modulus adder module comprise two quantum state output items to be operated, a first modulus rapid multiplication result output item and a first auxiliary output item;
The two input items of the modulus multiplier module comprise a first modulus fast multiplication result output item and a first auxiliary output item of the modulus adder module; the two output terms of the modulus multiplier module include a second modulus fast multiplication result output term and a second auxiliary output term.
Optionally, in the aspect of performing a modular fast multiplication operation on each qubit of the two first target quantum states through the target quantum circuit, generating a second target quantum state, the method includes:
preparing an input quantum state and an auxiliary input quantum state of a modulus rapid multiplication result;
Taking the two first target quantum states as the input of two quantum state input items to be operated, taking the input quantum state of the modulus rapid multiplication result as the input of the modulus rapid multiplication result input item, and taking the auxiliary input quantum state as the input of the auxiliary input item to obtain the target quantum circuit after the initial state is prepared;
And operating the target quantum circuit after the initial state is prepared, measuring quantum bits corresponding to the input quantum state of the modulus rapid multiplication result, and obtaining a second target quantum state.
Yet another embodiment of the present invention provides a quantum modular fast multiplication apparatus, the apparatus comprising:
the device comprises an acquisition unit, a first quantum state generation unit and a second quantum state generation unit, wherein the acquisition unit is used for acquiring two target data to be operated and converting the two target data to be operated into two first target quantum states;
The evolution unit is used for carrying out quantum state evolution corresponding to modulus rapid multiplication operation on the two first target quantum states to obtain a second target quantum state of the evolved storage modulus rapid multiplication operation result;
And the output unit is used for outputting the finally obtained second target quantum state as a modulus rapid multiplication result of the two target data to be operated.
Optionally, in the aspect that quantum states corresponding to the performing of the modulo rapid multiplication on the two first target quantum states evolve, a second target quantum state of an evolved storage modulo rapid multiplication result is obtained, where the evolution unit is specifically configured to:
obtaining a modulus adder module and a modulus multiplier module;
cascading the modulus adder module and the modulus multiplier module to generate a target quantum circuit corresponding to the modulus fast multiplier;
and carrying out modular rapid multiplication operation on each quantum bit of the two first target quantum states through the target quantum circuit to generate a second target quantum state.
Optionally, the number of modulo-adder modules is the same as the number n of qubits of the first target quantum state; the number of the modulus multiplier modules is one less than the number n of the quantum bits of the first target quantum state; in the aspect of cascading the modulus adder module and the modulus multiplier module to generate a target quantum circuit corresponding to the modulus fast multiplier, the evolution unit is specifically configured to:
And alternately cascading the n modulus adder modules and the n-1 modulus multiplier modules to generate a target quantum circuit corresponding to the modulus fast multiplier.
Optionally, the modulus adder module includes four input terms and four output terms, and the modulus multiplier module includes two input terms and two output terms; in the aspect of alternately cascading the n modulo adder modules and the n-1 modulo multiplier modules to generate a target quantum circuit corresponding to the modulo fast multiplier, the evolution unit is specifically configured to:
taking two output items of the current modulus adder module as two input items of the current modulus multiplier module, and taking the other two output items of the current modulus adder and the two output items of the current modulus multiplier as four input items of the next modulus adder module;
and alternately cascading the n modulus adder modules and the n-1 modulus multiplier modules to generate a target quantum circuit corresponding to the modulus fast multiplier.
Optionally, the four input items of the modulus adder module include two quantum state input items to be operated, a modulus fast multiplication result input item and an auxiliary input item; the four output items of the modulus adder module comprise two quantum state output items to be operated, a first modulus rapid multiplication result output item and a first auxiliary output item;
The two input items of the modulus multiplier module comprise a first modulus fast multiplication result output item and a first auxiliary output item of the modulus adder module; the two output terms of the modulus multiplier module include a second modulus fast multiplication result output term and a second auxiliary output term.
Optionally, in the aspect of performing a modular fast multiplication operation on each qubit of the two first target quantum states through the target quantum circuit to generate a second target quantum state, the evolution unit is specifically configured to:
preparing an input quantum state and an auxiliary input quantum state of a modulus rapid multiplication result;
Taking the two first target quantum states as the input of two quantum state input items to be operated, taking the input quantum state of the modulus rapid multiplication result as the input of the modulus rapid multiplication result input item, and taking the auxiliary input quantum state as the input of the auxiliary input item to obtain the target quantum circuit after the initial state is prepared;
And operating the target quantum circuit after the initial state is prepared, measuring quantum bits corresponding to the input quantum state of the modulus rapid multiplication result, and obtaining a second target quantum state.
A further embodiment of the invention provides a storage medium having a computer program stored therein, wherein the computer program is arranged to perform the method of any of the preceding claims when run.
Yet another embodiment of the invention provides an electronic device comprising a memory having a computer program stored therein and a processor configured to run the computer program to perform the method described in any of the above.
Yet another embodiment of the present invention provides a quantum modular arithmetic assembly comprising a quantum modular fast multiplier determined according to the method described in any of the preceding claims.
Compared with the prior art, the quantum modulus rapid multiplication method provided by the invention has the advantages that two target data to be operated are obtained, and the two target data to be operated are converted into two first target quantum states; performing quantum state evolution corresponding to modulus rapid multiplication operation on the two first target quantum states to obtain a second target quantum state of the evolved storage modulus rapid multiplication operation result; and outputting the finally obtained second target quantum state as a modulus rapid multiplication operation result of the two target data to be operated, so that the modulus rapid multiplication operation in a quantum circuit is realized, and the blank of the related technology is filled.
Drawings
FIG. 1 is a block diagram of a hardware architecture of a computer terminal of a method for quantum modulus fast multiplication according to an embodiment of the present invention;
FIG. 2 is a schematic flow chart of a method for quantum modulus fast multiplication according to an embodiment of the present invention;
FIG. 3 is a diagram of a target quantum circuit corresponding to a fast modulus multiplier according to an embodiment of the present invention;
FIG. 4 is a quantum circuit diagram corresponding to a modulo adder according to an embodiment of the invention;
FIG. 5 is a quantum circuit diagram corresponding to an analog-to-digital multiplier according to an embodiment of the present invention;
fig. 6 is a quantum circuit diagram corresponding to a comparator according to an embodiment of the present invention;
Fig. 7 is a schematic structural diagram of a quantum modulus fast multiplication device according to an embodiment of the present invention.
Detailed Description
The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention.
The embodiment of the invention firstly provides a quantum modulus rapid multiplication method which can be applied to electronic equipment such as computer terminals, in particular to common computers, quantum computers and the like.
The following describes the operation of the computer terminal in detail by taking it as an example. Fig. 1 is a hardware block diagram of a computer terminal of a quantum modulus rapid multiplication method according to an embodiment of the present invention. As shown in fig. 1, the computer terminal may include one or more (only one is shown in fig. 1) processors 102 (the processor 102 may include, but is not limited to, a microprocessor MCU or a processing device such as a programmable logic device FPGA) and a memory 104 for storing quantum-wire-based quantum-modulus fast multiplication methods, and optionally, a transmission device 106 for communication functions and an input-output device 108. It will be appreciated by those skilled in the art that the configuration shown in fig. 1 is merely illustrative and is not intended to limit the configuration of the computer terminal described above. For example, the computer terminal may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.
The memory 104 may be used to store software programs and modules of application software, such as program instructions/modules corresponding to the quantum modulus fast multiplication method in the embodiment of the present invention, and the processor 102 executes the software programs and modules stored in the memory 104 to perform various functional applications and data processing, that is, implement the method described above. Memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory remotely located relative to the processor 102, which may be connected to the computer terminal via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The transmission means 106 is arranged to receive or transmit data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of a computer terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, NIC) that can connect to other network devices through a base station to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module for communicating with the internet wirelessly.
It should be noted that a real quantum computer is a hybrid structure, which includes two major parts: part of the computers are classical computers and are responsible for performing classical computation and control; the other part is quantum equipment, which is responsible for running quantum programs so as to realize quantum computation. The quantum program is a series of instruction sequences written in a quantum language such as QRunes language and capable of running on a quantum computer, so that the support of quantum logic gate operation is realized, and finally, quantum computing is realized. Specifically, the quantum program is a series of instruction sequences for operating the quantum logic gate according to a certain time sequence.
In practical applications, quantum computing simulations are often required to verify quantum algorithms, quantum applications, etc., due to the development of quantum device hardware. Quantum computing simulation is a process of realizing simulated operation of a quantum program corresponding to a specific problem by means of a virtual architecture (namely a quantum virtual machine) built by resources of a common computer. In general, it is necessary to construct a quantum program corresponding to a specific problem. The quantum program, namely the program for representing the quantum bit and the evolution thereof written in the classical language, wherein the quantum bit, the quantum logic gate and the like related to quantum computation are all represented by corresponding classical codes.
Quantum circuits, which are one embodiment of quantum programs and weigh sub-logic circuits as well, are the most commonly used general quantum computing models, representing circuits that operate on qubits under an abstract concept, and their composition includes qubits, circuits (timelines), and various quantum logic gates, and finally the result often needs to be read out through quantum measurement operations.
Unlike conventional circuits, which are connected by metal lines to carry voltage or current signals, in a quantum circuit, the circuit can be seen as being connected by time, i.e., the state of the qubit naturally evolves over time, as indicated by the hamiltonian operator, during which it is operated until a logic gate is encountered.
One quantum program is corresponding to one total quantum circuit, and the quantum program refers to the total quantum circuit, wherein the total number of quantum bits in the total quantum circuit is the same as the total number of quantum bits of the quantum program. It can be understood that: one quantum program may consist of a quantum circuit, a measurement operation for the quantum bits in the quantum circuit, a register to hold the measurement results, and a control flow node (jump instruction), and one quantum circuit may contain several tens of hundreds or even thousands of quantum logic gate operations. The execution process of the quantum program is a process of executing all quantum logic gates according to a certain time sequence. Note that the timing is the time sequence in which a single quantum logic gate is executed.
It should be noted that in classical computation, the most basic unit is a bit, and the most basic control mode is a logic gate, and the purpose of the control circuit can be achieved by a combination of logic gates. Similarly, the way in which the qubits are handled is a quantum logic gate. Quantum logic gates are used, which are the basis for forming quantum circuits, and include single-bit quantum logic gates, such as Hadamard gates (H gates, ada Ma Men), bery-X gates (X gates), bery-Y gates (Y gates), bery-Z gates (Z gates), RX gates, RY gates, RZ gates, and the like; multi-bit quantum logic gates such as CNOT gates, CR gates, iSWAP gates, toffoli gates, and the like. Quantum logic gates are typically represented using unitary matrices, which are not only in matrix form, but also an operation and transformation. The general function of a quantum logic gate on a quantum state is to calculate through a unitary matrix multiplied by a matrix corresponding to the right vector of the quantum state.
In the number theory, a unit of measure is referred to as a modulus or a modulus, for example, the clock is counted in 12 cycles, i.e., in 12. The modular operation has wide application in both number theory and program design, and the distinguishing of odd and even numbers to the distinguishing of prime numbers, from modular exponentiation operation to the solving of greatest common divisor, from the grandson problem to the Kaiser password problem, has no figure of influence of the modular operation. Modulo fast multiplication refers to the operation of modulo the product of any two data, e.g., any modulo fast multiplication of 10, 5 x 9mod 10 = 5. In the field of quantum computing, there is an urgent need to provide a technology capable of implementing fast modular multiplication operation in quantum circuits, so as to fill the gap of the related technology.
Referring to fig. 2, fig. 2 is a schematic flow chart of a quantum modulus fast multiplication method according to an embodiment of the present invention. The method comprises the following steps:
step 201: acquiring two target data to be operated, and converting the two target data to be operated into two first target quantum states;
Specifically, in the aspect of acquiring the two target data to be operated and converting the two target data to be operated into the two first target quantum states, the decimal data to be operated may be converted into binary quantum state representation by using an existing amplitude coding mode. For example, one target data is 7, a signed binary representation 0111; another target data is 4, a signed binary representation 011; wherein, the most significant bit 0 represents a positive number and1 represents a negative number. The target quantum states are eigenstates corresponding to two target quantum bits, and the number of all eigenstate representations corresponding to the quantum bits is the power of 2 quantum bits. For example: for example, a group of qubits is q 0、q1、q2, which represents the 0 th, 1 st and 2 nd qubits, and the sequence from the high order to the low order is q 2q1q0, the number of eigenstates (i.e., quantum states) corresponding to the group of qubits is 8 in total, and the eigenstates are respectively: |000>, |001>, |010>, |011>, |100>, |101>, |110>, |111>, the superposition state between the 8 eigenstates. The number of the group of the quantum bits can be set according to actual operation requirements.
Step 202: performing quantum state evolution corresponding to modulus rapid multiplication operation on the two first target quantum states to obtain a second target quantum state of the evolved storage modulus rapid multiplication operation result;
The present embodiment is used to introduce a logic circuit for implementing a fast multiplication operation in a quantum computer, and describes each module in conjunction with pre-development software QPanda. Any classical logic circuit may also be represented by a quantum circuit. The classical circuit corresponds to the quantum circuit one by one, the input and the output of the quantum logic gate/the quantum circuit are all quantum bits, and the quantity of the quantum bits of the input and the output is equal. The quantum circuit allows quantum states to be input in a superposition manner, and states of output can be output in a superposition manner in the same manner. Reversible computation is the fundamental of quantum computation, i.e. any reversible line exists as a reverse line, i.e. each original output is taken as an input, just mapped onto the original input. Reversible wiring means that there is exactly one input for each output, and this mapping is a one-to-one mapping. For example, an NOT gate is a typical reversible logic gate, whose inverse is itself. Typical irreversible logic gates are and gates, or gates. For example, the inputs to the AND gates are 0,0;0,1;1,0, which indicates that there is no unique mapping from output to input. Reversible computation means that the information is not lost in the computation process, and the original state can be recovered after the inverse transformation. Irreversible computation means that the information is lost. The state of the input cannot be deduced, for example, from the output of an and gate. For reversible calculations, it can be inferred. Any successively executing reversible logic gates together are one reversible operation. The quantum logic gates are all reversible logic gates, so the quantum wires are reversible wires. But quantum measurements are not reversible calculations.
Specifically, in the aspect of performing quantum state evolution corresponding to modular rapid multiplication operation on the two first target quantum states, obtaining a second target quantum state of the evolved storage modular rapid multiplication operation result, the method includes:
obtaining a modulus adder module and a modulus multiplier module;
cascading the modulus adder module and the modulus multiplier module to generate a target quantum circuit corresponding to the modulus fast multiplier;
and carrying out modular rapid multiplication operation on each quantum bit of the two first target quantum states through the target quantum circuit to generate a second target quantum state.
Further, the number of modulo-adder modules is the same as the number n of qubits of the first target quantum state; the number of the modulus multiplier modules is one less than the number n of the quantum bits of the first target quantum state; the step of cascading the modulus adder module and the modulus multiplier module to generate a target quantum circuit corresponding to the modulus fast multiplier comprises the following steps:
And alternately cascading the n modulus adder modules and the n-1 modulus multiplier modules to generate a target quantum circuit corresponding to the modulus fast multiplier.
Wherein the number of qubits of the first target quantum state is the number of qubits used to encode the target data. The specific form of the alternating cascade is as follows:
A0B0A1B1······AiBi······An-2Bn-2An-1
Wherein A i is the ith modulo adder module, and B i is the ith modulo multiplier module.
Still further, the modulo-adder module includes four inputs and four outputs, and the modulo-multiplier module includes two inputs and two outputs; the alternately cascading n modulus adder modules and n-1 modulus multiplier modules to generate a target quantum circuit corresponding to a modulus fast multiplier includes:
taking two output items of the current modulus adder module as two input items of the current modulus multiplier module, and taking the other two output items of the current modulus adder and the two output items of the current modulus multiplier as four input items of the next modulus adder module;
and alternately cascading the n modulus adder modules and the n-1 modulus multiplier modules to generate a target quantum circuit corresponding to the modulus fast multiplier.
The four input items of the modulus adder module comprise two quantum state input items to be operated, a modulus rapid multiplication result input item and an auxiliary input item; the four output items of the modulus adder module comprise two quantum state output items to be operated, a first modulus rapid multiplication result output item and a first auxiliary output item;
The two input items of the modulus multiplier module comprise a first modulus fast multiplication result output item and a first auxiliary output item of the modulus adder module; the two output terms of the modulus multiplier module include a second modulus fast multiplication result output term and a second auxiliary output term.
Each quantum state input item to be operated comprises n sub-quantum state input items, wherein each sub-quantum state input item corresponds to a quantum state of one quantum bit as input, and the quantum state of the quantum bit is |0> or |1 >. One input item of the modulo-adder module is a sub-quantum state input item of a quantum state input item to be operated, and a quantum state input by the sub-quantum state input item is used for controlling whether to execute the modulo-adder module modulo addition operation, so the sub-quantum state input item can also be called a control bit input item. The input quantum state of the control bit input item is |0>, and the modular addition operation is not executed; and if the input quantum state is |1 >, performing a modular addition operation. The control bit input item of the ith modular adder module is a sub-quantum state input item corresponding to the n-1-i quantum bits, wherein i takes a value from 0.
Further, before acquiring the modulo-adder module and the modulo-multiplier module, the method further includes:
acquiring a first common adder module, a constant modulus subtracter module, a constant modulus adder module and a comparator module;
And cascading the first common adder module, the constant modulus subtractor module, the constant modulus adder module and the comparator module to generate a modulus adder module.
Still further, the first normal adder module includes four input terms and four output terms, the constant modulus subtractor module includes three input terms and three output terms, the constant modulus adder module includes three input terms and three output terms, and the comparator module includes four input terms and four output terms;
The cascade connection of the first common adder module, the constant modulus subtractor module, the constant modulus adder module and the comparator module generates a modulus adder module, which comprises:
And cascading the first ordinary adder module, the constant modulus subtractor module, the constant modulus adder module and the comparator module to generate a modulus adder module.
The four input items of the first common adder module comprise two quantum state input items to be added, one addition carry input item and one addition auxiliary input item, and the four output items of the first common adder module comprise two first addition intermediate result output items, one first addition carry output item and one first addition auxiliary output item;
The three input items of the constant modulus subtracter module comprise one first addition intermediate result output item, one first addition carry output item and one first addition auxiliary output item of the first common adder module, and the three output items of the constant modulus subtracter module comprise one second addition intermediate result output item, one second addition carry output item and one second addition auxiliary output item;
The three input items of the constant modulus adder module comprise a second addition intermediate result output item, a second addition carry output item and a second addition auxiliary output item of the constant modulus subtractor module, and the three output items of the constant modulus adder module comprise a third addition intermediate result output item, a third addition carry output item and a third addition auxiliary output item;
The four input items of the comparator module comprise another first addition intermediate result output item of the first common adder module, a third addition intermediate result output item of the constant modulus adder module, a third addition carry output item and a third addition auxiliary output item, and the four output items of the comparator module comprise a quantum state output item to be added, a modulus addition result output item, an addition carry result output item and an addition auxiliary result output item.
In the embodiment of the invention, two quantum state input items to be added correspond to one quantum state input item to be calculated and one modulus fast multiplication result input item of the modulus adder module, one addition carry input item and one addition auxiliary input item correspond to one auxiliary input item of the modulus adder module, and the one auxiliary input item can comprise a plurality of sub auxiliary input items; one quantum state output item to be added corresponds to one quantum state output item to be calculated of the modulus adder module, one modulus addition result output item corresponds to one first modulus fast multiplication result output item of the modulus adder module, and one addition carry result output item and one addition auxiliary result output item correspond to one first auxiliary output item.
Further, before acquiring the modulo-adder module and the modulo-multiplier module, the method further includes:
obtaining a constant multiplier module, a constant modulus subtracter module and a constant modulus adder module;
And cascading the constant multiplier module, the constant modulus subtracter module and the constant modulus adder module to generate a modulus multiplier module.
Still further, the constant multiplier module, the constant modulo subtractor module, and the constant modulo adder module each include three input terms and three output terms, and the cascading the constant multiplier module, the constant modulo subtractor module, and the constant modulo adder module generates a modulo multiplier module, including:
And cascading the constant multiplier module, the constant modulus subtractor module and the constant modulus adder module to generate a modulus multiplier module.
The three input items of the constant multiplier module comprise a quantum state input item to be multiplied, a multiplication carry input item and a multiplication auxiliary input item; the three output terms of the constant multiplier module comprise a first multiplication intermediate result output term, a first multiplication intermediate carry output term and a first multiplication intermediate auxiliary output term;
The three inputs of the constant modulus subtractor module include a first multiplication intermediate result output term, a first multiplication intermediate carry output term, and a first multiplication intermediate auxiliary output term of the constant multiplier module; the three output items of the constant modulus subtracter module comprise a second multiplication intermediate result output item, a second multiplication intermediate carry output item and a second multiplication intermediate auxiliary output item;
The three inputs of the constant modulus adder module include a second multiplication intermediate result output term, a second multiplication intermediate carry output term, and a second multiplication intermediate auxiliary output term of the constant modulus subtractor module; the three output terms of the constant modulus adder module include a modulus multiplication result output term, a multiplication carry output term, and a multiplication auxiliary output term.
In the embodiment of the invention, the quantum state input item to be multiplied corresponds to a first modulus fast multiplication result output item of the modulus adder module, and one multiplication carry input item and one multiplication auxiliary input item correspond to a first auxiliary output item; the modulo multiplication result output term corresponds to a second modulo fast multiplication result output term, and one multiplication carry output term and one multiplication auxiliary output term correspond to a second auxiliary output term.
The constant multiplier can realize constant multiplication by exchanging quantum states on two adjacent quantum bits through a SWAP gate or realize constant multiplication directly in dislocation coding. For example, if the target data is 7 and the binary representation is 111, the input of the added carry term is 0111, and the quantum states on two adjacent quantum bits are exchanged through the SWAP gate, so that the output is 1110, and the decimal representation is 14. For another example, the set of qubits is q 0、q1、q2、q3, representing the 0 th, 1 st, and 2 nd qubits, ordered from high to low as q 3q2q1q0. Binary representation 111 of target data 7 is converted to quantum state 111q 0 of the qubit, and the quantum state of q 0 is prepared as 0, and output is 1110, which is represented as 14 in decimal.
Specifically, in the aspect of performing a modular fast multiplication operation on each qubit of the two first target quantum states through the target quantum circuit to generate a second target quantum state, the method includes:
preparing an input quantum state and an auxiliary input quantum state of a modulus rapid multiplication result;
Taking the two first target quantum states as the input of two quantum state input items to be operated, taking the input quantum state of the modulus rapid multiplication result as the input of the modulus rapid multiplication result input item, and taking the auxiliary input quantum state as the input of the auxiliary input item to obtain the target quantum circuit after the initial state is prepared;
And operating the target quantum circuit after the initial state is prepared, measuring quantum bits corresponding to the input quantum state of the modulus rapid multiplication result, and obtaining a second target quantum state.
For example, as shown in fig. 3, fig. 3 is a quantum circuit diagram corresponding to a fast analog-to-digital multiplier according to an embodiment of the present invention. The two first target quantum states are |x >, |y >, respectively, wherein |x >, which is obtained by encoding n quantum bits, can be written as |x 0>|x1>···|xn-1 >; the quantum state corresponding to the modulus fast multiplication result input item is represented by n quantum bits, the quantum state corresponding to the auxiliary input item is represented by n+3 quantum bits, and the modulus fast multiplication result input quantum state and the auxiliary input quantum state are prepared as |0 >. The module of the modulus adder is realized by a circuit shown in fig. 4, the modulus multiplier is realized by a circuit shown in fig. 5, fig. 4 is a quantum circuit diagram corresponding to the modulus adder provided by the embodiment of the invention, and fig. 5 is a quantum circuit diagram corresponding to the modulus multiplier provided by the embodiment of the invention. Four inputs of the first general adder module: the quantum states corresponding to the two quantum state input items to be added correspond to the first target quantum state |y > encoded by n quantum bits and the modulus fast multiplication result input quantum state |0 >), one addition carry input item and the quantum state corresponding to one addition auxiliary input item are respectively encoded by one quantum bit and n+2 quantum bits, and the quantum state corresponding to the auxiliary input item encoded by n+3 quantum bits is just encoded.
For the first modulo adder module, determining whether to execute by control bit |x n-1 > and outputting |y mod p > if |x n-1 > is |1 >; if |x n-1 > is |0 >, then the output is |y >; for the first modulo multiplier, if the input is |y mod p >, the output is |2 (y mod p) >, if the input is |y >, the output is |2y mod p >, and the input and output of the subsequent modules can be derived according to the above principle, which is not described in detail here.
For the quantum state of the four output items of the last modulus adder module, the quantum state of one output item of the comparator module, the quantum state of one output item of the quantum state to be added, the quantum state of one output item of the modulus addition result, the quantum state of one output item of the addition carry result and the quantum state of one output item of the addition auxiliary result are the final result.
Further, fig. 6 is a quantum circuit diagram of a comparator according to an embodiment of the present invention. The first target quantum state |y > and the modulus fast multiplication result input quantum state |0 > in fig. 4 are two quantum states to be added, and correspond to the two quantum states |x > and |y > to be compared in fig. 6, where |x > represents an intermediate state of the modulus fast multiplication result input quantum state |0 > operation process, and is written as the forms of |x 0···xn-2 > and |x n-1 >. The qubits corresponding to the |a > and the |b > are respectively used for auxiliary carry in the operation process and recording comparison results, and the final comparison results can be determined according to the |g >. The modules in the comparator and their connection relationships can be obtained according to fig. 6, and will not be described here again.
Step 203: and outputting the finally obtained second target quantum state as a modulus rapid multiplication operation result of the two target data to be operated.
In this embodiment, two first target quantum states obtained by converting two target data to be operated are input into a quantum modulus fast multiplier (i.e. the target quantum circuit), so as to obtain a second target quantum state of a corresponding binary representation modulus fast multiplication result. And then directly outputting a second target quantum state which is expressed by the binary system and represents the modulus rapid multiplication result, and completing the modulus rapid multiplication operation of the target data.
Compared with the prior art, the quantum modulus rapid multiplication method provided by the invention has the advantages that two target data to be operated are obtained, and the two target data to be operated are converted into two first target quantum states; performing quantum state evolution corresponding to modulus rapid multiplication operation on the two first target quantum states to obtain a second target quantum state of the evolved storage modulus rapid multiplication operation result; and outputting the finally obtained second target quantum state as a modulus rapid multiplication operation result of the two target data to be operated, so that the modulus rapid multiplication operation in a quantum circuit is realized, and the blank of the related technology is filled.
It should be noted that other operations implemented by a single or multiple modulo fast multipliers and other operators are also within the protection scope of the present application, for example, let two first target quantum states be |x n >, |1 >, or let two first target quantum states be |x n-1 >, |x >, respectively, or be other input quantum states, where the mode of implementing |x n > by |x > may be a modulo operation component mentioned in the present application, or may be a component with other line forms, which is not limited.
Another embodiment of the present invention provides a quantum modulus fast multiplication device, as shown in fig. 7, fig. 7 is a schematic structural diagram of the quantum modulus fast multiplication device provided in the embodiment of the present invention, where the device includes:
an obtaining unit 701, configured to obtain two target data to be operated, and convert the two target data to be operated into two first target quantum states;
the evolution unit 702 is configured to perform quantum state evolution corresponding to the modular rapid multiplication operation on the two first target quantum states, and obtain a second target quantum state after evolution, where the second target quantum state stores a result of the modular rapid multiplication operation;
And an output unit 703, configured to output the finally obtained second target quantum state as a modular fast multiplication result of the two target data to be operated.
Optionally, in the aspect that the quantum states corresponding to the performing the modulo rapid multiplication on the two first target quantum states evolve, a second target quantum state of the evolved storage modulo rapid multiplication result is obtained, where the evolution unit 702 is specifically configured to:
obtaining a modulus adder module and a modulus multiplier module;
cascading the modulus adder module and the modulus multiplier module to generate a target quantum circuit corresponding to the modulus fast multiplier;
and carrying out modular rapid multiplication operation on each quantum bit of the two first target quantum states through the target quantum circuit to generate a second target quantum state.
Optionally, the number of modulo-adder modules is the same as the number n of qubits of the first target quantum state; the number of the modulus multiplier modules is one less than the number n of the quantum bits of the first target quantum state; in the aspect of cascading the modulo adder module and the modulo multiplier module to generate a target quantum circuit corresponding to a modulo fast multiplier, the evolution unit 702 is specifically configured to:
And alternately cascading the n modulus adder modules and the n-1 modulus multiplier modules to generate a target quantum circuit corresponding to the modulus fast multiplier.
Optionally, the modulus adder module includes four input terms and four output terms, and the modulus multiplier module includes two input terms and two output terms; in the aspect of alternately cascading the n modulo adder modules and the n-1 modulo multiplier modules to generate a target quantum circuit corresponding to the modulo fast multiplier, the evolution unit 702 is specifically configured to:
taking two output items of the current modulus adder module as two input items of the current modulus multiplier module, and taking the other two output items of the current modulus adder and the two output items of the current modulus multiplier as four input items of the next modulus adder module;
and alternately cascading the n modulus adder modules and the n-1 modulus multiplier modules to generate a target quantum circuit corresponding to the modulus fast multiplier.
Optionally, the four input items of the modulus adder module include two quantum state input items to be operated, a modulus fast multiplication result input item and an auxiliary input item; the four output items of the modulus adder module comprise two quantum state output items to be operated, a first modulus rapid multiplication result output item and a first auxiliary output item;
The two input items of the modulus multiplier module comprise a first modulus fast multiplication result output item and a first auxiliary output item of the modulus adder module; the two output terms of the modulus multiplier module include a second modulus fast multiplication result output term and a second auxiliary output term.
Optionally, in terms of performing a modular fast multiplication operation on each qubit of the two first target quantum states through the target quantum circuit to generate a second target quantum state, the evolution unit 702 is specifically configured to:
preparing an input quantum state and an auxiliary input quantum state of a modulus rapid multiplication result;
Taking the two first target quantum states as the input of two quantum state input items to be operated, taking the input quantum state of the modulus rapid multiplication result as the input of the modulus rapid multiplication result input item, and taking the auxiliary input quantum state as the input of the auxiliary input item to obtain the target quantum circuit after the initial state is prepared;
And operating the target quantum circuit after the initial state is prepared, measuring quantum bits corresponding to the input quantum state of the modulus rapid multiplication result, and obtaining a second target quantum state.
A further embodiment of the invention provides a storage medium having a computer program stored therein, wherein the computer program is arranged to perform the steps of the method embodiment of any of the above-mentioned methods when run.
Specifically, in the present embodiment, the above-described storage medium may be configured to store a computer program for executing the steps of:
Acquiring two target data to be operated, and converting the two target data to be operated into two first target quantum states;
Performing quantum state evolution corresponding to modulus rapid multiplication operation on the two first target quantum states to obtain a second target quantum state of the evolved storage modulus rapid multiplication operation result;
And outputting the finally obtained second target quantum state as a modulus rapid multiplication operation result of the two target data to be operated.
Specifically, in the present embodiment, the storage medium may include, but is not limited to: a usb disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory RAM), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing a computer program.
Still another embodiment of the present invention provides an electronic device comprising a memory having a computer program stored therein and a processor configured to run the computer program to perform the steps of the method embodiment of any of the above.
Specifically, the electronic apparatus may further include a transmission device and an input/output device, where the transmission device is connected to the processor, and the input/output device is connected to the processor.
Specifically, in the present embodiment, the above-described processor may be configured to execute the following steps by a computer program:
Acquiring two target data to be operated, and converting the two target data to be operated into two first target quantum states;
Performing quantum state evolution corresponding to modulus rapid multiplication operation on the two first target quantum states to obtain a second target quantum state of the evolved storage modulus rapid multiplication operation result;
And outputting the finally obtained second target quantum state as a modulus rapid multiplication operation result of the two target data to be operated.
Yet another embodiment of the present invention provides a quantum modular arithmetic assembly comprising a quantum modular fast multiplier determined according to the method described in any of the preceding claims.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Claims (8)
1. A method of quantum modular rapid multiplication, the method comprising:
Acquiring two target data to be operated, and converting the two target data to be operated into two first target quantum states;
Taking two output items of a current modulus adder module as two input items of a current modulus multiplier module, taking the other two output items of the current modulus adder and the two output items of the current modulus multiplier as four input items of a next modulus adder module, and alternately cascading n modulus adder modules and n-1 modulus multiplier modules to generate a target quantum circuit corresponding to a modulus fast multiplier; the four input items of the modulus adder module comprise two quantum state input items to be operated, a modulus rapid multiplication result input item and an auxiliary input item; the four output items of the modulus adder module comprise two quantum state output items to be operated, a first modulus rapid multiplication result output item and a first auxiliary output item; the two input items of the modulus multiplier module comprise a first modulus fast multiplication result output item and a first auxiliary output item of the modulus adder module; the two output items of the modulus multiplier module comprise a second modulus fast multiplication result output item and a second auxiliary output item;
Performing modular rapid multiplication operation on each quantum bit of the two first target quantum states through the target quantum circuit to generate a second target quantum state;
And outputting the finally obtained second target quantum state as a modulus rapid multiplication operation result of the two target data to be operated.
2. The method of claim 1, wherein the method further comprises:
And acquiring the modulus adder module and the modulus multiplier module.
3. The method of claim 2, wherein the number of modulo-adder modules is the same as the number n of qubits of the first target quantum state; the number of the modulus multiplier modules is one less than the number n of qubits of the first target quantum state.
4. The method of claim 1, wherein said performing a modular fast multiplication operation on each qubit of two of said first target quantum states via said target quantum circuit to generate a second target quantum state comprises:
preparing an input quantum state and an auxiliary input quantum state of a modulus rapid multiplication result;
Taking the two first target quantum states as the input of two quantum state input items to be operated, taking the input quantum state of the modulus rapid multiplication result as the input of the modulus rapid multiplication result input item, and taking the auxiliary input quantum state as the input of the auxiliary input item to obtain the target quantum circuit after the initial state is prepared;
And operating the target quantum circuit after the initial state is prepared, measuring quantum bits corresponding to the input quantum state of the modulus rapid multiplication result, and obtaining a second target quantum state.
5. A quantum modular rapid multiplication apparatus, the apparatus comprising:
the device comprises an acquisition unit, a first quantum state generation unit and a second quantum state generation unit, wherein the acquisition unit is used for acquiring two target data to be operated and converting the two target data to be operated into two first target quantum states;
The evolution unit is used for taking two output items of the current modulus adder module as two input items of the current modulus multiplier module, taking the other two output items of the current modulus adder and the two output items of the current modulus multiplier as four input items of the next modulus adder module so as to realize the alternate cascade connection of n modulus adder modules and n-1 modulus multiplier modules and generate a target quantum circuit corresponding to the modulus fast multiplier; the four input items of the modulus adder module comprise two quantum state input items to be operated, a modulus rapid multiplication result input item and an auxiliary input item; the four output items of the modulus adder module comprise two quantum state output items to be operated, a first modulus rapid multiplication result output item and a first auxiliary output item; the two input items of the modulus multiplier module comprise a first modulus fast multiplication result output item and a first auxiliary output item of the modulus adder module; the two output items of the modulus multiplier module comprise a second modulus fast multiplication result output item and a second auxiliary output item; performing modular rapid multiplication operation on each quantum bit of the two first target quantum states through the target quantum circuit to generate a second target quantum state;
And the output unit is used for outputting the finally obtained second target quantum state as a modulus rapid multiplication result of the two target data to be operated.
6. A storage medium having a computer program stored therein, wherein the computer program is arranged to perform the method of any of claims 1 to 4 when run.
7. An electronic device comprising a memory and a processor, characterized in that the memory has stored therein a computer program, the processor being arranged to run the computer program to perform the method of any of the claims 1 to 4.
8. A quantum modular arithmetic assembly comprising a quantum modular fast multiplier determined according to the method of any one of claims 1 to 4.
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