CN115910797B - LDMOS device and manufacturing method thereof - Google Patents

Abstract

An LDMOS device and a method of manufacturing the same, the method comprising: providing a semiconductor substrate, and forming a gate structure on the semiconductor substrate; performing doping ion implantation of a first doping type on the semiconductor substrate to form a plurality of first source doped regions which are arranged at intervals on one side of the grid structure; forming an interlayer dielectric layer covering the semiconductor substrate; etching the interlayer dielectric layer and the semiconductor substrate to form a first contact hole between every two adjacent first source doped regions, wherein the bottom of the first contact hole is positioned inside the semiconductor substrate; and carrying out doped ion implantation of a second doping type on the first contact hole at a certain inclined angle to form a second source doped region, wherein the area of the second source doped region is larger than that of the first source doped region. The manufacturing method of the LDMOS device can enable the area of the second source doped region to be larger than that of the first source doped region, and improve the performance of the LDMOS device.

Description

LDMOS device and manufacturing method thereof

Technical Field

The invention relates to the technical field of semiconductors, in particular to an LDMOS device and a manufacturing method thereof.

Background

Compared with the conventional bipolar transistor, the lateral diffusion metal oxide semiconductor (Laterally Diffused Metal Oxide Semiconductor, LDMOS) device has better thermal stability and frequency stability, higher gain and durability, lower feedback capacitance and thermal resistance, constant input impedance and simpler bias current circuit, and thus is widely used.

Some LDMOS devices may form an N-type doped region and a P-type doped region alternately arranged at the source, and in theory, when the areas of the N-type doped region and the P-type doped region are different, the LDMOS device has better performance, but is limited by factors such as layout area, and the current N-type doped region and the P-type doped region are generally designed to have areas with the same size.

Disclosure of Invention

In the summary, a series of concepts in a simplified form are introduced, which will be further described in detail in the detailed description. The summary of the invention is not intended to define the key features and essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

In view of the existing problems, an aspect of an embodiment of the present invention provides a method for manufacturing an LDMOS device, including:

providing a semiconductor substrate, and forming a gate structure on the semiconductor substrate;

performing doping ion implantation of a first doping type on the semiconductor substrate to form a plurality of first source doped regions which are arranged at intervals on one side of the grid structure;

forming an interlayer dielectric layer covering the semiconductor substrate and the gate structure;

etching the interlayer dielectric layer and the semiconductor substrate to form a first contact hole between every two adjacent first source doped regions, wherein the bottom of the first contact hole is positioned inside the semiconductor substrate;

performing doped ion implantation of a second doping type on the first contact hole at a certain inclination angle to form a second source doped region, wherein the area of the second source doped region is larger than that of the first source doped region;

and filling conductive materials in the first contact holes.

In some embodiments, a drain doped region is also formed on the other side of the gate structure when the semiconductor substrate is subjected to the doping example implantation of the first doping type.

In some embodiments, after forming the interlayer dielectric layer and before forming the first contact hole, the method further comprises:

forming a second contact hole in the interlayer dielectric layer, wherein the second contact hole is in contact with the drain doped region;

and filling conductive materials in the second contact holes.

In some embodiments, a distance between two adjacent first source doped regions is less than or equal to a width of the first source doped regions.

In some embodiments, the etching the interlayer dielectric layer and the semiconductor substrate to form a first contact hole between each adjacent two of the first source doping regions includes:

forming a patterned photoresist layer on the interlayer dielectric layer, wherein a window of the photoresist layer corresponds to a position between every two adjacent first source doping regions;

etching the interlayer dielectric layer and the semiconductor substrate by taking the photoresist layer as a mask to form the first contact hole;

after forming the first contact hole, the method further includes: and removing the photoresist layer.

In some embodiments, after performing the doping ion implantation of the second doping type on the first contact hole at a certain inclination angle, the method further includes:

a rapid thermal annealing process is performed to diffuse dopant ions of the second doping type implanted into the semiconductor substrate.

In some embodiments, the ratio of the area of the second source doped region to the area of the first source doped region is not less than 2.

In some embodiments, the tilt angle is between 30 ° and 60 °.

Another aspect of the embodiments of the present invention provides an LDMOS device, including:

a semiconductor substrate;

a gate structure on the semiconductor substrate;

a plurality of first source doped regions and a plurality of second source doped regions in the semiconductor substrate at one side of the gate structure, the first source doped regions and the second source doped regions being alternately arranged, the first source doped regions having a first doping type, the second source doped regions having a second doping type, the second source doped regions being located lower than the first source doped regions, and the second source doped regions having an area larger than the first source doped regions;

an interlayer dielectric layer covering the semiconductor substrate and the gate structure;

the first contact hole is connected with the second source electrode doping region, penetrates through the interlayer dielectric layer, the bottom of the first contact hole is located inside the semiconductor substrate, and conductive materials are filled in the first contact hole.

In some embodiments, the semiconductor device further comprises:

and a drain doped region in the semiconductor substrate on the other side of the gate structure, the drain doped region having the first doping type.

In some embodiments, the semiconductor device further comprises:

and the second contact hole is connected with the drain electrode doping region, penetrates through the interlayer dielectric layer, is flush with the surface of the semiconductor substrate, and is filled with conductive materials.

According to the manufacturing method of the LDMOS device and the LDMOS device, the second source doped region is formed below the first source doped region, so that the area of the second source doped region is increased under the condition that the layout area of the LDMOS device is not increased, and the performance of the LDMOS device is improved.

Drawings

The following drawings are included to provide an understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and their description to explain the principles of the invention.

Fig. 1A and 1B are schematic diagrams of an LDMOS device in the prior art;

fig. 2 is a schematic flow chart of a method for manufacturing an LDMOS device according to an embodiment of the present invention;

fig. 3A to 3F are schematic cross-sectional views showing a semiconductor device obtained by sequentially performing steps in a method for manufacturing an LDMOS device according to an embodiment of the present invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without one or more of these details. In other instances, well-known features have not been described in detail in order to avoid obscuring the invention.

It should be understood that the present invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size of layers and regions, as well as the relative sizes, may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Referring to fig. 1A and 1B, a prior art ldo ms device is shown. In the LDMOS device shown in fig. 1A and 1B, an N-type drain doped region is formed in an N-type drift region (NDR), and P-type doped regions and N-type doped regions are alternately formed in a P-type body region (PB), and the ratio of the area A1 of the conventional P-type doped region to the area A2 of the N-type doped region is generally 1:1, but this is often a compromise due to layout area limitations and device performance limitations (e.g., SOA (safe operating area) and TLP (transmission line pulse), etc.), not an optimal design.

In the following description, for the purpose of providing a thorough understanding of the present invention, detailed structures and steps are presented in order to illustrate the technical solution presented by the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments in addition to these detailed descriptions.

Fig. 2 is a flowchart showing steps of a method of fabricating an LDMOS device according to an embodiment of the invention; fig. 3A to 3F are schematic cross-sectional views of a semiconductor device obtained by sequentially performing steps in a method for manufacturing an LDMOS device according to an embodiment of the invention. The following describes a method for fabricating an LDMOS device according to an embodiment of the invention in detail with reference to fig. 2 and fig. 3A to 3F.

First, referring to fig. 2, a method for manufacturing an LDMOS device according to an embodiment of the invention is described, and as shown in fig. 2, a method 200 for manufacturing an LDMOS device according to an embodiment of the invention includes the following steps:

providing a semiconductor substrate and forming a gate structure on the semiconductor substrate in step S201;

in step S202, a first doping type doping ion implantation is performed on the semiconductor substrate, so as to form a plurality of first source doped regions arranged at intervals on one side of the gate structure;

forming an interlayer dielectric layer covering the semiconductor substrate and the gate structure at step S203;

in step S204, the interlayer dielectric layer and the semiconductor substrate are etched to form a first contact hole between every two adjacent first source doped regions, wherein the bottom of the first contact hole is located inside the semiconductor substrate;

in step S205, performing a second doping type doping ion implantation on the first contact hole at a certain inclination angle to form a second source doping region, where the area of the second source doping region is larger than that of the first source doping region;

in step S206, a conductive material is filled in the first contact hole.

According to the manufacturing method 200 of the LDMOS device provided by the embodiment of the invention, the first contact hole penetrating into the semiconductor substrate is formed, and the first contact hole is subjected to inclined ion implantation to form the second source doped region, so that the area of the second source doped region is increased under the condition that the whole layout area of the LDMOS device is not increased, and the performance of the LDMOS device is improved.

An exemplary implementation of a method of fabricating an LDMOS device according to an embodiment of the invention is described below with reference to fig. 3A to 3F.

First, referring to fig. 3A, a semiconductor substrate 300 is provided, including but not limited to at least one of the following materials: silicon (Si), germanium (Ge), germanium silicon (SiGe), carbon Silicon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III/V compound semiconductors, or ceramic substrates such as silicon on dielectric (SOI), silicon on dielectric stack (SSOI), silicon germanium on dielectric stack (S-SiGeOI), silicon germanium on dielectric (SiGeOI) and germanium on dielectric (GeOI), or double-sided polished silicon wafers (Double Side Polished Wafers, DSP), aluminum oxide and the like, quartz or glass substrates, and the like.

Illustratively, a body region and a drift region plasma implant region are formed in the semiconductor substrate. Wherein the doping types of the body region and the drift region are different. For an N-type LDMOS device, P-type doping ions are doped in a body region, and N-type doping ions are doped in a drift region; for a P-type LDMOS device, N-type dopant ions are doped in the body region and P-type dopant ions are doped in the drift region. The N-type doping ions include, for example, phosphorus ions, arsenic ions, antimony ions, and the like; the P-type dopant ions include, for example, boron ions, indium ions, gallium ions, and the like.

The gate structure 303 formed on the semiconductor substrate 300 includes a gate dielectric layer, a gate electrode layer and a gate sidewall, and spans over the surfaces of the body region and the drift region. The surface of the semiconductor substrate 300 covered by the gate structure 303 is used to form a channel.

Specifically, the step of forming the gate structure 303 includes: first, a gate dielectric layer is formed on a semiconductor substrate 300; then, a gate electrode layer is formed to cover the gate dielectric layer. Wherein the gate dielectric layer is used to isolate the semiconductor substrate 300 from the gate electrode layer, the gate dielectric layer may be formed by a deposition process, such as a chemical vapor deposition process, and the gate dielectric layer may be formed by an oxidation process; the material of the gate dielectric layer includes silicon oxide or high-K dielectric material, such as HfO2, tiO2, hfZrO, hfSiNO, etc. The gate electrode layer is formed by a deposition process, such as a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or the like; the material of the gate electrode layer may be polysilicon or metal. Illustratively, after etching the gate dielectric layer and the gate electrode layer, forming a gate sidewall on sidewalls of the gate dielectric layer and the gate electrode layer, wherein the gate sidewall protects sidewalls of the gate structure from being damaged by ion implantation during subsequent formation of the source and the drain. The gate sidewall may have a single-layer or multi-layer structure, and the material of the gate sidewall includes silicon oxide, silicon nitride or other suitable materials.

Next, a first doping type doping ion implantation is performed on the semiconductor substrate 300 to form a plurality of first source doping regions 301 arranged at intervals at one side of the gate structure. In some embodiments, the first doping type is N-type, i.e. the first source doping region 301 has N-type doping ions, and correspondingly the subsequent second doping type is P-type. In further embodiments, the first doping type is P-type and the subsequent second doping type is N-type.

In some embodiments, the doping type of the drain doping region 302 is the same as that of the first source doping region 301, so that when the semiconductor substrate 300 is doped with the doping example of the first doping type, the drain doping region 302 is also formed on the other side of the gate structure 303, thereby forming the first source doping region 301 and the drain doping region 302 simultaneously through the same ion implantation process, and simplifying the process flow.

With continued reference to fig. 3A, after forming the first source doped region 301, the drain doped region 302, and the gate structure 303, an interlayer dielectric layer 304 is formed overlying the semiconductor substrate 300 and the gate structure 303. The material of the interlayer dielectric layer 304 may be a silicon oxide layer, and specifically may include a doped or undoped silicon oxide material layer formed by a thermal chemical vapor deposition process or a high-density plasma process.

In some embodiments, after forming the interlayer dielectric layer 304, the interlayer dielectric layer 304 is etched to form a second contact hole 305 contacting the drain doped region 302, and then a conductive material is filled in the second contact hole 305 for electrically connecting with the drain doped region 302, wherein the conductive material includes a metal material such as tungsten, nickel, titanium, and the like. The etching may be an anisotropic dry etching, such as reactive ion etching, ion beam etching, plasma etching, or laser ablation. Since the drain doped region 302 is formed by directly performing ion implantation on the surface of the semiconductor substrate 300, the semiconductor substrate 300 may be used as an etching stop layer when the second contact hole 305 is etched.

Next, referring to fig. 3C, the interlayer dielectric layer 304 and the semiconductor substrate 300 are etched to form first contact holes 307 between every adjacent two of the first source doping regions 301, the bottoms of the first contact holes 307 being located inside the semiconductor substrate 300, i.e., the first contact holes 307 include portions located in the interlayer dielectric layer 304 and portions located in the semiconductor substrate 300, the depth of which is greater than the thickness of the interlayer dielectric layer 304. Further, the bottom of the first contact hole 307 is not higher than the bottom of the first source doped region 301, so as to ensure that the doped ions implanted into the first contact hole 307 have a sufficient depth.

Illustratively, as shown in fig. 3B, the step of forming the first contact hole 307 specifically includes: forming a patterned photoresist layer 306 on the interlayer dielectric layer 304, wherein a window of the photoresist layer 306 corresponds to a position between every two adjacent first source doped regions 301; the interlayer dielectric layer 304 and the semiconductor substrate 300 are etched using the photoresist layer 306 as a mask to form the first contact hole 307, and the etching may be anisotropic dry etching, for example, reactive ion etching, ion beam etching, plasma etching, or laser ablation. After the first contact hole 307 is formed, the photoresist layer 306 may be removed using a photoresist ashing or the like process.

Referring to fig. 3D, after forming the first contact hole 307, a second doping type doping ion implantation is performed on the first contact hole 307 at a certain inclination angle to form a second source doping region 308, and the area of the second source doping region 308 is larger than that of the first source doping region 301. In the embodiment of the present invention, a certain inclination angle is adopted when the first contact hole 307 is doped with ions, that is, the inclination angle (that is, the included angle between the direction of ion implantation and the normal direction of the semiconductor substrate) is greater than 0 °, and the implantation area is greater than the cross-sectional area of the first contact hole 307 by adopting a certain inclination angle to perform ion implantation. In some embodiments, the tilt angle may be between 30 ° and 60 °, further, the tilt angle may be greater than or equal to 45 °, to increase the implantation area.

It should be noted that, in the embodiment of the present invention, the area of the first source doped region 301 refers to the area of the first source doped region 301 in the horizontal direction parallel to the surface of the semiconductor substrate, and specifically includes, but is not limited to, the maximum area or the average area in the horizontal direction. The area of the second source doped region 308 in the embodiment of the present invention refers to the area of the second source doped region 308 in the horizontal direction parallel to the surface of the semiconductor substrate, and specifically includes, but is not limited to, the maximum area or the average area in the horizontal direction.

Illustratively, after the first contact hole 307 is subjected to the second doping type doping ion implantation at a certain inclination angle, a Rapid Thermal Annealing (RTA) process may be performed to diffuse the second doping type doping ion implanted into the semiconductor substrate 300. The rapid thermal annealing process also enables recovery of the single crystal structure to eliminate damage to the semiconductor substrate 300 caused by ion implantation. The area of the second source doped region 308 may refer to the area of the second source doped region 308 after the rapid thermal annealing process.

Theoretically, when the area of the second source doped region 308 is larger than that of the first source doped region 301, the LDMOS device has better performance, but in the past, both the first source doped region 301 and the second source doped region 308 are formed on the surface of the semiconductor substrate 300, which is limited by factors such as layout area, and it is difficult to reduce the area of the first source doped region 301 to increase the area of the second source doped region 308. In contrast, in the embodiment of the present invention, a three-dimensional structure is adopted, and the area of the second source doped region 308 can be increased more flexibly by forming the first contact hole 307 penetrating into the semiconductor substrate 300 and performing the inclined ion implantation on the first contact hole 307, so that the second source doped region 308 is formed under the first source doped region 301.

Illustratively, the ratio of the area A2 of the second source doped region 308 to the area A1 of the first source doped region 301 is not less than 2, thereby achieving enhancement of the LDMOS device pick up, SOA (safe operating area), TLP (transmission line pulse) and the like. Further, the ratio of the area of the second source doped region 308 to the area of the first source doped region 301 may be 3:1.

in some embodiments, referring to fig. 3E and 3F, the distance between two adjacent first source doped regions 301 is less than or equal to the width of the first source doped regions 301, and the width of the first source doped regions 301 refers to the width of the first source doped regions 301 in a first direction, where the first direction is the direction in which the first source doped regions 301 and the second source doped regions 308 are alternately arranged. Because the second source doped region 308 is below the first source doped region 301 in the embodiment of the present invention, the distance between adjacent first source doped regions 301 cannot limit the area of the second source doped region 308, so that the distance between two adjacent first source doped regions 301 can be properly reduced to increase the width of the first source doped region 301 while increasing the area of the second source doped region 308, thereby further improving the device performance.

With continued reference to fig. 3E, after the second source doped region 308 is formed, the first contact hole 307 is filled with a conductive material for electrical connection with the second source doped region 308, the conductive material including a metal material such as tungsten, nickel, titanium, or the like. After filling the conductive material, a chemical mechanical polishing process may be performed such that the top of the conductive material is flush with the top of the first contact hole 307.

Thus far, the process steps performed by the method for manufacturing an LDMOS device according to an embodiment of the invention are completed, and it will be understood that the method for manufacturing a semiconductor device according to the present embodiment may include not only the above steps, but also other steps as needed before, during or after the above steps, which are included in the scope of the method for manufacturing the LDMOS device according to the present embodiment.

According to the manufacturing method of the LDMOS device, the second source doped region is formed below the first source doped region, so that the area of the second source doped region is increased under the condition that the layout area of the LDMOS device is not increased, and the performance of the LDMOS device is improved.

As shown in fig. 3E, an embodiment of the present invention further provides an LDMOS device, which may be manufactured by using the method 200 for manufacturing an LDMOS device as described above.

Specifically, the LDMOS device of the embodiment of the invention comprises: a semiconductor substrate 300; a gate structure 303 located on the semiconductor substrate 300; a plurality of first source doped regions 301 and a plurality of second source doped regions 308 in the semiconductor substrate at one side of the gate structure 303, the first source doped regions 301 and the second source doped regions 308 being alternately arranged, the first source doped regions 301 having a first doping type, the second source doped regions 308 having a second doping type, the second source doped regions 308 being located at a lower position than the first source doped regions 301, and the second source doped regions 308 having an area larger than that of the first source doped regions 301; an interlayer dielectric layer 304 covering the semiconductor substrate 300 and the gate structure 303; the first contact hole 307 connected to the second source doped region 308, the first contact hole 307 penetrates through the interlayer dielectric layer 304, the bottom of the first contact hole 307 is located inside the semiconductor substrate 300, and the first contact hole 307 is filled with a conductive material.

The first doping type is N type, the second doping type is P type, or the first doping type is P type, and the second doping type is N type.

In some embodiments, the LDMOS device further comprises a drain doped region 302 in the semiconductor substrate 300 on the other side of the gate structure 303, the drain doped region 302 having a first doping type. The semiconductor device further comprises a second contact hole 305 connected with the drain doped region 302, the second contact hole 305 penetrates through the interlayer dielectric layer 304, the bottom of the second contact hole 305 is flush with the surface of the semiconductor substrate 300, and the second contact hole 305 is filled with conductive material.

In some embodiments, the ratio of the area of the second source doped region 308 to the area of the first source doped region 301 is not less than 2.

According to the LDMOS device provided by the invention, the second source doped region is formed below the first source doped region, so that the area of the second source doped region is increased under the condition that the layout area of the LDMOS device is not increased, and the performance of the LDMOS device is improved. For more details of the LDMOS device according to the embodiment of the invention, reference may be made to the above description of the method for manufacturing the LDMOS device, which is not repeated here.

The present invention has been illustrated by the above-described embodiments, but it should be understood that the above-described embodiments are for purposes of illustration and description only and are not intended to limit the invention to the embodiments described. In addition, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications are possible in light of the teachings of the invention, which variations and modifications are within the scope of the invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims (10)

1. A method of fabricating an LDMOS device, the method comprising:

providing a semiconductor substrate, and forming a gate structure on the semiconductor substrate;

performing doping ion implantation of a first doping type on the semiconductor substrate to form a plurality of first source doping regions which are arranged at intervals along the extending direction of the gate structure on one side of the gate structure;

forming an interlayer dielectric layer covering the semiconductor substrate and the gate structure;

etching the interlayer dielectric layer and the semiconductor substrate to form a first contact hole between every two adjacent first source doped regions, wherein the bottom of the first contact hole is positioned inside the semiconductor substrate;

performing doping ion implantation of a second doping type on the first contact hole at a certain inclination angle to form a second source doping region, wherein the area of the second source doping region is larger than that of the first source doping region, and the top of the second source doping region is positioned below the top of the first source doping region;

and filling conductive materials in the first contact holes.

2. The method of manufacturing of claim 1, wherein a drain doped region is also formed on the other side of the gate structure when the semiconductor substrate is subjected to the first doping type of dopant ion implantation.

3. The method of manufacturing of claim 2, wherein after forming the interlayer dielectric layer and before forming the first contact hole, the method further comprises:

forming a second contact hole in the interlayer dielectric layer, wherein the second contact hole is in contact with the drain doped region;

and filling conductive materials in the second contact holes.

4. The method of manufacturing of claim 1, wherein a distance between two adjacent first source doped regions is less than or equal to a width of the first source doped regions.

5. The method of manufacturing of claim 1, wherein said etching said interlayer dielectric layer and said semiconductor substrate to form a first contact hole between each adjacent two of said first source doped regions comprises:

forming a patterned photoresist layer on the interlayer dielectric layer, wherein a window of the photoresist layer corresponds to a position between every two adjacent first source doping regions;

etching the interlayer dielectric layer and the semiconductor substrate by taking the photoresist layer as a mask to form the first contact hole;

after forming the first contact hole, the method further includes: and removing the photoresist layer.

6. The method of manufacturing of claim 1, wherein after performing the second doping type doping ion implantation at an oblique angle to the first contact hole, the method further comprises:

a rapid thermal annealing process is performed to diffuse dopant ions of the second doping type implanted into the semiconductor substrate.

7. The method of manufacturing of claim 1, wherein a ratio of an area of the second source doped region to an area of the first source doped region is greater than or equal to 2.

8. The method of manufacturing according to claim 1, wherein the tilt angle is between 30 ° and 60 °.

9. An LDMOS device manufactured by the method of any of claims 1-8, the LDMOS device comprising:

a semiconductor substrate;

a gate structure on the semiconductor substrate;

a plurality of first source doped regions and a plurality of second source doped regions in the semiconductor substrate at one side of the gate structure, the first source doped regions and the second source doped regions being alternately arranged along the extending direction of the gate structure, the first source doped regions having a first doping type, the second source doped regions having a second doping type, the second source doped regions being located at a lower position than the first source doped regions, and the second source doped regions having an area larger than that of the first source doped regions;

an interlayer dielectric layer covering the semiconductor substrate and the gate structure;

the first contact hole is connected with the second source electrode doping region, penetrates through the interlayer dielectric layer, the bottom of the first contact hole is located inside the semiconductor substrate, and conductive materials are filled in the first contact hole.

10. The LDMOS device of claim 9, further comprising:

a drain doped region in the semiconductor substrate on the other side of the gate structure, the drain doped region having the first doping type;

and the second contact hole is connected with the drain electrode doping region, penetrates through the interlayer dielectric layer, is flush with the surface of the semiconductor substrate, and is filled with conductive materials.

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