CN115939192B - Semiconductor device with high-K metal gate structure and manufacturing method thereof - Google Patents
Semiconductor device with high-K metal gate structure and manufacturing method thereofInfo
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Abstract
The invention provides a semiconductor device with a high-K metal gate structure and a manufacturing method thereof, comprising the following steps of providing a semiconductor layer comprising a gate dielectric layer, a bottom barrier layer and a grid side wall, wherein the bottom barrier layer is positioned on the gate dielectric layer to enclose an accommodating space with an opening at the top, and the bottom wall and the side wall of the accommodating space form corners; forming a P-type work function metal side wall at a corner, forming a P-type work function layer covering the P-type work function metal side wall on the bottom wall and the side wall of the accommodating space, and sequentially forming an N-type work function layer, a top barrier layer and a metal layer in the accommodating space, wherein the N-type work function layer covers the P-type work function layer and is separated from the metal layer by the top barrier layer. The method can effectively improve the aluminum diffusion effect in the N-type work function layer, and improves the performance stability, the product yield and the reliability evaluation of the device. The invention also provides a semiconductor device with the high-K metal gate structure, and the device has better performance stability and reliability.
Description
Technical Field
The invention belongs to the field of integrated circuit production and manufacturing, and relates to a semiconductor device with a high-K metal gate structure and a manufacturing method thereof.
Background
The main semiconductor device of integrated circuits, especially very large scale integrated circuits, is a Metal-Oxide-semiconductor field effect transistor (MOSFET) for short. With the continuous development of integrated circuit fabrication technology, the technology nodes of semiconductor devices are continuously reduced, and the geometric dimensions of semiconductor devices are continuously reduced according to moore's law. As semiconductor device dimensions decrease to some extent, various secondary effects due to physical limitations of the semiconductor device continue to occur, and scaling down the feature sizes of the semiconductor device becomes increasingly difficult. Among them, in the field of semiconductor fabrication, how to solve the problem of large leakage current of semiconductor devices is the most challenging. The high leakage current of the semiconductor device is mainly caused by the continuous reduction of the thickness of the traditional gate dielectric layer.
With the development of semiconductor technology, a gate structure of a semiconductor device with a High-process node generally adopts a High-K material to replace a traditional silicon dioxide material as a gate dielectric layer, and adopts metal as a gate electrode, so that a High-K metal gate (High-K METAL GATE, abbreviated as HKMG) structure is formed by superposition to avoid the fermi level pinning effect and the boron penetration effect of the High-K material and the traditional gate electrode material, thereby reducing the leakage current of the semiconductor device. In HKMG, a work function layer is required, an N-type semiconductor device uses an N-type work function layer such as TiAl, and the work function of the N-type work function layer is close to the conduction band of a semiconductor substrate such as a silicon substrate, which is beneficial to reducing the threshold voltage of the N-type semiconductor device, and a P-type semiconductor device uses a P-type work function layer such as TiN, and the work function of the P-type work function layer is close to the valence band of the semiconductor substrate such as the silicon substrate, which is beneficial to reducing the threshold voltage of the P-type semiconductor device, i.e., the absolute value of the threshold voltage.
Referring to fig. 1, a schematic cross-sectional structure of a semiconductor device having a high-K metal gate structure in the prior art is shown, in which during the formation of a conventional P-type work function layer (titanium nitride layer), the titanium nitride deposition process behavior may cause corners in the titanium nitride layer 1, and if Al is included in other layers deposited on the layer, in the subsequent production process, a high-temperature process environment may cause an aluminum diffusion effect, that is, the Al element in other structural layers deposited on the titanium nitride layer may diffuse into the structural layers (such as the dielectric layer 2) below the titanium nitride layer 1 along the arrows at the corners as shown in fig. 1, so that the effective work function of the dielectric layer may severely drift, which may cause abnormal increase of the threshold voltage of the PMOS device, decrease the control capability of the device, cause serious degradation of the electrical performance of the device, and even produce product yield loss and related reliability evaluation.
Therefore, how to provide a semiconductor device with a high-K metal gate structure and a method for manufacturing the same, so as to improve the structure of the conventional P-type work function at the weak corner caused by depositing titanium nitride, thereby avoiding the aluminum diffusion effect possibly generated to stabilize the performance of the P-type device, and improving the product yield and the related reliability evaluation, which is an important technical problem to be solved by those skilled in the art.
It should be noted that the foregoing description of the background art is only for the purpose of providing a clear and complete description of the technical solution of the present application and is presented for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background of the application section.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an objective of the present invention is to provide a semiconductor device with a high-K metal gate structure and a method for fabricating the same, which are used for solving the problems of poor corner caused by the formation of a P-type work function layer, deposition on the P-type work function layer and the occurrence of aluminum diffusion effect due to a high-temperature process environment in the subsequent production process if Al is included in other layers, thereby affecting the performance of the P-type device, and even producing yield loss and related reliability evaluation.
To achieve the above and other related objects, the present invention provides a method for fabricating a semiconductor device having a high-K metal gate structure, comprising the steps of:
providing a semiconductor layer, wherein the semiconductor layer comprises a gate dielectric layer, a bottom barrier layer and grid side walls, the bottom barrier layer is positioned on the gate dielectric layer, the grid side walls are positioned on two sides of the gate dielectric layer and the bottom barrier layer, the bottom barrier layer encloses an accommodating space with an opening at the top, and the bottom wall and the side walls of the accommodating space form corners;
forming a P-type work function metal side wall at the corner;
forming a P-type work function layer covering the P-type work function metal side wall on the bottom wall and the side wall of the accommodating space;
and forming an N-type work function layer, a top barrier layer and a metal layer in the accommodating space in sequence, wherein the N-type work function layer covers the P-type work function layer, and the N-type work function layer and the metal layer are separated by the top barrier layer.
Optionally, the method for forming the P-type work function metal side wall comprises the steps of depositing a P-type work function metal conformal layer in the accommodating space, and etching back the P-type work function metal conformal layer until a part of side wall and a part of bottom wall of the accommodating space are exposed, wherein the P-type work function metal conformal layer remained in the accommodating space forms the P-type work function metal side wall.
Optionally, the gate dielectric layer includes a stacked interface layer and a high-K dielectric layer, and the high-K dielectric layer is located above the interface layer.
Optionally, the material of the interface layer includes at least one of SiO 2 and SiON, and the material of the high-K dielectric layer includes at least one of HfO 2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、ZrO2 and Al 2O3.
Optionally, the bottom barrier layer includes a first bottom barrier layer and a second bottom barrier layer, where the second bottom barrier layer is located above the first bottom barrier layer, and the accommodating space is located in the second bottom barrier layer.
Optionally, the material of the first bottom barrier layer includes at least one of TiN and TaN, and the material of the second bottom barrier layer includes at least one of TiN and TaN.
Optionally, the material of the P-type work function layer comprises at least one of TiN and TaN, the material of the N-type work function layer comprises at least one of TiAl, tiAlC, tiAlN and AlN, the material of the P-type work function metal side wall comprises at least one of TiN and TaN, the material of the metal layer comprises at least one of Al, cu, ag, W and Ni, the gate side wall structure comprises a single-layer or laminated structure, and the material of the gate side wall comprises at least one of SiO2, siN and SiON.
Optionally, the exposed surface of the P-type work function metal side wall is a convex surface.
The invention also provides a semiconductor device with a high-K metal gate structure, comprising:
The semiconductor layer comprises a gate dielectric layer, a bottom barrier layer and a grid side wall, wherein the bottom barrier layer is positioned on the gate dielectric layer, the grid side wall is positioned on two sides of the gate dielectric layer and the bottom barrier layer, the bottom barrier layer encloses an accommodating space with an opening at the top, and the bottom wall and the side wall of the accommodating space form corners;
The P-type work function metal side wall is positioned at the corner;
the P-type work function layer is positioned on the bottom wall and the side wall of the accommodating space and covers the P-type work function metal side wall;
The N-type work function layer is positioned in the accommodating space and covers the P-type work function layer;
the top barrier layer is positioned in the accommodating space and covers the N-type work function layer;
And the metal layer is positioned in the accommodating space and covers the top barrier layer.
Optionally, the surface of the P-type work function metal side wall facing to one side of the P-type work function layer is a convex surface.
As described above, the manufacturing method of the semiconductor device with the high-K metal gate structure changes the structural morphology of the P-type work function layer by forming the P-type work function metal side wall before forming the P-type work function layer, overcomes the structural defect of weak corners caused by the deposition behavior of the P-type work function material in the traditional P-type work function layer forming process, effectively avoids the aluminum diffusion effect of the N-type work function layer formed subsequently under the subsequent high-temperature process condition, and remarkably improves the product yield while improving the performance stability and the reliability of the device. The semiconductor device with the high-K metal gate structure has the advantages that the P-type work function metal side wall structure is arranged in the structure, so that the aluminum diffusion effect under the high-temperature condition is effectively avoided, and the semiconductor device with the high-K metal gate structure has excellent device performance stability and use reliability.
Drawings
Fig. 1 is a schematic cross-sectional view showing a semiconductor device having a high-K metal gate structure according to the prior art.
Fig. 2 is a flow chart showing the steps of a method for fabricating a semiconductor device having a high-K metal gate structure according to the present invention.
Fig. 3 is a schematic cross-sectional view showing a structure obtained after step S1 is performed in the method for fabricating a semiconductor device having a high-K metal gate structure according to the present invention.
Fig. 4 is a schematic cross-sectional view of a semiconductor device having a high-K metal gate structure and a method for fabricating the same according to the present invention after step S2 is performed.
Fig. 5 is a schematic cross-sectional view of a semiconductor device having a high-K metal gate structure and a method for fabricating the same according to the present invention after step S3 is performed.
Fig. 6 is a schematic cross-sectional view showing the structure obtained after step S4 is performed in the method for manufacturing a semiconductor device having a high-K metal gate structure according to the present invention.
Description of element reference numerals
1. Titanium nitride layer
2. Dielectric layer
3. Gate dielectric layer
31. Interfacial layer
32. High-K dielectric layer
4. Bottom barrier layer
41. First bottom barrier layer
42. Second bottom barrier layer
5. Grid side wall
6. Accommodation space
7. Corner
8P work function metal side wall
9P work function layer
10 N-type work function layer
11. Top barrier layer
12. Metal layer
S1-S4 step
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 2 to fig. 6. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Example 1
The embodiment provides a method for manufacturing a semiconductor device with a high-K metal gate structure, please refer to fig. 2, which shows a step flowchart of the method, including steps S1 to S4.
Referring to fig. 3, step S1 is performed to provide a semiconductor layer, where the semiconductor layer includes a gate dielectric layer 3, a bottom barrier layer 4 and a gate sidewall 5, the bottom barrier layer 4 is located on the gate dielectric layer 3, the gate sidewall 5 is located on two sides of the gate dielectric layer 3 and the bottom barrier layer 4, the bottom barrier layer 4 encloses a top-opened accommodating space 6, and corners 7 are formed on the bottom wall and the sidewall of the accommodating space 6.
As an example, the semiconductor layer further includes a substrate layer (not labeled in the figure), the gate dielectric layer 2 is located above the substrate layer, the material of the substrate layer includes at least one of Si, ge, siGe, siC and GaIn, and the substrate layer may also be a Si substrate or a Ge substrate on an insulator.
The method for forming the accommodating space 6 includes the steps of forming a polysilicon gate, wherein the polysilicon gate comprises a polysilicon layer and a gate sidewall 5 positioned on the side surface of the polysilicon layer, removing at least a part of the polysilicon layer to form a groove, sequentially forming the gate dielectric layer 3 and the bottom barrier layer 4 at the bottom of the groove from bottom to top, and etching at least a part of the bottom barrier layer 4 to form the accommodating space 6.
As an example, the gate dielectric layer 3 includes an interfacial layer 31 and a high-K dielectric layer 32 stacked, and the high-K dielectric layer 32 is located above the interfacial layer 31.
As an example, the material of the interfacial layer 31 includes at least one of SiO 2 and SiON, and the function of the interfacial layer 31 includes that the interfacial layer 31 and the subsequently formed high-K dielectric layer 32 may form a stacked structure, and the stacked structure forms the gate dielectric layer 3, and the interfacial layer 31 further provides a good interface foundation for the subsequently formed high-K dielectric layer 32 to improve the quality of forming the high-K dielectric layer 32, reduce the interface state density between the high-K dielectric layer 32 and the substrate layer, and avoid adverse effects caused by direct contact between the high-K dielectric layer 32 and the substrate layer. The thickness of the interfacial layer 31 is set reasonably based on practical requirements, and the structural and performance requirements of the device are required to be met. The interfacial layer 31 may be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or oxidation, and in this embodiment, it is preferably formed by thermal oxidation, so as to improve the interfacial properties between the interfacial layer 31 and the high-K dielectric layer 32.
As an example, the material of the high-K dielectric layer 32 includes HfO 2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、ZrO2 or Al 2O3. Other high-K dielectric materials may be used for the high-K dielectric layer 32, and the high-K dielectric material refers to a gate dielectric material having a relative dielectric constant greater than that of silicon oxide. The high-K dielectric layer 32 may be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In addition, the thickness of the high-K dielectric layer 32 is in the range of 5 to 15 angstroms.
As an example, the bottom barrier layer 4 includes a first bottom barrier layer 41 and a second bottom barrier layer 42 stacked, the second bottom barrier layer 42 is located above the first bottom barrier layer 41, and the accommodating space 6 is located in the second bottom barrier layer 42.
As an example, the material of the first bottom barrier layer 41 includes at least one of TiN and TaN, and the material of the second bottom barrier layer 42 includes at least one of TiN and TaN. The material of the second bottom barrier layer 42 may be the same or different from the material of the first bottom barrier layer 41, and in this embodiment, the material of the first bottom barrier layer 41 is TiN, and the material of the second bottom barrier layer 42 is TaN. When the first bottom blocking layer 41 and the bottom second bottom blocking layer 42 function to form the P-type work function layer 9 in the opening later, metal ions in the P-type work function layer 9 may diffuse into the high-K dielectric layer 32 at high temperature, and protect the high-K dielectric layer 32 so that the high-K dielectric layer 32 maintains good performance, and the second bottom blocking layer 42 also can avoid metal ions from diffusing into the gate sidewall 5, so as to ensure that the work function value of the P-type work function layer 9 is not affected.
As an example, the gate sidewall 5 structure includes a single layer or a stacked layer structure, and the material of the gate sidewall 5 includes at least one of SiO 2, siN and SiON, and in this embodiment, the gate sidewall is a stacked layer structure.
Referring to fig. 4, step S2 is performed to form a P-type work function metal sidewall 8 at the corner 7, where the P-type work function metal sidewall has a function of avoiding damage to device performance caused by diffusion of easily-diffused ions in the P-type work function layer into the high-K dielectric layer 32 under high temperature conditions due to weakness at the corner 7 caused by self-deposition characteristics of the material of the P-type work function layer 9 when the P-type work function layer 9 is formed later, wherein the specifications of the P-type work function metal sidewall 8 are reasonably set based on practical conditions.
As an example, the exposed surface of the P-type work function metal sidewall 8 is a convex surface. In practical application, the morphology of the P-type work function metal side wall 8 is not limited to the foregoing morphology, and may be a convex morphology, a concave morphology or a flush morphology, so long as the morphology of the P-type work function metal side wall 8 can make up for the structural defect at the weak corner generated when the P-type work function layer is deposited in the prior art, so that the thickness of the P-type work function layer in the corner region is not smaller than the thickness of the P-type work function layer in the non-corner region, and the occurrence of aluminum diffusion effect can be avoided, which is preferably a convex morphology in the embodiment.
As an example, the method for forming the P-type work function metal sidewall 8 includes depositing a P-type work function metal conformal layer (not shown) in the accommodating space 6, and etching back the P-type work function metal conformal layer until a portion of the sidewall and a portion of the bottom wall of the accommodating space 6 are exposed, wherein the remaining P-type work function metal conformal layer in the accommodating space 6 forms the P-type work function metal sidewall 8, and the etching method includes anisotropic etching or other suitable etching methods.
Referring to fig. 5, step S3 is performed to form a P-type work function layer 9 covering the P-type work function metal sidewall 8 on the bottom wall and the sidewall of the accommodating space 6.
As an example, the method for forming the P-type work function layer 9 includes at least one of chemical vapor deposition, physical vapor deposition and atomic layer deposition, and the material of the P-type work function layer 9 includes at least one of TiN and TaN. The P-type work function layer 9 is used for adjusting the threshold voltage of the transistor, the thickness of the P-type work function layer 9 is suitable, and the requirement on the threshold voltage is met, so that the threshold voltage cannot be adversely affected. The material of the P-type work function layer 9 and the material of the P-type work function metal side wall 8 may be the same or different, in this embodiment, the material of the P-type work function layer 9 and the material of the P-type work function metal side wall 8 are preferably the same, and are both TiN, when the material of the P-type work function layer 9 and the material of the P-type work function metal side wall 8 are the same, the interface bonding between the P-type work function layer 9 and the P-type work function metal side wall 8 is tighter, and the adverse effect of the generation of interface defects on the device performance is reduced. In addition, the thickness of the P-type work function layer 9 ranges from 10 to 20 angstroms.
Referring to fig. 6, step S4 is performed, in which an N-type work function layer 10, a top barrier layer 11 and a metal layer 12 are sequentially formed in the accommodating space 6, the N-type work function layer 10 covers the P-type work function layer 9, and the N-type work function layer 10 and the metal layer 12 are separated by the top barrier layer 11.
As an example, the method for forming the N-type work function layer 10 includes at least one of chemical vapor deposition, physical vapor deposition and atomic layer deposition, the material of the N-type work function layer 10 includes at least one of TiAl, tiAlC, tiAlN and AlN, in this embodiment, the material of the N-type work function layer 10 is preferably TiAl, and in addition, the thickness of the N-type work function layer 10 is in the range of 30-80 angstroms.
By way of example, the top barrier layer 11 may comprise at least one of TiN and TaN, and the top barrier layer 11 may have a thickness in the range of 15-40 angstroms, including but not limited to 20 angstroms, 25 angstroms, 30 angstroms, and 35 angstroms. The top barrier layer 11 may prevent the diffusion of the easily diffused ions in the metal layer 12 into the N-type work function layer 10, and the lowering of the work function value may decrease the threshold voltage of the formed semiconductor device, and the top barrier layer 11 may further improve the quality of the subsequent formation of the metal layer 12 and the adhesion of the metal layer 12 in the opening. The top barrier layer 11 has a thickness that is suitable, and too low a thickness may cause the barrier effect of the top barrier layer 11 to be too poor, while too large a thickness may be detrimental to the formation of the metal layer 12, and may easily cause the resistance of the high-K metal gate structure to be increased, thereby adversely affecting the electrical performance. The material of the top barrier layer 11 in this embodiment is preferably TiN.
As an example, the material of the metal layer 12 includes at least one of Al, cu, ag, W and Ni, in this embodiment, the material of the metal layer 12 is Al, and the metal layer 12 can reduce the resistance value of the high-K metal gate. The metal layer 12 may be filled with the remaining accommodating space 6, or may not be filled according to actual production requirements, so as to facilitate the formation of other subsequent structural layers.
As an example, the method for manufacturing a semiconductor device with a high-K metal gate structure further includes a chemical mechanical polishing step, which is performed after forming the metal layer 12, so that the top of each layer deposited in the opening is kept level, thereby improving the performance of the device.
According to the manufacturing method of the semiconductor device with the high-K metal gate structure, the structure morphology of the P-type work function layer is changed by forming the P-type work function metal side wall before forming the P-type work function layer, the structural defect that corners of the traditional P-type work function layer are weak due to the deposition behavior of the P-type work function material is overcome, the aluminum diffusion effect of the N-type work function layer formed later under the subsequent high-temperature process condition is effectively avoided, and therefore the performance stability and reliability of the device are improved, and meanwhile the product yield is remarkably improved.
Example two
Referring to fig. 6, a schematic cross-sectional view of the semiconductor device with a high-K metal gate structure of the present embodiment is shown, and the semiconductor device includes a semiconductor layer, a P-type work function metal sidewall 8, a P-type work function layer 9, an N-type work function layer 10, a top barrier layer 11 and a metal layer 12, wherein the semiconductor layer includes a gate dielectric layer 3, a bottom barrier layer 4 and a gate sidewall 5, the bottom barrier layer 4 is located on the gate dielectric layer 3, the gate sidewall 5 is located on two sides of the gate dielectric layer 3 and the bottom barrier layer 4, the bottom barrier layer 4 encloses a top-opened accommodating space 6, and a bottom wall and a sidewall of the accommodating space 6 form corners 7; the P-type work function metal side wall 8 is located at the corner 7, the P-type work function layer 9 is located at the bottom wall and the side wall of the accommodating space 6 and covers the P-type work function metal side wall 8, the N-type work function layer 10 is located in the accommodating space 6 and covers the P-type work function layer 9, the top barrier layer 11 is located in the accommodating space 6 and covers the N-type work function layer 10, and the metal layer 12 is located in the accommodating space 6 and covers the top barrier layer 11.
As an example, the surface of the P-type work function metal sidewall 8 facing the P-type work function layer 9 is a convex surface. The P-type work function metal side wall 8 is arranged to effectively prevent easily-diffused ions (such as Al ions) in the N-type work function layer 10 on the P-type work function layer 9 from diffusing into the gate dielectric layer 3 through the weak part of the corner 7, so that the technical effects of stable device performance, product yield and subsequent reliability evaluation are achieved.
The relevant parameters and functions of each structure in this embodiment are the same as those in the first embodiment, and will not be described here.
The semiconductor device with the high-K metal gate structure of the embodiment has the advantages that the P-type work function metal side wall structure is arranged in the structure, so that the aluminum diffusion effect under the high-temperature condition is effectively avoided, and the device performance stability and the use reliability are excellent.
In summary, in the method for manufacturing the semiconductor device with the high-K metal gate structure, the P-type work function metal side wall is formed before the P-type work function layer is formed, so that the structural morphology of the P-type work function layer is changed, the structural defect that the corner is weak due to the deposition behavior of the P-type work function material in the traditional P-type work function layer forming process is overcome, the aluminum diffusion effect of the subsequently formed N-type work function layer under the subsequent high-temperature process condition is effectively avoided, and the performance stability and reliability of the device are improved, and meanwhile, the product yield is remarkably improved. The semiconductor device with the high-K metal gate structure has the advantages that the P-type work function metal side wall structure is arranged in the structure, so that the aluminum diffusion effect under the high-temperature condition is effectively avoided, and the semiconductor device with the high-K metal gate structure has excellent device performance stability and use reliability. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
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| CN107492498A (en) * | 2016-06-13 | 2017-12-19 | 中芯国际集成电路制造(上海)有限公司 | The forming method of fin field effect pipe |
| CN111883494A (en) * | 2020-07-21 | 2020-11-03 | 联合微电子中心有限责任公司 | Power MOSFET device and forming method thereof |
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| US6291298B1 (en) * | 1999-05-25 | 2001-09-18 | Advanced Analogic Technologies, Inc. | Process of manufacturing Trench gate semiconductor device having gate oxide layer with multiple thicknesses |
| KR100823874B1 (en) * | 2006-12-28 | 2008-04-21 | 경북대학교 산학협력단 | High Density FUNI Field Effect Transistor with Low Leakage Current and Manufacturing Method Thereof |
| CN105448831A (en) * | 2014-08-05 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | High-K metal gate CMOS device and forming method thereof |
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| CN107492498A (en) * | 2016-06-13 | 2017-12-19 | 中芯国际集成电路制造(上海)有限公司 | The forming method of fin field effect pipe |
| CN111883494A (en) * | 2020-07-21 | 2020-11-03 | 联合微电子中心有限责任公司 | Power MOSFET device and forming method thereof |
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