CN115933457A - A Kind of FPGA Facilitating Timing Closure - Google Patents

Abstract

The application discloses an FPGA which is convenient for realizing timing convergence, and relates to the FPGA field. In addition to the global clock signal in the FPGA being connected to the clock input ports of multiple target resource modules via the first global clock tree, the phase-shifted clock signal of the global clock signal is also connected to the clock input ports of each target resource module via the second clock tree The path direction of the second clock tree is the same as that of the first global clock tree so that the delay difference between the second clock tree and the corresponding positions of the first global clock tree is consistent and the delay difference can be adjusted. Each target resource module can have multiple clock signals to choose as the module clock signal. Therefore, local debugging can be performed by adjusting the module clock signal of the local target resource module, so that timing convergence can be achieved more conveniently, which is conducive to speeding up the design process.

Description

An FPGA that facilitates Timing Closure

technical field

The invention relates to the FPGA field, in particular to an FPGA which is convenient for realizing timing convergence.

Background technique

FPGA (Field Programmable Gate Array, Field Programmable Logic Gate Array) contains a large number of resource modules such as CLB, BRAM, DSP, IOB, etc. These resource modules are usually arranged in rows and columns to form a two-dimensional array. The clock signals required for the operation of these resource modules come from multiple preset global clock trees. The global clock tree is a clock network structure, which is connected to the clock input ports of different resource modules through a preset bus structure, so that the global The clock tree can provide clock signals for multiple resource modules inside the FPGA.

When implementing a user design, the global clock signal is generally used as a synchronization signal, that is, a global clock signal is required to be connected to each resource module through the global clock tree, and the rising or falling edge of the global clock signal must be able to reach each resource module at the same time. Clock input port. However, the global clock tree has a large coverage area and long traces. When the global clock signal is transmitted in the global clock tree, there will be a transmission delay, which makes it difficult for the rising or falling edges of the global clock signal to reach the clock input ports of each resource module at the same time. Especially in larger FPGAs, the out-of-synchronization of the global clock signal caused by the transmission delay of the global clock tree is more obvious, that is, clock skew occurs.

The maximum permissible clock skew in the whole film is an important design parameter of FPGA. In order to better meet the requirements of clock skew when designing FPGA circuits, theoretically, it can be transmitted through differential signal transmission, such as , Increase the driving capability and other circuit techniques to design the global clock tree, but this approach will lead to increased circuit area or increased power consumption. Therefore, in order to balance the performance of all aspects, the maximum allowable clock skew in the entire chip generally cannot Feel free to decrease. This leads to the impact of the high proportion of clock skew on the clock period becoming more obvious, especially in advanced FPGA devices, the user design is complex, the clock frequency path is high, and the complex large FPGA user design , it is not easy to fully satisfy all the timing requirements once the layout and routing are completed. Generally, there will be a small number of paths that do not meet the timing requirements. Therefore, it is often necessary to repeatedly debug these local problems, resulting in a longer design cycle.

Contents of the invention

The present inventor proposes a kind of FPGA that is convenient to realize timing convergence for above-mentioned problem and technical demand, and the technical scheme of the present invention is as follows:

The present application discloses a kind of FPGA which is convenient to realize timing convergence, and it is characterized in that, in FPGA, the global clock signal is connected to the clock input ports of multiple target resource modules via the first global clock tree; the phase-shifted clock signal of the global clock signal The clock input port of each target resource module is also connected via the second clock tree, the path of the second clock tree is the same as that of the first global clock tree, and each target resource module obtains the global clock signal or the phase-shifted clock signal as the module clock signal;

When the initial layout and routing of the FPGA is completed and all target resource modules obtain the corresponding global clock signal as the module clock signal but timing convergence is not reached, adjust at least one target resource module to obtain the phase-shifted clock signal as the module clock signal and adjust Shifts the phase difference of the clock signal relative to the global clock signal until timing closure is reached.

Its further technical solution is to adjust at least one target resource module to obtain the phase-shifted clock signal as the module clock signal and adjust the phase difference between the phase-shifted clock signal and the global clock signal until the module clock signals of any two target resource modules The clock offset between them does not exceed a predetermined offset threshold, and the setup time and hold time of the transmission path formed between any two target resource modules satisfy corresponding time constraints.

Its further technical solution is that the method for adjusting the module clock signal of at least one target resource module includes:

After completing the initial layout and routing of the FPGA, perform timing analysis and determine the path to be optimized between any two target resource modules that do not meet the setup time constraints or do not meet the hold time constraints;

Traverse and process each path to be optimized in turn, and for each path to be optimized through traversal processing, adjust the target resource module at the input end of the path to be optimized to obtain a phase-shifted clock signal as the module clock signal, or adjust the path to be optimized The target resource module at the output end obtains the phase-shifted clock signal as the module clock signal, and adjusts the phase difference of the phase-shifted clock signal relative to the global clock signal, so that all paths to be optimized that have been traversed and processed meet the setup time constraints and hold time constraints.

Its further technical solution is, when adjusting the module clock signal of a target resource module, ensure that the transmission path of the input end of the target resource module meets the time constraints corresponding to the setup time and hold time, and ensure that the transmission path of the output end of the target resource module satisfies Time constraints corresponding to setup time and hold time.

Its further technical solution is that when traversing and processing each path to be optimized in sequence, the paths to be optimized that do not satisfy the hold time constraint are processed first, and then the paths to be optimized that do not satisfy the setup time constraint are processed in order to traverse and process each path to be optimized sequentially. Optimize the path.

Its further technical solution is, when there are multiple paths to be optimized that do not satisfy the hold time constraint, traverse and process each path to be optimized in order of the timing margin of the hold time from small to large; when there are multiple paths to be optimized that do not satisfy the establishment When the paths to be optimized are time-constrained, each path to be optimized is traversed and processed in sequence according to the sequence margin of the establishment time from small to large.

Its further technical scheme is that the phase-shifted clock signal is drawn from the predetermined position of the first global clock tree and connected to the input end of the second clock tree through the phase shifter, and the phase-shifted clock signal and the global clock signal are adjusted by the phase shifter. phase difference between them.

Its further technical solution is that the first global clock tree includes a clock trunk line, a plurality of clock branch lines connected in sequence from the clock trunk line to form several levels, and a clock branch line connected to the last level and the corresponding target resource module between the clock end lines;

The predetermined position of the first global clock tree is located on the clock trunk line, or on the clock branch line, or on the clock stub line.

Its further technical solution is that the user signal generates a global clock signal through the phase-locked loop to connect to the input end of the first global clock tree, and generates a phase-shifted clock signal to connect to the input end of the second clock tree, and through the phase-shift adjustment of the phase-locked loop The function adjusts the phase difference between the phase-shifted clock signal and the global clock signal.

Its further technical solution is that a plurality of different phase-shifted clock signals of the global clock signal are respectively connected to the clock input ports of each target resource module through a plurality of different second clock trees, and there is at least one target resource module connected to the first A global clock tree and multiple second clock trees, the target resource module obtains the global clock signal or one of the phase-shifted clock signals as the module clock signal; the phase differences of the multiple phase-shifted clock signals relative to the global clock signal are different.

The beneficial technical effect of the present invention is:

This application discloses an FPGA that facilitates timing convergence. In the FPGA, a second clock tree that has the same path direction as the first global clock tree is added as hardware support, so that each target resource module can have multiple clock signals. It is selected as the module clock signal, and the delay difference between the second clock tree and the corresponding position of the first global clock tree is consistent and easy to adjust. Therefore, local debugging can be performed by adjusting the module clock signal of the local target resource module, which can be more convenient Achieve timing closure, which helps speed up the design process.

Description of drawings

FIG. 1 is a schematic structural diagram of multiple first global clock trees included in the FPGA of the present application.

Fig. 2 is a schematic diagram of a clock tree structure of a second clock tree added to a first global clock tree in an embodiment of the present application.

FIG. 3 is a schematic diagram of another clock tree structure of a second clock tree added to a first global clock tree in another embodiment of the present application.

FIG. 4 is a schematic diagram of another clock tree structure of a second clock tree added to a first global clock tree in another embodiment of the present application.

FIG. 5 is a schematic diagram of another clock tree structure of a second clock tree added to a first global clock tree in another embodiment of the present application.

6 is a schematic diagram of the transmission delay when the two target resource modules M1 and M2 both use the global clock signal CLK1, and a schematic diagram of the transmission delay when M1 is changed to use the phase-shifted clock signal CLK2.

Detailed ways

The specific embodiments of the present invention will be further described below in conjunction with the accompanying drawings.

The present application discloses an FPGA which is convenient for realizing timing convergence. The FPGA is optimized based on the existing FPGA architecture. Therefore, the FPGA also includes several resource modules and a global clock tree, as shown in FIG. 1 , such as CLB, BRAM, Resource modules such as DSP and IOB are arranged in rows and columns to form a two-dimensional array inside the FPGA. The global clock signal CLK1 is connected to clock input ports of multiple target resource modules via the first global clock tree. In this application, the target resource module corresponding to the first global clock tree refers to the resource module connected to the first global clock tree.

Wherein, the first global clock tree includes a main clock line GC, a plurality of branch clock lines HC connected successively from the main clock line GC to form several levels, and a clock branch line HC connected at the last level and the corresponding target resource module Between the clock end lines LC, the multiple clock branch lines HC of each level generally include multiple to cover different areas of the two-dimensional array, and the clock end lines LC also generally include multiple to cover different areas of the two-dimensional array. The clock branch line HC of the first level is connected to the main clock line GC, the clock branch line HC of the second level is connected to the clock branch line HC of the first level, and so on, until the clock branch line HC of the last level, through The clock terminal line LC is connected to the target resource module. The first global clock tree can adopt various existing clock tree structures. Figure 1 shows an exemplary structure of the first global clock tree. The main clock line GC is set in the center of the two-dimensional array and along the vertical direction Set such that it covers the entire 2D array in the vertical direction. The example shown in Figure 1 only includes one level of branch clock lines HC, and each branch clock line HC is arranged at a row of the two-dimensional array and connected to the main clock line GC along the horizontal direction, thereby covering the entire row in the horizontal direction A multi-column resource module in . A clock terminal line LC is provided at a column of resource modules covered by each clock branch line HC to connect the clock branch line HC and the clock input port of the resource module of the corresponding column (ie, the target resource module). The same clock terminal line LC can branch upward and/or downward to cover and connect multiple target resource modules on the same column, for example, branch upward to cover 20 target resource modules. The global clock signal CLK1 is finally output to the clock input port of the target resource module through the clock main line GC, clock branch line HC and clock end line LC in the first global clock tree, that is, the default global clock signal CLK1 of this application is located in the first global clock tree. The most upstream input of the clock tree signal.

In practical applications, there are multiple clock trunk lines inside the FPGA. For example, the common setting has 32 clock trunk lines with different paths, which are respectively written as GC1, GC2...GC32. These multiple clock trunk lines are arranged in parallel in two dimensions. The center of the array, as shown in Figure 1. Multiple clock branch lines with different paths are arranged in parallel at each row of resource modules of the two-dimensional array. For example, 10 clock branch lines are commonly set as HC1, HC2...HC10. The branch clock line of each path is connected to the main clock line of each path. Each target resource module is connected to the clock branch lines of the respective paths in the row through the clock terminal line LC1 . Therefore, the end clock line LC1 connected to a target resource module M1 can be connected to one of the clock branch lines of each path, and the clock branch line of each path can be connected to one of the main clock lines of each path. one.

Therefore, it can be considered that multiple first global clock trees are formed inside the FPGA, and each global clock tree includes a main clock line, multiple clock branch lines at several levels, and clock end lines to form a path direction. The paths of the clock branches and/or clock trunk lines in the two different first global clock trees are different, so that the two different first global clock trees have different path directions. For example, based on the example in FIG. 1 , one first global clock tree includes GC1 , HC1 and LC1 , another first global clock tree includes GC1 , HC3 and LC1 , and another first global clock tree includes GC5 , HC1 and LC1 .

The paths of different first global clock trees are different, and the resource modules connected to different first global clock trees can also be different. The same resource module can be connected to multiple different first global clock trees to obtain different global clock signals CLK1. The goal of this application is to quickly achieve timing convergence. The most important thing is to realize the synchronization design between resource modules in the same clock domain to achieve timing convergence. Therefore, this application is aimed at several goals of a first global clock tree and its connections The resource module is introduced, and the target resource module referred to in this application is a plurality of resource modules connected to the first global clock tree of the same path direction to obtain the same global clock signal CLK1, and these multiple target resource modules can be connected to the same A clock end line and a clock branch line, or paths in different regions may be connected to the same clock end line and clock branch line. For example, in comparison with Figure 1, take a clock branch line containing only one level as an example. Each row of resource modules covers a row of clock branch lines HC1. The clock branch line HC1 in the first row is connected to each resource module in the first row through LC1. The clock branch line HC1 in the second row is connected to each resource module in the second row through LC1. Although the resource module M1 in the first row and the resource module M2 in the second row are actually connected to LC1 and HC1 in different rows, they are connected The paths of HC1 and LC1 are the same, so the resource module M1 in the first row and the resource module M2 in the second row are still connected to the same first global clock tree. Those skilled in the art can understand that, for multiple first global clock trees inside the FPGA, the design provided in this application can be implemented for each first global clock tree respectively.

Please refer to Figure 2, for a first global clock tree and several target resource modules connected to it, the phase-shifted clock signal CLK2 of the global clock signal CLK1 obtained by the first global clock tree is also connected to each target resource module through the second clock tree The clock input port of the resource module, so that each target resource module can obtain the global clock signal CLK1 or the phase-shifted clock signal CLK2 as its own module clock signal. The timing of the phase-shifted clock signal CLK2 is advanced or delayed relative to the global clock signal CLK1. The path direction of the second clock tree is the same as that of the first global clock tree, so the delay difference at the corresponding point of the second clock tree and the first global clock tree is consistent, and the delay difference is determined by the global clock signal CLK1 and the phase-shifted clock signal The time delay difference between CLK2 is determined, thereby forming an adjustable time delay difference.

(1) In one embodiment, the phase-shifted clock signal CLK2 is generated at a predetermined position of the first global clock tree and connected to the input end of the second clock tree through a phase shifter, and the phase-shifted clock signal and the phase-shifted clock signal are adjusted by the phase shifter The phase difference between the global clock signals CLK1. One way of implementation is that the phase shifter can be implemented by using the phase shift adjustment function of the phase locked loop.

In this embodiment, when the signals drawn from the predetermined position of the first global clock tree are connected to the phase shifter, the predetermined position of the drawn signal on the first global clock tree is located on the main clock line or on the branch line of the clock, Or on the clock end line:

When the predetermined position of the derived signal on the first global clock tree is on the clock trunk line, the structure of the second clock tree is similar to that of the first global clock tree, that is, the second clock tree also includes the clock trunk line GCE2, and the clock trunk line Several levels of clock branch lines HCE2 connected to GCE2 in turn, each level of clock branch lines HCE2 include multiple clock branch lines HCE2 covering different areas, and each clock branch line HCE2 is connected to multiple different clock lines through multiple clock end lines LCE2 The clock input port of the target resource module. In this case, the phase-shifted clock signal CLK2 is connected to the position corresponding to the predetermined position on the first global clock tree on the clock branch line HCE2, and the second clock tree can cover the target resource modules connected to multiple rows and columns, as shown in the figure 2 shown.

When the predetermined position of the derived signal on the first global clock tree is located on one of the clock branch lines, the architecture of the second clock tree is a local clock tree architecture, that is, the second clock tree contains the clocks at the corresponding rows of the two-dimensional array A branch line HCE2, the clock branch line HCE2 is connected to clock input ports of multiple different target resource modules through multiple clock end lines LCE2. In this case, the phase-shifted clock signal CLK2 is connected to the clock branch line HCE2 corresponding to the predetermined position on the first global clock tree, and the second clock tree can be connected to target resource modules located in different columns in several rows covered by it. , as shown in Figure 3.

When the predetermined position of the derived signal on the first global clock tree is located on one of the clock end lines LC1, the architecture of the second clock tree is a local clock tree architecture, that is, the second clock tree includes a clock end line LCE2 connected to multiple Clock input ports of different target resource modules. In this case, the phase-shifted clock signal CLK2 is connected to the position corresponding to the predetermined position on the first global clock tree on the clock end line LCE2, and the second clock tree can cover and connect the target resources located in the same column in several rows covered by it. As for the module, as shown in FIG. 4 , the signal drawn from one of the clock terminal lines LC1 is taken as an example, and not all of them are shown.

It can be seen that when the predetermined positions of the derived signals on the first global clock tree are different, the architecture of the second clock tree is also different, and the number and distribution range of target resource modules that can cover connections are also different. The closer the predetermined position of the derived signal on the first global clock tree is to the upstream of the signal, the larger the scale of the second clock tree is, and the wider the distribution range and the greater the number of target resource modules that can cover connections are.

(2) In another embodiment, there is no need to additionally add a phase shifter, as shown in Figure 2, in a conventional FPGA, the user signal CLK0 generates the global clock signal CLK1 through the phase-locked loop PLL to connect the input end of the first global clock tree , as shown in FIG. 5 , that is, access to the main clock line GC1. In this embodiment, the phase-locked loop used to generate the global clock signal CLK1 is directly multiplexed, and the phase-shift adjustment function of the phase-locked loop is used to not only generate the global clock signal CLK1 connected to the input end of the first global clock tree, but also generate a phase-shifted clock The signal CLK2 is connected to the input end of the second clock tree, and the phase difference between the phase-shifted clock signal CLK2 and the global clock signal CLK1 can be adjusted and controlled through the phase-shift adjustment function of the phase-locked loop.

In this embodiment, since the phase-shifted clock signal CLK2 is generated by the user signal CLK0 through the phase-locked loop, it is equivalent to being located at the most upstream signal of the first global clock tree, so the structure of the second clock tree in this embodiment and can be connected The situation of the target resource module is similar to the situation in the above embodiment that the predetermined position of the derived signal on the first global clock tree is located on the clock trunk line, so this embodiment will not be described again.

No matter which method is used to generate the phase-shifted clock signal CLK2, and no matter what kind of clock tree structure the second clock tree adopts, in the design process of the FPGA of the present application, the initial layout and wiring of the FPGA is first carried out. This step is different from that of the existing FPGA. The initial placement and routing are the same, so that all target resource modules obtain the corresponding global clock signal CLK1 as the module clock signal. If the state of timing convergence has been reached at this time, the design is completed. However, due to the complex internal structure of the FPGA, timing convergence is often not achieved after the initial layout and routing. According to the conventional FPGA design process, local repeated debugging is required at this time, and the problem that the debugging process described in the background part takes too long will appear. However, the FPGA of this application adds a second clock tree to provide hardware support. A target resource module is not fixed and can only choose the global clock signal CLK1, but also can choose the phase-shifted clock signal CLK2. When the timing does not converge, adjust at least A target resource module instead acquires the phase-shifted clock signal CLK2 as the module clock signal, and adjusts the phase difference between the phase-shifted clock signal CLK2 and the global clock signal CLK1, so that timing convergence can be achieved relatively quickly.

Timing non-convergence between multiple target resource modules connected to the same first global clock tree mainly includes two situations. For any two target resource modules M1 and M2 when acquiring CLK1:

(1) There will be a transmission delay when the global clock signal CLK1 is transmitted on the first global clock tree, so that when each target resource module obtains the global clock signal CLK1 as the module clock signal, the actually acquired CLK1 is delayed by the transmission time Assume that the module clock signal obtained by the target resource module M1 is clk1, and assume that the module clock signal obtained by the target resource module M2 is clk2. Since the positions of the target resource modules M1 and M2 in the two-dimensional array are different, the transmission delays when the global clock signal CLK1 is transmitted to M1 and M2 are different. The clock skew between the rising edges of clk2 exceeds the predetermined skew threshold, and the timing closure requirement is not met.

(2) When there is signal transmission before the target resource modules M1 and M2, the target resource modules M1 and M2 need to meet the time constraints corresponding to the setup time and hold time. Please refer to Figure 6, the signal S1 is connected from the output of the target resource module M1 to the input of the target resource module M2, as above, assuming that the module clock signal obtained by M1 is clk1, and the module clock signal obtained by M2 is clk2, the following needs to be met The build time constraints of:

d1+T(CK1→Q1)+T(p1)+Tsetup(M2)<d2+Period(CLK1);

And need to meet the following hold time constraints:

d1+T(CK1→Q1)+T(p1)>d2+Thold(M2);

Among them, d1 represents the transmission delay of the global clock signal CLK1 to the target resource module M1 via the first global clock tree, T(CK1→Q1) represents the transmission delay from the clock terminal CK1 of the target resource module M1 to the output Q terminal, T (p1) represents the transmission delay between the output of the target resource module M1 and the input of the target resource module M2, and Tsetup(M2) represents the setup time of the target resource module M2. d2 represents the transmission delay of the global clock signal CLK1 to the target resource module M2 via the first global clock tree, Period(CLK1) represents the clock period of the global clock signal CLK1, and Thold(M2) represents the holding time of the target resource module M2.

After completing the initial placement and routing, the layout positions of the target resource modules M1 and M2 are fixed, which means that both d1 and d2 are fixed. Therefore, due to the inappropriate layout positions of some target resource modules, it may be difficult to locally meet the above setup time constraints and To maintain time constraints, conventional practice requires repeated debugging, which is time-consuming and may require re-localization.

In view of the above two situations where timing does not converge, the present application adjusts at least one target resource module to obtain the phase-shifted clock signal CLK2 as the module clock signal, and when adjusting the phase difference of the phase-shifted clock signal CLK2 relative to the global clock signal CLK1, The goal is to adjust until the clock offset between the module clock signals of any two target resource modules does not exceed the predetermined offset threshold, and the setup time and hold time of the transmission path formed between any two target resource modules meet the corresponding time constraints. By adding the second clock tree, when the target resource module M2 is changed to obtain the phase-shifted clock signal CLK2 as the module clock signal, the following setup time constraints need to be met in Figure 6:

d1+T(CK1→Q1)+T(p1)+Tsetup(M2)<Tps+d3+Period(CLK1);

And need to meet the following hold time constraints:

d1+T(CK1→Q1)+T(p1)>Tps+d3+Thold(M2);

Wherein, Tps represents the phase difference between the global clock signal CLK1 and the phase-shifted clock signal CLK2, which can be positive or negative. d3 represents the transmission delay of the phase-shifted clock signal CLK2 to the target resource module M2 via the second clock tree. After completing the initial placement and routing to determine the layout positions of the target resource modules M1 and M2, it means that both d1 and d3 are fixed, but Tps is easy to adjust, so it is easier to adjust to achieve the above constraints.

In order to achieve the timing convergence requirements of the above setup time and hold time, the method for adjusting the module clock signal of at least one target resource module includes: performing timing analysis after completing the initial placement and routing of the FPGA and determining the time between any two target resource modules. The path to be optimized that does not satisfy the setup time constraint or the hold time constraint is traversed in turn to process each path to be optimized.

In one embodiment, when traversing and processing each path to be optimized in sequence, the paths to be optimized that do not satisfy the hold time constraint are processed first, and then the paths to be optimized that do not satisfy the setup time constraint are processed in order to traverse and process each path to be optimized in turn. path. Because the hold time constraint is relatively more difficult to achieve than the setup time constraint, the hold time constraint problem is prioritized.

In another embodiment, when there are multiple paths to be optimized that do not satisfy the hold time constraint, each path to be optimized is sequentially traversed and processed according to the sequence margin of the hold time from small to large, that is, the timing margin of the hold time is The smaller the amount, the more the path does not meet the hold time constraint, and the more priority it will be processed. When there are multiple paths to be optimized that do not meet the setup time constraints, the paths to be optimized are traversed in order of the timing margin of the setup time from small to large, that is, the smaller the timing margin of the setup time, the more If the constraint of the establishment time is not met, the priority is given to processing.

Regardless of the order in which each path to be optimized is sequentially traversed and processed, for each path to be optimized through traversal processing: adjust the target resource module at the input end of the path to be optimized to obtain the phase-shifted clock signal CLK2 as the module clock signal, or , adjust the target resource module at the output end of the path to be optimized to obtain the phase-shifted clock signal CLK2 as the module clock signal instead. That is, for example, as shown in Figure 6, assuming that the path of the signal S1 is the path to be optimized, the target resource module M1 can be modified to obtain the phase-shifted clock signal CLK2 as the module clock signal, and the target resource module M2 can also be modified to obtain the phase-shifted clock signal CLK2 is used as the module clock signal. And adjust the phase difference Tps of the phase-shifted clock signal CLK2 relative to the global clock signal CLK1, so that all paths to be optimized that have been previously traversed and processed satisfy the setup time constraint and the hold time constraint. Traverse sequentially until all paths to be optimized are traversed, so that all paths to be optimized can meet the constraints of setup time and hold time, and the final phase difference Tps between CLK2 and CLK1 can be determined.

In addition, the input and output of each target resource module are connected with signals. For a path to be optimized transmitted from M1 to M2, if the path to be optimized must always be adjusted to meet the constraints of setup time and hold time, if M1's The arrival of the module clock signal clk1 earlier than the module clock signal clk2 of M2 is beneficial to achieving the hold time constraint of the path to be optimized, but not conducive to achieving the setup time constraint of the path to be optimized. If the module clock signal clk1 of M1 arrives later than the module clock signal clk2 of M2, it is beneficial to achieve the constraint of the setup time of the path to be optimized, but not conducive to the constraint of the hold time of the path to be optimized. By switching M1 to obtain CLK2 and adjusting Tps, the module clock signal clk1 of M1 can be advanced or delayed to meet the constraints of the path to be optimized from M1 to M2, but after the module clock signal clk1 of M1 is advanced or delayed, It will affect the path transmitted by other target resource modules to M1. It is also similar to switch M2 to obtain CLK2 and adjust Tps.

Therefore, when adjusting the module clock signal of a target resource module, it is necessary to consider not only the path to be optimized connected to the input or output of the target resource module, but also the path to be optimized relative to the connection to the other end, that is, not only It is necessary to ensure that the transmission path of the input terminal of the target resource module satisfies the time constraints corresponding to the setup time and the hold time, and also ensure that the transmission path of the output terminal of the target resource module satisfies the time constraints corresponding to the setup time and the hold time.

In the process of traversing and processing the path to be optimized, the problem that the clock offset between some target resource modules exceeds a predetermined offset threshold can be solved together with a high probability. If the clock offset of some target resource modules still exceeds the predetermined offset threshold, select one of the target resource modules to obtain the phase-shifted clock signal CLK2 as the module clock signal, and adjust the phase difference Tps between CLK2 and CLK1. The requirements of clock skew can be met smoothly, and the constraints of relative setup time and hold time will be easier to achieve.

In another embodiment, a plurality of different phase-shifted clock signals CLK2 of the global clock signal CLK1 are respectively connected to the clock input port of each target resource module through a plurality of different second clock trees, and there is at least one target resource module connected simultaneously A first global clock tree and a plurality of second clock trees, each of which is derived from a predetermined position of the first global clock tree and generated by a phase shifter, or generated by a user signal CLK0 through a phase-locked loop, related The technical features are as described above, and this embodiment will not be described in detail. The phase-shifted clock signal CLK2 connected to each second clock tree may be drawn from different predetermined positions of the first global clock tree, and the phase difference of each phase-shifted clock signal relative to the global clock signal is different. Then the target resource module obtains the global clock signal CLK1 or one of the phase-shifted clock signals CLK2 as the module clock signal, so that it is easier to achieve timing convergence through multiple second clock trees.

Claims (10)

1. a kind of FPGA that is convenient to realize timing convergence is characterized in that, in described FPGA, global clock signal is connected to the clock input port of a plurality of target resource modules via the first global clock tree; The phase shifting of described global clock signal The clock signal is also connected to the clock input port of each target resource module through the second clock tree. The path of the second clock tree is the same as that of the first global clock tree. Each of the target resource modules obtains the global clock signal or moves The phase clock signal is used as the module clock signal; When the initial layout and routing of the FPGA is completed, and all target resource modules obtain the corresponding global clock signal as the module clock signal but timing convergence is not reached, at least one target resource module is adjusted to obtain a phase-shifted clock signal as the module clock signal And adjust the phase difference of the phase-shifted clock signal relative to the global clock signal until timing convergence is achieved. 2. FPGA according to claim 1, it is characterized in that, adjust at least one target resource module to obtain phase-shifted clock signal as module clock signal and adjust described phase-shifted clock signal relative to the phase difference of described global clock signal instead , until the clock offset between the module clock signals of any two target resource modules does not exceed the predetermined offset threshold, and the setup time and hold time of the transmission path formed between any two target resource modules meet the corresponding time constraints . 3. FPGA according to claim 2, is characterized in that, the method for adjusting the module clock signal of at least one target resource module comprises: After completing the initial layout and routing of the FPGA, perform a timing analysis and determine a path to be optimized between any two target resource modules that does not satisfy the setup time constraint or does not satisfy the hold time constraint; Traverse and process each path to be optimized in turn, and for each path to be optimized through traversal processing, adjust the target resource module at the input end of the path to be optimized to obtain a phase-shifted clock signal as a module clock signal, or adjust the The target resource module at the output end of the path to be optimized instead obtains the phase-shifted clock signal as the module clock signal, and adjusts the phase difference of the phase-shifted clock signal relative to the global clock signal, so that all the processed paths to be optimized have been traversed Both meet the setup time constraints and meet the hold time constraints. 4. FPGA according to claim 3, is characterized in that, when adjusting the module clock signal of a target resource module, guarantees that the transmission path of the input end of described target resource module satisfies the corresponding time constraints of setup time and hold time, and Ensure that the transmission path of the output terminal of the target resource module satisfies the time constraint corresponding to the setup time and the hold time. 5. FPGA according to claim 3, it is characterized in that, when traversing and processing each path to be optimized in turn, process the path to be optimized that does not satisfy the setup time constraint according to first processing the path to be optimized that does not satisfy the hold time constraint The order of traversing and processing each path to be optimized in turn. 6. FPGA according to claim 5, it is characterized in that, when there are multiple paths to be optimized that do not satisfy the hold time constraint, each path to be optimized is traversed in order according to the sequence margin of hold time from small to large ; When there are multiple paths to be optimized that do not satisfy the setup time constraints, each path to be optimized is traversed and processed in sequence according to the sequence margin of the setup time from small to large. 7. FPGA according to claim 1, is characterized in that, draws at the predetermined position of described first global clock tree and produces described phase-shifted clock signal by phase shifter and connects the input end of described second clock tree, The phase difference between the phase-shifted clock signal and the global clock signal is adjusted by the phase shifter. 8. FPGA according to claim 2, it is characterized in that, described first global clock tree comprises clock main line, starts to connect successively from described clock main line to form a plurality of clock branch lines of several levels, and connects at the end The clock terminal line between the clock branch line of a level and the corresponding target resource module; The predetermined position of the first global clock tree is located on the clock trunk line, or on the clock branch line, or on the clock terminal line. 9. FPGA according to claim 1, is characterized in that, user signal produces described global clock signal to connect the input end of described first global clock tree through phase-locked loop, and produces described phase-shifted clock signal to connect described The input terminal of the second clock tree adjusts the phase difference between the phase-shifted clock signal and the global clock signal through the phase-shift adjustment function of the phase-locked loop. 10. The FPGA according to claim 1, wherein a plurality of different phase-shifted clock signals of the global clock signal are respectively connected to the clock input ports of each target resource module via a plurality of different second clock trees, There is at least one target resource module connected to the first global clock tree and multiple second clock trees at the same time, and the target resource module obtains the global clock signal or one of the phase-shifted clock signals as the module clock signal; multiple phase-shifted clock signals The phase difference with respect to the global clock signal is different.

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